CN107068090A - A kind of gate driving circuit and the display panel comprising it - Google Patents
A kind of gate driving circuit and the display panel comprising it Download PDFInfo
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- CN107068090A CN107068090A CN201710285966.8A CN201710285966A CN107068090A CN 107068090 A CN107068090 A CN 107068090A CN 201710285966 A CN201710285966 A CN 201710285966A CN 107068090 A CN107068090 A CN 107068090A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of gate driving circuit and the display panel comprising it, the gate driving circuit, driving for display panel scan line, the gate driving circuit includes multi-stage shift register circuit, the multi-stage shift register circuit is used to export stages shift signal respectively, the multi-stage shift register circuit is sequentially connected, and the output end of previous stage shift-register circuit connects the input of rear stage shift-register circuit, and every grade of shift-register circuit exports shift signal by the output end；Wherein, the inversion signal of the shift signal of the input access previous stage shift-register circuit output of even level shift-register circuit in the input incoming clock signal of odd level shift-register circuit in the multi-stage shift register circuit, the multi-stage shift register circuit.The gate driving circuit of the present invention can reduce clock signal during circuit operation constantly to the power wastage caused by parasitic capacitance discharge and recharge.
Description
Technical field
A kind of display panel the present invention relates to gate driving circuit and comprising it, more particularly to a kind of grid of low-power consumption
Drive circuit and the display panel comprising it.
Background technology
In liquid crystal display device, in order to display picture, it is usually provided with to drive the raster data model electricity of scan line
Road (gate driver) and the source gate drive circuit (Source Driver) for driving data line, wherein, grid drives
Dynamic circuit is mainly made up of shift-register circuit (shift register circuit).Presently, raster data model
Circuit mainly has following two mode to be driven.
Fig. 1 is the partial schematic diagram of the gate driving circuit of display panel in the prior art.It refer to Fig. 1, raster data model
Circuit 100 is by shift register SR1To SRnIt is connected in sequence, the shift register input clock signal CK of odd level, even number
The clock signal XCK of the shift register input inversion of level, the output signal GL of one phase of displacement to the right is exported step by step with this1
To GLn。
Fig. 2 is the partial schematic diagram of the gate driving circuit of another display panel in the prior art.It refer to Fig. 2, grid
Drive circuit 200 is also by shift register SR1To SRnIt is connected in sequence, but different from gate driving circuit 100 is：Grid
The even level shift register of pole drive circuit 200 also with the equal input clock signal CK of odd level shift register, then by
Increase by one group of buffer circuit on the output circuit of even level shift register, the defeated of one phase of displacement to the right is exported step by step with this
Go out signal GL1To GLn。
In above two gate driving circuit, because clock signal CK can be connected in every one-level shift register, clock
Signal CK phase transition each time all can carry out discharge and recharge to its corresponding parasitic capacitance (Loading), cause power consumption
Waste.And because clock signal CK is frequency of use highest control signal in shift-register circuit operating process, therefore
The power wastage that it is produced is also very big.
The content of the invention
To reduce the power consumption of gate driving circuit, the present invention provides a kind of gate driving circuit.
Above-mentioned gate driving circuit, for the driving of display panel scan line, the gate driving circuit includes multistage move
Bit register circuit, the multi-stage shift register circuit is used to export stages shift signal respectively, multi-stage shift register electricity
Road is sequentially connected, and the output end of previous stage shift-register circuit connects the input of rear stage shift-register circuit, every grade
Shift-register circuit exports shift signal by the output end；
Wherein, the input incoming clock letter of the odd level shift-register circuit in the multi-stage shift register circuit
Number, the input access previous stage shift register electricity of the even level shift-register circuit in the multi-stage shift register circuit
The inversion signal of the shift signal of road output.
As optional technical scheme, the odd level shift-register circuit includes n-th grade of shift-register circuit, and n is
Odd number, the even level shift-register circuit includes (n+1)th grade of shift-register circuit, and in the first period, this n-th grade shifts
Register circuit receives the clock signal and is driven and exports n-th grade of shift signal, and in the second period, this n-th grade shifts
The inversion signal of signal is anti-phase in the clock signal, and (n+1)th grade of shift-register circuit receives the anti-of n-th grade of shift signal
Phase signals are driven and export (n+1)th grade of shift signal, and n-th grade of shift signal of (n+1)th grade of shift signal and this differs one
Individual phase, wherein, first period, second period time span be the clock signal a cycle, and this second when
Cycle of the paragraph after half of clock signal of the first period.
As optional technical scheme, n-th grade of shift-register circuit includes：
The first transistor, the first transistor is n-type transistor, and the grid of the first transistor couples (n-1)th grade of displacement
Signal, the source electrode coupling source electrode of the first transistor provides voltage；
Second transistor, third transistor, the second transistor and the third transistor are P-type transistor, second crystalline substance
A pole in the source-drain electrode of body pipe is mutually coupled to the first pole with the pole in the source-drain electrode of the third transistor, the second transistor
Source-drain electrode in another pole be mutually coupled to the second pole with another pole in the source-drain electrode of the third transistor, first pole coupling
Panel driving voltage, second pole couples the drain electrode of the first transistor；
First phase inverter, the input of first phase inverter couples second pole；
First CMOS inverter, the input of first CMOS inverter couples the output end of first phase inverter, and this
The output end of one CMOS inverter couples the drain electrode of the first transistor, the drain electrode of first CMOS inverter couple this (n-1)th
Level shift signal, the source electrode of first CMOS inverter couples the inversion signal of (n+1)th grade of shift signal；
4th transistor, the 5th transistor, the 4th transistor are n-type transistor, and the 5th transistor is P-type crystal
A pole in pipe, the source-drain electrode of the 4th transistor is coupled to the 3rd pole with the pole in the source-drain electrode of the 5th transistor, should
Another pole in the source-drain electrode of 4th transistor is coupled to quadrupole with another pole in the source-drain electrode of the 5th transistor, and this
The grid of four transistors couples the output end of first phase inverter, and the grid of the 5th transistor couples second pole, and this
Three poles couple the clock signal, and the quadrupole couples (n+1)th grade of shift signal；
6th transistor, the 6th transistor is n-type transistor, and the grid of the 6th transistor couples second pole, should
The drain electrode of 6th transistor couples (n+1)th grade of shift signal, and the source electrode of the 6th transistor couples the source electrode and provides voltage；
Second phase inverter, the input of second phase inverter couples second pole, the output end output of second phase inverter
The inversion signal of n-th grade of shift signal；And
3rd phase inverter, the input of the 3rd phase inverter couples the output end of second phase inverter, the 3rd phase inverter
Output end export n-th grade of shift signal.
As optional technical scheme, (n+1)th grade of shift-register circuit also includes the first transistor, the second crystal
Pipe, third transistor, the first phase inverter, the first CMOS inverter, the 4th transistor, the 5th transistor, the 6th transistor, second
Phase inverter and the 3rd phase inverter, wherein, the grid coupling n-th of the first transistor in (n+1)th grade of shift-register circuit
The drain electrode of first CMOS inverter in level shift signal, (n+1)th grade of shift-register circuit couples this n-th grade displacement letter
Number and source electrode couple the inversion signals of the n-th+2 grades shift signals, the 3rd pole coupling in (n+1)th grade of shift-register circuit
The quadrupole in the inversion signal of n-th grade of shift signal, (n+1)th grade of shift-register circuit directly couples the 6th
The output end of the 3rd phase inverter in the drain electrode of transistor, (n+1)th grade of shift-register circuit exports this (n+1)th grade displacement
Signal.
As optional technical scheme, Neng Hao≤74% of energy consumption/first grid drive circuit of the gate driving circuit,
When the first grid drive circuit accesses for the input of all grades of shift-register circuit in the gate driving circuit
Circuit during clock signal.
As optional technical scheme, n-th grade of shift signal is believed for the final output of n-th grade of shift-register circuit
Number.
As optional technical scheme, n-th grade of shift-register circuit has final output signal, this n-th grade displacement
Signal optimizes to be used as the final output signal by multiple signal.
As optional technical scheme, n-th grade of shift-register circuit carries out the anti-phase of signal by phase inverter.
The present invention also provides a kind of display panel, and display panel includes above-mentioned gate driving circuit.
Compared to prior art, gate driving circuit of the invention utilizes the shift signal of odd level shift-register circuit
Inversion signal be used as the input signal of even level shift-register circuit, so as to replace original work to be even level shift register
The clock signal of the input signal of circuit, and then clock signal is reduced during circuit operation constantly to parasitic capacitance discharge and recharge
Caused power wastage.
Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail, but not as a limitation of the invention.
Brief description of the drawings
Fig. 1 is the partial schematic diagram of the gate driving circuit of display panel in the prior art；
Fig. 2 is the partial schematic diagram of the gate driving circuit of another display panel in the prior art；
Fig. 3 is the partial schematic diagram of gate driving circuit of the present invention；
Fig. 4 is the partial schematic diagram of the timing diagram of gate driving circuit in Fig. 3；
Fig. 5 is the schematic diagram of n-th grade of shift-register circuit in gate driving circuit of the present invention；
Fig. 6 is the schematic diagram of (n+1)th grade of shift-register circuit in gate driving circuit of the present invention.
Embodiment
Technical solution of the present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings, to be further understood that
The purpose of the present invention, scheme and effect, but it is not intended as the limitation of scope of the appended claims of the present invention.
Fig. 3 is the partial schematic diagram of gate driving circuit of the present invention.Fig. 3 is refer to, gate driving circuit 300 is used to show
The driving of panel scan line, gate driving circuit 300 includes multi-stage shift register circuit SR1To SRm, multi-stage shift register
Circuit SR1To SRmFor exporting stages shift signal SR respectively[1]To SR[m], multi-stage shift register circuit SR1To SRmSuccessively
Connection, the output end of previous stage shift-register circuit connects the input of rear stage shift-register circuit, while every grade of shifting
Bit register circuit exports shift signal by output end；Wherein, multi-stage shift register circuit SR1To SRmIn odd level move
The input incoming clock signal CK of bit register circuit, multi-stage shift register circuit SR1To SRmIn even level displacement post
The inversion signal of the shift signal of the input access previous stage shift-register circuit output of latch circuit, for example, such as Fig. 3 institutes
Show, the 1st grade of shift-register circuit SR1, 3rd level shift-register circuit SR3Deng the shift-register circuit input of odd level
Incoming clock signal CK, and the 2nd grade of shift-register circuit SR2Access the 1st grade of shift-register circuit SR1Shift signal
SR[1]Inversion signal, the 4th grade of shift-register circuit SR4Access 3rd level shift-register circuit SR3Shift signal SR[3]
Inversion signal, in the present embodiment, the anti-phase of signal can be carried out by phase inverter, to input to next stage needed for obtaining
The inversion signal of shift-register circuit.In addition, stages shift signal SR[1]To SR[m]Multi-stage shift register circuit can be used as
SR1To SRmOutput signal use.By taking n-th grade of shift-register circuit as an example, it has final output signal, above-mentioned n-th grade
Shift signal can be used as the final output signal of n-th grade of shift-register circuit.Certainly, in other embodiment, displacement letter
Number not directly as multi-stage shift register circuit SR1To SRmOutput signal, but to stages shift signal SR[1]To SR[m]
Continue to do signal transacting (optimizing signal such as by repeatedly anti-phase, buffering), to obtain more suitably output signal
It is supplied to corresponding gate lines.
In this way, gate driving circuit 300 is used using the inversion signal of the shift signal of odd level shift-register circuit
Make the input signal of even level shift-register circuit, so as to replace the input signal that original work are even level shift-register circuit
Clock signal CK or inverting clock signal XCK, and then reduce clock signal CK or inverting clock signal XCK circuit grasp
Constantly to the power wastage caused by parasitic capacitance discharge and recharge during work.
Fig. 4 is the partial schematic diagram of the timing diagram of gate driving circuit in Fig. 3.Please with reference to Fig. 3, Fig. 4, odd level is moved
Bit register circuit includes n-th grade of shift-register circuit SRn, n is odd number, and even level shift-register circuit includes (n+1)th
Level shift-register circuit SRn+1, in the first period T1, n-th grade of shift-register circuit SRnClock signal CK is received to enter
Row drives and exports n-th grade of shift signal SR[n], in the second period T2, (n+1)th grade of shift-register circuit SRn+1Receive n-th
Level shift signal SR[n]Inversion signal D[n]It is driven and exports (n+1)th grade of shift signal SR[n+1], wherein, the first period
T1, the second period T2 time span are clock signal CK Cycle Length, and the second period T2 lags behind the first period T1
Half of clock signal CK cycle.Since in the second period T2, n-th grade of shift signal SR[n]Inversion signal D[n]With clock
Signal CK is anti-phase, so (n+1)th grade of shift-register circuit SRn+1(n+1)th grade of shift signal SR of output[n+1]Can be with n-th grade of shifting
Position signal SR[n]Differ the odd level shift-register circuit that a phase, i.e. even level shift-register circuit access previous stage
Shift signal inversion signal after, the shift signal of the exportable odd level shift-register circuit with previous stage moves to right one
The output signal of phase, that is to say, that gate driving circuit 300 can produce step by step displacement one to the right while power consumption is reduced
Individual phase output signal (in such as Fig. 4, (n-1)th grade of shift signal SR[n-1], n-th grade of shift signal SR[n], (n+1)th grade of displacement letter
Number SR[n+1], the n-th+2 grades shift signal SR[n+2]One phase of displacement to the right step by step), with meet gate driving circuit 300 for
The driving demand of scan line.
Fig. 5 is the schematic diagram of n-th grade of shift-register circuit in gate driving circuit of the present invention.It refer to Fig. 5, n-th grade
Shift-register circuit SRnIncluding the first transistor T1, second transistor T2, third transistor T3, the first phase inverter Q1, first
CMOS inverter CQ1, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the second phase inverter Q2 and the 3rd phase inverter
Q3.The first transistor T1 is n-type transistor, and the first transistor T1 grid couples (n-1)th grade of shift signal SR[n-1], first is brilliant
Body pipe T1 source electrode coupling source electrode provides voltage VSS.Second transistor T2 and third transistor T3 is P-type transistor, and second is brilliant
A pole in body pipe T2 source-drain electrode is mutually coupled to the first pole (not marking) with the pole in third transistor T3 source-drain electrode, the
Another pole in two-transistor T2 source-drain electrode is mutually coupled to the second pole (not with another pole in third transistor T3 source-drain electrode
Mark), the first pole coupling panel driving voltage VDDP, the second pole coupling the first transistor T1 drain electrode.First phase inverter Q1's
Input couples the second pole.First CMOS inverter CQ1 input couples the first phase inverter Q1 output end, and the first CMOS is anti-
Phase device CQ1 output end coupling the first transistor T1 drain electrode, the first CMOS inverter CQ1 drain electrode couples (n-1)th grade of displacement
Signal SR[n-1], the first CMOS inverter CQ1 (n+1)th grade of shift signal SR of source electrode coupling[n+1]Inversion signal XSR[n+1].The
Four transistor T4 are n-type transistor, and the 5th transistor T5 is P-type transistor, the pole in the 4th transistor T4 source-drain electrode with
A pole in 5th transistor T5 source-drain electrode is coupled to another in the 3rd pole (not marking), the 4th transistor T4 source-drain electrode
Pole is coupled to quadrupole (not marking), the 4th transistor T4 grid coupling with another pole in the 5th transistor T5 source-drain electrode
First phase inverter Q1 output end, the 5th transistor T5 grid couples the second pole, the 3rd pole coupling clock signal CK, quadrupole
Couple (n+1)th grade of shift signal SR[n+1].6th transistor T6 is n-type transistor, the 6th transistor T6 grid coupling second
Pole, the 6th transistor T6 drain electrode couples (n+1)th grade of shift signal SR[n+1], the 6th transistor T6 source electrode coupling source electrode offer
Voltage VSS.Second phase inverter Q2 input couples the second pole, and the second phase inverter Q2 output end exports n-th grade of shift signal
SR[n]Inversion signal D[n].N-th grade of shift signal SR[n]Inversion signal D[n]It may be connected to (n+1)th grade of shift-register circuit
SRn+1Input to replace clock signal CK.3rd phase inverter Q3 input couples the second phase inverter Q2 output end, the
Three phase inverter Q3 output end exports n-th grade of shift signal SR[n].In the present embodiment, n-th grade of shift signal SR[n]It can pass through again
The multiple phase inverters for crossing the 3rd phase inverter Q3 of connection output end carry out the conversion of signal in favor of the output of signal, in such as Fig. 5
It is shown, n-th grade of shift signal SR[n]Change turns to n-th grade of shift signal SR[n]Inversion signal XSR[n], it is converted into n-th grade
Output signal SR_OUT[n]Inversion signal, be finally converted to n-th grade of final output signal SR_OUT[n]。
Fig. 6 is the schematic diagram of (n+1)th grade of shift-register circuit in gate driving circuit of the present invention.It refer to Fig. 6, n-th+
1 grade of shift-register circuit SRn+1Also the first transistor T1, second transistor T2, third transistor T3, the first phase inverter are included
Q1, the first CMOS inverter CQ1, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the second phase inverter Q2 and
Three phase inverter Q3, but compared to n-th grade shift-register circuit SRnFor, slightly have difference in the connection of signal, wherein, n-th
+ 1 grade of shift-register circuit SRn+1In the first transistor T1 grid couple n-th grade of shift signal SR[n], the first CMOS is anti-
Phase device CQ1 drain electrode couples n-th grade of shift signal SR[n]And source electrode couples the n-th+2 grades shift signal SR[n+2]Inversion signal
XSR[n+2], the 3rd pole couples n-th grade of shift signal SR[n]Inversion signal D[n], quadrupole directly couples the 6th transistor T6's
Drain electrode, the 3rd phase inverter Q3 output end exports (n+1)th grade of shift signal SR[n+1].With class in n-th grade of shift-register circuit
Seemingly, (n+1)th grade of shift-register circuit is also to (n+1)th grade of shift signal SR[n+1]Conversion is made in favor of follow-up output, (n+1)th
Level shift signal SR[n+1]Change turns to (n+1)th grade of shift signal SR[n+1]Inversion signal XSR[n+1], it is converted into (n+1)th grade
Output signal SR_OUT[n+1]Inversion signal, be finally converted to (n+1)th grade of output signal SR_OUT[n+1]。
Compared to first grid drive circuit, first grid drive circuit is all grades of displacement in gate driving circuit
Circuit during the equal incoming clock signal of the input of register circuit, the i.e. gate driving circuit as shown in Fig. 1 or Fig. 2,
Neng Hao≤74% of energy consumption/first grid drive circuit of the gate driving circuit 300 of the present invention, that is to say, that raster data model electricity
The energy consumption on road 300 can at least reduce by 26%.
The present invention also provides a kind of display panel (not shown), and display panel includes above-mentioned gate driving circuit 300.
In summary, gate driving circuit of the invention utilizes the anti-phase of the shift signal of odd level shift-register circuit
Signal is used as the input signal of even level shift-register circuit, so as to replace original work to be even level shift-register circuit
The clock signal of input signal, and then clock signal is reduced during circuit operation constantly to caused by parasitic capacitance discharge and recharge
Power wastage.
Certainly, the present invention can also have other various embodiments, ripe in the case of without departing substantially from spirit of the invention and its essence
Various corresponding changes and deformation, but these corresponding changes and change ought can be made according to the present invention by knowing those skilled in the art
Shape should all belong to the protection domain of appended claims of the invention.
Claims (9)
1. a kind of gate driving circuit, the driving for display panel scan line, it is characterised in that the gate driving circuit includes
Multi-stage shift register circuit, the multi-stage shift register circuit is used to export stages shift signal respectively, and the stages shift is posted
Latch circuit is sequentially connected, and the output end of previous stage shift-register circuit connects the input of rear stage shift-register circuit
End, every grade of shift-register circuit exports shift signal by the output end；
Wherein, the input incoming clock signal of the odd level shift-register circuit in the multi-stage shift register circuit, should
The input access previous stage shift-register circuit of even level shift-register circuit in multi-stage shift register circuit is defeated
The inversion signal of the shift signal gone out.
2. gate driving circuit as claimed in claim 1, it is characterised in that the odd level shift-register circuit includes n-th
Level shift-register circuit, n is odd number, and the even level shift-register circuit includes (n+1)th grade of shift-register circuit, in the
In one period, n-th grade of shift-register circuit receives the clock signal and is driven and exports n-th grade of shift signal, in
In two periods, the inversion signal of n-th grade of shift signal is anti-phase in the clock signal, and (n+1)th grade of shift-register circuit connects
The inversion signal for receiving n-th grade of shift signal is driven and exports (n+1)th grade of shift signal, (n+1)th grade of shift signal with
N-th grade of shift signal differs a phase, wherein, first period, the time span of second period are the clock signal
A cycle, and second period lag behind the cycle of half of clock signal of the first period.
3. gate driving circuit as claimed in claim 2, it is characterised in that n-th grade of shift-register circuit includes：
The first transistor, the first transistor is n-type transistor, and the grid of the first transistor couples (n-1)th grade of shift signal,
The source electrode coupling source electrode of the first transistor provides voltage；
Second transistor, third transistor, the second transistor and the third transistor are P-type transistor, the second transistor
Source-drain electrode in a pole be mutually coupled to the first pole, the source of the second transistor with the pole in the source-drain electrode of the third transistor
Another pole in drain electrode is mutually coupled to the second pole with another pole in the source-drain electrode of the third transistor, first pole coupling panel
Driving voltage, second pole couples the drain electrode of the first transistor；
First phase inverter, the input of first phase inverter couples second pole；
First CMOS inverter, the input of first CMOS inverter couples the output end of first phase inverter, and this first
The output end of CMOS inverter couples the drain electrode of the first transistor, and the drain electrode of first CMOS inverter couples this (n-1)th grade
Shift signal, the source electrode of first CMOS inverter couples the inversion signal of (n+1)th grade of shift signal；
4th transistor, the 5th transistor, the 4th transistor are n-type transistor, and the 5th transistor is P-type transistor, should
A pole in the source-drain electrode of 4th transistor is coupled to the 3rd pole with the pole in the source-drain electrode of the 5th transistor, and the 4th is brilliant
Another pole in the source-drain electrode of body pipe is coupled to quadrupole, the 4th crystal with another pole in the source-drain electrode of the 5th transistor
The grid of pipe couples the output end of first phase inverter, and the grid of the 5th transistor couples second pole, the 3rd pole coupling
The clock signal is connect, the quadrupole couples (n+1)th grade of shift signal；
6th transistor, the 6th transistor is n-type transistor, and the grid of the 6th transistor couples second pole, the 6th
The drain electrode of transistor couples (n+1)th grade of shift signal, and the source electrode of the 6th transistor couples the source electrode and provides voltage；
Second phase inverter, the input of second phase inverter couples second pole, the output end of second phase inverter export this n-th
The inversion signal of level shift signal；And
3rd phase inverter, the input of the 3rd phase inverter couples the output end of second phase inverter, the 3rd phase inverter it is defeated
Go out end and export n-th grade of shift signal.
4. gate driving circuit as claimed in claim 3, it is characterised in that (n+1)th grade of shift-register circuit also includes
The first transistor, second transistor, third transistor, the first phase inverter, the first CMOS inverter, the 4th transistor, the 5th crystalline substance
Body pipe, the 6th transistor, the second phase inverter and the 3rd phase inverter, wherein, in (n+1)th grade of shift-register circuit this first
The grid of transistor couples the leakage of first CMOS inverter in n-th grade of shift signal, (n+1)th grade of shift-register circuit
Pole couples n-th grade of shift signal and source electrode couples the inversion signal of the n-th+2 grades shift signals, (n+1)th grade of shift register
The 3rd pole in circuit couples the inversion signal of n-th grade of shift signal, being somebody's turn to do in (n+1)th grade of shift-register circuit
Quadrupole directly couples the drain electrode of the 6th transistor, the 3rd phase inverter in (n+1)th grade of shift-register circuit it is defeated
Go out end and export (n+1)th grade of shift signal.
5. gate driving circuit as claimed in claim 4, it is characterised in that energy consumption/first grid of the gate driving circuit
Neng Hao≤74% of drive circuit, the first grid drive circuit is all grades of shift register in the gate driving circuit
Circuit during the equal incoming clock signal of the input of circuit.
6. gate driving circuit as claimed in claim 2, it is characterised in that n-th grade of shift signal is that this n-th grade displacement is posted
The final output signal of latch circuit.
7. gate driving circuit as claimed in claim 2, it is characterised in that n-th grade of shift-register circuit has final
Output signal, n-th grade of shift signal optimizes to be used as the final output signal by multiple signal.
8. gate driving circuit as claimed in claim 2, it is characterised in that n-th grade of shift-register circuit passes through anti-phase
Device carries out the anti-phase of signal.
9. a kind of display panel, it is characterised in that the display panel includes any one of claim 1-8 raster data model electricity
Road.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710285966.8A CN107068090A (en) | 2017-04-27 | 2017-04-27 | A kind of gate driving circuit and the display panel comprising it |
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| CN201710285966.8A CN107068090A (en) | 2017-04-27 | 2017-04-27 | A kind of gate driving circuit and the display panel comprising it |
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| CN107068090A true CN107068090A (en) | 2017-08-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112233630A (en) * | 2020-10-15 | 2021-01-15 | Tcl华星光电技术有限公司 | Gate drive circuit and display panel |
| CN114333667A (en) * | 2020-09-30 | 2022-04-12 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method thereof and display panel |
-
2017
- 2017-04-27 CN CN201710285966.8A patent/CN107068090A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114333667A (en) * | 2020-09-30 | 2022-04-12 | 京东方科技集团股份有限公司 | Gate drive circuit, drive method thereof and display panel |
| CN114333667B (en) * | 2020-09-30 | 2024-01-23 | 京东方科技集团股份有限公司 | Gate driving circuit, driving method thereof and display panel |
| CN112233630A (en) * | 2020-10-15 | 2021-01-15 | Tcl华星光电技术有限公司 | Gate drive circuit and display panel |
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Application publication date: 20170818 |