WO2022077645A1 - Procédé et système de génération de fnc pour vérification d'équivalence - Google Patents

Procédé et système de génération de fnc pour vérification d'équivalence Download PDF

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Publication number
WO2022077645A1
WO2022077645A1 PCT/CN2020/126824 CN2020126824W WO2022077645A1 WO 2022077645 A1 WO2022077645 A1 WO 2022077645A1 CN 2020126824 W CN2020126824 W CN 2020126824W WO 2022077645 A1 WO2022077645 A1 WO 2022077645A1
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cnf
cone
circuit
reference circuit
comparison
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PCT/CN2020/126824
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English (en)
Chinese (zh)
Inventor
刘美华
陈巨光
张岩
金玉丰
黄国勇
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国微集团(深圳)有限公司
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Publication of WO2022077645A1 publication Critical patent/WO2022077645A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Definitions

  • the invention relates to the field of chip design, in particular to a CNF generation method and system for equivalence verification.
  • Equivalence verification of combinational circuits is a key issue in the verification of digital circuits.
  • Structure-based methods can use the ATPG algorithm or recursive learning, while hybrid methods use structural information, simplified ordered binary decision graphs, or Boolean satisfiability algorithms, and in some cases, different forms of learning.
  • the Boolean satisfiability algorithm is based on the Conjunctive Normal Form (CNF) formula.
  • CNF Conjunctive Normal Form
  • the CNF formula of a combinatorial circuit is the conjunction of the CNF formulas of the outputs of each gate, where the CNF formula of each gate indicates that the valid input and output are assigned to the gate, each The CNF formula for each logic gate is shown in the table below.
  • the CNF formula for a circuit is defined by the set union (or conjunction) of the CNF formulas for each gate, so, given a combinational circuit, it's easy to create a CNF for that circuit Formulas and CNF formulas that prove properties of circuit propositions.
  • the purpose of the present invention is that the traditional Boolean satisfiability algorithm cannot be directly used for equivalence verification, and the present invention proposes a CNF generation method and system for equivalence verification.
  • a CNF generation method for equivalence verification which includes:
  • the reference circuit has a plurality of comparison points
  • the implementation circuit also has a plurality of comparison points corresponding to the plurality of comparison points of the reference circuit one-to-one ;
  • numbering each node of the merged logic cone includes:
  • two comparison points corresponding to the reference circuit and the implementation circuit are set as a group of comparison point pairs, from the first group of comparison point pairs to the last group of comparison point pairs, the The equivalence verification of the corresponding logic cones is performed on the comparison points of the reference circuit and the implementation circuit.
  • a CNF generation system for equivalence verification which adopts the CNF generation method for equivalence verification to generate CNF expressions to perform equivalence verification.
  • the outputs of the logic cones corresponding to each group of comparison points in the reference circuit and the realization circuit are respectively combined with XOR gates, Build a new circuit, then number each node of the merged logic cone, bind the cone base number of the merged logic cone with the CNF formula, iterate from the cone base, and build the merged logic cone.
  • CNF expression the time complexity generated by the CNF formula is reduced to a linear relationship, and finally the obtained CNF expression is imported into the miniSat solver for verification.
  • each group of comparisons in the reference circuit and the implementation circuit can be known Whether the logical cones corresponding to the points are equivalent.
  • FIG. 1 is a schematic flowchart of a CNF generation method for equivalence verification according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a logic cone merging according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another logic cone merging according to an embodiment of the present invention.
  • a CNF generation method for equivalence verification includes the following steps:
  • the reference circuit Cref has n comparison points (x1, x2, . . . xn), and the implementation circuit Cimp also has n comparison points (x1) with the test circuit Cref ,x2,...xn) corresponding n comparison points (y1,y2,...yn), n is a natural number;
  • each node of the merged logic cone is numbered, and is processed in the following situations:
  • the CNF expression obtained by the CNF generation method of the present invention if the output result after entering the Boolean satisfiability verification tool is SATISFIABLE, the two logic cones are not equivalent at this time, if it is UNSATISFIABLE. , then the two logical cones are equivalent.
  • the CNF expression obtained by the traditional CNF generation method grows exponentially with the depth of the input and the node.
  • the CNF generation method of the present invention can reduce the time complexity of the CNF expression generation to a linear relationship.
  • the outputs of the logic cones corresponding to each group of comparison points in the reference circuit and the realization circuit are combined with the XOR gate to construct a New circuit, then number each node of the merged logic cone, bind the cone base number of the merged logic cone with the CNF formula, iterate from the cone base, and construct the CNF expression of the merged logic cone formula, the time complexity generated by the CNF formula is reduced to a linear relationship, and finally the obtained CNF expression is imported into the miniSat solver for verification. Whether the corresponding logical cones are equivalent.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

L'invention concerne un procédé et un système de génération de forme normale conjonctive (FNC) pour vérification d'équivalence. Le procédé comprend : la réception d'un circuit de référence et d'un circuit de mise en œuvre correspondant au circuit de référence, la combinaison de sorties de cônes logiques correspondant respectivement à deux points de comparaison correspondants du circuit de référence et du circuit de mise en œuvre avec des portes OU Exclusif, et la numérotation de chaque nœud du cône logique combiné; la liaison d'un numéro de bas de cône du cône logique combiné à une FNC, le démarrage d'une itération à partir d'un bas de cône, et la construction d'une expression en FNC du cône logique combiné; et l'importation de l'expression en FNC obtenue dans un solveur miniSat pour vérification, si un résultat de vérification indique une insatisfiabilité, l'indication du fait que les cônes logiques correspondant respectivement aux deux points de comparaison correspondants du circuit de référence et du circuit de mise en œuvre sont équivalents, et si le résultat de vérification indique une satisfiabilité, l'indication du fait que les cônes logiques ne sont pas équivalents. La solution technique décrite par la présente invention peut être utilisée directement pour une vérification d'équivalence.
PCT/CN2020/126824 2020-10-13 2020-11-05 Procédé et système de génération de fnc pour vérification d'équivalence WO2022077645A1 (fr)

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CN202011091880.X 2020-10-13
CN202011091880.XA CN112257366B (zh) 2020-10-13 2020-10-13 一种用于等价性验证的cnf生成方法及系统

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CN112257366B (zh) * 2020-10-13 2024-05-07 深圳国微芯科技有限公司 一种用于等价性验证的cnf生成方法及系统
WO2023272424A1 (fr) * 2021-06-28 2023-01-05 华为技术有限公司 Procédé et appareil de vérification de circuit basés sur la génération d'un motif de test automatique
CN115062566B (zh) * 2022-06-21 2023-06-27 深圳国微芯科技有限公司 含有x值的电路的简化方法、验证方法、存储介质
CN115048887A (zh) * 2022-06-21 2022-09-13 深圳国微芯科技有限公司 带门控时钟的实现电路的处理方法、验证方法、存储介质
CN116050311B (zh) * 2023-02-06 2023-08-08 中国科学院软件研究所 一种基于完备仿真的组合运算电路等价性验证方法及系统

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