WO2022077456A1 - 单光子雪崩二极管、图像传感器及电子设备 - Google Patents

单光子雪崩二极管、图像传感器及电子设备 Download PDF

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Publication number
WO2022077456A1
WO2022077456A1 PCT/CN2020/121558 CN2020121558W WO2022077456A1 WO 2022077456 A1 WO2022077456 A1 WO 2022077456A1 CN 2020121558 W CN2020121558 W CN 2020121558W WO 2022077456 A1 WO2022077456 A1 WO 2022077456A1
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Prior art keywords
avalanche diode
photon avalanche
groove structure
light
region
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PCT/CN2020/121558
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English (en)
French (fr)
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章健
曹均凯
余力强
李云涛
程文譞
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华为技术有限公司
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Priority to CN202080104210.9A priority Critical patent/CN116097456A/zh
Priority to PCT/CN2020/121558 priority patent/WO2022077456A1/zh
Publication of WO2022077456A1 publication Critical patent/WO2022077456A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Definitions

  • the present application relates to the field of optoelectronic technology, and in particular, to a single-photon avalanche diode, an image sensor and an electronic device.
  • Single photon avalanche diode is a photodiode with single photon detection capability, which is widely used in Raman spectroscopy, positron emission tomography, and fluorescence lifetime imaging.
  • the PN junction of the diode acts as an avalanche region, and above the PN junction is an absorption region (also known as an effective absorption region, high-field region), where incident light is absorbed and converted into electron-hole pairs, and in the avalanche region After amplification (that is, multiplication effect occurs), it is converted into a signal output.
  • absorption region also known as an effective absorption region, high-field region
  • the electron carriers generated by the incident light entering the side of the absorption region not only need to drift longitudinally, but also need to drift laterally for a certain distance to reach the avalanche region for amplification.
  • the laterally drifting electron carriers enter the avalanche region at a slower rate, thereby increasing the uncertainty of the avalanche triggering time and increasing the time jitter.
  • Embodiments of the present application provide a single-photon avalanche diode, an image sensor, and an electronic device, which can improve the quantum efficiency of a SPAD while reducing the jitter caused by the lateral drift of electron carriers.
  • the present application provides a single-photon avalanche diode, comprising: a semiconductor photoelectric conversion structure; the semiconductor photoelectric conversion structure includes a first doped region, a second doped region, and a third doped region; the second doped region is opposite to The first doping region is close to the light incident side of the single photon avalanche diode; the outer edge of the second doping region is located within the outer edge of the first doping region; the third doping region covers the second doping region and faces away from the first doping region The surface on one side of the region and the side surfaces of the first doping region and the second doping region; one of the first doping region and the second doping region is an N-type doping region, and the other is a P-type doping region;
  • the photon avalanche diode further includes: a light trapping structure arranged on the light incident side of the third doping region; the projection of the light trapping structure is located in the first doping region; the light trapping structure includes a middle
  • a light trapping structure is provided on the light incident side of the semiconductor photoelectric conversion structure, and the depth of the edge groove structure in the light trapping structure is greater than the depth of the middle groove structure, so that the light trapping structure can be Part of the light that may enter the side of the high-field area (including part of the directly incident light, part of the light that is refracted, reflected, and scattered by the middle groove structure, etc.), is reflected, refracted, and scattered by the light trapping structure of the edge groove structure. , entering the high-field region and being absorbed and converted into electron-hole pairs, thereby reducing the jitter caused by the light entering the side of the high-field region and improving the quantum absorption rate of the SPAD.
  • the edge groove structure is a closed annular groove, so as to effectively ensure that the light at the edge position can be reflected and scattered by the middle groove structure and then enter the high field region and be absorbed.
  • the depth of the edge groove structure is 1.2-2 times the depth of the middle groove structure. Specifically, by setting the depth of the edge groove structure to be greater than or equal to 1.2 times the depth of the middle groove structure, the light in the edge region can be effectively reflected, refracted and scattered to the high field region to reduce jitter and improve the quantum absorption rate;
  • the depth of the edge groove structure is set to be less than or equal to twice the depth of the middle groove structure, which can avoid excessive thickness of the SPAD, which limits its application range.
  • the width of the edge groove structure is greater than the width of the middle groove structure. In this case, when the edge groove structure and the middle groove structure are formed by the dry etching process, it can be ensured that the depth of the edge groove structure is greater than that of the middle groove structure.
  • the plane where the groove wall of the middle groove structure and the edge groove structure and the notch are located is at an angle of 30° to 90° on one side of the notch; After the reflection, scattering and refraction of the middle groove structure and the edge groove structure, they can effectively enter the high field area.
  • the middle groove structure includes a plurality of grooves that are evenly distributed; alternatively, the middle groove structure includes a mesh groove; or the middle groove structure includes a plurality of concentric annular grooves ;
  • the edge groove structure is a closed annular groove.
  • the third doped region includes a substrate and an epitaxial layer; the epitaxial layer is close to the second doped region relative to the substrate; and the light trapping structure is disposed on the surface of the substrate on the light incident side.
  • the third doped region includes a buried layer and an epitaxial layer; the epitaxial layer is close to the second doped region relative to the buried layer; the single-photon avalanche diode further includes an anti-ablation device disposed on the side of the buried layer away from the epitaxial layer. Reflective film; the light trapping structure is arranged on the surface of the anti-reflection film on the light incident side.
  • the single-photon avalanche diode further includes a microlens, which is disposed on the light incident side of the light trapping structure, so as to effectively condense the incident light to the high field region of the semiconductor photoelectric conversion structure through the microlens.
  • the single-photon avalanche diode further includes a focal length adjustment layer disposed on the side of the microlens close to the light trapping structure; by setting the thickness of the focal length adjustment layer, most of the light passing through the microlens can be incident. To the area of the light trapping structure, that is, by setting the thickness of the focal length adjusting layer, the incident range of light is controlled, thereby improving the utilization rate of light and increasing the quantum efficiency of the SPAD.
  • the focal length adjustment layer and the microlens are integral structures, that is, the microlens and the focal length adjustment layer are both made of the same material, and there is no interface between them, so as to avoid light from occurring at the interface loss.
  • the single-photon avalanche diode further includes a light absorption layer; the light absorption layer is located on the side of the microlens facing the light trapping structure, and the light absorption layer is located at the edge region of the microlens, so that the light absorption layer can pass through the microlens.
  • the light in the edge area is absorbed, reducing the light entering the side of the effective absorption area, thereby reducing the jitter.
  • the single-photon avalanche diode further includes: an insulating medium layer and a reflective layer; the insulating medium layer is disposed on the surface of the semiconductor photoelectric conversion structure away from the light incident side; the reflecting layer is disposed on the insulating medium layer away from the semiconductor photoelectric conversion structure the surface of one side, and the reflective layer is disposed opposite to the second doped region.
  • the light entering the bottom of the semiconductor photoelectric conversion structure is reflected by the reflective layer and then enters the high field region (ie, the effective absorption region) again and is absorbed, thereby further improving the quantum efficiency of the SPAD.
  • the single-photon avalanche diode further includes an isolation deep trench located around the semiconductor photoelectric conversion structure; the isolation deep trench is filled with metal.
  • the isolation deep groove can reflect part of the light entering the side of the high field area to the high field area, thereby improving the quantum absorption rate of the SPAD; especially when the high field area is in contact with the isolation deep groove, by The optical reflection of the isolation deep groove can effectively increase the optical path of light, and does not increase the jitter while improving the quantum absorption rate.
  • Embodiments of the present application further provide an image sensor, including the single-photon avalanche diode provided in any of the foregoing possible implementation manners.
  • Embodiments of the present application also provide an electronic device, including the single-photon avalanche diode provided in any of the foregoing possible implementation manners.
  • FIG. 1 is a schematic top-view structure diagram of a single-photon avalanche diode according to an embodiment of the present application
  • Fig. 2 is the sectional schematic diagram of Fig. 1 along OO' position
  • FIG. 3 is a schematic diagram of an optical path of a single-photon avalanche diode according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 6 is a schematic top-view structure diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 7a is a schematic top-view structure diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 7b is a schematic cross-sectional view of the single-photon avalanche diode of FIG. 7a;
  • FIG. 8 is a schematic top-view structure diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 9 is a schematic top-view structure diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 10 is a schematic top-view structure diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of an optical path of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • FIG. 14 is a schematic top-view structural diagram of a single-photon avalanche diode according to an embodiment of the present application.
  • the embodiment of the present application provides an electronic device, which includes an image sensor; the present application does not limit the specific setting form of the electronic device, for example, the electronic device may be a laser radar, a medical imaging device, a mobile phone, or a digital camera. Wait.
  • a single photon avalanche diode (hereinafter referred to as SPAD) is used as the photoelectric detection unit.
  • SPAD photon avalanche diode
  • a plurality of SPADs arranged in an array may generally be provided.
  • the SPAD used can reduce the incident light entering the side of the absorption region, improve the quantum efficiency of the SPAD, and reduce the jitter caused by the lateral drift of carriers.
  • the SPAD includes a semiconductor photoelectric conversion structure 1, and the semiconductor photoelectric conversion structure 1 receives incident light and performs photoelectric conversion.
  • the semiconductor photoelectric conversion structure 1 can be obtained by ion doping on a silicon epitaxial wafer.
  • the above-mentioned semiconductor photoelectric conversion structure 1 includes a first doped region 10 , a second doped region 20 , and a third doped region 30 arranged in sequence.
  • One of the first doped region 10 and the second doped region 20 is an N-type doped region (eg, a phosphorus-doped silicon semiconductor region), and the other is a P-type doped region (eg, a boron-doped silicon semiconductor region) ;
  • the edge of the second doped region 20 can generally be set to be located inside the edge of the first doped region 10, that is, the area of the second doped region 20 is smaller than that of the first doped region 10. area.
  • the first doped region 10 may be a P-type doped region, and the second doped region 20 may be an N-type doped region; or, the first doped region 10 may be an N-type doped region, and the second doped region 20 is a P-type doped region.
  • the present application is schematically illustrated by taking the first doped region 10 as a P-type doped region and the second doped region 20 as an N-type doped region as an example.
  • the third doping region 30 covers the surface of the second doping region 20 on the side away from the first doping region 10 and the side surfaces of the first doping region 10 and the second doping region 20 ; schematically, the third doping region 30 It may be formed by ion implantation on the silicon epitaxial wafer on which the first doped region 10 and the second doped region 20 are formed.
  • the present application does not limit the specific structure and ion doping type of the third doping region 30 (for example, the third doping region 30 may include an N-type doping region and a P-type doping region), which can be implemented as required in practice. set up.
  • an avalanche region 301 is formed between the first doping region 10 and the second doping region 20 , and the region in the third doping region 30 opposite to the first doping region 10 is used as the In the high field region 302 of the SPAD (or called the absorption region, the effective absorption region), the incident light is absorbed and converted into electron-hole pairs in the high field region 302, and converted into electron-hole pairs after being amplified (ie, multiplication effect occurs) in the avalanche region 301 signal output.
  • a light trapping structure A can be provided on the light incident side of the third doping region 30 , and the projection of the light trapping structure A on the first doping region 10 does not exceed the first doping region 10 .
  • the edge of the impurity region 10 ie, the region within the first impurity region 10 ).
  • the light trapping structure A includes a middle groove structure b and an edge groove structure a located around the middle groove structure b, and the depth of the edge groove structure a is greater than that of the middle groove structure b.
  • the light trapping structure A may include a high-resistance, low-refractive-index medium filled in the edge groove structure a and the middle groove structure b, that is, the edge groove structure a and the middle groove structure b.
  • the inside of the trench structure b has a high-resistance, low-refractive-index filling medium; illustratively, the filling medium may include one or more of Al 2 O 3 , Ta 2 O 5 , SiO 2 , and Si 3 N 4 .
  • the light incident on the third doped region 30 can be scattered, refracted, and reflected by the light trapping structure to increase the optical path, thereby improving the quantum absorption rate of light; on this basis
  • the depth of the edge groove structure a in the light trapping structure A is set to be greater than the depth of the middle groove structure b.
  • the depth of the edge groove structure a may be set to be 1.2 to 2 times the depth of the middle groove structure b. Specifically, by setting the depth of the edge groove structure a to be greater than or equal to 1.2 times the depth of the middle groove structure b, the light in the edge region can be effectively reflected, refracted, and scattered to the high field region, so as to reduce jitter and improve the quantum absorption rate. ; By setting the depth of the edge groove structure a to be less than or equal to twice the depth of the middle groove structure b, it can avoid that the thickness of the SPAD is too large, resulting in a limited application range. For example, in some embodiments, the depth of the edge groove structure a may be set to be 1.5 times the depth of the middle groove structure b.
  • a light trapping structure is provided on the light incident side of the semiconductor photoelectric conversion structure, and the depth of the edge groove structure in the light trapping structure is greater than that of the middle groove structure depth, so that part of the light that may enter the side of the high field area (including part of the light that is directly incident, part of the light that is refracted, reflected, and scattered through the middle groove structure, etc.), is reflected by the light trapping structure of the edge groove structure. , after refraction and scattering, it enters the high-field area and is absorbed and converted into electron-hole pairs, thereby reducing the jitter caused by the light entering the side of the high-field area and improving the quantum absorption rate of SPAD.
  • An isolation deep groove 2 is set around.
  • the interior of the isolation deep trench 2 may be filled with one or more of metal oxides (eg, Al 2 O 3 , Ta 2 O 5 , etc.), silicon oxide, polysilicon, or metals.
  • the isolation deep trench 2 can reflect part of the light entering the side of the high field region 302 to the high field region, so as to be able to Improve the quantum absorption rate of SPAD; especially for the case where the high field area 301 is in contact with the isolation deep groove 2, through the optical reflection of the isolation deep groove 2, the optical path of the light can be effectively increased, and the quantum absorption rate can be improved. At the same time, jitter is not increased.
  • a microlens 3 may be disposed on the light incident side of the semiconductor photoelectric conversion structure 1 .
  • the microlens 3 can be hemispherical with a certain curvature, and the curved convex surface faces the light incident side, and the curved convex surface can converge the incident light, so as to gather the large-area light into the high-field area for absorption, thereby
  • the absorption of incident light by the high field region 302 of the semiconductor photoelectric conversion structure 1 is improved, the quantum absorption rate is improved, and the jitter is reduced.
  • an anti-reflection film (not shown in FIG. 3 ) can be covered on the upper surface (ie, the curved convex surface) of the micro-lens 4 , and the refractive index of the anti-reflection film can be located between the micro-lens and the air. between, in order to reduce the reflected light when the light enters the microlens 4 .
  • the upper surface of the semiconductor photoelectric conversion structure 1 can be covered with a layer of anti-reflection film 4 , that is, the anti-reflection film 4 is arranged to cover the
  • the semiconductor photoelectric conversion structure 1 is provided with a surface on the side of the light trapping structure A; schematically, the antireflection film 4 can be arranged between the semiconductor photoelectric conversion structure 1 and the microlens 3; to reduce the reflected light on the incident surface of the semiconductor photoelectric conversion structure 1 , increasing the light entering the semiconductor photoelectric conversion structure 1 .
  • the anti-reflection films involved in this application can be made of Al 2 O 3 , Ta It is made of one or more of 2 O 3 , SiO 2 and Si 3 N 4 .
  • the thickness and refractive index of the anti-reflection film can be adjusted according to the specific setting of the anti-reflection film; wherein, the adjustment of the refractive index of the anti-reflection film can be realized by adjusting the component materials and the component distribution ratio.
  • an insulating dielectric layer 5 may be provided on the lower surface (ie, the surface away from the light incident side) of the semiconductor photoelectric conversion structure 1 , and a first electrode E1 may be provided on the lower surface of the insulating dielectric layer 5 and the second electrode E2; wherein, the first electrode E2 is connected to the first doping region 10, and the second electrode E1 is connected to the doping region located around the isolation deep trench 2 in the third doping region 30; the first electrode E1 and One of the second electrodes E2 is an anode and the other is a cathode.
  • the first doped region 10 is a P-type doped region and the second doped region 20 is an N-type doped region
  • the first electrode E1 is an anode
  • the second electrode E2 is a cathode
  • the third doping region 30 can be a P-type doping region in the doping region around the isolation deep trench 2; thus, it is ensured that after the light is converted into carriers in the high field region, it enters the avalanche region and passes through the multiplication effect.
  • the first electrode and the second electrode are transmitted to the external circuit.
  • the light trapping structure A may be provided in the semiconductor photoelectric conversion structure 1, or may not be provided in the semiconductor photoelectric conversion structure 1.
  • the installation position of the light trapping structure A will be described below with reference to the specific installation situation of the semiconductor photoelectric conversion structure 1 .
  • the third doped region 30 may include a substrate 31 and an epitaxial layer 32 located on the substrate 31 ;
  • the second doped region 20 that is, the substrate 31 is located on the side of the epitaxial layer 32 away from the second doped region 20 ); in this case, the light trapping structure A can be provided on the surface of the substrate 31 on the light incident side.
  • the depth of the edge groove structure a in the light trapping structure A may be the same as the thickness of the substrate 31 ; of course, the depth of the edge groove structure a may be smaller than the thickness of the substrate 31 .
  • the substrate 31 located on the light incident side of the semiconductor photoelectric conversion structure 1
  • the substrate 31 can be a P-type high-concentration doped region, which is mainly used for charge transfer;
  • the epitaxial layer 32 can be a P-type doped region When the SPAD works, the absorbed light is transmitted to the avalanche region for multiplication in the absorption region.
  • the third doped region 30 may include a buried layer 31 ′ and an epitaxial layer 32 ; the epitaxial layer 32 is close to the second doped region 20 ( That is, the buried layer 31' is located on the side of the epitaxial layer 32 away from the second doping region).
  • the light trapping structure A can be arranged on the light incident side of the antireflection film 4 covering the surface of the buried layer 31'. s surface.
  • the above-mentioned buried layer 31' may be a layer of P-type doped region formed by ion implantation on the surface of the epitaxial layer 32 at any depth.
  • the buried layer 31' serves as a charge transport layer for charge transport, and at the same time, the buried layer 31' can also serve as a thinning stop layer.
  • edge groove structure a and the middle groove structure b in the light trapping structure A will be further described below.
  • the edge groove structure a may be a plurality of groove structures distributed around the middle groove structure b; the opening of the groove structure may be circular or rectangular , triangle, etc.
  • the edge groove structure a may be a closed annular groove arranged around the middle groove structure b; the application does not make any changes to the shape of the opening of the closed annular groove.
  • it can be a closed ring structure such as a circular ring or a rectangular ring.
  • the extension direction of the edge groove structure a can be set and the first doping in the semiconductor photoelectric conversion structure 1 can be set. The direction of extension of the outer edge of the zone 10 remains the same.
  • the groove structure b may adopt a symmetrical groove structure as much as possible, or use a uniformly dispersed groove structure.
  • the middle groove structure b may adopt a plurality of closed annular grooves arranged concentrically.
  • the middle groove structure b can be uniformly dispersed grooves, and the shape of the opening of the groove can be a circle, a rectangle, a triangle, or the like.
  • the middle groove structure b may be a mesh groove structure.
  • the middle groove structure b may include a plurality of strip-shaped groove structures that are uniformly dispersed and extend from the central area to the edge area.
  • a dry etching or wet etching (etching) process may be used for the fabrication of the edge groove structure a and the middle groove structure b in the light trapping structure A.
  • the plane of the groove wall and the groove of the groove structure (a, b) can be controlled by adjusting the etching angle, and the angle ⁇ on one side of the groove is 30° ⁇ 90° °; for example, 30°, 54.7°, 90°, etc., to ensure that the incident light can effectively enter the high field area after being reflected, scattered and refracted by the middle groove structure and the edge groove structure.
  • the cross section of the groove structure (a, b) may be an inverted trapezoid (as shown in FIG. 2 ), a rectangle (as shown in FIG. 7 b ), an inverted triangle, and the like.
  • the plane where the groove walls of the groove structures (a, b) and the notch are located may have an included angle ⁇ on one side of the notch of 60°.
  • the angle ⁇ on one side of the notch can be is 90° (that is, the two are perpendicular).
  • the plane where the groove wall of the partial groove structure and the notch are located can be set, the angle ⁇ on one side of the notch is 90°, and the groove wall of the partial groove structure and the notch are located.
  • the angle ⁇ on the side of the notch is 70°; for example, it can be the plane where the groove wall of the middle groove structure b and the notch are located, the angle ⁇ on the side of the notch is 90°, and the edge
  • the plane where the groove wall of the groove structure a and the notch are located, the angle ⁇ on one side of the notch is 70°; this application does not limit this, in practice, it can be based on the edge groove structure a, the middle groove
  • the structure b needs to set the appropriate angle ⁇ .
  • the width of the edge groove structure a can be set to be 1.5-2.5 times the width of the middle groove structure b to ensure that the width of the formed edge groove structure a and the width of the middle groove structure b meet the requirements.
  • the lower surface of the insulating dielectric layer 5 located at the bottom of the semiconductor photoelectric conversion structure 1 that is, the insulating dielectric layer 5 is away from the semiconductor photoelectric conversion structure 1—
  • the reflective layer 6 is provided in the region corresponding to the first doped region 10, so that the light entering the bottom of the semiconductor photoelectric conversion structure 1 is reflected by the reflective layer and then enters the high field region 302 (ie, the effective absorption region) again and is then absorbed by the reflective layer. absorption, thereby further improving the quantum efficiency of SPAD.
  • the electrode E1 and the second electrode E2 can be fabricated by processing the same metal thin film, that is, the reflective layer 6, the first electrode E1, and the second electrode E2 are provided in the same layer and the same material.
  • the reflective layer 6 , the first electrode E1 , and the second electrode E2 can be made of metals such as copper and aluminum.
  • the reflective layer 6 may be located on the lower surface of the first doped region 10 and disposed opposite to the second doped region 20; the size and shape of the reflective layer 6 may be substantially the same as those of the second doped region 20; for example, The reflective layer can be round or square.
  • the second electrode E2 may be a ring-shaped structure located outside the reflective layer 6
  • the first electrode E1 may be a ring-shaped structure located outside the second electrode E2 .
  • a focal length adjusting layer 7 may be provided at the bottom of the microlens 3 (that is, the surface close to the light trapping structure A side), and the thickness of the focal length adjusting layer 7 can be set by adjusting , so that most of the light passing through the microlens 3 can be incident in the area of the light trapping structure A, that is, the incident range of the light is controlled by setting the thickness of the focal length adjustment layer, thereby improving the utilization rate of light and increasing the SPAD. quantum efficiency.
  • Both the focus adjustment layers 7 are made of the same material, and there is no interface between them, so as to avoid loss of light at the interface.
  • a light-absorbing layer 8 can be provided at the edge region of the bottom of the microlens 3 (that is, the side facing the light trapping structure A), through which the light-absorbing layer 8 can pass through the edge of the microlens 3.
  • the light in the area is absorbed to reduce the light entering the sides of the effective absorption area, thereby reducing the jitter.
  • the light-absorbing layer 8 may use a light-absorbing material, and the material may be one or more of organic and inorganic substances that absorb specific wavelengths; for example, a black resin material.

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Abstract

本申请提供了一种单光子雪崩二极管、图像传感器及电子设备，涉及光电技术领域，能够在降低因电子载流子的横向漂移引起的jitter的同时，提高SPAD的量子效率。该单光子雪崩二极管包括：半导体光电转换结构；半导体光电转换结构包括依次设置的第一掺杂区、第二掺杂区、第三掺杂区；该单光子雪崩二极管还包括：设置在第三掺杂区的入光侧的陷光结构；陷光结构的投影位于第一掺杂区内；陷光结构包括中间凹槽结构和边缘凹槽结构；边缘凹槽结构位于中间凹槽结构的四周，且边缘凹槽结构的深度大于中间凹槽结构的深度。

Description

单光子雪崩二极管、图像传感器及电子设备 技术领域
本申请涉及光电技术领域，尤其涉及一种单光子雪崩二极管、图像传感器及电子设备。
背景技术
单光子雪崩二极管(single photon avalanche diode，SPAD)是一种具有单光子探测能力的光电二极管，广泛的应用于拉曼光谱、正电子发射断层扫描和荧光寿命成像等领域。
在SPAD中，二极管的PN结作为雪崩区，PN结上方为吸收区(也可以称为有效吸收区、高场区)，入射光在吸收区被吸收转换成电子空穴对，并在雪崩区进行放大(也即发生倍增效应)后转换成信号输出。然而，部分入射光会进入吸收区的侧面，在此情况下，进入吸收区侧面的入射光产生的电子载流子不仅需要纵向漂移，而且需要横向漂移一定的距离才能到达雪崩区进行放大，由于横向漂移的电子载流子进入雪崩区的速度较慢，从而增加了雪崩触发时间的不确定性，增加了时间抖动(jitter)。
发明内容
本申请实施例提供一种单光子雪崩二极管、图像传感器及电子设备，能够在降低因电子载流子的横向漂移引起的jitter的同时，提高SPAD的量子效率。
本申请提供一种单光子雪崩二极管，包括：半导体光电转换结构；半导体光电转换结构包括依次设置的第一掺杂区、第二掺杂区、第三掺杂区；第二掺杂区相对于第一掺杂区靠近单光子雪崩二极管的入光侧；第二掺杂区的外边缘位于第一掺杂区的外边缘以内；第三掺杂区覆盖第二掺杂区背离第一掺杂区一侧的表面以及第一掺杂区和第二掺杂区的侧面；第一掺杂区与第二掺杂区中一个为N型掺杂区，另一个为P型掺杂区；单光子雪崩二极管还包括：设置在第三掺杂区的入光侧的陷光结构；陷光结构的投影位于第一掺杂区内；陷光结构包括中间凹槽结构和边缘凹槽结构；边缘凹槽结构位于中间凹槽结构的四周，且边缘凹槽结构的深度大于中间凹槽结构的深度。
本申请实施例提供的单光子雪崩二极管中，通过在半导体光电转换结构的入光侧设置陷光结构，并设置陷光结构中的边缘凹槽结构的深度大于中间凹槽结构的深度，从而能够使得部分可能会进入高场区侧面的光线(包括直接入射的部分光线、经中间凹槽结构折射、反射、散射的部分光线等)，经边缘凹槽结构的陷光结构反射、折射、散射后，进入高场区被吸收转换成电子空穴对，从而降低了因光线进入高场区侧面而导致的jitter，提高了SPAD的量子吸收率。
在一些可能实现的方式中，边缘凹槽结构为封闭环状凹槽，以有效的保证在边缘位置的光线能够经中间凹槽结构反射、散射后进入高场区被吸收。
在一些可能实现的方式中，边缘凹槽结构的深度为中间凹槽结构的深度1.2～2倍。具体的，通过设置边缘凹槽结构的深度大于或等于中间凹槽结构的深度1.2倍，能够有效的将边缘区域的光线反射、折射、散射至高场区，以降低jitter，提高量子吸收率；通过设置 边缘凹槽结构的深度小于或等于中间凹槽结构的深度2倍，能够避免SPAD的厚度过大，导致其应用范围受限。
在一些可能实现的方式中，边缘凹槽结构的宽度大于中间凹槽结构的宽度。在此情况下，在通过干法刻蚀工艺形成边缘凹槽结构和中间凹槽结构时，即可能够保证边缘凹槽结构的深度大于中间凹槽结构。
在一些可能实现的方式中，中间凹槽结构和边缘凹槽结构的槽壁与槽口所在的平面，在位于槽口一侧的夹角为30°～90°；以保证入射的光线在经过中间凹槽结构和边缘凹槽结构的反射、散射、折射后，有效的进入高场区。
在一些可能实现的方式中，中间凹槽结构包括均匀分散设置的多个凹槽；或者，中间凹槽结构包括网状凹槽；或者，中间凹槽结构包括同心设置的多个圆环凹槽；边缘凹槽结构为封闭圆环状凹槽。
在一些可能实现的方式中，第三掺杂区包括衬底以及外延层；外延层相对于衬底靠近第二掺杂区；陷光结构设置于衬底位于入光侧的表面。
在一些可能实现的方式中，第三掺杂区包括埋层以及外延层；外延层相对于埋层靠近第二掺杂区；单光子雪崩二极管还包括设置在埋层背离外延层一侧的减反膜；陷光结构设置于减反膜位于入光侧的表面。
在一些可能实现的方式中，单光子雪崩二极管还包括微透镜，微透镜设置于陷光结构的入光侧，以通过微透镜将入射光有效的汇聚至半导体光电转换结构的高场区。
在一些可能实现的方式中，单光子雪崩二极管还包括设置在微透镜靠近陷光结构一侧的焦距调节层；通过设置该焦距调节层的厚度，能够使得透过微透镜的绝大部分光线入射至陷光结构的区域内，也即通过设置该焦距调节层的厚度控制光线的入射范围，从而提高光的利用率，增加SPAD的量子效率。
在一些可能实现的方式中，焦距调节层与微透镜为一体结构，也即微透镜和焦距调节层两者采用相同的材料，且两者之间不存在界面，以避免光线在界面位置处发生损失。
在一些可能实现的方式中，单光子雪崩二极管还包括吸光层；吸光层位于微透镜朝向陷光结构的一侧，且吸光层位于微透镜的边缘区域，以通过该吸光层对透过微透镜边缘区域的光线进行吸收，减少进入有效吸收区侧面的光线，从而降低jitter。
在一些可能实现的方式中，单光子雪崩二极管还包括：绝缘介质层和反射层；绝缘介质层设置于半导体光电转换结构背离入光侧的表面；反射层设置于绝缘介质层背离半导体光电转换结构一侧的表面，且反射层与第二掺杂区相对设置。在此情况下，进入半导体光电转换结构的底部的光线经反射层反射后再次进入高场区(也即有效吸收区)进而被吸收，从而进一步的提高了SPAD的量子效率。
在一些可能实现的方式中，单光子雪崩二极管还包括位于半导体光电转换结构四周的隔离深槽；隔离深槽内部填充有金属。在此情况下，该隔离深槽能够将进入高场区侧面的部分光线反射至高场区，从而能够提高SPAD的量子吸收率；尤其是对于高场区与隔离深槽相接触的情况下，通过该隔离深槽的光学反射，能够有效的增加光线的光程，在提高量子吸收率的同时不增加jitter。
本申请实施例还提供一种图像传感器，包括如前述任一种可能实现的方式中提供的单光子雪崩二极管。
本申请实施例还提供一种电子设备，包括如前述任一种可能实现的方式中提供的单光子雪崩二极管。
附图说明
图1为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图；
图2为图1沿OO’位置的剖面示意图；
图3为本申请实施例提供的一种单光子雪崩二极管的光路示意图；
图4为本申请实施例提供的一种单光子雪崩二极管的结构示意图；
图5为本申请实施例提供的一种单光子雪崩二极管的结构示意图；
图6为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图；
图7a为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图；
图7b为图7a的单光子雪崩二极管的剖面示意图；
图8为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图；
图9为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图；
图10为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图；
图11为本申请实施例提供的一种单光子雪崩二极管的光路示意图；
图12为本申请实施例提供的一种单光子雪崩二极管的结构示意图；
图13为本申请实施例提供的一种单光子雪崩二极管的结构示意图；
图14为本申请实施例提供的一种单光子雪崩二极管的俯视结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“连接”、“相连”等类似的词语，用于表达不同组件之间的互通或互相作用，可以包括直接相连或通过其他组件间接相连。“上”、“下”、“左”、“右”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备中包括图像传感器；本申请对于该电子设备的具体设置形式不做限制，例如，该电子设备可以为激光雷达、医疗成像设备、手机、数码相机等。
上述图像传感器中采用单光子雪崩二极管(下文可简称SPAD)作为光电探测单元。示意的，在一些图像传感器中，一般可以设置多个阵列排布的SPAD。
本申请实施例提供的图像传感器中，采用的SPAD能够减少进入吸收区侧面的入射光线，提高SPAD的量子效率，降低因载流子的横向漂移引起的jitter。
以下对本申请实施例提供的SPAD的具体设置情况进行说明。
如图1和图2(图1沿OO’位置的剖面示意图)，SPAD中包括半导体光电转换结构1，通过该半导体光电转换结构1接收入射光线，并进行光电转换。示意的，在一些可能实现的方式中该半导体光电转换结构1可以通过在硅外延片上通过离子掺杂得到。
如图2所示，在沿靠近入光侧的方向上，上述半导体光电转换结构1包括依次设置的第一掺杂区10、第二掺杂区20、第三掺杂区30。
第一掺杂区10和第二掺杂区20中一个为N型掺杂区(例如磷掺杂的硅半导体区域)，另一个为P型掺杂区(例如硼掺杂的硅半导体区域)；通常为了减少电场的边缘击穿，一般可以设置第二掺杂区20的边缘位于第一掺杂区10的边缘内侧，也即第二掺杂区20的面积小于第一掺杂区10的面积。
示意的，第一掺杂区10可以为P型掺杂区，第二掺杂区20为N型掺杂区；或者，第一掺杂区10为N型掺杂区，第二掺杂区20为P型掺杂区。以下实施例均是以第一掺杂区10为P型掺杂区，第二掺杂区20为N型掺杂区为例，对本申请进行示意说明的。
第三掺杂区30覆盖第二掺杂区20背离第一掺杂区10一侧的表面以及第一掺杂区10和第二掺杂区20的侧面；示意的，第三掺杂区30可以在形成有第一掺杂区10和第二掺杂区20的硅外延片上通过离子注入形成。本申请对于第三掺杂区30具体设置结构以及离子掺杂类型不做限制(例如，第三掺杂区30可以包括N型掺杂区、P型掺杂区)，实际中可以根据需要进行设置。
此处可以理解的是，参考图2，第一掺杂区10与第二掺杂区20之间形成雪崩区301，第三掺杂区30中与第一掺杂区10正对的区域作为SPAD的高场区302(或者称为吸收区、有效吸收区)，入射的光线在高场区302被吸收转换成电子空穴对，并在雪崩区301放大(即发生倍增效应)后转换成信号输出。
另外，在SPAD中，如图2所示，可以在位于第三掺杂区30的入光侧设置陷光结构A，该陷光结构A在第一掺杂区10的投影不超出第一掺杂区10的边缘(也即位于第一掺杂区10以内的区域)。其中，该陷光结构A包括中间凹槽结构b以及位于中间凹槽结构b四周的边缘凹槽结构a，且该边缘凹槽结构a的深度大于中间凹槽结构b的深度。
另外，在一些可能实现的方式中，该陷光结构A可以包括填充于边缘凹槽结构a和中间凹槽结构b内部的高阻、低折射率介质，也即边缘凹槽结构a和中间凹槽结构b内部具有高阻、低折射率的填充介质；示意的，该填充介质可以包括Al 2O 3、Ta 2O 5、SiO 2、Si 3N 4中的一种或多种。
参考图3所示，基于陷光结构A的设置，入射至第三掺杂区30的光线能够经过陷光结构散射、折射、反射后增加光程，进而提高光的量子吸收率；在此基础上，本申请通过设置陷光结构A中边缘凹槽结构a的深度大于中间凹槽结构b的深度，在此情况下，部分可能会进入高场区302侧面的光线l(包括直接入射的部分光线、经中间凹槽结构b折射、反射、散射的部分光线等)，在经边缘凹槽结构a的反射、折射、散射后，能够正常进入高场区302被吸收转换成电子空穴对，降低了因光线进入高场区侧面而导致的jitter，提高了SPAD的量子吸收率。
示意的，在一些可能实现的方式中，可以设置边缘凹槽结构a的深度为中间凹槽结构b的深度1.2～2倍。具体的，通过设置边缘凹槽结构a的深度大于或等于中间凹槽结构b的深度1.2倍，能够有效的将边缘区域的光线反射、折射、散射至高场区，以降低jitter，提高量子吸收率；通过设置边缘凹槽结构a的深度小于或等于中间凹槽结构b的深度2倍，能够避免SPAD的厚度过大，导致其应用范围受限。例如，在一些实施例中，可以设置边缘凹槽结构a的深度为中间凹槽结构b的深度1.5倍。
综上所述，本申请实施例提供的单光子雪崩二极管中，通过在半导体光电转换结构的入光侧设置陷光结构，并设置陷光结构中的边缘凹槽结构的深度大于中间凹槽结构的深度，从而能够使得部分可能会进入高场区侧面的光线(包括直接入射的部分光线、经中间凹槽结构折射、反射、散射的部分光线等)，经边缘凹槽结构的陷光结构反射、折射、散射后，进入高场区被吸收转换成电子空穴对，从而降低了因光线进入高场区侧面而导致的jitter，提高了SPAD的量子吸收率。
为了防止SPAD与外部(例如相邻的两个SPAD之间或者外界环境)发生光学、电学串扰，在一些可能实现的方式中，如图1和图2所示，可以在半导体光电转换结构1的四周设置隔离深槽2。示意的，该隔离深槽2内部可以填充有金属氧化物(如Al 2O 3、Ta 2O 5等)、氧化硅、多晶硅或者金属中的一种或多种。
此处可以理解的是，对于在隔离深槽2中的填充物采用金属而言，在此情况下，该隔离深槽2能够将进入高场区302侧面的部分光线反射至高场区，从而能够提高SPAD的量子吸收率；尤其是对于高场区301与隔离深槽2相接触的情况下，通过该隔离深槽2的光学反射，能够有效的增加光线的光程，在提高量子吸收率的同时不增加jitter。
如图3所示，为了将入射光有效的汇聚至半导体光电转换结构1的高场区302，可以在半导体光电转换结构1的入光侧设置微透镜3。该微透镜3可以为曲率一定的半球形，且弯曲的凸面朝向入光侧，通过该弯曲的凸面能够对入射光线起到汇聚作用，以将大面积的光汇聚到高场区进行吸收，从而提高半导体光电转换结构1的高场区302对入射光线的吸收，提高量子吸收率，减小jitter。
在一些可能实现的方式中，可以在微透镜4的上表面(即弯曲的凸面)覆盖一层减反膜(图3中未示出)，该减反膜的折射率可以位于微透镜和空气之间，以减少光线入射至微透镜4时的反射光线。
另外，如图3所示，为了进一步的增加入射至半导体光电转换结构1的光线，可以在半导体光电转换结构1的上表面覆盖一层减反膜4，也即该减反膜4覆盖设置于半导体光电转换结构1设置陷光结构A一侧的表面；示意的，减反膜4可以设置在半导体光电转换结构1与微透镜3之间；以减少半导体光电转换结构1的入射面的反射光线，增加进入半导体光电转换结构1的光线。
示意的，本申请中所涉及的减反膜，如前述覆盖在微透镜3表面的减反膜、覆盖在半导体光电转换结构1上表面的减反膜4，均可以采用Al 2O 3、Ta 2O 3、SiO 2和Si 3N 4中的一种或多种等材料制成。实际中，可以根据减反膜的具体设置情况来调整其厚度和折射率；其中，减反膜的折射率的调整可以通过调整组分材料以及组分配比来实现。
另外，如图3所示，在SPAD中，可以在半导体光电转换结构1的下表面(即背离入光侧的表面)设置绝缘介质层5，在绝缘介质层5的下表面设置第一电极E1和第二电极 E2；其中，第一电极E2与第一掺杂区10连接，第二电极E1与第三掺杂区30中位于隔离深槽2四周的掺杂区连接；第一电极E1和第二电极E2中一个为阳极，另一个为阴极。示意的，在第一掺杂区10为P型掺杂区，第二掺杂区20为N型掺杂区的情况下，第一电极E1为阳极，第二电极E2为阴极；在此情况下，第三掺杂区30在位于隔离深槽2四周的掺杂区可以为P型掺杂区；从而保证光在高场区被转换成载流子后，进入雪崩区发生倍增效应后通过第一电极和第二电极传输至外电路。
以下对前述陷光结构A的具体设置情况做进一步的说明。
首先，对于前述设置于第三掺杂区30入光侧的陷光结构A而言，可以理解的是，该陷光结构A可以设置在半导体光电转换结构1中，也可以不设置在半导体光电转换结构1中，以下结合半导体光电转换结构1的具体设置情况，对陷光结构A的设置位置进行说明。
例如，在一些可能实现的方式中，如图4所示，第三掺杂区30可以包括衬底31以及位于衬底31上的外延层32；其中，外延层32相对于衬底31靠近第二掺杂区20(也即衬底31位于外延层32背离第二掺杂区20的一侧)；在此情况下，可以将陷光结构A设置于衬底31位于入光侧的表面。示意的，陷光结构A中的边缘凹槽结构a的深度可以与衬底31的厚度相同；当然，也可以设置边缘凹槽结构a的深度可以小于衬底31的厚度。
示意的，对于上述衬底31位于半导体光电转换结构1的入光侧而言，衬底31可以为P型高浓度掺杂区，主要用于进行电荷传输；外延层32可以为P型掺杂区，在SPAD进行工作时，在吸收区将吸收的光传输到雪崩区进行倍增。
又例如，在一些可能实现的方式中，如图5所示，第三掺杂区30可以包括埋层31’以及外延层32；外延层32相对于衬底31靠近第二掺杂区20(也即埋层31’位于外延层32背离第二掺杂区的一侧)，在此情况下，可以将陷光结构A设置于覆盖在埋层31’表面的减反膜4的入光侧的表面。
示意的，上述埋层31’可以是通过离子注入的方式在外延层32的表面以任意深度注入形成的一层P型掺杂区。埋层31’作为电荷传输层进行电荷传输，同时埋层31’还可以作为减薄停止层。
以下对陷光结构A中的边缘凹槽结构a、中间凹槽结构b的具体设置情况做进一步的说明。
对于边缘凹槽结构a而言：
在一些可能实现的方式中，如图6所示，边缘凹槽结构a可以是位于中间凹槽结构b四周的分散设置的多个凹槽结构；该凹槽结构的开口可以为圆形、矩形、三角形等。
在一些可能实现的方式中，如图1所示，边缘凹槽结构a可以是设置在中间凹槽结构b四周的封闭环状凹槽；本申请对于该封闭环状凹槽的开口形状不做限制，例如可以为圆环、矩形环等封闭环结构。当然，为了有效的保证在边缘位置的光线能够经中间凹槽结构b反射、散射后进入高场区被吸收，可以设置边缘凹槽结构a的延伸方向与半导体光电转换结构1中第一掺杂区10的外边缘的延伸方向保持一致。
对于中间凹槽结构b的设置而言，只要保证入射的光线在经过中间凹槽结构b的陷光结构的反射、散射、折射后，均匀分散进入高场区即可，因此实际在设计中间凹槽结构b可以尽可能采用对称的凹槽结构，或者采用均匀分散设置的凹槽结构。
例如，在一些可能实现的方式中，如图1所示，中间凹槽结构b可以采用同心设置的 多个封闭圆环凹槽。
又例如，在一些可能实现的方式中，如图7a、图8所示，中间凹槽结构b可以采用均匀分散设置的凹槽，该凹槽的开口形状可以为圆形、矩形、三角形等。
再例如，在一些可能实现的方式中，如图9所示，中间凹槽结构b可以为网状凹槽结构。
再例如，在一些可能实现的方式中，如图10所示，中间凹槽结构b可以包括从中心区域向边缘区域延伸的多个均匀分散设置的条状凹槽结构。另外，对于陷光结构A中的边缘凹槽结构a、中间凹槽结构b的制作而言，在一些可能实现的方式中，可以采用干法刻蚀或者湿法腐蚀(刻蚀)工艺制作。
参考图2所示，实际中，可以通过调整刻蚀角度，控制凹槽结构(a、b)的槽壁与槽口所在的平面，在位于槽口一侧的夹角β为30°～90°；例如，30°、54.7°、90°等，以保证入射的光线在经过中间凹槽结构和边缘凹槽结构的反射、散射、折射后，有效的进入高场区。在此情况下，凹槽结构(a、b)的横截面可以为倒梯形(如图2)、矩形(如图7b)、倒三角形等等。示意的，在一些可能实现的方式中，如图2所示，凹槽结构(a、b)的槽壁与槽口所在的平面，在位于槽口一侧的夹角β可以为60°。在一些可能实现的方式中，如图7b(图7a的剖面示意图)所示，凹槽结构(a、b)的槽壁与槽口所在的平面，在位于槽口一侧的夹角β可以为90°(也即两者垂直)。在一些可能实现的方式中，可以设置部分凹槽结构的槽壁与槽口所在的平面，在位于槽口一侧的夹角β为90°，部分凹槽结构的槽壁与槽口所在的平面，在位于槽口一侧的夹角β为70°；例如，可以是中间凹槽结构b的槽壁与槽口所在的平面，在位于槽口一侧的夹角β为90°，边缘凹槽结构a的槽壁与槽口所在的平面，在位于槽口一侧的夹角β为70°；本申请对此均不做限制，实际中可以根据边缘凹槽结构a、中间凹槽结构b需要，设置合适的夹角β。
另外，实际中通过设置边缘凹槽结构a的宽度大于中间凹槽结构b的宽度，从而在通过干法刻蚀工艺形成凹槽结构(a、b)时，能够保证边缘凹槽结构a的深度大于中间凹槽结构b。示意的，可以设置边缘凹槽结构a的宽度为中间凹槽结构b的宽度的1.5～2.5倍，以保证形成的边缘凹槽结构a的宽度和中间凹槽结构b的宽度满足需求。
此外，考虑到存在部分光线在第三掺杂区30不能完全被吸收，而进入半导体光电转换结构1的底部(也即背离入光侧的表面)；尤其是针对半导体光电转换结构1采用硅半导体材料的情况下，由于硅(Si)对于800nm-1000nm的近红外光的吸收深度很大，会出现部分光线进入半导体光电转换结构1的底部无法被吸收。
在此前情况下，如图11所示，在一些可能实现的方式中，可以在位于半导体光电转换结构1底部的绝缘介质层5的下表面，也即绝缘介质层5背离半导体光电转换结构1一侧的表面，对应第一掺杂区10的区域设置反射层6，以使得进入半导体光电转换结构1的底部的光线经反射层反射后再次进入高场区302(也即有效吸收区)进而被吸收，从而进一步的提高了SPAD的量子效率。
另外，对于设置于绝缘介质层5下表面的反射层6、第一电极E1、第二电极E2而言，在一些可能实现的方式中，为了简化工艺，降低制作成本，反射层6、第一电极E1、第二电极E2可以采用同一金属薄膜加工制作而成，也即反射层6、第一电极E1、第二电极E2同层同材料设置。
示意的，反射层6、第一电极E1、第二电极E2可以采用铜、铝等金属。
示意的，反射层6可以位于第一掺杂区10的下表面，且与第二掺杂区20相对设置；反射层6的大小、形状可以与第二掺杂区20的基本一致；例如，反射层可以为圆形、方形。
示意的，第二电极E2可以为位于反射层6外侧的环状结构，第一电极E1可以为位于第二电极E2外侧的环状结构。
参考图12所示，在一些可能实现的方式中，可以在微透镜3的底部(也即靠近陷光结构A一侧的表面)设置焦距调节层7，通过调整设置该焦距调节层7的厚度，以使得透过微透镜3的绝大部分光线能够入射至陷光结构A的区域内，也即通过设置该焦距调节层的厚度控制光线的入射范围，从而提高光的利用率，增加SPAD的量子效率。
为了避免光线从微透镜3进入焦距调节层7导致光损失，在一些可能实现的方式中，参考图13所示，可以设置微透镜3和焦距调节层7为一体结构，也即微透镜3和焦距调节层7两者采用相同的材料，且两者之间不存在界面，以避免光线在界面位置处发生损失。
此外，由于在微透镜3的边缘区域的曲率不一致，容易导致光线会直接透过透镜入射至有效吸收区的边缘，进而可能导致jitter的增加；基于此，在一些可能实现的方式中，如图13和图14(图13的俯视图)，可以在微透镜3底部(也即朝向陷光结构A的一侧)的边缘区域设置吸光层8，通过该吸光层8能够对透过微透镜3边缘区域的光线进行吸收，以减少进入有效吸收区侧面的光线，从而降低jitter。
示意的，在一些可能实现的方式中，上述吸光层8可以采用吸光材料，该材料可以为吸收特定波长的有机物、无机物中的一种或多种；例如黑色树脂材料。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种单光子雪崩二极管，其特征在于，包括：半导体光电转换结构；
    所述半导体光电转换结构包括依次设置的第一掺杂区、第二掺杂区、第三掺杂区；
    所述第二掺杂区相对于所述第一掺杂区靠近所述单光子雪崩二极管的入光侧；所述第二掺杂区的外边缘位于所述第一掺杂区的外边缘以内；所述第三掺杂区覆盖所述第二掺杂区背离所述第一掺杂区一侧的表面以及所述第一掺杂区和所述第二掺杂区的侧面；
    所述第一掺杂区与所述第二掺杂区中一个为N型掺杂区，另一个为P型掺杂区；
    所述单光子雪崩二极管还包括：设置在所述第三掺杂区的入光侧的陷光结构；所述陷光结构的投影位于所述第一掺杂区内；
    所述陷光结构包括中间凹槽结构和边缘凹槽结构；所述边缘凹槽结构位于所述中间凹槽结构的四周，且所述边缘凹槽结构的深度大于所述中间凹槽结构的深度。
  2. 根据权利要求1所述的单光子雪崩二极管，其特征在于，
    所述边缘凹槽结构为封闭环状凹槽。
  3. 根据权利要求1或2所述的单光子雪崩二极管，其特征在于，
    所述边缘凹槽结构的深度为所述中间凹槽结构的深度1.2～2倍。
  4. 根据权利要求1-3任一项所述的单光子雪崩二极管，其特征在于，
    所述边缘凹槽结构的宽度大于所述中间凹槽结构的宽度。
  5. 根据权利要求1-4任一项所述的单光子雪崩二极管，其特征在于，
    所述中间凹槽结构和所述边缘凹槽结构的槽壁与槽口所在的平面，在位于槽口一侧的夹角为30°～90°。
  6. 根据权利要求1-5任一项所述的单光子雪崩二极管，其特征在于，
    所述中间凹槽结构包括均匀分散设置的多个凹槽；或者，所述中间凹槽结构包括网状凹槽；或者，所述中间凹槽结构包括同心设置的多个圆环凹槽；
    所述边缘凹槽结构为封闭圆环状凹槽。
  7. 根据权利要求1-6任一项所述的单光子雪崩二极管，其特征在于，
    所述第三掺杂区包括衬底以及外延层；所述外延层相对于所述衬底靠近所述第二掺杂区；所述陷光结构设置于所述衬底位于入光侧的表面；
    或者，所述第三掺杂区包括埋层以及外延层；所述外延层相对于所述埋层靠近所述第二掺杂区；所述单光子雪崩二极管还包括设置在所述埋层背离所述外延层一侧的减反膜；所述陷光结构设置于所述减反膜位于入光侧的表面。
  8. 根据权利要求1-7任一项所述的单光子雪崩二极管，其特征在于，
    所述单光子雪崩二极管还包括微透镜，所述微透镜设置于所述陷光结构的入光侧。
  9. 根据权利要求8所述的单光子雪崩二极管，其特征在于，
    所述单光子雪崩二极管还包括设置在所述微透镜靠近所述陷光结构一侧的焦距调节层；且所述焦距调节层与所述微透镜为一体结构。
  10. 根据权利要求8或9所述的单光子雪崩二极管，其特征在于，
    所述单光子雪崩二极管还包括吸光层；
    所述吸光层位于所述微透镜朝向所述陷光结构的一侧，且所述吸光层位于所述微透镜 的边缘区域。
  11. 根据权利要求1-10任一项所述的单光子雪崩二极管，其特征在于，
    所述单光子雪崩二极管还包括：绝缘介质层和反射层；
    所述绝缘介质层设置于所述半导体光电转换结构背离入光侧的表面；
    所述反射层设置于所述绝缘介质层背离所述半导体光电转换结构一侧的表面，且所述反射层与所述第二掺杂区相对设置。
  12. 根据权利要求1-11任一项所述的单光子雪崩二极管，其特征在于，
    所述单光子雪崩二极管还包括位于所述半导体光电转换结构四周的隔离深槽；
    所述隔离深槽内部填充有金属。
  13. 一种图像传感器，其特征在于，包括如权利要求1-12任一项所述的单光子雪崩二极管。
  14. 一种电子设备，其特征在于，包括如权利要求1-12任一项所述的单光子雪崩二极管。
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CN109659377A (zh) * 2018-12-13 2019-04-19 深圳市灵明光子科技有限公司 单光子雪崩二极管及制作方法、探测器阵列、图像传感器
CN109659374A (zh) * 2018-11-12 2019-04-19 深圳市灵明光子科技有限公司 光电探测器、光电探测器的制备方法、光电探测器阵列和光电探测终端

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109659374A (zh) * 2018-11-12 2019-04-19 深圳市灵明光子科技有限公司 光电探测器、光电探测器的制备方法、光电探测器阵列和光电探测终端
CN109659377A (zh) * 2018-12-13 2019-04-19 深圳市灵明光子科技有限公司 单光子雪崩二极管及制作方法、探测器阵列、图像传感器

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