WO2022073363A1 - 增强型spi控制器以及操作spi控制器的方法 - Google Patents

增强型spi控制器以及操作spi控制器的方法 Download PDF

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Publication number
WO2022073363A1
WO2022073363A1 PCT/CN2021/103232 CN2021103232W WO2022073363A1 WO 2022073363 A1 WO2022073363 A1 WO 2022073363A1 CN 2021103232 W CN2021103232 W CN 2021103232W WO 2022073363 A1 WO2022073363 A1 WO 2022073363A1
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Prior art keywords
spi
controller
configuration
state
dma
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PCT/CN2021/103232
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English (en)
French (fr)
Inventor
吴承恩
多姆堡耶伦
萧旭峯
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乐鑫信息科技（上海）股份有限公司
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Priority to US18/031,129 priority Critical patent/US20230385226A1/en
Publication of WO2022073363A1 publication Critical patent/WO2022073363A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • G06F2213/2804—Systems and methods for controlling the DMA frequency on an access bus

Definitions

  • the invention belongs to the field of SoC integrated circuit design, and in particular relates to an SPI controller and a method for operating the SPI controller.
  • SPI Serial Peripheral Interface, Serial Peripheral Interface
  • the traditional SPI interface includes 4 signal lines: SS (Slave Select, slave select line), SCK (SPI Clock, SPI clock line), MOSI (Master Output/Slave Input, master output slave input line) and MISO (Master output slave input line) Input/Slave Output, master input slave output line).
  • SPI interface technology people put forward higher and higher requirements for the data reliability and throughput rate of the SPI interface.
  • the transmission speed of the mainstream SPI memory exceeds 100MB/s.
  • the speed of the parallel 8-channel flash memory of Zhaoyi Innovation Company has reached 200MB/s.
  • Multi-data channel, high-speed, high-reliability SPI communication enables SoC (System on Chip, system-on-chip) chips to quickly access external memory. In this way, the memory size inside the SoC chip can be reduced, the area and power consumption of the SoC chip can be reduced, and the performance of the embedded system can be greatly improved.
  • SoC System on Chip, system-on-chip
  • Chinese Patent Application Publication No. CN101819560B proposes a method and device for executing a program in an SPI interface memory, which adopts a state machine including 6 working states to realize compatibility with various types of single, dual, and quad-channel multi-channel SPI interface memory instructions. .
  • This solution is limited to SPI interface memory, does not involve compatibility with more types of SPI interface devices, and does not consider the optimization of SPI transmission continuity.
  • Chinese Patent Application Publication No. CN103064805A proposes a method in which the SS is controlled by the SPI host controller and the CPU can optionally read and receive buffered data, but this cannot meet the CPU's requirements for the throughput rate of the SPI interface.
  • This solution fails to take into account and solve the flexible configuration of the SPI controller, the compatibility and the co-optimization of the SPI transmission continuity.
  • Chinese Patent No. CN104809094B proposes a scheme of buffering the input and adding delay to the output, but it is mainly aimed at the situation of one data channel, such as MOSI or MISO. This solution also fails to take into account and solve the flexible configuration of the SPI controller, the compatibility and the co-optimization of the SPI transmission continuity.
  • an SPI controller and a method of operation thereof which can provide at least one or more of the following desired benefits: (1) provide a more flexible configuration for the SPI controller, further increase the SPI controller's Compatibility; (2) Improve the continuity of SPI transmission and the speed of multiple SPI transmissions; and (3) Consider and solve the flexible configuration of the SPI controller, compatibility and co-optimization of SPI transmission continuity.
  • the inventor also noticed that, in a scenario, when an SPI controller according to the prior art is used in an embedded device (such as a microcontroller MCU) for continuous transmission, the CPU on the one hand has to perform two consecutive SPI Entering the "idle" state between transfers, on the other hand, the contents of the entire register group in the SPI controller have to be updated, so as to avoid the confusion of the current SPI transfer state caused by the remaining values in the register group used for the last SPI transfer. Updating or resetting the entire register set by the CPU further places an additional burden on the CPU and is not conducive to the continuity of the transfer.
  • the register sets of multiple modules (not limited to the SPI controller) need to be updated in an embedded device to configure the function of each module or modify its state
  • the prior art also needs to occupy CPU resources to update
  • the register bank of each module is also required to be able to update the register bank of multiple modules conveniently, reliably and in batches.
  • a SPI controller comprising: an SPI clock signal generator, which is configured to generate an SPI clock signal; a register group, which is configured to save the SPI of the SPI controller Working configuration; a plurality of SPI pins, which are configured to be connected to one or more SPI peripherals; and an input and output controller, which is configured to execute the SPI controller according to the SPI clock signal and the SPI working configuration Data input or output with the SPI peripherals; an SPI state machine configured to control the working state of the SPI controller; wherein the SPI controller is electrically coupled to a device located outside the SPI controller through a bus CPU, DMA controller, and system memory; and the I/O controller is further configured to receive an updated SPI working configuration from the DMA controller between two consecutive SPI transfers and send the updated SPI working configuration updated into the register set.
  • the SPI controller also includes one or more of the following components: a SPI clock mode control module, which is configured to adjust the polarity and phase of the output clock signal; an input and output timing adjustment module, which is configured to adjust The timing of SPI input and output; the SPI cache, which is used to cache the data that the SPI controller interacts with the SPI peripheral under the control of the CPU; and the interrupt control module, which is used for the SPI controller to generate the corresponding data after completing the specified transmission. interrupt, and transmit the interrupt to the CPU through the bus.
  • a SPI clock mode control module which is configured to adjust the polarity and phase of the output clock signal
  • an input and output timing adjustment module which is configured to adjust The timing of SPI input and output
  • the SPI cache which is used to cache the data that the SPI controller interacts with the SPI peripheral under the control of the CPU
  • the interrupt control module which is used for the SPI controller to generate the corresponding data after completing the specified transmission. interrupt, and transmit the interrupt to the CPU through the bus.
  • the multiple SPI pins include one or more SPI chip select pins, one or more SPI clock pins, and one or more SPI input and output pins.
  • the plurality of SPI pins further include SPI command/data signal pins, SPI frame frequency signal pins, SPI line frequency signal pins, and SPI display valid signal pins.
  • the SPI controller is arranged in an embedded device, and the bus is an on-chip bus.
  • a method of operating an SPI controller that is electrically coupled to a CPU and a DMA controller via a bus, and that is electrically coupled to one or more SPI peripherals via a plurality of SPI pins coupling, wherein the SPI controller includes a register set and is configured to be able to operate in a CPU control mode or a DMA control mode, the method comprising: S1) determining a connection with each of the one or more SPI peripherals Corresponding one or more SPI work configuration; S2) create SPI transmission plan, and described SPI transmission plan comprises multiple SPI transmissions carried out to described one or more SPI peripherals, the execution sequence of described multiple SPI transmissions and The SPI operation configuration corresponding to each SPI transmission in the multiple SPI transmissions, wherein the SPI controller performs each SPI transmission according to the corresponding SPI operation configuration; and S3) under the control of the DMA controller Execute the set SPI transmission plan, wherein the multiple SPI transmissions are performed according to the execution order
  • the SPI controller is operated according to an SPI state machine, and the SPI state machine is configured to include the following states cyclically cycled in sequence: "Idle” "state, used to represent that the SPI controller is in a non-working state; “configured” state, used by the I/O controller to receive the SPI working configuration from the DMA controller and update the SPI working configuration to the register In the group; the "ready” state is used to control the chip select setup time of the SPI; the "command” state is used for the SPI controller to send the SPI command and control the number of clock cycles that the SPI command lasts; the "address” state is used for The SPI controller sends the SPI address and controls the number of clock cycles that the SPI address lasts; the "waiting" state is used by the SPI controller to control the number of clock cycles waiting to transmit SPI valid data according to the requirements of the SPI slave device; the "output” state ,
  • each working state in the SPI state machine is configured to have a respective SPI working configuration.
  • the SPI controller and the method of operating the SPI controller according to the present invention preferably, when the SPI controller is configured to operate in a CPU control mode, other states except the "idle" state are configured to be able to be jumped and when the SPI controller is operating in DMA control mode, states other than the "idle” state are configured to be able to be skipped, and the "idle” state is configured to be able to be skipped directly from the "idle” state Complete" state to enter the "Configure” state.
  • the SPI working configuration includes a combination of one or more of the following modes: 1/2/4/8 data channels mode, SPI clock mode, SDR/DDR data sampling mode, full-duplex/half-duplex communication mode.
  • a DMA configuration linked list including one or more configuration nodes is provided, wherein each configuration node corresponds to an SPI transfer and includes a An SPI work configuration is linked to the transmission data linked list of this SPI transmission, the transmission data linked list is linked to the next configuration node, and the information of the SPI work configuration is stored in an area in the DMA configuration buffer; and in a SPI After the transmission is completed, modifying the current SPI working configuration to the SPI working configuration corresponding to the next SPI transmission by the DMA controller includes: from an area of the configuration node corresponding to the next SPI transmission in the DMA configuration buffer, read Get the SPI working configuration corresponding to the next SPI transmission, and write the SPI working configuration into the register group.
  • this SPI transmission includes the "output" state
  • the configuration node is linked to the sending data linked list of this SPI transmission, and the sending data linked list is linked to the next configuration node; otherwise, the configuration node directly Link to the next configuration node.
  • the information of the SPI working configuration includes the values of one or more registers corresponding to the SPI working configuration.
  • the information of the SPI working configuration includes the value of one or more registers corresponding to the SPI working configuration of the current configuration node and the value of one or more registers corresponding to the SPI working configuration of the previous configuration node in the DMA configuration linked list. difference between.
  • each bit in one or more bits in a specified position in an area in the DMA configuration buffer corresponds to a register in one or more registers corresponding to the SPI working configuration of the currently configured node, indicating that Whether the value of the register has changed compared with the SPI working configuration of the last configuration node
  • the method preferably further includes: when the SPI working configuration is written into the register group, only the SPI of the last configuration node is updated. The value of the register changed compared to the working configuration.
  • a plurality of bits at specified positions in an area in the DMA configuration buffer are set as error check numbers, and an error check reference number is provided inside the SPI controller; and only when the error
  • the SPI work corresponding to the next SPI transfer is read from an area in the DMA configuration buffer of the configuration node corresponding to the next SPI transfer only when the check number and the error check reference number conform to the pre-specified relationship. configuration, and write the SPI working configuration into the register group.
  • the SPI peripheral is an LCD
  • the following steps are performed: LCD output data is provided, and the LCD output data includes a valid data area and an upper blank area, a lower blank area, a front blank area and a rear blank area; configure the SPI state machine to enable the "configure” state in the front blank area, enable the "output” state in the valid data area, in the upper blank area, the lower blank area, and the rear blank area Enable any state except “output” and "idle” in "configure” state; load SPI working configuration in "configure” state; output one line of LCD output data at a time in "output” state.
  • a method for updating a register comprising the steps of: providing one or more bitmap registers; providing one or more target registers; establishing a register in the one or more bitmap registers A mapping between each bit and the corresponding target content block in the one or more target registers; providing a register update instruction, the register update instruction includes: one or more flag bits at specified positions, wherein each flag A bit corresponds to a bit in the one or more bitmap registers, indicating whether the target content block corresponding to the bit needs to be updated, wherein for each target content block indicated by the bit that needs to be updated, the The register update instruction also includes the new content of the target content block or the source of the new content; writing the one or more flag bits in the register update instruction into the one or more bitmap registers; and by updating the controller executes the register update instruction to update the target block of content in the one or more target registers according to the bits in the one or more bitmap registers, wherein only the update needs to be updated as indicated by the bits
  • the step of establishing the mapping between each bit in the one or more bitmap registers and the corresponding target content block in the one or more target registers includes: establishing the each bit A direct correspondence with corresponding target content blocks in the one or more target registers.
  • the size of the target content block is fixed, wherein establishing a direct correspondence between the each bit and the corresponding target content block in the one or more target registers includes establishing the each bit. Corresponding relationship with the start address of the corresponding target content block in the one or more target registers.
  • each address mapping register includes one or more groups of content block address information; wherein each bit in the one or more bit mapping registers is established to be associated with all the address mapping registers.
  • the step of mapping between the corresponding target content blocks in the one or more target registers includes: establishing each bit in the one or more bitmap registers and a bit in the one or more address map registers. A correspondence between a set of content block address information; and establishing a correspondence between the set of content block address information in the one or more address mapping registers and a corresponding target content block in the one or more target registers A corresponding relationship, wherein the corresponding target content block is located according to the content block address information.
  • the content block address information includes a content block start address and a content block size.
  • the content block address information includes a content block start address and a content block end address.
  • the step of executing the register update instruction by the update controller according to the bits in the one or more bitmap registers to update the target content block in the one or more target registers includes: each bit in the one or more bitmap registers, according to the mapping, locate the target content block corresponding to the bit; and if the bit indicates whether the target content block corresponding to the bit needs to be updated , the target content block is updated with the new content of the target content block.
  • the one or more flag bits are located in the header of the register update instruction.
  • the source of the new content includes one or more of memory, registers, and flash memory.
  • the update controller is a module in an embedded device.
  • the SPI controller and the method for operating the SPI controller according to the present invention can improve the throughput rate of the SPI interface, expand the versatility of the SPI controller, improve the utilization rate of the CPU, and improve the performance of the SoC system.
  • the throughput rate of the SPI interface can be greatly improved, the versatility of the SPI controller can be expanded, and the utilization rate of the CPU can be improved, thereby significantly improving the performance of the SoC system.
  • the SPI controller can reconfigure the SPI controller in the "configured" state of each segment transfer in the DMA-controlled segmented configuration transfer mode (herein referred to as "DMA control mode"). Therefore, the operation modes of each segment configuration transmission are independent of each other, and a flexible and powerful continuous transmission mode is formed.
  • the DMA segment configuration transfer only needs to be configured once by the CPU, and multiple SPI transfers can be completed.
  • the register group can be updated quickly and reliably in the embedded device, the update of the register group occupies as little or no CPU resources as possible, and the register groups of multiple modules can be conveniently updated in batches.
  • FIG. 1 schematically shows a structural block diagram of an SPI controller according to an embodiment of the present invention.
  • FIG. 2 schematically shows a detailed structural block diagram of an SPI controller according to an embodiment of the present invention.
  • FIG. 3 schematically shows a finite state machine jump diagram of an SPI controller according to the present invention.
  • FIG. 4 schematically shows a structural block diagram of an SPI controller accessing a flash memory (Flash), SRAM, and LCD in a time-sharing manner according to the present invention.
  • FIG. 5 schematically shows a schematic flow chart of a method of operating an SPI controller according to an embodiment of the present invention.
  • FIG. 6 schematically shows a flow chart of SPI transmission according to an embodiment of the present invention.
  • FIG. 7 schematically shows a flow chart of SPI segment configuration transmission according to an embodiment of the present invention.
  • Figure 8 schematically shows a timing diagram of a DMA controlled segment configuration transfer according to the present invention.
  • FIG. 9 schematically shows the frame format used by the SPI controller to access the parallel 8-bit RGB format LCD according to the present invention.
  • FIG. 10 schematically shows a timing diagram of an SPI controller accessing a parallel 8-bit RGB format LCD according to the present invention.
  • FIG. 11 schematically shows a flow chart of an embodiment of a method for updating a register according to the present invention.
  • Figure 12 schematically shows a block diagram of the mapping in one embodiment of the method of updating a register according to the present invention.
  • FIG. 13 schematically shows a block diagram of mapping in another embodiment of the method for updating a register according to the present invention.
  • an SPI controller 100 including: an SPI clock signal generator 110, which is configured to generate an SPI clock signal SPI_CLK; a register group 114, which is configured to save the SPI an SPI operating configuration of the controller 100; a plurality of SPI pins 118 configured to connect to one or more SPI peripherals (not shown); and an input output controller 116 configured to operate according to the SPI clock signal and The SPI working configuration performs data input or output between the SPI controller 110 and the SPI peripherals; the SPI state machine 112 is configured to control the working state of the SPI controller 100; wherein the SPI The controller 100 is electrically coupled to the CPU 104, the DMA controller 106 and the system memory 102 located outside the SPI controller through the bus 108; and the I/O controller 116 is also configured to, between two consecutive SPI transfers, An updated SPI operating configuration is received from the DMA controller 106 and updated into the register bank 114 .
  • an SPI controller 200 which mainly includes an SPI state machine 212, an SPI clock signal generator 210, an SPI clock mode control module 220, a register set 214, I/O controller 216 , I/O timing adjustment module 222 , SPI cache 226 and interrupt control module 224 .
  • the SPI controller 200 is connected to the CPU 204, the DMA controller 206 and the system memory 202 through the bus 208.
  • the specific connection relationship between the components may be: the CPU 204 is connected to the SPI state machine 212, the register group 214, the interrupt control module 224 and the SPI cache 226 through the bus 208; the SPI clock signal generator 210 is connected to the bus 208.
  • the SPI clock mode control module 220, the register group 214 are connected to the SPI state machine 212; the SPI clock mode control module 220 is connected to the register group 214, and outputs the SPI clock signal SPI_CLK through the input and output timing adjustment module 222;
  • the frequency clock signal HCLK is transmitted to the input and output timing adjustment module 222;
  • the SPI state machine 212 is connected with the register group 214, controlled by the register group 214, and is connected with the SPI clock signal generator 210, the input and output controller 216, and the interrupt control module 224 at the same time, Control the state of the transmission clock and data on the SPI interface, and generate corresponding interrupts; the interrupt control module 224 generates interrupts under the control of the SPI state machine, and transmits it to the CPU 204 through the bus 208; the register group 214 and the SPI state machine 212, SPI
  • the SPI controller of the present invention includes the following SPI pins (represented by reference numerals 118 and 218 in FIGS. 1 and 2, respectively) that constitute the SPI interface: SPI chip select pin SPI_CS (corresponding to the slave select line SS), SPI clock pin SPI_CLK (corresponding to SPI clock line SCK), and multiple SPI input and output pins SPI_IO.
  • SPI chip select pin SPI_CS corresponding to the slave select line SS
  • SPI clock pin SPI_CLK corresponding to SPI clock line SCK
  • multiple SPI input and output pins SPI_IO multiple SPI input and output pins
  • SPI_IO[7:0] eight SPI input and output pins SPI_IO[7:0] are shown, wherein SPI_IO[0] corresponds to the master output slave input line MOSI, and SPI_IO[1] corresponds to the master input slave
  • the output line MISO is added, and SPI_IO[7:2] is added to enable the SPI controller of the present invention to support multi-data channel transmission such as 2/4/8 at the hardware level.
  • the SPI controller of the present invention further includes the following SPI pins: SPI command/data signal pin SPI_CD, SPI frame frequency signal pin SPI_VSYNC, SPI horizontal frequency signal pin SPI_HSYNC and SPI display valid signal pin Pin SPI_DE, in order to expand the compatibility of the SPI controller of the present invention at the hardware level, so that it can support LCD (Liquid Crystal Display, liquid crystal display) interface peripherals and continuous LCD data transmission, such as supporting Motorola 6800, Intel 8080 and/or LCD interface peripheral in parallel 8-bit RGB mode.
  • LCD Liquid Crystal Display, liquid crystal display
  • bus shown in FIG. 1 and FIG. 2 may be an on-chip bus, including but not limited to an AMBA (Advanced Microcontroller Bus Architecture) bus. It should also be understood that the SPI controller according to the present invention may be arranged in various embedded devices.
  • AMBA Advanced Microcontroller Bus Architecture
  • the SPI state machine 112 or 212 controls the states included in the operation of the SPI controller 100 or 200 , the clock cycles that each state lasts, and the jumping direction of each state.
  • the operation of the SPI state machine will be described in detail below with reference to FIG. 3 .
  • the SPI clock signal generator 210 includes a prescaler and a counter module, and is used to generate a serial output SPI with variable frequency according to the prescaler coefficient and the count frequency division coefficient configured by the register. Clock signal SPI_CLK. It should be understood that the implementation of the present invention is not limited thereto, and the SPI clock signal generator 210 may be implemented to include different components to achieve the same or similar functions.
  • the SPI clock mode control module 220 is configured to adjust the polarity and phase of the output clock signal SPI_CLK, so as to be compatible with the four timing types specified in the SPI protocol, that is, depending on CPOL (Clock Polarity, clock polarity) and CPHA (Clock Phase, four different data transfer timings combined with the clock phase).
  • Register set 114 or 214 is used to configure the SPI controller in different modes of operation to perform various functions.
  • the input/output controller 116 or 216 is used for inputting or outputting corresponding data according to the state of the SPI state machine. Further, the I/O controller 116 or 216 is further configured to receive an updated SPI working configuration from the DMA controller 106 or 206 and update the updated SPI working configuration into the register bank 114 or 214 between two consecutive SPI transfers . In other words, the I/O controller 116 or 216 can update the SPI operating configuration in the register set 114 or 214 without CPU intervention.
  • the input and output timing adjustment module 222 is used to adjust the timing of the SPI interface, for example, by adding a delay to the input or output data of each channel, respectively, to adjust the sampling or transmission timing of the data, so as to ensure the correct transmission of the data.
  • the SPI controller may be configured to be able to operate in a CPU control mode or a DMA control mode.
  • the SPI cache 226 is used to store data for the SPI controller to interact with the SPI peripherals in the CPU control mode.
  • the CPU 204 configures the register group 214 of the SPI controller through the bus, and at the same time writes the data to be sent into the SPI buffer 226; Data is sent to the corresponding SPI peripheral (not shown).
  • the CPU 204 In the write data operation controlled by the CPU, the CPU 204 first configures the register group 214 of the SPI controller 200; the SPI controller 200 will store the received data in the SPI cache 226 during the running process; the CPU 204 can wait for the SPI transmission after the end of the transfer. The data in the SPI buffer 226 is read over the bus.
  • the interrupt control module 224 is used for the SPI controller 200 to generate a corresponding interrupt after completing the specified transmission, and to transmit the interrupt to the CPU 204 through the bus 208.
  • the DMA controller 206 can realize the data transmission between the SPI peripheral device and the system memory 202 through the SPI controller 200 under the configuration of the CPU 204.
  • the DMA can be configured by the CPU only once to complete multiple SPI transfers, especially multiple consecutive SPI transfers.
  • the CPU 204 controls the SPI controller 200 and the DMA controller 206 via the bus 208.
  • FIG. 3 schematically shows a state machine state transition diagram 300 of an SPI controller according to the present invention.
  • the functionality of the SPI controller is achieved by configuring the SPI state machine and register set.
  • the state machine of the SPI controller jumps in the direction of the arrow in Figure 3, and except for the "idle" state, other states can be skipped directly. Users can choose to execute a specific state according to their needs, so as to achieve different functions.
  • the various states of the SPI state machine according to the present invention are detailed below.
  • states other than the "idle” state are configured to be able to be skipped; and when the SPI controller is configured to operate in a DMA mode
  • states other than the "idle” state are configured to be able to be skipped, and the "idle” state is configured to be able to be skipped to go directly from the "done" state to the "configured" state.
  • the "IDLE" state 302 is used to indicate that the SPI controller is in an inactive state.
  • the SPI clock pin SPI_CLK can always be at a low level or a high level according to the four clock modes specified by the SPI protocol; the SPI chip select pin SPI_CS is always at a high level, and the SPI command /
  • the data signal pin SPI_CD, the SPI frame frequency signal pin SPI_VSYNC, the SPI horizontal frequency signal pin SPI_HSYNC, the SPI display valid signal pin SPI_DE, and the SPI input and output pins SPI_IO[7:0] are always at a configurable fixed level.
  • the "Configuration (CONF)" state 304 is used for the SPI controller to take out the corresponding data from the DMA transmit buffer (TX_buf) in the DMA-controlled segmented configuration transmission mode, and configure it into the register group through the input and output controller.
  • the implementation can reconfigure the register bank of the SPI controller before each segment configuration transfer. Therefore, the specific mode of each segment configuration transfer can be different, which is equivalent to a DMA-controlled segment configuration transfer including multiple different SPI single transfers, and can access different SPI peripherals in a time-sharing manner.
  • the "preparation (PREP)" state 306 is used to control the chip selection setup time of the SPI to meet the chip selection setup time sequence requirements of each SPI peripheral.
  • the ready state is also used by the SPI controller to prepare commands, addresses and data to be sent.
  • the "command (CMD)" state 308 is used by the SPI controller to send SPI commands and controls the number of clock cycles that the SPI commands last.
  • the "Address (ADDR)" state 310 is used by the SPI controller to send the SPI address and controls the number of clock cycles for which the SPI address lasts.
  • the "waiting (DUMMY)" state 312 is used by the SPI controller to control the number of clock cycles waiting to transmit SPI valid data according to the requirements of the SPI slave device.
  • the "OUT (DOUT)" state 314 is used by the SPI controller to control the number of clock cycles to output valid data.
  • the transmitted data comes from the SPI cache; in DMA control mode, the transmitted data comes from the memory configured with the DMA configuration linked list or the DMA TX linked list.
  • the "IN (DIN)" state 316 is used by the SPI controller to control the number of clock cycles to input valid data.
  • the input data is stored in the SPI cache; in the DMA control mode, the input data is stored in the memory configured by the DMA transmit data linked list (RX linked list).
  • the "DONE" state 318 is used to control the chip select hold time of the SPI to meet the chip select hold time sequence requirements of each SPI peripheral.
  • the next state of the SPI state machine is the "idle" state.
  • the DMA-controlled segmented configuration transfer mode if the next state that controls the SPI state machine to jump to is the "configured" state, the DMA-controlled segmented configuration transfer continues; if the SPI state machine is controlled to jump to the next state In the "idle” state, the DMA-controlled segment configuration transfer ends, and a corresponding interrupt is generated.
  • the SPI controller can independently control 1/2 of the SPI interface in the states of "command", “address”, “output” and “input” in a single SPI transmission /4/8 data channel mode, can independently control SDR (Single Data Rate, single data sampling) and DDR (Double Data) of SPI_CLK of SPI clock signal in "command", “address”, “output” and “input” states Rate, double data sampling) data sampling mode, supports full-duplex and half-duplex transmission, supports CPU-controlled data transmission and DMA-controlled data transmission, so as to meet most 1/2/4/8 multi-data channel SPI
  • the timing requirements of the peripheral interface greatly improve the throughput of the SPI interface and greatly expand the versatility of the SPI controller.
  • the delay value of each data channel can be finely adjusted, thereby ensuring the correctness of data transmission and improving the reliability of SPI data transmission.
  • each working state in the SPI state machine may be configured to have a respective SPI working configuration.
  • the SPI operating configuration includes one or a combination of the following modes: 1/2/4/8 data channel mode, SPI clock mode, SDR/DDR data sampling mode, full-duplex/half-duplex communication mode.
  • each state of the state machine can be independently enabled or disabled, and the clock cycle of each state can also be independently configured.
  • the state machine can be controlled by the enabled states and their clock cycle lengths.
  • the SPI controller can be configured to be in different modes of operation, thereby implementing various functions.
  • the current state of the SPI state machine, the working configuration of the SPI controller, and the properties of the SPI controller can be reflected in the register values contained in the registers in the register group.
  • the current state of the SPI state machine, the working configuration of the SPI controller, the properties of the SPI controller, and the like can be changed by modifying the register values in the corresponding registers.
  • the register group in the SPI controller according to the present invention may be configured to include but not limited to the registers shown in Table 1 below.
  • register values in the registers may be read-only, read-write (R/W), or variable (ie, configurable to be read-only or readable and writable).
  • register values of the registers in the SPI controller according to the present invention may be configured to include, but not limited to, the register values shown in Table 2 below.
  • the SPI controller lists 1 in the "command", "address”, “wait”, “input” and “output” states, respectively, in Tables 3 and 4 below.
  • /2/4/8 data channel mode corresponding value and number of continuous clock cycles control the register values contained in the registers in the register bank. The control of each state is independent of each other, so almost any 1/2/4/8 data channel mode SPI transfer can be realized.
  • "1/2/4/8 data lane mode” refers to a mode in which 1, 2, 4 or 8 data lanes are used for SPI transfers.
  • each data channel corresponds to an SPI input and output pin, and each data channel transmits 1 bit of data at a time.
  • Table 3 Command configuration table for 1 data channel/2 data channel mode
  • the working configuration corresponding to the "command", “address”, “waiting”, "input” and “output” states of an SPI controller according to the present invention may be controlled as follows.
  • the command value sent by the SPI controller is configured in SPI_USR_COMMAND_VALUE, and the number of continuous clock cycles is configured in SPI_USR_COMMAND_BITLEN; when the command value is sent in 8-data channel mode, the SPI_FCMD_OCT bit is set, and the SPI_FCMD_QUAD and SPI_FCMD_DUAL bits are cleared.
  • the "Address” state of the SPI controller is controlled by the register value in the same row as "Address” in Tables 3 and 4.
  • Set the SPI_USR_ADDR bit to enable the "address” state the SPI controller will include the "address” state and will send the configured SPI address; clear the SPI_USR_ADDR bit, the SPI controller will skip the "address” state and will not send the SPI address.
  • the SPI_USR_ADDR bit When the SPI_USR_ADDR bit is set, the address value sent by the SPI controller is configured in SPI_USR_COMMAND_VALUE, and the number of continuous clock cycles is configured in SPI_USR_COMMAND_BITLEN; when the address value is sent in 8 data channel mode, the SPI_FADDR_OCT bit is set, and the SPI_FADDR_QUAD and SPI_FADDR_DUAL bits are cleared.
  • the "waiting" state of the SPI controller is controlled by the register values in the same row as “waiting” in Tables 3 and 4. Set the SPI_USR_DUMMY bit to enable the "wait” state, and the SPI controller will remain in the "wait” state for SPI_USR_DUMMY_CYCLELEN SPI_CLK clock cycles; clear the SPI_USR_DUMMY bit, and the SPI controller will skip the "wait” state.
  • the "output" state of the SPI controller is controlled by the register value in the same row as “output” in Tables 3 and 4.
  • Set the SPI_USR_MOSI bit to enable the "output” state and the SPI controller will include the "output” state; clear the SPI_USR_MOSI bit, and the SPI controller will skip the "output” state and will not send SPI output data.
  • the SPI_USR_MOSI bit is set, the data in the SPI buffer will be sent in the CPU control mode. In the DMA control mode, the memory data configured by the DMA configuration linked list or the DMA TX linked list will be sent.
  • the number of clock cycles for which data is sent is configured in SPI_USR_MOSI_DBITLEN ;When sending data in 8 data channel mode, set SPI_FWRITE_OCT bit, clear SPI_FWRITE_QUAD and SPI_FWRITE_DUAL bits; when sending data in 4 data channel mode, set SPI_FWRITE_QUAD bit, clear SPI_FWRITE_OCT and SPI_FWRITE_DUAL bits; send data in 2 data channel mode When the SPI_FWRITE_DUAL bit is set, the SPI_FWRITE_OCT and SPI_FWRITE_QUAD bits are cleared; when sending data in 1 data channel mode, the SPI_FWRITE_OCT, SPI_FWRITE_QUAD and SPI_FWRITE_DUAL bits are cleared.
  • the "input” state of the SPI controller is controlled by the register value in the same row as “input” in Tables 3 and 4. Set the SPI_USR_MISO bit to enable the "input” state, and the SPI controller will include the “input” state; clear the SPI_USR_MISO bit, and the SPI controller will skip the "input” state and will not receive SPI input data.
  • the received data When the SPI_USR_MISO bit is set, the received data will be stored in the SPI buffer in the CPU control mode, and in the DMA control mode, the received data will be stored in the memory configured by the DMA RX linked list, and the number of clock cycles for which the received data lasts is configured in In SPI_USR_MISO_DBITLEN; when receiving data in 8 data channel mode, set SPI_FREAD_OCT bit, clear SPI_FREAD_QUAD and SPI_FREAD_DUAL bits; when receiving data in 4 data channel mode, set SPI_FREAD_QUAD bit, clear SPI_FREAD_OCT and SPI_FREAD_DUAL bits; in 2 data channel mode When receiving data, set the SPI_FREAD_DUAL bit and clear the SPI_FREAD_OCT and SPI_FREAD_QUAD bits; when receiving data in 1 data channel mode, clear the SPI_FREAD_OCT, SPI_FREAD_QUAD and SPI_FREAD_DUAL bits.
  • the SPI controller according to the present invention can implement any feasible SPI transmission in 1/2/4/8 data channel modes.
  • the SPI controller 402 according to the present invention can access the flash memory 404, the SRAM 406 and the 8-bit LCD in Intel 8080 mode as shown in FIG. 4 by time-sharing.
  • other 1/2/4/8 channel SPI peripherals can be accessed.
  • a new SPI communication data flow control mechanism is also implemented: segmented configuration transmission controlled by DMA.
  • the SPI controller according to the present invention supports multiple segment configuration transfers controlled by DMA, and the SPI controller can reconfigure the SPI registers through the DMA controller in the "configured" state before each SPI transfer.
  • the following functions may be implemented.
  • Each SPI transmission can be configured as full-duplex communication or half-duplex communication, SDR data sampling mode or DDR data sampling mode.
  • Each half-duplex communication can independently configure the 1/2/4/8 data channel mode of the SPI interface and the data delay of each channel in the "command", "address”, “output” and “input” states .
  • the SPI controller according to the present invention includes a plurality of CS chip select signals, and can independently control the working conditions of each CS in the multiple segment configuration transmission controlled by DMA, so it can support time-sharing access in different SPI transmission modes Functions of different SPI peripherals.
  • the data length of each SPI transmission is determined by the configured DMA controller, and can be independently configured to any value.
  • FIG. 5 schematically shows a schematic flow chart of a method 500 of operating an SPI controller according to an embodiment of the present invention.
  • an SPI controller is electrically coupled to the CPU and DMA controller through a bus, and to one or more SPI peripherals through a plurality of SPI pins, wherein the SPI controller includes a register set and is configured to be able to use CPU control mode or DMA control mode operation.
  • the SPI controller includes a register set and is configured to be able to use CPU control mode or DMA control mode operation.
  • the method 500 includes: S1) determining one or more SPI working configurations corresponding to each of the one or more SPI peripherals; S2) creating an SPI transmission plan, the SPI The transmission plan includes multiple SPI transmissions performed on the one or more SPI peripherals, the execution sequence of the multiple SPI transmissions, and the SPI working configuration corresponding to each SPI transmission in the multiple SPI transmissions, wherein the The SPI controller executes each SPI transmission according to the corresponding SPI work configuration; and S3) executes the set SPI transmission plan under the control of the DMA controller, wherein the multiple SPIs are executed according to the execution order
  • the current SPI transmission is performed according to the corresponding SPI working configuration, and after one SPI transmission is completed, the DMA controller modifies the current SPI working configuration to the SPI working configuration corresponding to the next SPI transmission.
  • one SPI peripheral may correspond to multiple SPI working configurations
  • multiple SPI transfers in the SPI transfer plan may include SPI transfers for multiple SPI peripherals , and can also include SPI transfers with multiple different SPI operating configurations for the application of one SPI peripheral.
  • FIG. 6 schematically shows a flow chart of SPI transmission according to an embodiment of the present invention.
  • the SPI controller is in an "idle" state.
  • the CPU configures the registers in the register group of the SPI controller.
  • the CPU configures the corresponding transceiving data of the DMA.
  • the SPI controller waits for the SPI slave device to be ready for data transfer.
  • the CPU sets the SPI interrupt enable register and enables SPI transfers.
  • the SPI transfer plan is executed until the corresponding interrupt is triggered.
  • FIG. 7 schematically shows a flow chart of SPI segment configuration transmission according to an embodiment of the present invention.
  • the SPI controller is in an "idle" state.
  • the CPU configures the registers in the register bank of the SPI controller.
  • the SPI controller is in a "configured” state, updating the registers of the SPI.
  • step 714 it is determined whether the register value SPI_USR_COMMAND is 1. If so, determine that the SPI controller is in the "command" state at step 716 and send SPI command data, otherwise jump to step 718 . In step 718, it is judged whether the register value SPI_USR_ADDR is 1, if so, in step 720, it is determined that the SPI controller is in the "address” state, and the SPI address data is sent, otherwise, jump to step 722.
  • step 722 it is judged whether the register value SPI_CS_DUMMY is 1, and if so, in step 724, it is determined that the SPI controller is in a "waiting" state, and no operation is performed, otherwise, jump to step 726.
  • step 726 it is judged whether the register value SPI_USR_MOSI is 1, if so, in step 728, it is determined that the SPI controller is in the "output" state, and the transmission data is output, otherwise, jump to step 730.
  • step 730 it is judged whether the register value SPI_USR_MISO is 1, if so, in step 732, it is determined that the SPI controller is in the "input” state, and the SPI data is received, otherwise, jump to step 734.
  • step 734 it is judged whether SPI_CS_HOLD is 1, and if so, in step 736, it is determined that the SPI controller is in the "done” state, and maintains the set chip select hold time.
  • step 738 it is determined in step 738 whether SPI_USR_NXT_CONT is 1, if so, it is determined that there is a next SPI transfer in the SPI transfer plan, and the process returns to step 708 to execute the next SPI transfer. If not, proceed to step 740, and the execution of the SPI transmission plan is completed.
  • FIG 8 schematically illustrates a timing diagram 800 of a DMA controlled segment configuration transfer in accordance with the present invention.
  • the horizontal axis of the SPI timing diagram 800 is time, and the multi-line chart arranged from top to bottom in the vertical axis direction shows various signals and states of the SPI controller.
  • the SPI_CS line shows the state of the chip select signal.
  • SPI_CS when SPI_CS is pulled low, it indicates that an SPI peripheral is selected, for example, the same or different SPI peripherals are selected at segment 1, segment 2, and segment n, where n is any positive value greater than 2. Integer.
  • the SPI_ST line represents the state of the SPI state machine.
  • segment 1 before segment 1 begins, ie, before time t1, the SPI state machine is in a "configured” state, and the SPI transmission schedule is configured by the CPU. Between time t1 and t2, the SPI state machine is in the "ready” state, which controls the chip select setup time of the SPI. When the CPU enables the SPI transfer at time t2, the transfer of segment 1 begins.
  • segment 1 includes "ready”, “command”, “address”, “waiting”, “output”, “output” and “complete” states, but those skilled in the art will understand that the present invention The implementation is not limited to this. Each SPI transfer of the present invention may include more or less than the states described, or a different number, order and content of states as shown.
  • the I/O controller in the SPI controller may be configured to receive an updated SPI working configuration from the DMA controller and update the updated SPI working configuration into the register set between two consecutive SPI transfers .
  • the update of the register set may be performed in the "configured" state between segment 1 and segment 2, for example.
  • SPI_CLK represents the SPI clock signal to control the beat of each state and the synchronization between various operations of the SPI controller
  • SPI_CD represents the SPI command/data signal
  • SPI_IO[7:0] schematically represents the SPI input
  • the state of the output pins[7:0] the transmission of valid data corresponds to the input and output states, while in the "configured" state, the SPI input and output pins do not carry valid data.
  • a line of Conf_buf/Tx_buf represents a DMA configuration linked list or a DMA transmission linked list (also known as a DMA TX linked list), where the configuration node Conf_buf corresponds to the DMA configuration buffer, which is used to configure the register set of the SPI controller, where the The sending node TX_buf corresponds to the DMA sending buffer, which is used for data sending in the DMA control mode, and configuration state switching.
  • One line of RX_buf represents the DMA receiving linked list, and the receiving node RX_buf corresponds to the DMA input buffer, which is used for data reception in the DMA control mode.
  • the register bank of the SPI controller can be configured through the configuration buffer (Conf_buf) before each segment configuration transfer.
  • a DMA configuration linked list including one or more configuration nodes is provided, wherein each configuration node corresponds to an SPI transfer, and includes an SPI working configuration corresponding to the SPI transfer and is linked to the SPI transfer.
  • this SPI transmission includes the "output" state
  • the configuration node is linked to the sending data linked list of this SPI transmission, and the sending data linked list is linked to the next configuration node; otherwise, the configuration node is directly linked to the next Configure the node.
  • One or more sending nodes linked together form a linked list of sending data.
  • the DMA configuration linked list includes multiple configuration nodes and multiple sending nodes linked together.
  • the DMA configuration linked list may also include one or more configuration nodes and one or more receiving nodes RX_buf1_1, RX_buf1_2, etc. linked together. More generally, the DMA configuration linked list, the DMA transmit linked list and the DMA receive linked list may be implemented in the same or different linked lists without departing from the scope of the present invention.
  • the SPI transmission plan is implemented as a DMA configuration linked list, but the DMA configuration linked list is only an implementation manner of the SPI transmission plan.
  • the SPI transmission plan described herein may be implemented using a data structure different from a linked list, and/or may be stored in a different storage device.
  • the register group in the SPI controller needs to be updated between consecutive multiple SPI transmissions.
  • the above-mentioned SPI working configuration information includes the value of one or more registers corresponding to the SPI working configuration. Therefore, when the SPI working configuration is changed, the value of the one or more registers will be Overall update.
  • the above-mentioned SPI working configuration information includes the value of one or more registers corresponding to the SPI working configuration of the current configuration node and the value of one or more registers corresponding to the SPI working configuration of the previous configuration node in the DMA configuration linked list. or the difference between the values of multiple registers. Further, each bit in the one or more bits at the specified position in an area in the DMA configuration buffer corresponds to one of the one or more registers corresponding to the SPI working configuration of the current configuration node, indicating the same as the above.
  • the method preferably further includes: when writing the SPI working configuration into the register group, only updating the SPI working configuration with the previous configuration node compared to the value of the register that changed.
  • the present invention further provides a solution for updating the contents of the registers in the register group of the SPI controller.
  • Table 5 presents the bit-wise configuration mapping table of the SPI segmented configuration transfer mode register according to one embodiment of the present invention.
  • Table 5 SPI register bitwise configuration mapping table
  • SPI_CMD 14 SPI_HOLD 1 SPI_ADDR 15 SPI_DMA_INT_ENA 2 SPI_CTRL 16 SPI_DMA_INT_RAW 3 SPI_CTRL1 17 SPI_DMA_INT_CLR 4 SPI_CTRL2 18 SPI_DIN_MODE 5 SPI_CLOCK 19 SPI_DIN_NUM 6 SPI_USER 20 SPI_DOUT_MODE 7 SPI_USER1 twenty one SPI_DOUT_NUM 8 SPI_USER2 twenty two SPI_LCD_CTRL 9 SPI_MOSI_DLEN twenty three SPI_LCD_CTRL1 10 SPI_MISO_DLEN twenty four SPI_LCD_CTRL2 11 SPI_MISC 25 SPI_LCD_D_MODE 12 SPI_SLAVE 26 SPI_LCD_D_NUM 13 SPI_FSM - -
  • the first few words (WORD) stored in each configuration buffer are used to determine whether the relevant registers of the SPI controller need to be reset, and these words are called Bitmap value SPI_BIT_MAP_REG.
  • the bitmap values are stored in a configuration buffer.
  • the bitmap values are stored in registers. Registers that store bitmap values may be referred to as "bitmap registers". It should be understood that, in the embodiments of the present invention, the bitmap register may be implemented to store the bitmap value exclusively, and may also be implemented to store other values than the bitmap value.
  • the low-order 27 bits in the first word of the configuration buffer are used as the bit map value to determine whether the 27 registers of the SPI controller need to be reset.
  • the second word, the third word is used as a bitmap value to accommodate the situation of resetting more registers.
  • the "word” may be 32 bits, but the implementation of the present invention is not limited thereto. The invention can also be implemented using words of 32 bits or more or less.
  • the bit map value SPI_BIT_MAP_REG in the configuration buffer of this segment configuration is all 0, and the register of the SPI controller does not need to be reset.
  • Table 6 below gives an example of the bitwise configuration mapping of the SPI registers according to the present invention.
  • the lower 27 bits of the first word of the configuration buffer of a segment configuration are shown in Table 6, and the registers that need to be reset for this segment configuration transfer are SPI_ADDR, SPI_CTRL, SPI_CLOCK, SPI_USER, and SPI_USER1.
  • Table 6 SPI register bitwise configuration mapping table
  • a plurality of bits at specified positions in an area in the DMA configuration buffer are set as error check numbers, and in the DMA configuration buffer
  • the SPI controller internally provides an error check reference number; and only when the error check number and the error check reference number conform to a pre-specified relationship, the DMA configuration buffer of the corresponding configuration node is transferred from the next SPI Read the SPI working configuration corresponding to the next SPI transmission from an area in the area, and write the SPI working configuration into the register group.
  • an error check number is added to the first word of each configuration buffer, hereinafter referred to as the first magic number.
  • the first word of the configuration buffer is used.
  • the upper 5 bits are used as the first magic number.
  • the first magic number can be anywhere in the configuration buffer.
  • the second magic number There is a correct error check reference number inside the SPI controller that cannot be modified by the configuration buffer, hereinafter referred to as the second magic number, it can be specified that the first magic number in the configuration buffer and the second magic number inside the SPI controller must be If the specified relationship is satisfied, the register of the SPI controller can be configured successfully, and the DMA-controlled segmented configuration transfer continues; otherwise, the configuration fails, the DMA-controlled segmented configuration transfer ends, and an interrupt and error flag are given at the same time.
  • the specified relationship satisfied by the two magic numbers can be that the two must be equal, or the CRC check values of the two must be equal, or the bitwise XOR value of the two is 0, or the bitwise XOR value is 0, and so on. It should be understood that the specified relationship between the two magic numbers can be determined according to implementation needs without departing from the scope of the present invention.
  • the SPI controller can configure the transfer mode by segments controlled by DMA, and in different segment configuration transfers, the flash memory, SRAM, and LCD are time-shared. Just configure the relevant registers that need to be modified when accessing the flash memory 404, SRAM 406, and LCD 408 in the configuration buffer before accessing the flash memory 404, SRAM 406, and LCD 408, and ensure that the first magic number in all Conf_buf is correct. .
  • the technical means used for the DMA-controlled segment configuration transmission may include:
  • the segmented SPI transmission is realized by means of DMA, and the type of each SPI transmission can be independently controlled.
  • the segmented configuration transmission controlled by DMA according to the present invention can be used as a handshake mechanism, which can only read and write a large amount of data, and can also access multiple different peripherals in a time-sharing manner.
  • the SPI controller and its operating method in the prior art perform continuous SPI transfers
  • the CPU needs to obtain control first between two SPI transfers, and the SPI state machine must return to the idle state when the SPI state machine returns to the idle state.
  • the CPU can update the register group.
  • the SPI register group is updated in the configuration state, and the configuration state can be directly entered from the completion state, thereby greatly reducing the configuration time and improving the data throughput rate.
  • the SPI controller is always in the working mode (non-idle state) during multiple SPI transmissions, and can flexibly configure the working configuration of each SP transmission.
  • FIG. 9 schematically shows the frame format used by the SPI controller to access the parallel 8-bit RGB format LCD according to the present invention.
  • one frame of LCD output data 900 includes a valid data area 906 and an upper blank area 902 , a lower blank area 910 , a front blank area 904 and a rear blank area 908 .
  • the size of each area is shown in FIG. 9 .
  • the width of one frame of LCD output data 900 is SPI_LCD_HT_WIDTH[11:0], and the height is SPI_LCD_VT_HEIGHT[9:0]; the upper blank area 902
  • the width is the same as the LCD frame 900, and the height is SPI_LCD_VB_FRONT[7:0];
  • the width of the valid data area 906 is SPI_LCD_HA_WIDTH[11:0], and the height is SPI_LCD_VA_HEIGHT[9:0];
  • the width of the left blank area 904 is SPI_LCD_HB_FRONT[10] :0]
  • the height is the same as the height of the valid data area.
  • the size of the right blank area 908 and the lower blank area can be determined simply by subtraction. In this embodiment, symbols such as [11:0] represent the lower 12 bits in a word.
  • FIG. 10 schematically shows a timing diagram 1000 of an SPI controller accessing a parallel 8-bit RGB format LCD in accordance with the present invention.
  • the horizontal axis of the timing diagram 1000 represents time, and the multi-line graph arranged vertically represents the time relationship between the SPI parameters.
  • SPI_VSYNC represents the frame frequency signal on the SPI frame frequency signal pin
  • SPI_HSYNC represents the horizontal frequency signal on the SPI horizontal frequency signal pin.
  • the rising edge of SPI_VSCNC represents the start of transmission of a new frame of image
  • the rising edge of SPI_HSYNC represents the start of transmission of a line of image data in the image.
  • SPI_DE indicates the display valid signal on the SPI display valid signal pin, and the value is 0 or 1, indicating whether there is a valid signal currently on the SPI input and output pins.
  • SPI_IO[7:0] represents the data signal on the 8 SPI input and output pins.
  • SPI_CLK represents the SPI clock signal.
  • the SPI command/data signal SPI_CD is used to characterize the Command/DATA signal, which can be applied to Motorola 6800 and Intel 8080LCD interfaces).
  • the period of the frame frequency signal or the frame timing SPI_VSYNC represents the duration of one frame
  • the period of the horizontal frequency signal or the horizontal timing SPI_HSYNC represents the duration of one line.
  • the SPI controller first detects the start of a frame through frame timing, and then detects the length of a line through line timing.
  • the SPI state machine is configured to enable the "configure” state in the front blank area, the "output” state in the valid data area, the upper blank area, the lower blank area and the rear blank area Enables any state except “Output” and "Idle”; loads the SPI working configuration in the "Configuration” state; and outputs the LCD output data one row at a time in the "Output” state.
  • the SPI controller according to the present invention can not only access multi-data channel SPI peripherals such as 1/2/4/8, but also support access to the LCD interface peripherals in Motorola 6800/Intel 8080/parallel 8-bit RGB format, thereby further Expand the versatility of SPI controllers.
  • Figure 10 shows the timing diagram of the SPI controller accessing the parallel 8-bit RGB format LCD through the segmented configuration transfer mode controlled by DMA.
  • this transfer mode select the "idle”, “configuration”, “output” and “complete” states, load the DMA configuration buffer Conf_buf in the "configuration” state, and do not modify the registers of the SPI controller in the "configuration” state;
  • In the "output” state one line of LCD RGB data is output at a time.
  • the configuration buffer and the transmit buffer (TX_buf) may be configured in the DMA configuration linked list or the DMA TX linked list in advance.
  • the SPI controller can continuously transmit the entire frame or multi-frame LCD RGB data without the intervention or operation of the CPU.
  • configuration buffer, transmit buffer and input buffer described herein may be areas in the system memory or areas in the memory set in the SPI controller, such as areas in RAM, or alternatively DRAM, SDRAM , area in SDRAM or PSRAM.
  • configuration buffer, send buffer and input buffer are regions in system memory.
  • the SPI controller of the present invention adds SPI_CD, SPI_VSYNC, SPI_HSYNC and SPI_DE signal lines, adds a "configured" state, adds an LCD mode, and increases the SPI_CD, Control logic for the SPI_VSYNC, SPI_HSYNC, and SPI_DE signal lines.
  • FIGS. 8 to 10 illustrate embodiments in which the SPI controller on the SPI master interacts with the SPI slave, the principles of the present invention can also be applied to the SPI controller on the SPI slave.
  • FIG. 11 schematically shows a flow chart of an embodiment of a method for updating a register according to the present invention.
  • a method 1100 of updating registers begins at step 1102, where one or more bitmap registers are provided.
  • one or more target registers are provided.
  • a mapping between each bit in the one or more bitmap registers and a corresponding target content block in the one or more target registers is established.
  • a register update instruction is provided.
  • the register update instruction may include: one or more flag bits at specified positions, wherein each flag bit corresponds to a bit in the one or more bitmap registers, indicating that the corresponding bit Whether the target content block needs to be updated.
  • the register update instruction further includes the new content of the target content block or the source of the new content.
  • the one or more flag bits in the register update instruction are written to the one or more bitmap registers.
  • the register update instruction is executed by the update controller according to the bits in the one or more bitmap registers to update the target block of content in the one or more target registers, wherein only updating The above bits indicate each target content block that needs to be updated.
  • the update controller is implemented by a logic circuit other than the CPU, such as, but not limited to, an input and output controller in an SPI controller, or other control logic in an embedded device module. Therefore, according to the embodiment of the present invention, the update of the target register does not need to be intervened by the CPU, and does not occupy CPU resources.
  • FIG. 12 schematically shows a mapping block diagram 1200 in one embodiment of a method for updating a register according to the present invention.
  • the step of establishing the mapping between each bit [31:0] in the bitmap register 1202a and the corresponding target content block in the one or more target registers 1204 includes: establishing a mapping of the bitmap register 1202a. A direct correspondence between each of bits [31:0] and the corresponding target content block 1204a0-1204a31 in the one or more target registers.
  • the size of the target content block is fixed, wherein establishing a direct correspondence between the each bit and the corresponding target content block in the one or more target registers includes establishing all the the corresponding relationship between each bit and the start address of the corresponding target content block in the one or more target registers.
  • the bit at position 0 in the bitmap register 1202a may be mapped to the starting address of the target content block 1204a0.
  • Figure 13 schematically shows a block diagram 1300 of mapping in another embodiment of a method of updating a register according to the present invention.
  • the method may further include providing one or more address mapping registers, eg, 1303, each address mapping register including one or more sets of content block address information, eg, address mapping register 1303 including a content block Address information 1303a0-1303a31 . . .
  • the step of establishing the mapping between each bit in the one or more bitmap registers and the corresponding target content block in the one or more target registers comprises: establishing the A correspondence between each bit in the one or more bit-map registers and a set of content block address information in the one or more address-map registers; and establishing an address in the one or more address-map registers The correspondence between the set of content block address information and the corresponding target content blocks in the one or more target registers, wherein the corresponding target content blocks are located according to the content block address information.
  • the content block address information 1303a0 includes a content block start address Addr0 and a content block size Size0.
  • the content block address information may include a content block start address and a content block end address (not shown).
  • the update controller executes the register update instruction according to the bits in the one or more bitmap registers to update the target content block in the one or more target registers comprising: for each bit in the one or more bitmap registers, locating a target content block corresponding to the bit according to the mapping; and if the bit indicates the target content corresponding to the bit If the block needs to be updated, the target content block is updated with the new content of the target content block.
  • the contents of a target block of content in a register or registers eg, register banks
  • the one or more flag bits are located in the header of the register update instruction.
  • the flag bits may be located in the first 1 word, 2 words, or more words of the register update instruction, depending on the number of update target content blocks required.
  • the method of updating registers of the present invention is preferably used in embedded devices.
  • the source of the new content may include one or more of memory, registers, and flash memory.
  • the update controller is a module in an embedded device, for example including but not limited to SPI controller, I 2 S, I 2 C, DMA, UART and other modules.
  • Embedded devices may include, but are not limited to, MCUs, for example.
  • the method for updating registers of the present invention is executed by modules in an embedded device, does not occupy CPU resources, and can conveniently update registers of multiple modules in batches.
  • multiple modules in the embedded device are provided with respective register groups, and the current register values in the register groups reflect the current working configuration of each module. With the solution of the present invention, the register groups of multiple modules can be updated quickly and reliably, so that the working configurations of these modules can be switched quickly and in batches.

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Abstract

本发明公开了一种SPI控制器和操作SPI控制器的方法，该SPI控制器包括：SPI时钟信号产生器，其配置为产生SPI时钟信号；寄存器组，其配置为保存所述SPI控制器的SPI工作配置；多个SPI引脚，其配置为连接到一个或多个SPI外设；及输入输出控制器，其配置为根据所述SPI时钟信号及所述SPI工作配置，执行所述SPI控制器与所述SPI外设之间的数据输入或输出；SPI状态机，其配置为控制所述SPI控制器的工作状态；其中所述SPI控制器通过总线电耦合到位于所述SPI控制器外部的CPU、DMA控制器及系统内存；及所述输入输出控制器还配置为在连续的两次SPI传输之间，从所述DMA控制器接收更新的SPI工作配置并将所述更新的SPI工作配置更新到所述寄存器组中。

Description

增强型SPI控制器以及操作SPI控制器的方法 技术领域
本发明属于SoC集成电路设计领域，尤其涉及SPI控制器以及操作SPI控制器的方法。
背景技术
SPI(Serial Peripheral Interface，串行外围设备接口)是由摩托罗拉公司提出的一种同步串行传输接口，主要用于微控制器和外围设备、微控制器与微控制器之间的通信。具有电路实现简单、总线引脚少、传输速率较快等特点。
传统的SPI接口包括4根信号线：SS(Slave Select，从机选择线)、SCK(SPI Clock，SPI时钟线)、MOSI(Master Output/Slave Input，主机输出从机输入线)和MISO(Master Input/Slave Output，主机输入从机输出线)。
随着SPI接口技术的发展，人们对SPI接口的数据可靠性和吞吐率提出了越来越高的需求，主流的SPI存储器的传输速度超过了100MB/s。例如，兆易创新公司的并行8数据通道闪存的速率已经达到200MB/s。多数据通道、高速率、高可靠性的SPI通信，能够使得SoC(System on Chip，片上系统)芯片可以快速访问外部存储器。这样可以减少SoC芯片内部的内存大小，减小SoC芯片的面积和功耗，从而极大地提升嵌入式系统的性能。
然而，SPI传输的工作配置众多，例如不同SPI接口设备所需的SPI接口时钟模式、数据采样模式、全双工/半双工通信模式、控制模式各不相同，而不同SPI存储器支持的数据通道模式(例如1/2/4/8比特的数据通道模式)也不尽相同，因此SPI接口设备的兼容性问题不容忽视。另外，在SPI通信中，CPU对SPI控制器的工作配置进行调整会增加CPU的开销，从而影响CPU的性能。特别是，发明人注意到，当现有技术中的SPI控制器在不同的工作配置之间进行切换时，CPU对SPI控制器工作配置的调整造成连续传输之间的等待时间过长，从而对传输连续性和多次SPI传输的速度会产生明显 的瓶颈。
可见，对SPI控制器的灵活配置、兼容性的要求与对SPI传输连续性和传输速度的要求是现有技术中亟需解决的一对矛盾。经研究，发明人发现，现有技术中的SPI控制器方案往往着重于兼容性或传输速度中的一个方面，而未能两者兼顾。
例如，中国专利申请公开CN101819560B号提出了一种SPI接口存储器执行程序方法和装置，其采用了包含6个工作状态的状态机来实现兼容各类单、双、四通道等多通道SPI接口存储器指令。该方案限于SPI接口存储器，不涉及对更多类型SPI接口设备的兼容性，且并未考虑到对于SPI传输连续性的优化。
又如，中国专利申请公开CN103064805A号提出了SS由SPI主机控制器控制和CPU可选是否读取接收缓存的数据的方法，但是这样也无法满足CPU对SPI接口吞吐速率的要求。该方案未能考虑到及解决对SPI控制器的灵活配置、兼容性及对SPI传输连续性的协同优化。
再如，中国专利CN104809094B号提出了一种对输入加缓存和对输出加延时的方案，但是主要针对一条数据通道的情形，如MOSI或MISO。该方案亦未能考虑到及解决对SPI控制器的灵活配置、兼容性及对SPI传输连续性的协同优化。
因此，本领域中需要一种SPI控制器及其操作方法，其至少能够提供下列期望益处中的一种或多种：(1)对SPI控制器提供更加灵活的配置，进一步增加SPI控制器的兼容性；(2)提高SPI传输的连续性和多次SPI传输的速度；及(3)考虑到及解决对SPI控制器的灵活配置、兼容性及对SPI传输连续性的协同优化。
另外，发明人还注意到，在一种场景下，在嵌入式设备(例如微控制器MCU)中采用根据现有技术的SPI控制器进行连续传输时，CPU一方面不得不在连续的两次SPI传输之间进入“空闲”状态，另一方面不得不更新SPI控制器中整个寄存器组的内容，以免寄存器组中残留的用于上次SPI传输的值造成本次SPI传输状态的混乱。由CPU来更新或复位整个寄存器 组进一步对CPU造成了额外的负担，且不利于传输的连续性。在另一种场景下，在嵌入式设备中需要更新多个模块(不限于SPI控制器)的寄存器组以配置各模块的功能或修改其状态时，现有技术中同样需要占用CPU资源来更新各模块的寄存器组，而且还需要能够方便、可靠、批量地更新多个模块的寄存器组。
因此，本领域中还需要一种更新寄存器的方法，其至少能够提供下列期望益处中的一种或多种：(1)在嵌入式设备中快速且可靠地更新寄存器组；(2)寄存器组的更新尽量少占用或不占用CPU资源；及(3)方便地批量更新多个模块的寄存器组。
应理解，上述所列举的技术问题仅作为示例而非对本发明的限制，本发明不限于同时解决上述所有技术问题的技术方案。本发明的技术方案可以实施为解决上述或其他技术问题中的一个或多个。
发明内容
为实现上述目的，在本发明的一方面，提供了一种SPI控制器，包括：SPI时钟信号产生器，其配置为产生SPI时钟信号；寄存器组，其配置为保存所述SPI控制器的SPI工作配置；多个SPI引脚，其配置为连接到一个或多个SPI外设；及输入输出控制器，其配置为根据所述SPI时钟信号及所述SPI工作配置，执行所述SPI控制器与所述SPI外设之间的数据输入或输出；SPI状态机，其配置为控制所述SPI控制器的工作状态；其中所述SPI控制器通过总线电耦合到位于所述SPI控制器外部的CPU、DMA控制器及系统内存；及所述输入输出控制器还配置为在连续的两次SPI传输之间，从所述DMA控制器接收更新的SPI工作配置并将所述更新的SPI工作配置更新到所述寄存器组中。
可选地，所述SPI控制器还包括下述组件中的一个或多个：SPI时钟模式控制模块，其配置为调整输出时钟信号的极性和相位；输入输出时序调节模块，其配置为调节SPI输入输出的时序；SPI缓存，其用于缓存SPI控制器在CPU控制下与SPI外设进行交互的数据；及中断控制模块，其用 于SPI控制器在完成指定的传输后，产生对应的中断，并通过总线将中断传给CPU。
可选地，所述多个SPI引脚包括一个或多个SPI片选引脚、一个或多个SPI时钟引脚，及一个或多个SPI输入输出引脚。
优选地，所述多个SPI引脚还包括SPI命令/数据信号引脚、SPI帧频信号引脚、SPI行频信号引脚，及SPI显示有效信号引脚。
优选地，所述SPI控制器布置在嵌入式设备中，且所述总线是片内总线。
在本发明的另一方面，提供一种操作SPI控制器的方法，所述SPI控制器通过总线与CPU和DMA控制器电耦合，并通过多个SPI引脚与一个或多个SPI外设电耦合，其中所述SPI控制器包括寄存器组且配置为能够以CPU控制模式或DMA控制模式操作，所述方法包括：S1)确定与所述一个或多个SPI外设中的每个SPI外设对应的一个或多个SPI工作配置；S2)创建SPI传输计划，所述SPI传输计划包括对所述一个或多个SPI外设进行的多次SPI传输、所述多次SPI传输的执行顺序及所述多次SPI传输中的每次SPI传输对应的SPI工作配置，其中所述SPI控制器根据所述对应的SPI工作配置执行每次SPI传输；及S3)在所述DMA控制器的控制下执行设定的SPI传输计划，其中按照所述执行顺序执行所述多次SPI传输，并根据对应的SPI工作配置执行当前的SPI传输，且其中在一次SPI传输完成后，由所述DMA控制器将当前的SPI工作配置修改为与下一次SPI传输对应的SPI工作配置。
在根据本发明的SPI控制器以及操作SPI控制器的方法中，可选地，根据SPI状态机操作所述SPI控制器，所述SPI状态机配置为包括按顺序循环的下述状态：“空闲”状态，用于表征SPI控制器处于不工作状态；“配置”状态，用于由所述输入输出控制器从所述DMA控制器接收SPI工作配置并将所述SPI工作配置更新到所述寄存器组中；“准备”状态，用于控制SPI的片选建立时间；“命令”状态，用于SPI控制器发送SPI命令，并控制SPI命令所持续的时钟周期数；“地址”状态，用于SPI控制器发送SPI 地址，并控制SPI地址所持续的时钟周期数；“等待”状态，用于SPI控制器根据SPI从设备的要求，控制等待传输SPI有效数据的时钟周期数；“输出”状态，用于SPI控制器控制输出数据的时钟周期数；“输入”状态，用于SPI控制器控制输入数据的时钟周期数；及“完成”状态，用于控制SPI的片选保持时间。
在根据本发明的SPI控制器以及操作SPI控制器的方法中，可选地，所述SPI状态机中的每个工作状态配置为具有各自的SPI工作配置。
在根据本发明的SPI控制器以及操作SPI控制器的方法中，优选地，当所述SPI控制器配置为以CPU控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过；及当所述SPI控制器以DMA控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过，且所述“空闲”状态配置为能够被跳过以直接从“完成”状态进入“配置”状态。
在根据本发明的SPI控制器以及操作SPI控制器的方法中，可选地，所述SPI工作配置包括下述模式中的一种或多种模式的组合：1/2/4/8数据通道模式、SPI时钟模式、SDR/DDR数据采样模式、全双工/半双工通信模式。
在根据本发明的操作SPI控制器的方法中，可选地，提供包含一个或多个配置节点的DMA配置链表，其中每个配置节点对应于一次SPI传输，且包含与该次SPI传输对应的一个SPI工作配置并链接到该次SPI传输的发送数据链表，所述发送数据链表链接到下一个配置节点，该SPI工作配置的信息保存在DMA配置缓冲区中的一块区域中；及在一次SPI传输完成后，由所述DMA控制器将当前的SPI工作配置修改为与下一次SPI传输对应的SPI工作配置包括：从DMA配置缓冲区中对应下一次SPI传输的配置节点的一块区域中，读取与下一次SPI传输对应的SPI工作配置，并将该SPI工作配置写入所述寄存器组。
可选地，若该次SPI传输包括“输出”状态，则所述配置节点链接到该次SPI传输的发送数据链表，所述发送数据链表链接到下一个配置节点；否则，所述配置节点直接链接到下一个配置节点。
可选地，所述SPI工作配置的信息包括与所述SPI工作配置对应的一 个或多个寄存器的值。
替代地，所述SPI工作配置的信息包括当前配置节点的SPI工作配置对应的一个或多个寄存器的值与DMA配置链表中的上一配置节点的SPI工作配置对应的一个或多个寄存器的值之间的差异。
可选地，所述DMA配置缓冲区中的一块区域中指定位置的一个或多个比特中的每个比特对应于当前配置节点的SPI工作配置对应的一个或多个寄存器中的一个寄存器，指示与上一配置节点的SPI工作配置相比该寄存器的值是否发生改变，所述方法优选地还包括：在将该SPI工作配置写入所述寄存器组时，仅更新与上一配置节点的SPI工作配置相比发生改变的寄存器的值。
可选地，将所述DMA配置缓冲区中的一块区域中指定位置的多个比特设置为误差校验数，且在所述SPI控制器内部提供误差校验基准数；及仅当所述误差校验数与所述误差校验基准数符合预先指定的关系时，才从下一次SPI传输对应的配置节点的在DMA配置缓冲区中的一块区域中读取与下一次SPI传输对应的SPI工作配置，并将该SPI工作配置写入所述寄存器组。
可选地，当所述SPI外设为LCD时，执行下述步骤：提供LCD输出数据，所述LCD输出数据包括有效数据区及上空白区、下空白区、前空白区和后空白区；配置所述SPI状态机在所述前空白区中启用“配置”状态，在所述有效数据区中启用“输出”状态，在所述上空白区、所述下空白区和所述后空白区中启用除“输出”和“空闲”外的任意状态；在“配置”状态下加载SPI工作配置；在“输出”状态下每次输出一行LCD输出数据。
在本发明的又一方面，提供一种更新寄存器的方法，包括下述步骤：提供一个或多个比特映射寄存器；提供一个或多个目标寄存器；建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的映射；提供寄存器更新指令，所述寄存器更新指令包括：指定位置的一个或多个标志比特，其中每个标志比特对应于所述一个或多个比特映射寄存器中的一个比特位，指示对应于该比特位的目 标内容块是否需要更新，其中对于由所述比特位指示需要更新的每个目标内容块，所述寄存器更新指令还包括该目标内容块的新内容或新内容的来源；将所述寄存器更新指令中的所述一个或多个标志比特写入所述一个或多个比特映射寄存器；及由更新控制器根据所述一个或多个比特映射寄存器中的比特位执行所述寄存器更新指令，以更新所述一个或多个目标寄存器中的目标内容块，其中仅更新由所述比特位指示需要更新的每个目标内容块。
可选地，建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的映射的步骤包括：建立所述每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的直接对应关系。
可选地，所述目标内容块的大小固定，其中建立所述每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的直接对应关系包括建立所述每个比特位与所述一个或多个目标寄存器中对应的目标内容块的起始地址之间的对应关系。
可选地，还包括提供一个或多个地址映射寄存器，每个地址映射寄存器包括一组或多组内容块地址信息；其中建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的映射的步骤包括：建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个地址映射寄存器中的一组内容块地址信息之间的对应关系；及建立所述一个或多个地址映射寄存器中的所述一组内容块地址信息与所述一个或多个目标寄存器中对应的目标内容块之间的对应关系，其中根据所述内容块地址信息定位所述对应的目标内容块。
可选地，所述内容块地址信息包括内容块起始地址和内容块大小。
可选地，所述内容块地址信息包括内容块起始地址和内容块结束地址。
可选地，由更新控制器根据所述一个或多个比特映射寄存器中的比特位执行所述寄存器更新指令，以更新所述一个或多个目标寄存器中的目 标内容块的步骤包括：对于所述一个或多个比特映射寄存器中的每个比特位，根据所述映射，定位所述比特位对应的目标内容块；及如果所述比特位指示对应于该比特位的目标内容块是否需要更新，则用目标内容块的新内容更新所述目标内容块。
可选地，所述一个或多个标志比特位于所述寄存器更新指令的头部中。
可选地，所述新内容的来源包括内存、寄存器、闪存中的一个或多个。
可选地，所述更新控制器是嵌入式设备中的模块。
根据本发明的SPI控制器以及操作SPI控制器的方法能够提高SPI接口的吞吐率，扩展SPI控制器的通用性，提高CPU的利用率，提升SoC系统的性能。尤其是，根据本发明的新的连续传输模式，可以极大地提高SPI接口的吞吐率，扩展SPI控制器的通用性，提高CPU的利用率，从而显著提升SoC系统的性能。
如上所述，根据本发明的SPI控制器在DMA控制的分段配置传输模式(本文中简称为“DMA控制模式”)下，可以在每段传输的“配置”状态下，重新配置SPI控制器的寄存器组，从而实现每个分段配置传输的操作模式相互独立，进而组成一种灵活强大的连续传输模式。DMA分段配置传输仅需CPU配置一次，即可完成多次SPI传输。
通过本发明的更新寄存器的方法，可以在嵌入式设备中快速且可靠地更新寄存器组，寄存器组的更新尽量少占用或不占用CPU资源，且能够方便地批量更新多个模块的寄存器组。
附图说明
在下文中，将基于实施例参考附图进一步解释本发明。
图1示意性地示出根据本发明实施例的SPI控制器的结构框图。
图2示意性地示出本发明实施例的SPI控制器的详细结构框图。
图3示意性地示出根据本发明的SPI控制器的有限状态机跳转图。
图4示意性地示出根据本发明的SPI控制器分时访问闪存(Flash)、SRAM、LCD的结构框图。
图5示意性地示出根据本发明实施例的操作SPI控制器的方法的示意流程图。
图6示意性地示出根据本发明实施例的SPI传输流程图。
图7示意性地示出根据本发明实施例的SPI分段配置传输流程图。
图8示意性地示出根据本发明的DMA控制的分段配置传输的时序图。
图9示意性地示出根据本发明的SPI控制器访问并行8位RGB格式LCD所使用的帧格式。
图10示意性地示出根据本发明的SPI控制器访问并行8位RGB格式LCD的时序图。
图11示意性地示出根据本发明的更新寄存器的方法实施例的流程图。
图12示意性地示出根据本发明的更新寄存器的方法的一个实施例中的映射的框图。
图13示意性地示出根据本发明的更新寄存器的方法的另一实施例中的映射的框图。
具体实施方式
以下将结合附图和具体的实施方式，对本发明的方案进行详细说明。应理解，附图所示及下文所述的实施例仅仅是说明性的，而不作为对本发明的限制。
在本发明的一个实施例中，如图1所示，提供一种SPI控制器100，包括：SPI时钟信号产生器110，其配置为产生SPI时钟信号SPI_CLK；寄存器组114，其配置为保存SPI控制器100的SPI工作配置；多个SPI引脚118，其配置为连接到一个或多个SPI外设(未示出)；及输入输出控制器116，其配置为根据所述SPI时钟信号及所述SPI工作配置，执行所述SPI控制器110与所述SPI外设之间的数据输入或输出；SPI状态机112，其配置为控制所述SPI控制器100的工作状态；其中所述SPI控制器100通过总 线108电耦合到位于所述SPI控制器外部的CPU 104、DMA控制器106及系统内存102；及所述输入输出控制器116还配置为在连续的两次SPI传输之间，从所述DMA控制器106接收更新的SPI工作配置并将所述更新的SPI工作配置更新到所述寄存器组114中。
在本发明的一个详细实施例中，如图2所示，提供一种SPI控制器200，其主要包括SPI状态机212、SPI时钟信号产生器210、SPI时钟模式控制模块220、寄存器组214、输入输出控制器216、输入输出时序调节模块222、SPI缓存226以及中断控制模块224。SPI控制器200通过总线208与CPU 204、DMA控制器206以及系统内存202相连。作为非限制性示例，各组件之间的具体连接关系可以为：CPU 204通过总线208与SPI状态机212、寄存器组214、中断控制模块224和SPI缓存226相连；SPI时钟信号产生器210与总线208、SPI时钟模式控制模块220、寄存器组214和SPI状态机212相连；SPI时钟模式控制模块220与寄存器组214相连，并通过输入输出时序调节模块222将SPI时钟信号SPI_CLK输出；总线208将高频时钟信号HCLK传给输入输出时序调节模块222；SPI状态机212与寄存器组214相连，受寄存器组214控制，同时与SPI时钟信号产生器210、输入输出控制器216、中断控制模块224相连，控制SPI接口上传输时钟和数据的状态，并产生相应的中断；中断控制模块224在SPI状态机的控制下产生中断，并通过总线208传给CPU 204；寄存器组214与SPI状态机212、SPI时钟信号产生器210、SPI时钟模式控制模块220、输入输出控制器216、输入输出时序调节模块222、中断控制模块224相连，配置寄存器组214中相关的寄存器；输入输出控制器216与输入输出时序调节模块222相连并接收SPI接口上的数据或发送数据到SPI接口，并与SPI缓存226相连，传输CPU控制模式下的数据，又与DMA控制器206相连，传输DMA控制模式下的数据；DMA控制器206通过总线208连接寄存器组214，用于配置寄存器组214。
作为非限制性示例，本发明的SPI控制器包括构成SPI接口的以下SPI引脚(在图1和图2中分别以标号118和218表示)：SPI片选引脚 SPI_CS(对应从机选择线SS)、SPI时钟引脚SPI_CLK(对应SPI时钟线SCK)，及多个SPI输入输出引脚SPI_IO。在图1和图2的实施例中，示出八个SPI输入输出引脚SPI_IO[7:0]，其中SPI_IO[0]对应主机输出从机输入线MOSI，SPI_IO[1]对应主机输入从机输出线MISO，并增设SPI_IO[7:2]，以在硬件层面使得本发明的SPI控制器能够支持2/4/8等多数据通道传输。在一个优选实施例中，本发明的SPI控制器还包括以下SPI引脚：SPI命令/数据信号引脚SPI_CD、SPI帧频信号引脚SPI_VSYNC、SPI行频信号引脚SPI_HSYNC和SPI显示有效信号引脚SPI_DE，以便在硬件层面扩展本发明SPI控制器的兼容性，使之能够支持LCD(Liquid Crystal Display，液晶显示器)接口外设和连续的LCD数据传输，例如支持摩托罗拉6800、英特尔8080和/或并行8位RGB模式的LCD接口外设。
应理解，图1和图2中所示总线可以是片上总线，包括但不限于AMBA(Advanced Microcontroller Bus Architecture，高级微控制器总线架构)总线。还应理解，根据本发明的SPI控制器可以布置在各种嵌入式设备中。
在图1和图2所示实施例中，SPI状态机112或212控制SPI控制器100或200运行时所包含的状态、各个状态所持续的时钟周期及各个状态的跳转方向。SPI状态机的操作将在下文中参考图3详述。
在图2所示的实施例中，SPI时钟信号产生器210包括预分频器和计数器模块，用于根据寄存器配置的预分频系数和计数分频系数，产生频率可变的串行输出SPI时钟信号SPI_CLK。应理解，本发明的实施并不局限于此，SPI时钟信号产生器210可以实施为包含不同组件以实现相同或类似功能。
SPI时钟模式控制模块220配置为调整输出时钟信号SPI_CLK的极性和相位，从而兼容SPI协议中规定的4种时序类型，即，取决于CPOL(Clock Polarity，时钟极性)和CPHA(Clock Phase，时钟相位)组合的四种不同的数据传输时序。
寄存器组114或214用于配置SPI控制器处于不同的操作模式，从而 实现多种功能。
输入输出控制器116或216用于根据SPI状态机所处的状态，输入或输出相应的数据。进一步，输入输出控制器116或216还配置为在连续的两次SPI传输之间，从DMA控制器106或206接收更新的SPI工作配置并将更新的SPI工作配置更新到寄存器组114或214中。换言之，输入输出控制器116或216可以更新寄存器组114或214中的SPI工作配置而无需CPU的干预。
输入输出时序调节模块222用于调节SPI接口的时序，例如通过分别对输入或输出各通道数据加延时的方式，调整数据的采样或发送时序，从而确保数据的正确传输。
根据本发明的实施例，SPI控制器可以配置为能够以CPU控制模式或DMA控制模式操作。SPI缓存226用于在CPU控制模式下存储SPI控制器与SPI外设进行交互的数据。在CPU控制的读数据操作中，CPU 204通过总线配置SPI控制器的寄存器组214，同时将需要发送的数据写入SPI缓存226；SPI控制器200在运行的过程中会将SPI缓存226中的数据发送给对应的SPI外设(未示出)。在CPU控制的写数据操作中，CPU 204先配置SPI控制器200的寄存器组214；SPI控制器200在运行的过程中会将接收的数据存入SPI缓存226；CPU 204等SPI传输结束后可以通过总线来读取SPI缓存226中的数据。
中断控制模块224用于SPI控制器200在完成指定的传输后，产生对应的中断，并通过总线208将中断传给CPU 204。
在根据本发明的实施例中，DMA控制器206可以在CPU 204的配置下，通过SPI控制器200实现SPI外设和系统内存202之间的数据传输。尤其是，如下文详述，根据本发明的实施例，DMA可仅由CPU配置一次，即可完成多次SPI传输，特别是连续的多次SPI传输。
总体上，CPU 204通过总线208实现对SPI控制器200和DMA控制器206的控制。
图3示意性地示出根据本发明的SPI控制器的状态机状态跳转图300。 在本发明的上下文中，SPI控制器的功能是通过配置SPI状态机和寄存器组来实现的。SPI控制器的状态机按照图3中的箭头方向跳转，并且除了“空闲”状态外，其他状态都可以直接跳过。用户可以根据需要选择执行特定的状态，从而实现不同功能。根据本发明的SPI状态机的各个状态如下文详述。在本发明的优选实施例中，当所述SPI控制器配置为以CPU控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过；及当所述SPI控制器以DMA控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过，且所述“空闲”状态配置为能够被跳过以直接从“完成”状态进入“配置”状态。
1)“空闲(IDLE)”状态302用于表征SPI控制器处于不工作状态。此时，作为非限制性示例，SPI时钟引脚SPI_CLK可以根据SPI协议规定的4种时钟模式，一直处于低电平或高电平；SPI片选引脚SPI_CS一直处于高电平，SPI命令/数据信号引脚SPI_CD、SPI帧频信号引脚SPI_VSYNC、SPI行频信号引脚SPI_HSYNC、SPI显示有效信号引脚SPI_DE和SPI输入输出引脚SPI_IO[7:0]一直处于可配置的固定电平。
2)“配置(CONF)”状态304用于SPI控制器在DMA控制的分段配置传输模式下，从DMA发送缓冲区(TX_buf)中取出相应的数据，通过输入输出控制器配置到寄存器组的相应寄存器中，实现可以在每次分段配置传输之前重新配置SPI控制器的寄存器组。因而各个分段配置传输的具体模式可以不一样，相当于一次DMA控制的分段配置传输包含多个不同的SPI单次传输，且可以分时访问不同的SPI外设。
3)“准备(PREP)”状态306用于控制SPI的片选建立时间，满足各个SPI外设的片选建立时间时序要求。同时，准备状态也用于SPI控制器准备要发送的命令、地址和数据。
4)“命令(CMD)”状态308用于SPI控制器发送SPI命令，并控制SPI命令所持续的时钟周期数。
5)“地址(ADDR)”状态310用于SPI控制器发送SPI地址，并控制SPI地址所持续的时钟周期数。
6)“等待(DUMMY)”状态312用于SPI控制器根据SPI从设备的要求，控制等待传输SPI有效数据的时钟周期数。
7)“输出(DOUT)”状态314用于SPI控制器控制输出有效数据的时钟周期数。在CPU控制模式下，发送的数据来自于SPI缓存；在DMA控制模式下，发送的数据来自与DMA配置链表或DMA TX链表所配置的内存。
8)“输入(DIN)”状态316用于SPI控制器控制输入有效数据的时钟周期数。在CPU控制模式下，输入的数据存放到SPI缓存中；在DMA控制模式下，输入的数据存放到DMA发送数据链表(RX链表)所配置的内存里。
9)“完成(DONE)”状态318用于控制SPI的片选保持时间，满足各个SPI外设的片选保持时间时序要求。在单次SPI传输模式中，SPI状态机的下一个状态为“空闲”状态。在DMA控制的分段配置传输模式下，如果控制SPI状态机跳转的下一个状态为“配置”状态，则DMA控制的分段配置传输继续进行；如果控制SPI状态机跳转的下一个状态为“空闲”状态，则DMA控制的分段配置传输结束，并产生对应的中断。
基于本发明的硬件实现以及控制方法，根据本发明的SPI控制器在单次SPI传输中，能够独立控制“命令”、“地址”、“输出”和“输入”状态下SPI接口的1/2/4/8数据通道模式，能够独立控制“命令”、“地址”、“输出”和“输入”状态下SPI时钟信号的SPI_CLK的SDR(Single Data Rate，单倍数据采样)和DDR(Double Data Rate，双倍数据采样)数据采样模式，支持全双工和半双工传输，支持CPU控制的数据传输和DMA控制的数据传输，从而满足大多数1/2/4/8等多数据通道SPI外设接口的时序要求，从而极大地提高了SPI接口的吞吐率，极大地拓展了SPI控制器的通用性。同时通过时序调节模块，可以较为精细的调节每个数据通道的延时值，从而确保数据传输的正确性，提高SPI数据传输的可靠性。
在本发明的实施例中，SPI状态机中的每个工作状态可以配置为具有各自的SPI工作配置。SPI工作配置包括下述模式中的一种或多种模式的组 合：1/2/4/8数据通道模式、SPI时钟模式、SDR/DDR数据采样模式、全双工/半双工通信模式。
应理解，状态机的每个状态可以独立启用或禁用，每个状态的时钟周期也可以独立配置。通过启用的状态及其时钟周期长度，可以控制状态机。如上所述，通过寄存器组114或214，SPI控制器可以配置为处于不同的操作模式，从而实现多种功能。例如，SPI状态机的当前状态、SPI控制器的工作配置以及SPI控制器的属性等均可反映在寄存器组中的寄存器包含的寄存器值来反映。可选地，可以通过修改相应寄存器中的寄存器值来改变SPI状态机的当前状态、SPI控制器的工作配置以及SPI控制器的属性等。作为非限制性实施例，根据本发明的SPI控制器中的寄存器组可以配置为包括但不限于如以下表1所示的寄存器。
表1：寄存器示例
Figure PCTCN2021103232-appb-000001
Figure PCTCN2021103232-appb-000002
进一步，本领域技术人员应理解，可以通过寄存器中的寄存器值对SPI状态机以及SPI控制器的状态和操作进行控制。应理解，寄存器值可以是只读的、可读写(R/W)或可变的(即，可配置为只读或可读写的)。作为非限制性示例，根据本发明的SPI控制器中的寄存器的寄存器值可以配置为包括但不限于如以下表2所示的寄存器值。
表2：寄存器值示例
Figure PCTCN2021103232-appb-000003
Figure PCTCN2021103232-appb-000004
Figure PCTCN2021103232-appb-000005
Figure PCTCN2021103232-appb-000006
Figure PCTCN2021103232-appb-000007
以下表3和表4中列出了在非限制性实施例中，根据本发明的SPI控制器分别在“命令”、“地址”、“等待”、“输入”和“输出”状态下的1/2/4/8数据通道模式、对应的数值和持续的时钟周期数控制寄存器值，这些寄存器值包含在寄存器组中的寄存器内。每个状态的控制都相互独立，因而几乎可以实现任意1/2/4/8数据通道模式的SPI传输。应理解，在本文的上下文中，“1/2/4/8数据通道模式”是指使用1个、2个、4个或8个数据通道进行SPI传输的模式。在此，每个数据通道对应于一个SPI输入输出引脚，每个数据通道每次传输1比特的数据。
表3：1数据通道/2数据通道模式的命令配置表
Figure PCTCN2021103232-appb-000008
Figure PCTCN2021103232-appb-000009
Figure PCTCN2021103232-appb-000010
作为非限制性示例，可以按如下方式控制根据本发明的SPI控制器的“命令”、“地址”、“等待”、“输入”和“输出”状态所对应的工作配置。
1)SPI控制器的“命令”状态由上述表3和表4中，与“命令”同一行的寄存器值控制。置位SPI_USR_COMMAND比特使能“命令”状态，SPI控制器会包含“命令”状态，会发送配置的SPI命令；清零SPI_USR_COMMAND比特，SPI控制器会跳过“命令”状态，不会发送SPI命令。当置位SPI_USR_COMMAND比特时，SPI控制器发送的命令值配置在SPI_USR_COMMAND_VALUE中，持续的时钟周期数配置在SPI_USR_COMMAND_BITLEN中；以8数据通道模式发送命令值时，置位SPI_FCMD_OCT比特，清零SPI_FCMD_QUAD和SPI_FCMD_DUAL比特；以4数据通道模式发送命令值时，置位SPI_FCMD_QUAD比特，清零SPI_FCMD_OCT和SPI_FCMD_DUAL比特；以2数据通道模式发送命令值时，置位SPI_FCMD_DUAL比特，清零SPI_FCMD_OCT和SPI_FCMD_QUAD比特；以1数据通道模式发送命令值时，清零SPI_FCMD_OCT、SPI_FCMD_QUAD和SPI_FCMD_DUAL比特。
2)SPI控制器的“地址”状态由表3和表4中，与“地址”同一行的寄存器值控制。置位SPI_USR_ADDR比特使能“地址”状态，SPI控制器会包含“地址”状态，会发送配置的SPI地址；清零SPI_USR_ADDR比特，SPI控制器会跳过“地址”状态，不会发送SPI地址。当置位SPI_USR_ADDR比特时，SPI控制器发送的地址值配置在SPI_USR_COMMAND_VALUE中，持续的时钟周期数配置在SPI_USR_COMMAND_BITLEN中；以8数据通道模式发送地址值时，置位 SPI_FADDR_OCT比特，清零SPI_FADDR_QUAD和SPI_FADDR_DUAL比特；以4数据通道模式发送地址值时，置位SPI_FADDR_QUAD比特，清零SPI_FADDR_OCT和SPI_FADDR_DUAL比特；以2数据通道模式发送地址值时，置位SPI_FADDR_DUAL比特，清零SPI_FADDR_OCT和SPI_FADDR_QUAD比特；以1数据通道模式发送地址值时，清零SPI_FADDR_OCT、SPI_FADDR_QUAD和SPI_FADDR_DUAL比特。
3)SPI控制器的“等待”状态由表3和表4中，与“等待”同一行的寄存器值控制。置位SPI_USR_DUMMY比特使能“等待”状态，SPI控制器会在“等待”状态持续SPI_USR_DUMMY_CYCLELEN个SPI_CLK时钟周期；清零SPI_USR_DUMMY比特，SPI控制器会跳过“等待”状态。
4)SPI控制器的”输出“状态由表3和表4中，与“输出”同一行的寄存器值控制。置位SPI_USR_MOSI比特使能“输出”状态，SPI控制器会包含“输出”状态；清零SPI_USR_MOSI比特，SPI控制器会跳过“输出”状态，不会发送SPI输出数据。当置位SPI_USR_MOSI比特时，CPU控制模式下会发送SPI缓存中的数据，DMA控制模式下，会发送DMA配置链表或DMA TX链表所配置的内存数据，发送数据持续的时钟周期数配置在SPI_USR_MOSI_DBITLEN中；以8数据通道模式发送数据时，置位SPI_FWRITE_OCT比特，清零SPI_FWRITE_QUAD和SPI_FWRITE_DUAL比特；以4数据通道模式发送数据时，置位SPI_FWRITE_QUAD比特，清零SPI_FWRITE_OCT和SPI_FWRITE_DUAL比特；以2数据通道模式发送数据时，置位SPI_FWRITE_DUAL比特，清零SPI_FWRITE_OCT和SPI_FWRITE_QUAD比特；以1数据通道模式发送数据时，清零SPI_FWRITE_OCT、SPI_FWRITE_QUAD和SPI_FWRITE_DUAL比特。
5)SPI控制器的“输入”状态由表3和表4中，与“输入”同一行的寄存器值控制。置位SPI_USR_MISO比特使能“输入”状态，SPI控制器会包含“输入”状态；清零SPI_USR_MISO比特，SPI控制器会跳过“输入”状态，不会接收SPI输入数据。当置位SPI_USR_MISO比特时，CPU控制 模式下会将接收数据存入SPI缓存中，DMA控制模式下，会将接收数据存入DMA RX链表所配置的内存里，接收数据持续的时钟周期数配置在SPI_USR_MISO_DBITLEN中；以8数据通道模式接收数据时，置位SPI_FREAD_OCT比特，清零SPI_FREAD_QUAD和SPI_FREAD_DUAL比特；以4数据通道模式接收数据时，置位SPI_FREAD_QUAD比特，清零SPI_FREAD_OCT和SPI_FREAD_DUAL比特；以2数据通道模式接收数据时，置位SPI_FREAD_DUAL比特，清零SPI_FREAD_OCT和SPI_FREAD_QUAD比特；以1数据通道模式接收数据时，清零SPI_FREAD_OCT、SPI_FREAD_QUAD和SPI_FREAD_DUAL比特。
如上所述，根据本发明的SPI控制器可以实现任意可行的1/2/4/8数据通道模式的SPI传输。如图4所示，根据本发明的SPI控制器402可以分时访问如图4所示的闪存404、SRAM 406和英特尔8080模式的8比特LCD。同时可以访问其他1/2/4/8通道SPI外设。
在本发明的实施例中，还实现了一种新的SPI通信数据流控机制：DMA控制的分段配置传输。根据本发明的SPI控制器支持DMA控制的多次分段配置传输，SPI控制器在每次SPI传输前的“配置”状态下，可以通过DMA控制器重新配置SPI的寄存器。因此，作为非限制性示例，可以实现下述功能。
1)每段SPI传输都可以配置成全双工通信或半双工通信，SDR数据采样模式或DDR数据采样模式。
2)每段半双工通信都可以独立的配置“命令”、“地址”、“输出”和“输入”状态下SPI接口的1/2/4/8数据通道模式及各通道的数据延时。
3)根据本发明的SPI控制器包含多个CS片选信号，且在DMA控制的多次分段配置传输中可以独立控制各个CS的工作情形，因此可以支持以不同的SPI传输模式分时访问不同SPI外设的功能。
4)每段SPI传输的数据长度由配置的DMA控制器决定，且都可以独立的配置为任意值。
图5示意性地示出根据本发明实施例的操作SPI控制器的方法500的 示意流程图。在该实施例中，SPI控制器通过总线与CPU和DMA控制器电耦合，并通过多个SPI引脚与一个或多个SPI外设电耦合，其中SPI控制器包括寄存器组且配置为能够以CPU控制模式或DMA控制模式操作。如图5所示，方法500包括：S1)确定与所述一个或多个SPI外设中的每个SPI外设对应的一个或多个SPI工作配置；S2)创建SPI传输计划，所述SPI传输计划包括对所述一个或多个SPI外设进行的多次SPI传输、所述多次SPI传输的执行顺序及所述多次SPI传输中的每次SPI传输对应的SPI工作配置，其中所述SPI控制器根据所述对应的SPI工作配置执行每次SPI传输；及S3)在所述DMA控制器的控制下执行设定的SPI传输计划，其中按照所述执行顺序执行所述多次SPI传输，并根据对应的SPI工作配置执行当前的SPI传输，且其中在一次SPI传输完成后，由所述DMA控制器将当前的SPI工作配置修改为与下一次SPI传输对应的SPI工作配置。
应理解，在根据本发明的操作SPI控制器的方法中，一个SPI外设可以对应于多个SPI工作配置，且SPI传输计划中的多次SPI传输可以包括针对多个SPI外设的SPI传输，也可以包括针对一个SPI外设的应用多种不同SPI工作配置的SPI传输。
图6示意性地示出根据本发明实施例的SPI传输流程图。在步骤602，SPI控制器处于“空闲”状态。在步骤604，CPU对SPI控制器的寄存器组中的寄存器进行配置。在步骤606，对于DMA控制模式，CPU配置DMA对应的收发数据。在步骤608，SPI控制器等待SPI从机设备准备好数据传输。在步骤610，CPU置位SPI中断使能寄存器，并使能SPI传输。在步骤612，执行SPI传输计划，直至触发相应中断。
图7示意性地示出根据本发明实施例的SPI分段配置传输流程图。在步骤700，SPI控制器处于“空闲”状态。在步骤704，CPU配置SPI控制器的寄存器组中的寄存器。在步骤706，对于DMA控制模式，配置DMA对应的收发数据，或对于CPU模式，配置SPI缓存中的收发数据。在步骤708，SPI控制器处于“配置”状态，更新SPI的寄存器。在步骤710，判断寄存器值SPI_CS_SETUP是否为1。如果是，则确定SPI控制器处于“准 备”状态，并在步骤712拉低片选信号并控制SPI建立时间，否则跳转至步骤714。在步骤714，判断寄存器值SPI_USR_COMMAND是否为1。如果是，则在步骤716确定SPI控制器处于“命令”状态，并发送SPI命令数据，否则跳转至步骤718。在步骤718，判断寄存器值SPI_USR_ADDR是否为1，如果是，则在步骤720确定SPI控制器处于“地址”状态，并发送SPI地址数据，否则跳转至步骤722。在步骤722，判断寄存器值SPI_CS_DUMMY是否为1，如果是，则在步骤724确定SPI控制器处于“等待”状态，不执行任何操作，否则跳转至步骤726。在步骤726，判断寄存器值SPI_USR_MOSI是否为1，如果是，则在步骤728确定SPI控制器处于“输出”状态，并输出发送数据，否则跳转至步骤730。在步骤730，判断寄存器值SPI_USR_MISO是否为1，如果是，则在步骤732确定SPI控制器处于“输入”状态，并接收SPI数据，否则跳转至步骤734。在步骤734，判断SPI_CS_HOLD是否为1，如果是，则在步骤736确定SPI控制器处于“完成”状态，并保持设定的片选保持时间。接下来，在步骤738判断SPI_USR_NXT_CONT是否为1，如果是，则确定SPI传输计划中存在下一SPI传输，并返回步骤708执行下一SPI传输。如果否，则进行至步骤740，SPI传输计划执行完毕。
图8示意性地示出根据本发明的DMA控制的分段配置传输的时序图800。如图所示，SPI时序图800的横轴为时间，纵轴方向从上到下排列的多行图表显示出SPI控制器的各种信号及状态。SPI_CS一行显示片选信号的状态。在图800中，SPI_CS拉低时表示有SPI外设被选中，例如在分段1、分段2及分段n处有相同或不同的SPI外设被选中，其中n为大于2的任意正整数。SPI_ST一行表示SPI状态机的状态。在图800中，在分段1开始之前，即在时间t1之前，SPI状态机处于“配置”状态，由CPU对SPI传输计划进行配置。在时间t1至t2之间，SPI状态机处于“准备”状态，控制SPI的片选建立时间。在CPU于时间t2使能SPI传输时，开始进行分段1的传输。在所示实施例中，分段1包括“准备”、“命令”、“地址”、“等待”、“输出”、“输出”及“完成”状态，但本领域技术人员应理 解，本发明的实施并不局限于此。本发明的每段SPI传输可以包括多于或少于所述的状态，或者包括于所示不同数目、顺序和内容的状态。
在现有技术的SPI方案中，在一段SPI传输结束后，将触发中断，将控制返回到CPU，且SPI状态机进入“空闲”状态。相比之下，在根据本发明的SPI控制器方案中，在两次连续的SPI传输之间，例如分段1和分段2的SPI传输之间，SPI状态机并不进入“空闲”状态，且控制也不会返回到CPU。相反，在DMA控制模式下，在分段1的“完成”状态之后，SPI状态机进入“配置”状态而不需要CPU的干预或任何操作。例如，根据本发明的SPI控制器中的输入输出控制器可配置为在连续的两次SPI传输之间，从DMA控制器接收更新的SPI工作配置并将更新的SPI工作配置更新到寄存器组中。寄存器组的更新例如可以在分段1和分段2之间的“配置”状态执行。
在图8中，SPI_CLK表示SPI时钟信号，以此控制各状态的节拍以及SPI控制器各种操作之间的同步；SPI_CD表示SPI命令/数据信号；SPI_IO[7:0]示意性地表示SPI输入输出引脚[7:0]的状态，有效数据的传输对应于输入和输出状态，而在“配置”状态下，SPI输入输出引脚上并不携带有效数据。在图8中，Conf_buf/Tx_buf一行表示DMA配置链表或DMA发送链表(亦称为DMA TX链表)，其中的配置节点Conf_buf对应于DMA配置缓冲区，用于配置SPI控制器的寄存器组，其中的发送节点TX_buf对应于DMA发送缓冲区，用于在DMA控制模式下的数据发送，以及配置状态切换。RX_buf一行表示DMA接收链表，其中的接收节点RX_buf对应于DMA输入缓冲区，用于在DMA控制模式下的数据接收。
在每次分段配置传输之前，都可以通过配置缓冲区(Conf_buf)来配置SPI控制器的寄存器组。在本发明的实施例中，提供包含一个或多个配置节点的DMA配置链表，其中每个配置节点对应于一次SPI传输，且包含与该次SPI传输对应的一个SPI工作配置并链接到该次SPI传输的发送数据链表，所述发送数据链表链接到下一个配置节点，该SPI工作配置的信息保存在DMA配置缓冲区中的一块区域中；及在一次SPI传输完成后，由所述 DMA控制器将当前的SPI工作配置修改为与下一次SPI传输对应的SPI工作配置包括：从DMA配置缓冲区中对应下一次SPI传输的配置节点的一块区域中，读取与下一次SPI传输对应的SPI工作配置，并将该SPI工作配置写入所述寄存器组。
若该次SPI传输包括“输出”状态，则所述配置节点链接到该次SPI传输的发送数据链表，所述发送数据链表链接到下一个配置节点；否则，所述配置节点直接链接到下一个配置节点。如图8所示，对应于“配置”状态的多个(n个)配置节点Conf_buf1、Conf_buf2、…、Conf_bufn与对应于“输出”状态的发送节点TX_buf1_1、TX_buf2_1链接形成DMA配置链表。其中链接在一起的一个或多个发送节点形成为发送数据链表。虽然如图8所示，DMA配置链表包括链接在一起的多个配置节点以及多个发送节点。但应理解，在SPI从机上的SPI控制器的实施例中，DMA配置链表也可以包括链接在一起的一个或多个配置节点以及一个或多个接收节点RX_buf1_1、RX_buf1_2等。更一般地，DMA配置链表、DMA发送链表以及DMA接收链表可以实现在相同或不同的链表中，而不脱离本发明的范围。
应理解，在上述实施例中，SPI传输计划实施为DMA配置链表，但DMA配置链表仅仅是SPI传输计划的一种实现方式。本领域技术人员应理解，本文所述SPI传输计划可以采用不同于链表的数据结构实现，和/或可以存储在不同的存储装置中。
在本发明的方案中，在连续的多次SPI传输之间需要对SPI控制器中的寄存器组进行更新。在本发明的一个实施例中，上述SPI工作配置的信息包括与所述SPI工作配置对应的一个或多个寄存器的值，因此，在改变SPI工作配置时，该一个或多个寄存器的值将整体更新。
在本发明的一个优选实施例中，上述SPI工作配置的信息包括当前配置节点的SPI工作配置对应的一个或多个寄存器的值与DMA配置链表中的上一配置节点的SPI工作配置对应的一个或多个寄存器的值之间的差异。进一步，所述DMA配置缓冲区中的一块区域中指定位置的一个或多个比特中的每个比特对应于当前配置节点的SPI工作配置对应的一个或多个寄存器中 的一个寄存器，指示与上一配置节点的SPI工作配置相比该寄存器的值是否发生改变，所述方法优选地还包括：在将该SPI工作配置写入所述寄存器组时，仅更新与上一配置节点的SPI工作配置相比发生改变的寄存器的值。换言之，本发明进一步提供了一种更新SPI控制器的寄存器组中的寄存器的内容的方案。
例如，下面的表5给出了根据本发明一个实施例的SPI分段配置传输模式寄存器按位配置映射表。
表5：SPI寄存器按位配置映射表
配置映射位 寄存器名 配置映射位 寄存器名
0 SPI_CMD 14 SPI_HOLD
1 SPI_ADDR 15 SPI_DMA_INT_ENA
2 SPI_CTRL 16 SPI_DMA_INT_RAW
3 SPI_CTRL1 17 SPI_DMA_INT_CLR
4 SPI_CTRL2 18 SPI_DIN_MODE
5 SPI_CLOCK 19 SPI_DIN_NUM
6 SPI_USER 20 SPI_DOUT_MODE
7 SPI_USER1 21 SPI_DOUT_NUM
8 SPI_USER2 22 SPI_LCD_CTRL
9 SPI_MOSI_DLEN 23 SPI_LCD_CTRL1
10 SPI_MISO_DLEN 24 SPI_LCD_CTRL2
11 SPI_MISC 25 SPI_LCD_D_MODE
12 SPI_SLAVE 26 SPI_LCD_D_NUM
13 SPI_FSM - -
为减小硬件开销，在本发明的一个实施例中，用每个配置缓冲区中存放的前几个字(WORD)来判断是否需要重置SPI控制器的相关寄存器，并把这些字称为比特映射值SPI_BIT_MAP_REG。在本发明的一个实施例中，比特映射值存储于配置缓冲区中。在本发明的另一实施例中，比特映射值存储于寄存器中。存储比特映射值的寄存器可称为“比特映射寄存 器”。应理解，在本发明的实施例中，比特映射寄存器可以实现为专用于存储比特映射值，也可以实现为存储比特映射值之外的其他值。在本发明的一个实施例中，用配置缓冲区的第一个字中的低位27个比特作为比特映射值来判断是否需要重置SPI控制器的27个寄存器，当然可以通过增加配置缓冲区的第二个字、第三个字……的方式来作为比特映射值以适应重置更多寄存器的情形。应理解，在本实施例中，“字”可以是32比特，但本发明的实现不限于此。也可以使用32比特以上或以下的字来实现本发明。
在本发明的一个实施例中，可以定义：如果在比特映射值中用于判断的比特的值为1，则需要重置对应的寄存器；如果用于判断的比特的值为0，则不重置对应的寄存器。因此，在DMA控制的分段配置传输模式中，可以先配置好所有的寄存器，然后在任何一次分段配置传输的配置缓冲区中，配置与上一次分段配置传输不同的寄存器，从而重置需要修改的SPI寄存器，从而极大地减少硬件配置的时间和软件配置复杂度。如果某次分段配置传输的操作模式与上一次的相同，则该次分段配置的配置缓冲区中的比特映射值SPI_BIT_MAP_REG全为0，不用重置SPI控制器的寄存器。
下面的表6给出了根据本发明的SPI寄存器按位配置映射实例。例如一次分段配置的配置缓冲区的第一个字的低27位如表6中所示，则该次分段配置传输需要重置的寄存器为SPI_ADDR、SPI_CTRL、SPI_CLOCK、SPI_USER和SPI_USER1。
表6：SPI寄存器按位配置映射表
Figure PCTCN2021103232-appb-000011
Figure PCTCN2021103232-appb-000012
此外，为提高分段配置传输的可靠性，在本发明的一个实施例中，将所述DMA配置缓冲区中的一块区域中指定位置的多个比特设置为误差校验数，且在所述SPI控制器内部提供误差校验基准数；及仅当所述误差校验数与所述误差校验基准数符合预先指定的关系时，才从下一次SPI传输对应的配置节点的在DMA配置缓冲区中的一块区域中读取与下一次SPI传输对应的SPI工作配置，并将该SPI工作配置写入所述寄存器组。
在本发明的非限制性实施例中，在每个配置缓冲区的第一个字中加入误差校验数，以下称为第一魔术数，例如本发明中用配置缓冲区第一个字的高5位作为第一魔术数。当然第一魔术数可以在配置缓冲区中的任意位置。SPI控制器内部有一个配置缓冲区无法修改的正确的误差校验基准数，以下称为第二魔术数，可以规定配置缓冲区中的第一魔术数与SPI控制器内部的第二魔术数必须满足指定的关系，才能配置SPI控制器的寄存器成功，DMA控制的分段配置传输继续进行；否则配置失败，DMA控制的分段配置传输结束，同时给出中断和错误标志。
两个魔术数满足的指定关系可以是两者必须相等，或者两者的CRC校验值必须相等，或者两者按位异或值为0，或者按位同或值为0等等。应理解，两个魔术数之间的指定关系可以根据实现需要来确定，而不脱离本发明的范围。
例如，在图4所示实施例中，SPI控制器可以通过DMA控制的分段 配置传输模式，在不同的分段配置传输中，分时访问闪存、SRAM、LCD。只需分别在访问闪存404、SRAM 406、LCD 408前的配置缓冲区中配置访问闪存404、SRAM 406、LCD 408时需要修改的相关寄存器，同时确保所有的Conf_buf中的第一魔术数正确即可。
作为非限制示例，在根据本发明的SPI控制器和操作SPI控制器的方法中，DMA控制的分段配置传输采用的技术手段可以包括：
1)建立了DMA配置缓冲区中的比特映射值SPI_BIT_MAP_REG与SPI寄存器之间的映射关系，通过SPI_BIT_MAP_REG的比特值决定是否更新对应的寄存器；
2)用魔术数确保通信的正确性和安全性；及
3)借助DMA来实现分段的SPI传输，同时每段SPI传输的类型都可以独立控制。根据本发明DMA控制的分段配置传输可以用作握手机制，可仅读写大量数据，还可以分时访问多个不同的外设。
相比之下，现有技术中的SPI控制器及其操作方法在执行连续的SPI传输时，CPU需要在两次SPI传输之间先取得控制，且必须要在SPI状态机回到空闲状态时，CPU才能更新寄存器组，其结果是可能在时间上来不及更新寄存器，无法实现任意两次分段配置传输间的工作配置的无缝切换。本发明的分段配置传输模式，在配置状态下进行SPI寄存器组的更新，且可以从完成状态直接进入配置状态，从而极大减少配置时间，提高数据的吞吐率。换言之，根据本发明，SPI控制器进行多次SPI传输的过程中一直处于工作模式(非空闲状态)，且能够灵活配置每次SP传输的工作配置。
图9示意性地示出根据本发明的SPI控制器访问并行8位RGB格式LCD所使用的帧格式。在图9中，一帧LCD输出数据900包括有效数据区906及上空白区902、下空白区910、前空白区904和后空白区908。在本发明的一个实施例中，各区的尺寸如图9所示，总体上，一帧LCD输出数据900的宽度为SPI_LCD_HT_WIDTH[11:0]，高度为SPI_LCD_VT_HEIGHT[9:0]；上空白区902的宽度与LCD帧900相同，高度为SPI_LCD_VB_FRONT[7:0]；有效数据区906的宽度为 SPI_LCD_HA_WIDTH[11:0]，高度为SPI_LCD_VA_HEIGHT[9:0]；左空白区904的宽度为SPI_LCD_HB_FRONT[10:0]，高度与有效数据区高度相同。基于上述，右空白区908以及下空白区的尺寸可以简单地通过减法确定。在本实施例中，诸如[11:0]的符号表示一个字中的低12位比特。
图10示意性地示出根据本发明的SPI控制器访问并行8位RGB格式LCD的时序图1000。
时序图1000的横轴表示时间，而在纵向上排列的多行图表表示SPI参数之间的时间关系。在图10中，SPI_VSYNC表示SPI帧频信号引脚上的帧频信号，SPI_HSYNC表示SPI行频信号引脚上的行频信号。例如，SPI_VSCNC的上升沿表征新的一帧图像开始传输；SPI_HSYNC的上升沿表征图像中的一行图像数据开始传输。SPI_DE表示SPI显示有效信号引脚上的显示有效信号，取值为0或1，表示SPI输入输出引脚上当前是否存在有效信号。SPI_IO[7:0]表示8个SPI输入输出引脚上的数据信号。SPI_CLK表示SPI时钟信号。其中SPI命令/数据信号SPI_CD用于表征Command/DATA信号，可应用于摩托罗拉6800、英特尔8080LCD接口)。
如图10所示，帧频信号或帧定时SPI_VSYNC的周期表示一帧的时长，行频信号或行定时SPI_HSYNC的周期表示一行的时长。SPI控制器首先通过帧定时检测一帧的开始，然后通过行定时检测一行的长度。根据本发明的非限制性实施例，SPI状态机配置为在前空白区中启用“配置”状态，在有效数据区中启用“输出”状态，在上空白区、下空白区和后空白区中启用除“输出”和“空闲”外的任意状态；在“配置”状态下加载SPI工作配置；并在“输出”状态下每次输出一行LCD输出数据。
根据本发明的SPI控制器不仅能访问1/2/4/8等多数据通道SPI外设，而且还支持对摩托罗拉6800/英特尔8080/并行8位RGB格式的LCD接口外设的访问，从而进一步拓展SPI控制器的通用性。
图10示出了SPI控制器通过DMA控制的分段配置传输模式，访问并行8位RGB格式LCD的时序图。在该传输模式中，选取“空闲”、“配置”、“输出”和“完成”状态，在“配置”状态下加载DMA配置缓冲区 Conf_buf，在“配置”状态不修改SPI控制器的寄存器；在“输出”状态下每次输出一行LCD RGB数据。作为非限制实施例，可以提前在DMA配置链表或DMA TX链表中配置好配置缓冲区和发送缓冲区(TX_buf)，配置缓冲区中除了正确的第一魔术数外，其他值都为0，TX_buf刚好存一行的LCD RGB数据。可以用乒乓缓存或环形缓存的方式，实现一直输出新的LCD RGB数据。通过本发明的DMA控制的分段配置传输模式，SPI控制器可以连续传输整帧或多帧LCD RGB数据，而无需CPU的干预或操作。
应理解，本文所述配置缓冲区、发送缓冲区和输入缓冲区可以是系统内存中的区域或者SPI控制器中设置的存储器中的区域，例如可以RAM中的区域，或者替代地是DRAM、SDRAM、SDRAM或PSRAM中的区域。优选地，所述配置缓冲区、发送缓冲区和输入缓冲区是系统内存中的区域。
相比于现有的SPI控制器，本发明的SPI的控制器增加了SPI_CD、SPI_VSYNC、SPI_HSYNC和SPI_DE信号线，增加“配置”状态，增加LCD模式，增加了在每个状态下，对SPI_CD、SPI_VSYNC、SPI_HSYNC和SPI_DE信号线的控制逻辑。
应理解，虽然图8至图10示出了在SPI主机上的SPI控制器与SPI从机进行交互的实施例，但本发明的原理同样可以应用于SPI从机上的SPI控制器。
图11示意性地示出根据本发明的更新寄存器的方法实施例的流程图。如图11所示，更新寄存器的方法1100开始于步骤1102，其中提供一个或多个比特映射寄存器。在步骤1104，提供一个或多个目标寄存器。在步骤1106，建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的映射。在步骤1108，提供寄存器更新指令。特别是，所述寄存器更新指令可以包括：指定位置的一个或多个标志比特，其中每个标志比特对应于所述一个或多个比特映射寄存器中的一个比特位，指示对应于该比特位的目标内容块是否需要更新。进一步，对于由所述比特位指示需要更新的每个目标内容块，所述寄存器更新指令还包括该目标内容块的新内容或新内容的来源。在步骤1110，将所述 寄存器更新指令中的所述一个或多个标志比特写入所述一个或多个比特映射寄存器。在步骤1112，由更新控制器根据所述一个或多个比特映射寄存器中的比特位执行所述寄存器更新指令，以更新所述一个或多个目标寄存器中的目标内容块，其中仅更新由所述比特位指示需要更新的每个目标内容块。在本发明的一个实施例中，更新控制器由CPU之外的逻辑电路实现，例如但不限于，SPI控制器中的输入输出控制器，或嵌入式设备模块中的其他控制逻辑。由此，根据本发明的实施例，目标寄存器的更新不需要由CPU干预，不占用CPU资源。
图12示意性地示出根据本发明的更新寄存器的方法的一个实施例中的映射框图1200。可选地，建立比特映射寄存器1202a中的每个比特位[31:0]与所述一个或多个目标寄存器1204中对应的目标内容块之间的映射的步骤包括：建立比特映射寄存器1202a的比特位[31:0]中的每个比特位与所述一个或多个目标寄存器中对应的目标内容块1204a0-1204a31之间的直接对应关系。
在本发明的一个实施例中，所述目标内容块的大小固定，其中建立所述每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的直接对应关系包括建立所述每个比特位与所述一个或多个目标寄存器中对应的目标内容块的起始地址之间的对应关系。如图12所示，可以将比特映射寄存器1202a中的位置0处的比特位映射到目标内容块1204a0的起始地址。
图13示意性地示出根据本发明的更新寄存器的方法的另一实施例中的映射的框图1300。在本发明的替代实施例中，该方法还可以包括提供一个或多个地址映射寄存器，例如1303，每个地址映射寄存器包括一组或多组内容块地址信息，例如地址映射寄存器1303包括内容块地址信息1303a0-1303a31…。在本发明的实施例中，建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个目标寄存器中对应的目标内容块之间的映射的步骤包括：建立所述一个或多个比特映射寄存器中的每个比特位与所述一个或多个地址映射寄存器中的一组内容块地址信息之间的对应关系； 及建立所述一个或多个地址映射寄存器中的所述一组内容块地址信息与所述一个或多个目标寄存器中对应的目标内容块之间的对应关系，其中根据所述内容块地址信息定位所述对应的目标内容块。
如图13所示，所述内容块地址信息1303a0包括内容块起始地址Addr0和内容块大小Size0。替代地，所述内容块地址信息可以包括内容块起始地址和内容块结束地址(未示出)。
在本发明的实施例中，由更新控制器根据所述一个或多个比特映射寄存器中的比特位执行所述寄存器更新指令，以更新所述一个或多个目标寄存器中的目标内容块的步骤包括：对于所述一个或多个比特映射寄存器中的每个比特位，根据所述映射，定位所述比特位对应的目标内容块；及如果所述比特位指示对应于该比特位的目标内容块是否需要更新，则用目标内容块的新内容更新所述目标内容块。以此方式，在本发明的实施例中，可以快速且可靠地更新一个寄存器或者多个寄存器(例如寄存器组)中的目标内容块的内容。
在本发明的一个优选实施例中，所述一个或多个标志比特位于所述寄存器更新指令的头部中。例如，取决于所需更新目标内容块的数量，标志比特位可以位于寄存器更新指令的前1个字、2个字或更多字中。
应理解，本发明的更新寄存器的方法优选地用在嵌入式设备中。所述新内容的来源可以包括内存、寄存器、闪存中的一个或多个。更加优选地，更新控制器是嵌入式设备中的模块，例如包括但不限于SPI控制器、I 2S、I 2C、DMA、UART等模块。嵌入式设备例如可以包括但不限于MCU。以此方式，本发明的更新寄存器方法由嵌入式设备中的模块执行，不占用CPU资源，且能够方便地批量更新多个模块的寄存器。在一个实施例中，嵌入式设备中的多个模块设置有各自的寄存器组，寄存器组中当前的寄存器值反映各模块的当前工作配置。通过本发明的方案可以快速且可靠地更新多个模块的寄存器组，从而快速、批量地切换这些模块的工作配置。
虽然出于本公开的目的已经描述了本发明各方面的各种实施例，但是不应理解为将本公开的教导限制于这些实施例。在一个具体实施例中公 开的特征并不限于该实施例，而是可以和不同实施例中公开的特征进行组合。例如，在一个实施例中描述的根据本发明的装置或方法的一个或多个特征和/或操作，亦可单独地、组合地或整体地应用在另一实施例中。此外，应理解，上文所述方法步骤可以顺序执行、并行执行、合并为更少步骤、拆分为更多步骤，以不同于所述方式组合和/或省略。本领域技术人员应理解，还存在可能的更多可选实施方式和变型，可以对上述方法步骤进行各种改变和修改，而不脱离由本发明权利要求所限定的范围。

Claims (21)

  1. 一种SPI控制器，包括：
    SPI时钟信号产生器，其配置为产生SPI时钟信号；
    寄存器组，其配置为保存所述SPI控制器的SPI工作配置；
    多个SPI引脚，其配置为连接到一个或多个SPI外设；及
    输入输出控制器，其配置为根据所述SPI时钟信号及所述SPI工作配置，执行所述SPI控制器与所述SPI外设之间的数据输入或输出；
    SPI状态机，其配置为控制所述SPI控制器的工作状态；
    其中所述SPI控制器通过总线电耦合到位于所述SPI控制器外部的CPU、DMA控制器及系统内存；及
    所述输入输出控制器还配置为在连续的两次SPI传输之间，从所述DMA控制器接收更新的SPI工作配置并将所述更新的SPI工作配置更新到所述寄存器组中。
  2. 根据权利要求1所述的SPI控制器，其特征在于，所述SPI状态机配置为包括按顺序循环的下述状态：
    “空闲”状态，用于表征SPI控制器处于不工作状态；
    “配置”状态，用于由所述输入输出控制器从所述DMA控制器接收SPI工作配置并将所述SPI工作配置更新到所述寄存器组中；
    “准备”状态，用于控制SPI的片选建立时间；
    “命令”状态，用于SPI控制器发送SPI命令，并控制SPI命令所持续的时钟周期数；
    “地址”状态，用于SPI控制器发送SPI地址，并控制SPI地址所持续的时钟周期数；
    “等待”状态，用于SPI控制器根据SPI从设备的要求，控制等待传输SPI有效数据的时钟周期数；
    “输出”状态，用于SPI控制器控制输出数据的时钟周期数；
    “输入”状态，用于SPI控制器控制输入数据的时钟周期数；及
    “完成”状态，用于控制SPI的片选保持时间。
  3. 根据权利要求2所述的SPI控制器，其特征在于，所述寄存器组还配置为独立地保存与所述SPI状态机中的多个工作状态中的每个工作状态对应的SPI工作配置。
  4. 根据权利要求2所述的SPI控制器，其特征在于，所述SPI控制器配置为能够以CPU控制模式或DMA控制模式操作；
    当所述SPI控制器配置为以CPU控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过；及
    当所述SPI控制器以DMA控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过，且所述“空闲”状态配置为能够被跳过以直接从“完成”状态进入“配置”状态。
  5. 根据权利要求1所述的SPI控制器，其特征在于，所述SPI工作配置包括下述模式中的一种或多种模式的组合：1/2/4/8数据通道模式、SPI时钟模式、SDR/DDR数据采样模式、全双工/半双工通信模式。
  6. 根据权利要求1所述的SPI控制器，其特征在于，所述SPI控制器还包括下述组件中的一个或多个：
    SPI时钟模式控制模块，其配置为调整输出时钟信号的极性和相位；
    输入输出时序调节模块，其配置为调节SPI输入输出的时序；
    SPI缓存，其用于缓存SPI控制器在CPU控制下与SPI外设进行交互的数据；及
    中断控制模块，其用于SPI控制器在完成指定的传输后，产生对应的中断，并通过总线将中断传给CPU。
  7. 根据权利要求1所述的SPI控制器，其特征在于，所述多个SPI引脚包括一个或多个SPI片选引脚、一个或多个SPI时钟引脚，及一个或多个SPI输入输出引脚。
  8. 根据权利要求7所述的SPI控制器，其特征在于，所述多个SPI引脚还包括SPI命令/数据信号引脚、SPI帧频信号引脚、SPI行频信号引脚，及SPI显示有效信号引脚。
  9. 根据权利要求1所述的SPI控制器，其特征在于，所述SPI控制器布置在嵌入式设备中，且所述总线是片内总线。
  10. 一种操作SPI控制器的方法，所述SPI控制器通过总线与CPU和DMA控制器电耦合，并通过多个SPI引脚与一个或多个SPI外设电耦合，其中所述SPI控制器包括寄存器组且配置为能够以CPU控制模式或DMA控制模式操作，所述方法包括：
    S1)确定与所述一个或多个SPI外设中的每个SPI外设对应的一个或多个SPI工作配置；
    S2)创建SPI传输计划，所述SPI传输计划包括对所述一个或多个SPI外设进行的多次SPI传输、所述多次SPI传输的执行顺序及所述多次SPI传输中的每次SPI传输对应的SPI工作配置，其中所述SPI控制器根据所述对应的SPI工作配置执行每次SPI传输；及
    S3)在所述DMA控制器的控制下执行设定的SPI传输计划，其中按照所述执行顺序执行所述多次SPI传输，并根据对应的SPI工作配置执行当前的SPI传输，且其中在一次SPI传输完成后，由所述DMA控制器将当前的SPI工作配置修改为与下一次SPI传输对应的SPI工作配置。
  11. 根据权利要求10所述的方法，其特征在于，根据SPI状态机操作所述SPI控制器，所述SPI状态机配置为包括按顺序循环的下述状态：
    “空闲”状态，用于表征SPI控制器处于不工作状态；
    “配置”状态，用于由所述输入输出控制器从所述DMA控制器接收SPI工作配置并将所述SPI工作配置更新到所述寄存器组中；
    “准备”状态，用于控制SPI的片选建立时间；
    “命令”状态，用于SPI控制器发送SPI命令，并控制SPI命令所持续的时钟周期数；
    “地址”状态，用于SPI控制器发送SPI地址，并控制SPI地址所持续的时钟周期数；
    “等待”状态，用于SPI控制器根据SPI从设备的要求，控制等待传输SPI有效数据的时钟周期数；
    “输出”状态，用于SPI控制器控制输出数据的时钟周期数；
    “输入”状态，用于SPI控制器控制输入数据的时钟周期数；及
    “完成”状态，用于控制SPI的片选保持时间。
  12. 根据权利要求11所述的方法，其特征在于，所述SPI状态机中的每个工作状态配置为具有各自的SPI工作配置。
  13. 根据权利要求11所述的方法，其特征在于，当所述SPI控制器配置为以CPU控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过；及
    当所述SPI控制器以DMA控制模式操作时，除“空闲”状态之外的其他状态配置为能够被跳过，且所述“空闲”状态配置为能够被跳过以直接从“完成”状态进入“配置”状态。
  14. 根据权利要求10所述的方法，其特征在于，所述SPI工作配置包括下述模式中的一种或多种模式的组合：1/2/4/8数据通道模式、SPI时钟模式、SDR/DDR数据采样模式、全双工/半双工通信模式。
  15. 根据权利要求10所述的方法，其特征在于，提供包含一个或多个配置节点的DMA配置链表，其中每个配置节点对应于一次SPI传输，且包含与该次SPI传输对应的一个SPI工作配置并链接到该次SPI传输的发送数据链表，所述发送数据链表链接到下一个配置节点，该SPI工作配置的信息保存在DMA配置缓冲区中的一块区域中；及
    在一次SPI传输完成后，由所述DMA控制器将当前的SPI工作配置修改为与下一次SPI传输对应的SPI工作配置包括：从DMA配置缓冲区中对应下一次SPI传输的配置节点的一块区域中，读取与下一次SPI传输对应的SPI工作配置，并将该SPI工作配置写入所述寄存器组。
  16. 根据权利要求15所述的方法，其特征在于，若该次SPI传输包括“输出”状态，则所述配置节点链接到该次SPI传输的发送数据链表，所述发送数据链表链接到下一个配置节点；否则，所述配置节点直接链接到下一个配置节点。
  17. 根据权利要求15所述的方法，其特征在于，所述SPI工作配置的信 息包括与所述SPI工作配置对应的一个或多个寄存器的值。
  18. 根据权利要求15所述的方法，其特征在于，所述SPI工作配置的信息包括当前配置节点的SPI工作配置对应的一个或多个寄存器的值与DMA配置链表中的上一配置节点的SPI工作配置对应的一个或多个寄存器的值之间的差异。
  19. 根据权利要求18所述的方法，其特征在于，所述DMA配置缓冲区中的一块区域中指定位置的一个或多个比特中的每个比特对应于当前配置节点的SPI工作配置对应的一个或多个寄存器中的一个寄存器，指示与上一配置节点的SPI工作配置相比该寄存器的值是否发生改变，所述方法还包括：
    在将该SPI工作配置写入所述寄存器组时，仅更新与上一配置节点的SPI工作配置相比发生改变的寄存器的值。
  20. 根据权利要求15所述的方法，其特征在于，将所述DMA配置缓冲区中的一块区域中指定位置的多个比特设置为误差校验数，且在所述SPI控制器内部提供误差校验基准数；及
    仅当所述误差校验数与所述误差校验基准数符合预先指定的关系时，才从下一次SPI传输对应的配置节点的在DMA配置缓冲区中的一块区域中读取与下一次SPI传输对应的SPI工作配置，并将该SPI工作配置写入所述寄存器组。
  21. 根据权利要求11所述的方法，其特征在于，当所述SPI外设为LCD时，执行下述步骤：提供LCD输出数据，所述LCD输出数据包括有效数据区及上空白区、下空白区、前空白区和后空白区；
    配置所述SPI状态机在所述前空白区中启用“配置”状态，在所述有效数据区中启用“输出”状态，在所述上空白区、所述下空白区和所述后空白区中启用除“输出”和“空闲”外的任意状态；
    在“配置”状态下加载SPI工作配置；
    在“输出”状态下每次输出一行LCD输出数据。
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