WO2022068743A1 - 一种改变工作模式的方法、芯片系统及通信系统 - Google Patents

一种改变工作模式的方法、芯片系统及通信系统 Download PDF

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Publication number
WO2022068743A1
WO2022068743A1 PCT/CN2021/120781 CN2021120781W WO2022068743A1 WO 2022068743 A1 WO2022068743 A1 WO 2022068743A1 CN 2021120781 W CN2021120781 W CN 2021120781W WO 2022068743 A1 WO2022068743 A1 WO 2022068743A1
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Prior art keywords
code stream
response code
working mode
chip system
pulse width
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PCT/CN2021/120781
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English (en)
French (fr)
Inventor
眭克涵
万杰
祝栋柯
罗飞
许仕彬
李永耀
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华为技术有限公司
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Publication of WO2022068743A1 publication Critical patent/WO2022068743A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/04—TPC
    • H04W52/18—TPC being performed according to specific parameters
    • H04W52/28—TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non transmission
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a method for changing a working mode, a chip system and a communication system.
  • a terminal device often sets a transitional working mode with low power consumption, which can quickly connect to other working modes of the device.
  • the CPU Central Processing Unit, central processing unit
  • the clear photo is presented to the user, and the link in the camera-CPU direction has been in a high-speed transmission state.
  • the power consumption is large.
  • the user is not always in the state of shooting, and often stops shooting for a while.
  • the present application provides a method for changing a working mode, a chip system and a communication system, which reduce the energy consumption of the communication system.
  • a method for changing a working mode is provided, and the method is applied to a communication system including a first system-on-chip and a second system-on-chip, wherein the first system-on-chip has a sending port, and the second system-on-chip has A receiving port has a communication link between the sending port and the receiving port.
  • the method includes generating a first response code stream when the working mode of the sending port is switched, and using a pulse width coefficient K to process each bit in the first response code stream to obtain a second response code stream , wherein each bit in the first response code stream appears K consecutive times in the second response code stream; the second response code stream is sent to the receiving port through the sending port; Receive the second response code stream through the receiving port, and obtain the switched working mode of the receiving port by reading the second response code stream; switch the working mode of the receiving port to the switched working mode working mode.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • the pulse width coefficient K is determined according to the transmission rate fb of the sending port and the local reference clock Refclk of the sending port before the working mode of the sending port is switched.
  • the number of times that each bit in the second response code stream lasts is determined by the transmission rate and the local reference clock.
  • the reading the second response code stream specifically refers to: reading the second response code stream within a pulse width detection period.
  • the operating modes include a high-speed transmission mode, a low-speed transmission mode, a low power consumption mode, an ultra-low power consumption mode, and a reset mode. So as to achieve different data transmission requirements.
  • the generating the first response code stream occurs before the switching of the working mode of the sending port occurs, or after the switching occurs.
  • the switching of the first response code stream and the sending port can be performed in different sequences.
  • the first response code stream may include, but is not limited to, a code stream for carrying wake-up, reset, sleep and other instructions. Thereby different states can be indicated.
  • a method for changing a working mode includes: when a working mode of a sending port is switched, generating a first response code stream, and using a pulse width coefficient K to compare the content of the first response code stream in the first response code stream. process each bit of , to obtain a second response code stream, wherein each bit in the first response code stream appears K consecutive times in the second response code stream; The stream is sent to the receiving port of the opposite-end chip system, so that the opposite-end chip system receives the second response code stream through the receiving port, and obtains the switch of the receiving port according to the second response code stream. working mode, and switching the working mode of the receiving port to the switched working mode.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • the pulse width coefficient K is determined according to the transmission rate fb of the sending port and the local reference clock Refclk of the sending port before the working mode of the sending port is switched.
  • a method for changing a working mode comprising: receiving a second response code stream through a receiving port, where the second response code stream is a pulse width coefficient K for each of the first response code streams. obtained by processing one bit, wherein each bit in the first response code stream appears K consecutive times in the second response code stream, and the first response code stream is the same as the receiving port.
  • the working mode of the sending ports with the link relationship changes, generated by the chip system where the sending port is located; read the second response code stream and obtain the switched working mode; switch the receiving port to the switched operating mode.
  • the object to be identified is the first response code stream.
  • the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • the pulse width coefficient K is determined according to the transmission rate fb of the sending port and the local reference clock Refclk of the sending port before the working mode of the sending port is switched.
  • the reading the second response code stream and obtaining the switched working mode is specifically: reading the second response code stream through a pulse width detection circuit, and reading the second response code stream according to the pulse width detection circuit.
  • the second response code stream identified by the wide detection circuit acquires the switched working mode carried by the second response code stream.
  • a chip system in a fourth aspect, includes: a sending port and a controller; the controller is configured to generate a first response code stream when the working mode of the sending port is switched; using a pulse width coefficient K processes each bit in the first response code stream to obtain a second response code stream, wherein each bit in the first response code stream appears continuously in the second response code stream K times; the controller is further configured to control the sending port to send the second response code stream to the opposite-end chip system.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • the controller is further configured to determine the pulse rate according to the transmission rate fb of the sending port and the local reference clock Refclk of the sending port before switching the working mode of the sending port. Width factor K.
  • a chip system in a fifth aspect, includes a chip and a detection circuit; wherein, the chip has a receiving port; the receiving port is used for receiving a second response code stream sent by the opposite end chip system; the The second response code stream is obtained by using the pulse width coefficient K to process each bit in the first response code stream, wherein each bit in the first response code stream is in the second response code stream
  • the chip system where the sending port is located is generated; the detection a circuit for reading the second response code stream; the controller is further configured to obtain the switched working mode of the receiving port according to the second response code stream read by the detection circuit, and control all The receiving port is switched to the switched working mode.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • the pulse width coefficient K is determined according to the transmission rate fb of the sending port and the local reference clock Refclk of the sending port before the working mode of the sending port is switched.
  • the detection circuit is a pulse width detection circuit.
  • the second response code stream is detected by detecting the level duration.
  • a communication system in a sixth aspect, includes a first system-on-chip and a second system-on-chip, wherein the first system-on-chip is the system-on-chip described in any of the above, and the second system-on-chip It is the chip system according to any one of the above; there is a communication link between the sending port and the receiving port.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • a mobile terminal in a seventh aspect, includes a first system-on-chip and a second system-on-chip, wherein the first system-on-chip is the system-on-chip described in any one of the above, and the second system-on-chip It is the chip system according to any one of the above; there is a communication link between the sending port and the receiving port.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, the first response code stream needs to be identified by means of PLL and CDR. contained information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • an embodiment of the present application provides a communication apparatus, where the communication apparatus includes a processor, configured to implement the method described in the second aspect or the third aspect.
  • the communication device may also include a memory for storing instructions and data.
  • the memory is coupled to the processor, and when the processor executes the program instructions stored in the memory, the method described in the second aspect or the third aspect can be implemented.
  • the communication apparatus may also include a communication interface, and the communication interface is used for the apparatus to communicate with other devices.
  • the communication interface may be a transceiver, a circuit, a bus, a module or other types of communication interfaces, and other devices may For network equipment or terminal equipment, etc.
  • the communication apparatus includes: a memory for storing program instructions; a processor for invoking the instructions stored in the memory, so that the apparatus executes the first aspect of the present application and any one of the first aspects A possible design method, or any possible design method in the second aspect and the second aspect of the present application, or any possible design method in the third aspect and the third aspect of the present application.
  • an embodiment of the present application further provides a computer-readable storage medium, including instructions, which, when run on a computer, enable the computer to execute the first aspect of the present application and any possible design method in the first aspect , or any possible design method in the second aspect and the second aspect of the present application, or any possible design method in the third aspect and the third aspect of the present application.
  • the embodiments of the present application further provide a computer program product, including instructions, when running on a computer, the computer program product that enables the computer to execute the first aspect of the present application and any one of the possible designs in the first aspect, method, Or any possible design method in the second aspect and the second aspect of the present application, or any possible design method in the third aspect and the third aspect of the present application.
  • a computer program product including instructions, when running on a computer, the computer program product that enables the computer to execute the first aspect of the present application and any one of the possible designs in the first aspect, method, Or any possible design method in the second aspect and the second aspect of the present application, or any possible design method in the third aspect and the third aspect of the present application.
  • FIG. 1 is a scenario of an application of a chip system provided in an embodiment of the present application in a communication system
  • FIG. 2 is a scenario applied in a system-on-a-chip storage system provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of a simplified architecture of a chip system provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a working mode of a chip system provided by an embodiment of the present application.
  • FIG. 5 is a link topology of a communication system provided by an embodiment of the present application.
  • FIG. 6 is a structural block diagram of a communication system provided by an embodiment of the present application.
  • FIG. 7 is a waveform diagram corresponding to a wake-up 1 command provided by an embodiment of the present application.
  • FIG. 8 is a waveform diagram corresponding to a wake-up 2 command provided by an embodiment of the present application.
  • FIG. 9 is a waveform diagram corresponding to a reset 1 command provided by an embodiment of the present application.
  • FIG. 10 is a waveform diagram corresponding to a reset 2 command provided by an embodiment of the application.
  • FIG. 11 is a waveform diagram corresponding to a sleep 1 command provided by an embodiment of the present application.
  • FIG. 13 is a flowchart of a communication system provided by an embodiment of the present application.
  • FIG. 14 is a structural block diagram of a communication apparatus provided by an embodiment of the present application.
  • the chip system provided in the embodiments of the present application is applied to a common computer system or a communication system.
  • it is applied to various data communication links that require high-speed communication in terminal services.
  • Common scenarios include the processor-camera data communication link of terminal products such as mobile phones and tablets, the processor-display data communication link, and the data communication link between storage devices.
  • first chip system and second chip system are opposite-end chip systems.
  • first chip system and second chip system are opposite-end chip systems.
  • FIG. 1 shows a scenario in which the communication method provided by the embodiment of the present application may be applied in a terminal device.
  • the terminal device 200 includes a processor 210 , a camera module 220 , a display module 230 , a radio frequency module 240 , a storage module 250 , and the like, all of which can be regarded as a chip system.
  • the communication links 201 , 202 , 203 and 204 respectively represent the communication links between the processor 210 and the camera module 220 , the processor 210 and the display module 230 , the processor 210 and the radio frequency module 240 , and the processor 210 and the storage module 250 . .
  • the communication method provided by the embodiment of the present application can be applied to the port working modes on both sides of the data communication link such as 201 , 202 , 203 , and 204 for low power consumption management, so as to ensure stable and reliable data transmission in high-speed scenarios.
  • the chip systems at both ends of any communication link are the opposite end chip systems.
  • the processor 210 and the camera module 220 as an example, the processor 210 is the opposite end chip system of the camera module 220 , and the camera module 220 is the opposite end chip system of the processor 210 .
  • FIG. 2 shows a scenario in which the communication method provided by the embodiment of the present application may be applied in a storage device.
  • Data exchange is performed between the storage device 1 and the storage device 2 through the data port, and the receiving port between the two devices constitutes a data communication link 301 .
  • the communication method provided by the present application ensures the stable and reliable transmission of data in a high-speed scenario by performing low power consumption management on the port working modes on both sides of the data communication link such as 301 .
  • FIG. 3 shows a simplified schematic diagram of the architecture of a chip system 400 provided by an embodiment of the present application.
  • the chip system 400 is composed of a protocol layer 401 , a physical layer 402 (Physical Layer, PHY), and a medium 403 .
  • the protocol layer 401 may be composed of an application layer, a data link layer, etc.
  • the physical layer 402 is the layer to which the method of the present application is applied, and specifically includes a physical coding sublayer PCS (Physical Coding Sublayer), a physical medium additional sublayer PMA (Physical Coding Sublayer). Medium Attachment Sublayer) and Physical Media Dependent Sublayer PMD (Physical Media Dependent).
  • PCS Physical Coding Sublayer
  • PMA Physical Medium Attachment Sublayer
  • PMD Physical Media Dependent
  • the PMD is the electrical block responsible for serial signal transmission
  • the PMA is responsible for serialization/deserialization
  • the PCS is responsible for the encoding/decoding of the data stream.
  • the present application relates to the rapid response of devices in the physical layer 402 and the transition of operating modes.
  • the protocol layer interface is used to transmit the clock, data, control and other instructions of the protocol layer 401 .
  • the medium 403 includes actual physical channels, such as PCB (Printed Circuit Board, printed circuit board) traces, cables, and optical fibers.
  • the communication system (the first chip system, the second chip system) involved in this application can work in the working mode shown in FIG. 4 , and this working mode is limited to the communication link from one end device TX to the other end device RX , such as the transmitting port TX (Transmitter, transmitter) of the first chip system ⁇ the receiving port RX (Receiver, receiver) of the second chip system, TX of the second chip system ⁇ RX of the first chip system, etc.
  • the transmitting port TX (Transmitter, transmitter) of the first chip system ⁇ the receiving port RX (Receiver, receiver) of the second chip system
  • TX of the second chip system ⁇ RX of the first chip system, etc.
  • the communication link LINK including but not limited to the following working modes:
  • High-speed transmission mode The communication link LINK performs high-speed data information transmission (such as images, stored information, etc.), and its working mode can support multiple transmission rates, and the code stream transmitted in the high-speed transmission mode is a high-speed code stream.
  • Low-speed transmission mode The device mainly transmits some control information, such as some control code streams, etc., and its power consumption is higher than that of high-speed transmission, and the code stream transmitted in the low-speed transmission mode is a low-speed code stream.
  • Low-power mode This mode is the energy-saving mode of the device. This mode can support jumping to multiple working modes. It is a transitional working mode, and the power consumption is lower and the transmission mode is lower.
  • Ultra Low Power Mode This mode is the deep sleep mode of the device.
  • Reset mode This mode is the forced restart mode of the device. When a serious error is encountered, the device is forced to reset. In this mode, the device needs to re-establish a link and other operations.
  • working mode switching refers to switching from one working mode to another working mode.
  • the power mode can sleep into the ultra-low power mode, and wake up from the low power mode to enter the high-speed transmission mode or the low-speed transmission mode.
  • the communication system provided by the embodiment of the present application mainly improves the power consumption of the chip system when the working mode of the above-mentioned link is changed. It will be described in detail below.
  • the communication system includes a first chip system 500 and a second chip system 600 , and the sending ports and the receiving ports of the first chip system 500 and the second chip system 600 are connected in a one-to-one correspondence. It is assumed that the direction from the first chip system 500 to the second chip system 600 is four LANEs, such as four LANEs numbered 00, 01, 10, and 11. The direction from the second chip system 600 to the first chip system 500 is also four LANEs, such as four LANEs numbered 00, 01, 10, and 11.
  • the arrows represent the direction of data transmission, and the LANE in each transmission direction is logically encoded in the process of establishing a link (establishing a communication link).
  • the communication methods provided in the embodiments of the present application can be applied to any LANE, and the number and direction of the LANEs are not limited, so the conversion between modes on each LANE is independent.
  • the following takes two LANEs as an example for description.
  • the two LANEs are LANE1 in the direction from the first chip system 500 to the second chip system 600 , and LANE2 in the direction from the second chip system 600 to the first chip system 500 .
  • the communication system provided by the embodiment of the present application includes a first chip system 500 and a second chip system 600 , and the first chip system 500 and the second chip system 600 both include a protocol layer and a physical layer.
  • the function please refer to the related description in FIG. 3 , which will not be repeated here.
  • the first chip system 500 includes a first sending port 502 , a first receiving port 503 , a first controller 501 and a first detection circuit 504 .
  • the first sending port 502 is used for sending data and the first response code stream
  • the first receiving port 503 is used for receiving the data and the response code stream sent by the peer chip.
  • the first controller 501 is configured to receive an instruction of the protocol layer of the first system-on-a-chip 500, and control the first sending port 502 to send data and the second receiving port 603 to receive data according to the instruction.
  • the first controller 501 is further configured to feed back the data sent or received by the first sending port 502 and the first receiving port 503 to the protocol layer.
  • the first detection circuit 504 is used for identifying the response code stream sent by the second chip system received by the first receiving port 503 .
  • the first controller 501 is further configured to judge according to the response code stream detected by the first detection circuit 504, to determine the corresponding command information of the response code stream, and to control the working mode of the first receiving port 503 according to the command information. switch.
  • the controller refers to a circuit that can realize the control function.
  • the circuit that can realize the control function can be located in the chip or in the peripheral circuit of the chip, but in most cases, the circuit that can realize the control function
  • a functional circuit is a circuit located within a chip.
  • the above-mentioned first sending port 502 and the first receiving port 503 are the physical layer structure of the first chip system 500, which may specifically include the above-mentioned physical coding sublayer PCS, physical medium additional sublayer PMA and physical medium correlation.
  • the sublayer PMD has the function of processing data.
  • the first sending port 502 and the first receiving port 503 can implement the high-speed transmission mode, low-speed transmission mode, low power consumption mode, super power consumption mode and reset in the above-mentioned link mode, etc., and can switch among the above modes.
  • the first chip system 500 includes a chip and a peripheral circuit, where the peripheral circuit refers to a circuit connected to the chip and located around the chip, and used for processing signals and currents of the chip.
  • the first detection circuit 504 may be located in the chip, or may be located in a peripheral circuit outside the chip.
  • the first detection circuit 504 has the ability to identify the amplified waveform.
  • the first detection circuit 504 may be a pulse width detection circuit, which is used to detect the duration of the level.
  • the second chip system 600 includes a second sending port 602 , a second receiving port 603 , a second controller 601 and a second detection circuit 604 .
  • the second chip system 600 includes a second transmit port 602 and a second receive port 603 .
  • the above-mentioned structure of the second system-on-chip 600 may refer to the description of the structure of the same type of the above-mentioned first system-on-chip 500 , which is not repeated here.
  • the second chip system 600 includes a chip and a peripheral circuit, and the peripheral circuit refers to a circuit connected to the chip but not connected to the periphery of the chip, and is used for processing signals and currents of the chip.
  • the second detection circuit 604 may be located in the chip, or may be located in a peripheral circuit outside the chip.
  • the second detection circuit 604 has the ability to identify the amplified waveform.
  • the second detection circuit 604 may be a pulse width detection circuit, which is used to detect the duration of the level.
  • the link between the first sending port 502 and the second receiving port 603 is connected to form the LANE1 from the first chip system 500 to the second chip system 600, so as to realize the first
  • the chip system 500 transmits data to the second chip system 600 .
  • the link between the second sending port 602 and the first receiving port 503 is the LANE2 from the second system-on-a-chip 600 to the system-on-a-chip 500 , enabling the second system-on-a-chip 600 to send data to the system-on-a-chip 500 .
  • the above-mentioned two LANEs (LANE1 and LANE2) have the same manner for data transmission, so LANE1 is used as an example for description.
  • the response code stream is sent to the second receiving port 603 through the first sending port 502 , and the second chip system 600 identifies the response code stream by identifying the response code stream. Then switch the working mode.
  • each operating mode switch needs to use an independent and specific code stream (including high-speed and low-speed code streams).
  • One working mode switching, switching from a low power consumption mode to a high-speed transmission mode is another working mode switching, two different working mode switching Different working mode switching requires different specific code streams.
  • the specific code stream contains a combination of multiple "0” and “1” arrangements, where "0” represents a low level, and "1" represents a high level.
  • the second chip system 600 identifies the above-mentioned specific code stream, it needs to use the PLL and CDR to lock "0" and "1" in each bit in the response code stream for identification.
  • a specific code stream adopts a high-speed code stream, the transmission rate of the specific code stream is relatively fast, and the power consumption is relatively large when the PLL and CDR lock and identify "0” and “1” in each bit, which in turn causes the second chip The power consumption of the system 600 is relatively large.
  • the communication system provided by the embodiment of the present application adopts a new control code stream for handover, which will be described in detail below.
  • the first response code stream is a control code stream that controls the second receiving port 603 of the second system-on-chip 600 to switch the working mode.
  • the first chip system 500 uses the pulse width coefficient K to process each bit in the first response code stream to obtain a second response code stream, wherein each bit in the first response code stream appears K consecutive times in the second response code stream. That is, each bit in the first response code stream corresponds to K consecutive and repeated bits in the second response code stream.
  • the first response code stream is 101010
  • K is 4
  • the second response code stream is formed, the second response code stream is 111100001111000011110000.
  • the second detection circuit 604 identifies the duration of "1" and "0" in the second response code stream to identify the waveform formed by the second response code stream.
  • the waveform of the second response code stream is the same as that of the low-speed code stream by controlling the value of K.
  • the second response code stream forms the same waveform as the low-speed code stream when the first sending port 502 is at the transmission rate when the working mode is not switched.
  • the data packet is sent from the first sending port 502 to the second receiving port 603, and the second response code stream has one data packet or multiple data packets.
  • k is the pulse width coefficient of the waveform formed by the first sending port.
  • the pulse width detection cycle P Pulse Width detection cycle
  • N can be a decimal or a natural number.
  • the number of continuous bits of high level and low level in the first response code stream is determined by the value of k. Therefore, when the first sending port 502 has different transmission rates, the value of k can be used to determine To adjust the Bit (bit) duration of "0" and "1" in each Symbol (symbol) in the first response code stream to form a second response code stream, and the formed second response code stream at different transmission rates
  • bit (bit) duration of "0" and "1" in each Symbol (symbol) in the first response code stream to form a second response code stream
  • the formed second response code stream at different transmission rates
  • the same waveform is formed below (the waveform is equivalent to the waveform of the low-speed code stream).
  • Table 1 illustrates the local reference clock, bit time, and the time occupied by the Symbol and the pulse width detection period P of the first system-on-a-chip 500 under different transmission rates (in Table 1, the time T when the data packet is sent is replaced by ).
  • Table 2 illustrates the number of bits occupied by the high level and the low level of the second response code stream carrying different commands under different transmission rates in Table 1.
  • the transmission time of each bit is 20.83ns
  • k is 4
  • the transmission time of each symbol is 83.33ns
  • the transmission time of each data packet is 83.33ns.
  • the time is 2us.
  • the transmission time of each bit is 13.02ms
  • k 6
  • the transmission time of each symbol is 78.13ns
  • each The transmission time of the data packet is 1.875us.
  • the bits occupied by the second response code stream "1" are Bit0 ⁇ Bit(k-1), namely Bit0 ⁇ Bit5, occupying 6 bits in total, and "0" occupies Bitk ⁇ Bit (2k-1), namely Bit6 to Bit11, occupies 6 bits.
  • the first response code stream is "10".
  • the second response code stream is formed, "1" in the first response code stream appears 6 times in a row, and "0” appears 6 times continuously, forming "111111000000” " of the second response code stream.
  • the second detection circuit 604 has the ability to identify the amplified waveform.
  • the second detection circuit 604 may be a pulse width detection circuit, which is used to detect the duration of the level.
  • the second detection circuit 604 After the second response code stream continues each bit in the first response code stream for k times, it is equivalent to amplifying the corresponding waveform formed by the first response code stream.
  • the second detection circuit 604 The amplified waveform can be recognized.
  • the object to be identified is the first response code stream. Since the transmission rate of the first response code stream is relatively high and the period is small, it is necessary to use the PLL and CDR to identify the first response code stream contained in the information.
  • the waveform corresponding to the second response code stream can be understood to be obtained after K-fold amplification of the waveform corresponding to the first response code stream, and the waveform can be identified by the pulse width detection circuit of the second chip system , it no longer needs to be identified by PLL and CDR, so it can greatly reduce the power of the chip system in the communication system.
  • the amplified waveform formed by the second response code stream may be the same as the waveform formed by the low-speed code stream (which carries the same command as the second response code stream), and the second response code stream can be directly detected by the pulse width detection circuit.
  • the formed waveform can acquire the instruction carried by the second response code stream.
  • the value of k affects the number of consecutive occurrences of "1" and "0", that is, the number of bits occupied by "1” and “0”, which in turn affects the pulse width of the waveform formed by the second response code stream.
  • the transmission rate of the first sending port 502 changes, the number of bits occupied by each "0" and “1” in the second response code stream can be changed by correspondingly adjusting the k value, so that under different transmission rates, "1" and “1”
  • the duration of 0" is the same, so that the same waveform can be formed under different transmission rates, and the transmission rate of the first sending port 502 when the working mode is not switched will not affect the formed waveform.
  • the second system-on-a-chip 600 can perform detection by identifying the alternate "0" and "1" pulse width signal duty ratio (number of occupied bits) in the second response code stream, so as to obtain the switched operating mode of the second receiving port 603 .
  • the second response code stream provided by the embodiment of the present application when adopted, the second response code stream under different transmission rates can be normalized to form the same waveform.
  • the waveform formed by the low-speed code stream the waveform is also formed by "1" and "0". Since the transmission rate of the low-speed code stream is relatively low, the transmission time of each bit is relatively long, so the pulse width detection circuit can be formed. recognized waveforms.
  • the pulse width signals of "1" and "0" by adjusting the number of times (K times) the pulse width signals of "1" and "0" appear consecutively, the "1" and "0" of the high-speed code stream are equal to the "1" of the low-speed code stream.
  • the second response code stream can be identified by using the pulse width detection circuit to identify the duration of "1" and "0", which reduces the number of peer chip systems. power consumption.
  • the first response code stream in this embodiment of the present application may include different instructions.
  • the first response code stream may include, but is not limited to, an instruction for carrying wake-up, reset, sleep and other instructions. code stream, so that different functions can be implemented through the first response code stream.
  • two schemes are designed for the first response code stream (wake-up, reset, sleep) respectively, and it is assumed that the data packet of each first response code stream is a combination of 24 symbols.
  • the Bit (Bite, bit) between the two bit periods satisfies the maximum Han Ming distance (Hamming distance is used in data transmission error control coding, Hamming distance is a concept, it represents the number of different bits corresponding to two (same length) words, we use d(x, y) to represent two Hamming distance between words x, y. Perform XOR operation on two strings, and count the number of 1s, then this number is the Hamming distance).
  • the waveform formed by the first response code stream is described by taking an example that the first response code stream includes wake-up, sleep, and reset.
  • FIG. 7 shows a waveform diagram corresponding to wake-up 1.
  • the second system-on-chip 600 detects the waveform shown in FIG. 7
  • the second system-on-chip 600 can obtain the waveform corresponding to wake-up 1 according to the waveform shown in FIG. 7 .
  • FIG. 8 shows a waveform diagram corresponding to wake-up 2.
  • the second chip system 600 detects the waveform shown in FIG. 8, the second chip system 600 can obtain the waveform corresponding to wake-up 2 according to the waveform shown in FIG. 8. instruction.
  • FIG. 9 shows a waveform diagram corresponding to reset 1.
  • the second system-on-chip 600 detects the waveform shown in FIG. 9
  • the second system-on-chip 600 can obtain the waveform corresponding to reset 1 according to the waveform shown in FIG. 9 .
  • FIG. 10 shows a waveform diagram corresponding to reset 2.
  • the second system-on-chip 600 detects the waveform shown in FIG. 10
  • the second system-on-chip 600 can obtain the waveform corresponding to reset 2 according to the waveform shown in FIG. 10 . instruction.
  • FIG. 11 shows a waveform diagram corresponding to sleep 1.
  • the second system-on-chip 600 detects the waveform shown in FIG. 11
  • the second system-on-chip 600 can obtain the corresponding waveform of sleep 1 according to the waveform shown in FIG. 11 .
  • FIG. 12 shows a waveform diagram corresponding to sleep 2.
  • the second system-on-chip 600 detects the waveform shown in FIG. 12
  • the second system-on-chip 600 can obtain the corresponding waveform of sleep 2 according to the waveform shown in FIG. 12. instruction.
  • the first controller 501 sends an instruction to control the first sending port 502 through the protocol layer, and the first controller 501 is used to receive the instruction of the protocol layer, and form a corresponding first response code stream according to the instruction, and Use the pulse width coefficient K to process each bit in the first response code stream to obtain a second response code stream, wherein each bit in the first response code stream is in the second response code stream Occurs K consecutive times within the stream.
  • the first response code stream provided by this embodiment of the present application includes, but is not limited to, a code stream that carries commands such as wake-up, reset, and sleep.
  • the first controller 501 determines the transmission rate and the local reference clock of the first sending port 502 when the working mode is not switched, so as to determine the first sending port 502 A pulse width coefficient of the waveform is formed, and the number of consecutive occurrences of "0" and "1" in the second response code stream is determined according to the pulse width coefficient.
  • Step 001 the first chip system obtains the transmission rate fb of the first sending port when the working mode is not switched;
  • the first controller acquires the current working mode when the first sending port does not switch the working mode, and obtains the transmission rate of the code stream sent by the first sending port in the working mode.
  • the working mode in which the first sending port is not switched to the working mode may also be referred to as the current working mode of the first sending port.
  • Step 002 the first chip system obtains the reference clock Refclk of the first transmission port in its current working mode
  • the current local reference clock Refclk of the first sending port is obtained through the first controller.
  • Step 003 the first chip system determines the pulse width coefficient k according to the transmission rate fb and the local reference clock Refclk;
  • the pulse width coefficient k is determined by the first controller according to the transmission rate fb and the reference clock Refclk, so that normalized pulse width detection can be formed in different working modes.
  • the above-mentioned normalized pulse width detection refers to that, no matter what the current working mode of the first sending port is, when the second response code stream is formed, the second response code stream is formed.
  • the waveform is the same as the waveform formed by the low-speed code stream, and the waveform formed by the second response code stream containing the same response command is exactly the same.
  • the first controller adjusts the k value according to the above conditions, so that the waveform corresponding to the second response code stream formed is: The first waveform; when the first sending port is at the second rate, the first controller adjusts the k value according to the above conditions, so that the waveform corresponding to the second response code stream is the first waveform.
  • the first controller adjusts the k value according to the above conditions, so that the waveform corresponding to the second response code stream is the first waveform.
  • Step 004 the first chip system generates a corresponding second response code stream
  • the first controller when the working mode of the first sending port is switched, the first controller generates a first response code stream; and uses the determined pulse width coefficient K to process each bit in the first response code stream to obtain The second response code stream, wherein each bit in the first response code stream appears K consecutive times in the second response code stream.
  • Step 005 the first chip system sends a second response code stream to the second chip system
  • the first sending port sends the second response code stream to the second receiving port at the transmission rate of the current mode.
  • the transmission rate fb is the transmission rate of the current operating mode of the first chip system and the second chip system. For example, if the current working mode is the high-speed transmission mode (there are different speed gears in this mode), the first chip system sends the second response code stream in the current high-speed transmission mode.
  • Step 006 the second chip system receives the second response code stream
  • the second system on chip when the second system on chip receives the second response code stream, it is also in high-speed transmission mode to receive the second response code stream sent by the first system on chip.
  • the transfer rate is fb.
  • Step 007 the second chip system identifies the second response code stream
  • the second chip system identifies the second response code stream sent by the first sending port through the second detection circuit.
  • the pulse width detection circuit identifies the duration of the "0" and "1" bits in the second response code stream to identify the waveform, and the second controller reads the second response code stream to obtain the second receiving port after switching. Operating mode.
  • Step 008 the second chip system switches the working mode according to the instruction of the second response code stream
  • the second controller controls the second receiving port to switch to the switched working mode according to the second response code stream, and feeds back the switching information to the upper protocol layer.
  • the second response code stream provided by the embodiment of the present application
  • the second response code stream under different transmission rates can be normalized to form the same waveform.
  • the waveform formed by the low-speed code stream the waveform is also formed by "1" and "0". Since the transmission rate of the low-speed code stream is relatively low, the transmission time of each bit is relatively long, so the pulse width detection circuit can be formed. recognized waveforms.
  • the pulse width signals of "1" and "0" by adjusting the number of times (K times) the pulse width signals of "1" and "0" appear consecutively, the "1" and "0" of the high-speed code stream are equal to the "1" of the low-speed code stream.
  • the second response code stream can be identified by using the pulse width detection circuit to identify the duration of "1" and "0", which reduces the number of peer chip systems. power consumption.
  • the response operation is usually performed by pulling the level, and the scene of the AC coupling circuit usually adopts the sending of a high-speed code stream to the other party for specific identification.
  • the first response code stream provided in this embodiment of the present application is compatible with both AC and DC coupled physical circuits, and is widely used in scenarios.
  • the first chip system sends information to the second chip system as an example.
  • the PHY layer of the first chip system receives an instruction (wake-up, reset or sleep) from the protocol layer. If it is a wake-up command, the PHY layer of the first chip system first performs a wake-up operation to the TX of the local end (the first chip system) through its first controller, and after the TX wakes up, the wake-up code stream (a part of the second response code stream) is sent. species) to the RX of the second SoC. If the command passed by the protocol layer is a reset or sleep command, the PHY layer of the first chip system controls the local TX to send a reset or sleep code stream through the first controller. When the local TX sends a reset or sleep code stream X times , the local TX resets or sleeps.
  • the code stream is identified by the second detection circuit, because the second response code stream can be identified within the pulse width detection period of the second chip system. out the waveform. Therefore, the second detection circuit can detect the second response code stream only by using the pulse width detection circuit.
  • the pulse width detection circuit identifies the second response code stream by detecting the bit durations of "0" and "1" in the second response code stream.
  • the second detection circuit identifies the switched operating mode of the second receiving port, and transmits the information to the second controller of the second chip system, and the second controller performs corresponding operations on the second receiving port after receiving the information. And while the second controller is operating, it also informs the protocol layer that the second receiving port is to enter a corresponding working mode state.
  • the above-mentioned second response code stream can be sent first, and then the sending port can be controlled to switch the working mode; alternatively, the working mode can also be switched first. , and then send the second response code stream.
  • the above-mentioned different ways can be implemented by the first controller.
  • the first controller can control the first sending port to switch the working mode to send the second response code stream to the second chip system; or, the first controller can also be used to send the second response code stream to the second chip system, control the The first sending port switches the working mode. Both manners can be applied to the communication system provided by the embodiments of the present application.
  • the first response code stream is a wake-up command
  • the first system-on-chip and the system-on-chip can be in low-power or ultra-low-power operating modes, and the transmission rate is very low.
  • the second receiving port performs a quick wake-up operation after receiving the wake-up command. If it is a sleep command, the first chip system and the second chip system can work in high-speed, low-speed transmission mode or low power consumption mode, the first chip system enters the ultra-low power consumption mode after sending the sleep command for a period of time, and the second chip system The system enters the ultra-low power consumption mode after receiving the sleep command within the specified time. If it is a reset command, the first and second chip systems can work in high-speed transmission or low-speed transmission mode. The first chip system enters the reset mode after sending the command for a period of time, and the second chip system receives the reset command within a specified time. Enter reset mode.
  • LANE1 is used as an example for description.
  • LANE2 the above functions can also be implemented, and reference may be made to the manner in which the first sending port of the first system-on-chip sends the response code stream to the second receiving port of the second system-on-chip.
  • the functions of the first detection circuit and the first receiving port in the first chip system reference may be made to the functions of the second receiving port and the second detection circuit in the above-mentioned second chip system, and details are not repeated here.
  • the functions of the second controller and the second sending port of the second chip system reference may be made to the functions of the first controller and the first sending port of the first chip system, and details are not described herein again.
  • the embodiments of the present application further provide a communication method.
  • the communication method includes the following steps:
  • Step 01 When the working mode of the sending port is switched, generate a first response code stream, and use the pulse width coefficient K to process each bit in the first response code stream to obtain a second response code stream. , wherein each bit in the first response code stream appears K consecutive times in the second response code stream;
  • the second response code stream can form the same waveform as the low-speed code stream at the transmission rate when the sending port does not switch the working mode.
  • the second response code stream obtain the transmission rate of the first sending port of the local chip system when the working mode is not switched; obtain the local reference clock of the first sending port when the working mode is not switched; The clock determines the pulse width coefficient K; and generates a corresponding second response code stream according to the determined K value.
  • the chip system sends the second response code stream at the transmission rate when the sending port does not switch the working mode.
  • Step 02 sending the second response code stream to the receiving port through the sending port
  • the first sending port can transmit the second response code stream at the transmission rate in the current working mode.
  • Step 03 Receive the second response code stream through the receiving port, and obtain the working mode after the receiving port is switched by reading the second response code stream;
  • the opposite-end chip system receives the second response code stream through the second receiving port, wherein, when the opposite-end chip system receives the second response code stream, it receives the second response code stream at the transmission rate of the local chip system when the working mode is not switched. Two response code streams.
  • the opposite chip system can detect the second response code stream through the second detection circuit. For details, reference may be made to steps 006 to 007 of the process shown in FIG. 7 , which will not be repeated here.
  • Step 04 Switch the working mode of the receiving port to the switched working mode.
  • the second controller determines the switched working mode of the receiving port according to the acquired second response code stream, and controls the receiving port to switch to the switched working mode. For details, refer to step 008 of the process shown in FIG. 7 .
  • the second response code stream provided by the embodiment of the present application
  • the second response code stream under different transmission rates can be normalized to form the same waveform.
  • the waveform formed by the low-speed code stream the waveform is also formed by "1" and "0". Since the transmission rate of the low-speed code stream is relatively low, the transmission time of each bit is relatively long, so the pulse width detection circuit can be formed. recognized waveforms.
  • the pulse width signals of "1" and "0" by adjusting the number of times (K times) the pulse width signals of "1" and "0" appear consecutively, the "1" and "0" of the high-speed code stream are equal to the "1" of the low-speed code stream.
  • the second response code stream can be identified by using the pulse width detection circuit to identify the duration of "1" and "0", which reduces the number of peer chip systems. power consumption.
  • the adopted response code stream does not limit the specific bit combination form, so the specific bit combination can be specified according to different instruction information.
  • the method for changing the duration of the pulse width of "0" and “1” is not limited to the above method, and PWM or other forms of changing the pulse width may also be used.
  • An embodiment of the present application further provides a chip system, where the chip system is the above-mentioned first chip system or second chip system.
  • the chip system provided by the embodiments of the present application includes some or all of the components such as a sending port, a controller, a receiving port, and a detection circuit.
  • the chip system only includes a sending port and a controller, and at this time, the chip system only has the function of sending data, and does not have the function of receiving.
  • the chip system includes all components such as sending port, controller, receiving port and detection circuit.
  • the chip system has the functions of sending and receiving data.
  • the embodiments of the present application also provide working steps of the chip system, which are as follows.
  • the chip system When the chip system is used as the local chip, it is used to send the response code stream to control the switching of the peer chip.
  • the specific process is as follows:
  • Step 1 When the working mode of the sending port is switched, a first response code stream is generated, and each bit in the first response code stream is processed by using the pulse width coefficient K to obtain a second response code stream, wherein the first response code stream is obtained. Each bit in one response code stream appears K consecutive times in the second response code stream;
  • the second response code stream can form the same waveform as the low-speed code stream at the transmission rate when the sending port does not switch the working mode.
  • the second response code stream obtain the transmission rate of the first sending port of the local chip system when the working mode is not switched; obtain the local reference clock of the first sending port when the working mode is not switched; The clock determines the pulse width coefficient K; and generates a corresponding second response code stream according to the determined K value.
  • the chip system sends the second response code stream at the transmission rate when the sending port does not switch the working mode.
  • Step 2 Send the second response code stream to the receiving port of the opposite end chip system, so that the opposite end chip system receives the second response code stream through the receiving port, and obtains the working mode after the switch of the receiving port according to the second response code stream , and switch the working mode of the receiving port to the switched working mode.
  • the waveform formed by the second response code stream sent by the opposite chip system is identified by the pulse width detection circuit. Reference may be made to steps 006 to 008 shown in FIG. 7 .
  • Step 3 Control the first receiving port to switch according to the second response code sent by the opposite-end chip system identified by the first detection circuit.
  • the workflow is as follows:
  • Step 10 Receive the second response code stream through the receiving port, the second response code stream is obtained by processing each bit in the first response code stream by using the pulse width coefficient K, wherein each bit in the first response code stream is obtained. One bit appears K consecutive times in the second response code stream, and the first response code stream is generated by the chip system where the sending port is located when the working mode of the sending port that has a link relationship with the receiving port changes;
  • Step 20 read the second response code stream and obtain the switched operating mode
  • step 007 in the flow shown in FIG. 7 .
  • Step 30 Switch the receiving port to the switched working mode.
  • step 008 in the flow shown in FIG. 7 .
  • An embodiment of the present application further provides a mobile terminal, the mobile terminal includes a first chip system and a second chip system, wherein the first chip system and the second chip system are any one of the chip systems described above; wherein the first chip system In the chip system and the second chip system, the sending port and the receiving port are connected in one-to-one correspondence.
  • the low frequency of high-frequency information is realized without using PLL and CDR, which greatly reduces the power of the chip system, and promotes the chip system to perform rapid response operations in different working modes.
  • an embodiment of the present application further provides a communication apparatus 1000 for implementing the functions of the above method.
  • the communication apparatus 1000 may be a communication system, or may be a device in a communication system.
  • the communication apparatus 1000 includes at least one processor 1001 for implementing the functions of the apparatus in the above method.
  • the processor 1001 may be configured to send a code stream according to the acquired instruction of the first chip system, and change according to the instruction.
  • the detailed description in the method which will not be described here.
  • the communication device 1000 may also include at least one memory 1002 for storing program instructions and/or data.
  • Memory 1002 is coupled to processor 1001 .
  • the coupling in the embodiments of the present application is the spaced coupling or communication connection between devices, units or modules, which may be in electrical, mechanical or other forms, and is used for information interaction between the devices, units or modules.
  • the memory 1002 may also be located external to the communication device 1000 .
  • the processor 1001 may cooperate with the memory 1002 .
  • Processor 1001 may execute program instructions stored in memory 1002 . At least one of the at least one memory may be included in the processor.
  • the communication apparatus 1000 includes a communication interface 1003 for communicating with other devices through a transmission medium, so that the devices used in the communication apparatus 1000 can communicate with other devices.
  • the communication interface 1003 may be a transceiver, circuit, bus, module or other type of communication interface, and the other device may be a network device or other terminal device or the like.
  • the processor 1001 uses the communication interface 1003 to send and receive data, and is used to implement the methods in the above embodiments.
  • the communication interface 1003 may be used to communicate signals.
  • the embodiment of the present application does not limit the connection medium between the communication interface 1003 , the processor 1001 , and the memory 1002 .
  • the memory 1002, the processor 1001, and the communication interface 1003 may be connected by a bus in FIG. 12, and the bus may be divided into an address bus, a data bus, a control bus, and the like.
  • the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, which can implement or
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the steps of the methods disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), etc., or may also be a volatile memory (volatile memory), for example Random-access memory (RAM).
  • Memory is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.
  • the memory in this embodiment of the present application may also be a circuit or any other device capable of implementing a storage function, for storing program instructions and/or data.
  • the methods provided in the embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software When implemented in software, it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, network equipment, user equipment, or other programmable apparatus.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server or data center by wire (eg coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available media that can be accessed by a computer, or a data storage device such as a server, data center, etc. that includes one or more available media integrated.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, digital video discs (DVD)), or semiconductor media (eg, SSDs), and the like.

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Abstract

本申请提供了一种改变工作模式的方法、芯片系统及通信系统，该方法应用于包括第一芯片系统和第二芯片系统的通信系统，在发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对第一响应码流内的每一个比特进行处理，得到第二响应码流。其中，第一响应码流内的每一个比特均在第二响应码流内连续出现K次。发送端口将第二响应码流发送给接收端口；接收端口接收第二响应码流，并通过读取第二响应码流获得接收端口切换后的工作模式；将接收端口的工作模式切换为切换后的工作模式。在采用上述方案中，第二响应码流可形成与低速码流相同的波形，在识别第二响应码流时不需要使用PLL和CDR，极大减少通信系统中芯片系统的功率。

Description

一种改变工作模式的方法、芯片系统及通信系统
相关申请的交叉引用
本申请要求在2020年09月30日提交中国专利局、申请号为202011063750.5、申请名称为“一种改变工作模式的方法、芯片系统及通信系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及到通信技术领域，尤其涉及到一种改变工作模式的方法、芯片系统及通信系统。
背景技术
通常终端设备为了实现快速响应，同时又能最大程度节省功耗，往往会设置一种低功耗的过渡工作模式，此工作模式能够快速衔接设备的其他工作模式。例如Camera场景，用户在拍摄照片时，为了CPU(Central Processing Unit，中央处理器)的及时处理图像信息，将清楚的照片呈现给用户，在摄像头-CPU方向的链路上一直处于高速传输的状态，功耗大。但用户并不是一直处于拍摄的状态，经常是拍一会停一会。由于终端设备电池容量有限，为了尽可能地减少功耗，增加设备的使用时长，大多数设备在用户未使用时将设备置为休眠的状态进行节能。若从休眠状态再进入高速传输状态，需要重新配置寄存器、PLL(Phase Locked Loop，锁相环)、CDR(Clock Data Recover，时钟数据恢复电路)等，进行Bit、Symbol锁定，整个操作过程时间长，且功耗比较大。
发明内容
本申请提供了一种改变工作模式的方法、芯片系统及通信系统，降低了通信系统的能耗。
第一方面，提供了一种改变工作模式的方法，该方法应用于包括第一芯片系统和第二芯片系统的通信系统中，所述第一芯片系统具有发送端口，所述第二芯片系统具有接收端口，所述发送端口与所述接收端口之间具有通信链路。该方法包括在所述发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；通过所述发送端口将所述第二响应码流发送给所述接收端口；通过所述接收端口接收所述第二响应码流，并通过读取所述第二响应码流获得所述接收端口切换后的工作模式；将所述接收端口的工作模式切换为所述切换后的工作模式。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
在一个具体的可实施方案中，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。通过传输速率与本地参考时钟确定第二响应码流中每个比特持续的次数。
在一个具体的可实施方案中，所述脉宽系数K满足：K＝2*fb/Refclk。
在一个具体的可实施方案中，所述读取所述第二响应码流，具体是指：在脉宽检测周期内读取所述第二响应码流。
在一个具体的可实施方案中，所述工作模式包括高速传输模式、低速传输模式、低功耗模式、超低功耗模式和重置模式。从而实现不同的数据传输的要求。
在一个具体的可实施方案中，所述生成第一响应码流发生在所述发送端口的工作模式发生切换之前，或者发生切换之后。第一响应码流与发送端口的切换可采用不同的顺序。
在一个具体的可实施方案中，所述第一响应码流可包含但不限定用于携带唤醒、复位、休眠等指令的码流。从而可指示不同的状态。
第二方面，提供了一种改变工作模式的方法，该方法包括：在发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；将所述第二响应码流发送给对端芯片系统的接收端口，以使所述对端芯片系统通过所述接收端口接收所述第二响应码流，并根据所述第二响应码流获得所述接收端口切换后的工作模式，以及将所述接收端口的工作模式切换为所述切换后的工作模式。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
在一个具体的可实施方案中，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
在一个具体的可实施方案中，所述脉宽系数K满足：K＝2*fb/Refclk。
第三方面，提供了一种改变工作模式的方法，该方法包括：通过接收端口接收第二响应码流，所述第二响应码流是利用脉宽系数K对第一响应码流内的每一个比特进行处理得到的，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次，且所述第一响应码流是与所述接收端口之间具有链路关系的发送端口的工作模式发生变化时，所述发送端口所在的芯片系统生成的；读取所述第二响应码流并获取切换后的工作模式；将所述接收端口切换到所述切换后的工作模式。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
在一个具体的可实施方案中，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
在一个具体的可实施方案中，所述脉宽系数K满足：K＝2*fb/Refclk。
在一个具体的可实施方案中，所述读取所述第二响应码流并获取切换后的工作模式具体为：通过脉宽检测电路读取所述第二响应码流，并根据所述脉宽检测电路识别的所述第二响应码流，获取所述第二响应码流携带的切换后的工作模式。
第四方面，提供了一种芯片系统，该芯片系统包括：发送端口及控制器；所述控制器用于在所述发送端口的工作模式发生切换时，生成第一响应码流；利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；所述控制器还用于控制所述发送端口将所述第二响应码流发送到对端芯片系统。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
在一个具体的可实施方案中，所述控制器还用于根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定所述脉宽系数K。
在一个具体的可实施方案中，所述脉宽系数K满足：K＝2*fb/Refclk。
第五方面，提供了一种芯片系统，该芯片系统包括芯片以及检测电路；其中，所述芯片具有接收端口；所述接收端口用于接收对端芯片系统发送的第二响应码流；所述第二响应码流是利用脉宽系数K对第一响应码流内的每一个比特进行处理得到的，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次，且所述第一响应码流是与所述接收端口之间具有链路关系的发送端口的工作模式发生变化时，所述发送端口所在的芯片系统生成的；所述检测电路，用于读取所述第二响应码流；所述控制器还用于根据所述检测电路读取的所述第二响应码流获取所述接收端口切换后的工作模式，并控制所述接收端口切换到所述切换后的工作模式。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
在一个具体的可实施方案中，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
在一个具体的可实施方案中，所述脉宽系数K满足：K＝2*fb/Refclk。
在一个具体的可实施方案中，所述检测电路为脉宽检测电路。通过检测电平持续时间检测第二响应码流。
第六方面，提供了一种通信系统，该通信系统包括第一芯片系统和第二芯片系统，其中，所述第一芯片系统为上述任一项所述的芯片系统，所述第二芯片系统为上述任一项所述的芯片系统；所述发送端口与所述接收端口之间具有通信链路。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流 对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
第七方面，提供了一种移动终端，该移动终端包括第一芯片系统和第二芯片系统，其中，所述第一芯片系统为上述任一项所述的芯片系统，所述第二芯片系统为上述任一项所述的芯片系统；所述发送端口与所述接收端口之间具有通信链路。在当前技术中，需要识别的对象是第一响应码流，由于第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别所述第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。
第八方面，本申请实施例提供一种通信装置，所述通信装置包括处理器，用于实现上述第二方面或第三方面描述的方法。所述通信装置还可以包括存储器，用于存储指令和数据。所述存储器与所述处理器耦合，所述处理器执行所述存储器中存储的程序指令时，可以实现上述第二方面或第三方面描述的方法。所述通信装置还可以包括通信接口，所述通信接口用于该装置与其它设备进行通信，示例性的，通信接口可以是收发器、电路、总线、模块或其它类型的通信接口，其它设备可以为网络设备或终端设备等。
在一个具体的可实现方案中，该通信装置包括：存储器，用于存储程序指令；处理器，用于调用存储器中存储的指令，使得所述装置执行本申请第一方面以及第一方面中任意一种可能的设计的方法、或者本申请第二方面以及第二方面中任意一种可能的设计的方法、或者本申请第三方面以及第三方面中任意一种可能的设计的方法。
第九方面，本申请实施例还提供一种计算机可读存储介质，包括指令，当其在计算机上运行时，使得计算机执行本申请第一方面以及第一方面中任意一种可能的设计的方法、或者本申请第二方面以及第二方面中任意一种可能的设计的方法、或者本申请第三方面以及第三方面中任意一种可能的设计的方法。
第十方面，本申请实施例中还提供一种计算机程序产品，包括指令，当其在计算机上运行时，使得计算机执行本申请第一方面以及第一方面中任意一种可能的设计的方法、或者本申请第二方面以及第二方面中任意一种可能的设计的方法、或者本申请第三方面以及第三方面中任意一种可能的设计的方法。另外，第二方面至第三方面中任一种可能设计方式所带来的技术效果可参见方法部分中不同设计方式带来的效果，在此不再赘述。
附图说明
图1为本申请实施例提供的芯片系统在通信系统中的应用的场景；
图2为本申请实施例提供的芯片系统存储系统中应用的场景；
图3为本申请实施例提供的芯片系统简化的架构示意图；
图4为本申请实施例提供的芯片系统的工作模式示意图；
图5为本申请实施例提供的通信系统的链路拓扑；
图6为本申请实施例提供的通信系统的结构框图；
图7为本申请实施例提供的唤醒1指令对应的波形图；
图8为本申请实施例提供的唤醒2指令对应的波形图；
图9为本申请实施例提供的复位1指令对应的波形图；
图10为本申请实施例提供的复位2指令对应的波形图；
图11为本申请实施例提供的休眠1指令对应的波形图；
图12为本申请实施例提供的休眠1指令对应的波形图；
图13为本申请实施例提供的通信系统的流程图；
图14为本申请实施例提供的通信装置的结构框图。
具体实施方式
下面将结合附图对本申请实施例作进一步描述。
本申请实施例提供的芯片系统应用于常见的计算机系统或通信系统中。如应用于终端业务中各种需要高速通信的数据通信链路。常见的场景如手机、平板等终端产品的处理器—摄像头的数据通信链路、处理器—显示器的数据通信链路、存储设备间的数据通信链路等。
为方便描述，在本申请实施例中，定义相互通信的两个芯片系统分别为第一芯片系统和第二芯片系统。其中，第一芯片系统和第二芯片系统互为对端芯片系统。应理解本申请实施例涉及到的“第一”和“第二”仅为方便区分部件，并不具有实际的含义，下文中对相同类型的部件通过第一部件和第二部件进行区分，以方便描述。
参考图1，图1示出了本申请实施例提供的通信方法可能在终端设备中应用的场景。终端设备200中，包括处理器210、摄像模组220、显示模组230、射频模块240和存储模块250等，上述几种模块均可看作为芯片系统。通信链路201、202、203、204分别表示处理器210与摄像模组220、处理器210与显示模组230、处理器210与射频模块240、处理器210与存储模块250间的通信链路。本申请实施例提供的通信方法可应用于如201、202、203、204的数据通信链路两侧的端口工作模式进行低功耗管理，以保障高速场景下数据的稳定可靠的传输。应理解，任一通信链路两端的芯片系统互为对端芯片系统。以处理器210与摄像模组220为例，处理器210为摄像模组220的对端芯片系统，摄像模组220为处理器210的对端芯片系统。
参考图2，图2示出了本申请实施例提供的通信方法可能在存储设备中应用的场景。存储设备1和存储设备2之间通过数据端口进行数据交互，两个设备间的接收端口构成数据通信链路301。本申请提供的通信方法通过对如301的数据通信链路两侧的端口工作模式进行低功耗管理，保障高速场景下数据的稳定可靠的传输。
图3示出了本申请实施例提供的芯片系统400简化的架构示意图，芯片系统400由协议层401、物理层402(Physical Layer，PHY)、媒介403组成。其中，协议层401可由应用层、数据链路层等组成，而物理层402就是本申请方法所应用的层面，具体包括物理编码子层PCS(Physical Coding Sublayer)、物理媒介附加子层PMA(Physical Medium Attachment Sublayer)和物理介质相关子层PMD(Physical Media Dependent)所组成。其中的PMD是负责串行信号传输的电气块，PMA负责串化/解串化，PCS负责数据流的编码/解码。本申请涉及物理层402中的设备快速响应和工作模式的转变。协议层接口用来传递协议层401的时钟、数据、控制等指令。媒介403包括实际的物理信道，如PCB(Printed Circuit Board，印刷电路板)走线，线缆和光纤等。
为方便理解本申请实施例提供的芯片系统，首先说明一下本申请实施例提供的芯片系 统在工作时所处的工作模式。
本申请所涉及的通信系统(第一芯片系统、第二芯片系统)可工作在图4所示的工作模式，此工作模式被限定为一端设备TX至另一端设备的RX这条通信链路上，如第一芯片系统的发送端口TX(Transmitter，发射机)→第二芯片系统的接收端口RX(Receiver，接收机)、第二芯片系统的TX→第一芯片系统的RX等。在其中的通信链路LINK上，包括但不限定以下的几种工作模式：
高速传输模式：通信链路LINK进行高速数据信息传输(如图像、存储信息等)，其工作模式可支持多种传输速率，在高速传输模式传送的码流为高速码流。
低速传输模式：设备主要传输一些控制信息，如传递一些控制码流等，其功耗较高速传输小，在低速传输模式传送的码流为低速码流。
低功耗模式：此模式为设备的节能模式，此模式能够支持向多个工作模式进行跳转，属于过渡工作模式，功耗较低速传输模式更低。
超低功耗模式：此模式为设备的深度睡眠模式。
重置模式：此模式为设备的强制重启模式，当遇到严重的错误时进行的强制复位，此模式下设备需要重新进行建链等操作。
本申请实施例中，工作模式之间可进行切换，工作模式切换指代的是由一种工作模式切换到另外一种工作模式，如超低功耗模式可唤醒进入到低功耗模式，低功耗模式可休眠进入到超低功耗模式、低功耗模式还唤醒进入到高速传输模式或低速传输模式等不同的切换方式。
应理解，上述几种工作模式仅为本申请实施例提供的一种具体的示例，本申请实施例提供的通信系统可包含上述所有的工作模式，或者仅包含其中的几种工作模式，在此不做具体限定。
本申请实施例提供的通信系统主要改善在上述链路发生工作模式改变时芯片系统的功耗。下面对其进行详细说明。
参考图5，本申请实施例提供的通信系统的链路拓扑如图5所示。通信系统包括第一芯片系统500和第二芯片系统600，第一芯片系统500和第二芯片系统600的发送端口和接收端口一一对应连接。假定第一芯片系统500到第二芯片系统600的方向为四条LANE，如编号00、01、10、11四条LANE。第二芯片系统600到第一芯片系统500的方向也是四条LANE，如编号00、01、10、11四条LANE。其中，箭头代表数据传输的方向，每个传输方向的LANE都在建链(建立通信链路)的过程中进行逻辑编码。本申请实施例提供的通信方法可应用于任意LANE，不限定LANE的数目和方向，因此对于每条LANE上的模式之间的转换都是独立的。下面以其中的两个LANE为例进行说明，两个LANE分别为第一芯片系统500到第二芯片系统600的方向的LANE1，以及第二芯片系统600到第一芯片系统500方向的LANE2。
参考图6，本申请实施例提供的通信系统包括第一芯片系统500和第二芯片系统600，第一芯片系统500和第二芯片系统600均包含协议层和物理层，协议层和物理层的功能可参考图3中的相关描述，在此不再赘述。
下面主要说明对物理层的划分。第一芯片系统500包括第一发送端口502、第一接收端口503、第一控制器501以及第一检测电路504。第一发送端口502用于发送数据以及第一响应码流，第一接收端口503用于接收对端芯片发送的数据以及响应码流。第一控制 器501用于接收第一芯片系统500的协议层的指令，并根据指令控制第一发送端口502发送数据和第二接收端口603接收数据。另外，第一控制器501还用于将第一发送端口502和第一接收端口503发送或接收的数据反馈给协议层。第一检测电路504用于识别第一接收端口503接收到的第二芯片系统发送的响应码流。第一控制器501还用于根据第一检测电路504检测到的响应码流进行判断，以确定该响应码流对应的指令信息，并可根据该指令信息控制第一接收端口503的工作模式进行切换。
需要说明的是，在本申请中，控制器是指能够实现控制功能的电路，该能够实现控制功能的电路可以位于芯片内，也可以位于芯片的外围电路，但是多数情况下，该能够实现控制功能的电路是位于芯片内的电路。
应理解，上述第一发送端口502和第一接收端口503为第一芯片系统500的物理层结构，其具体可包含上述提到的物理编码子层PCS、物理媒介附加子层PMA和物理介质相关子层PMD，具备对数据进行处理的功能。同时，在上述第一芯片系统500工作时，第一发送端口502和第一接收端口503可实现上述链路中的高速传输模式、低速传输模式、低功耗模式、超级功耗模式以及重置模式等模式，并可在上述模式中进行切换。
第一芯片系统500包括芯片和外围电路，该外围电路指代的是与芯片连接并位于芯片周边的电路，用于对芯片的信号和电流进行处理。作为一个可选的方案，第一检测电路504可位于芯片内，也可位于芯片的外部的外围电路。其中，第一检测电路504具备识别放大后波形的能力，示例性的，第一检测电路504可为脉宽检测电路，用于检测电平的持续时间。
第二芯片系统600包括第二发送端口602、第二接收端口603、第二控制器601以及第二检测电路604。第二芯片系统600包括第二发送端口602和第二接收端口603。其中，第二芯片系统600的上述结构可参考上述第一芯片系统500的相同类型结构的描述，在此不再赘述。同理，第二芯片系统600包括芯片和外围电路，该外围电路指代的是与芯片连接并未与芯片周边的电路，用于对芯片的信号和电流进行处理。作为一个可选的方案，第二检测电路604可位于芯片内，也可位于芯片的外部的外围电路。第二检测电路604具备识别放大后波形的能力，示例性的，第二检测电路604可为脉宽检测电路，用于检测电平的持续时间。
在第一芯片系统500和第二芯片系统600通信时，第一发送端口502和第二接收端口603之间的链路连接组成第一芯片系统500到第二芯片系统600的LANE1，实现第一芯片系统500向第二芯片系统600发送数据。第二发送端口602到第一接收端口503之间的链路为第二芯片系统600到第一芯片系统500的LANE2，实现第二芯片系统600向第一芯片系统500发送数据。上述两个LANE(LANE1和LANE2)对于数据传输的方式相同，因此以LANE1为例进行说明。
在第一芯片系统500到第二芯片系统600方向的LANE1的工作模式需要进行切换时，通过第一发送端口502发送响应码流到第二接收端口603，第二芯片系统600通过识别响应码流后进行工作模式的切换。而现有技术中在发送响应码流时，每种工作模式切换都需要采用独立且特定的码流(包括高速和低速码流)，示例性的，从低功耗模式切换为高速传输模式是一种工作模式切换，由低功耗模式切换成高速传输模式是另一种工作模式切换，两种不同的工作模式切换不同工作模式切换需要不同的特定的码流。该特定的码流包含多个“0”和“1”排列形成的组合，其中，“0”代表低电平，“1”代表高电平。第二芯片系统600 在识别上述的特定的码流时，需要使用PLL和CDR锁定响应码流中每个比特中的“0”和“1”以进行识别。在特定的码流采用高速码流时，特定的码流的传输速率比较快，在PLL和CDR锁定和识别每个比特中“0”和“1”时功耗比较大，进而造成第二芯片系统600的功耗比较大。为此本申请实施例提供的通信系统采用了一种新的切换用的控制码流，下面详细对其进行说明。
在本申请实施例中，第一响应码流为控制第二芯片系统600的第二接收端口603进行工作模式切换的控制码流。在第一发送端口502的工作模式发生切换时，第一芯片系统500生成第一响应码流，并利用脉宽系数K对第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，第一响应码流内的每一个比特均在第二响应码流内连续出现K次。也即第一响应码流内的每一个比特与第二响应码流内K个连续且重复的比特相对应。例如：第一响应码流为101010，且K为4，在形成第二响应码流时，第二响应码流为111100001111000011110000。即第一响应码流中的“1”和“0”分别重复4次，以组成第二响应码流。形成的第二响应码流通过第一发送端口502以未切换工作模式时的传输速率向第二接收端口603发送。第二接收端口603接收到第二响应码流后，第二检测电路604识别第二响应码流中的“1”和“0”持续的时间，以识别第二响应码流形成的波形。在本申请实施例中，第二响应码流通过控制K值使得其形成的波形与低速码流的波形相同。
为方便理解第二响应码流如何在第一发送端口502以未切换工作模式时的传输速率下形成与低速码流相同的波形。首先介绍一下数据包。数据包由第一发送端口502发送到第二接收端口603，第二响应码流具有一个数据包或者多个数据包。每个数据包中包含A个Symbol(符号)，每个Symbol包含有多个比特，每个Symbol发送的时间Symbol time＝k*UI。则整个数据包发送占用的时间T＝A*k*UI。其中，A为自然数，示例性的，A＝24，则T＝24*k*UI；UI为第一发送端口502当前传输速率下传输每个比特的时间，UI满足：UI＝1/fb，fb为第一发送端口502未切换工作模式时的传输速率；k为第一发送端口形成波形的脉宽系数。
在本申请实施例中，第一控制器501可用于根据第一发送端口502未切换工作模式时的传输速率fb；以及第一发送端口502未切换工作模式时的本地参考时钟；确定脉宽系数k，示例性的，k满足：k＝2*fb/Refclk，Refclk为第一芯片系统500未切换工作模式时的本地参考时钟。
另外介绍一下脉宽检测周期P(Pulse Width detection cycle)，脉宽检测周期为第二芯片系统600检测码流的时间，示例性的P＝1.92us。脉宽检测周期P与数据包发送占用的时间T之间满足：P＝N*T，N可为小数或者自然数。示例性的，当N＝1时，只需要1个脉宽检测周期P即可检测完一个数据包；当N＝0.5时，则需要两个脉冲检测周期才可检测完一个数据包。在第一响应码流包含有1个数据包时，且N＝1时，则只需要一个脉宽检测周期即可检测完第一响应码流。在第一响应码流包含有2个数据包，且N＝1时，则需要两个脉宽检测周期才可检测完第一响应码流。在本申请实施例中，以P＝T＝24*k*UI为例进行说明。
在本申请实施例中，通过k值确定第一响应码流中的高电平和低电平的持续的比特个数，因此，在第一发送端口502具有不同的传输速率时，可根据k值来调节第一响应码流中每个Symbol(符号)里“0”和“1”的Bit(比特)持续的时间以形成第二响应码流，且形成的第二响应码流在不同传输速率下形成相同的波形(该波形等效为低速码流的波形)，为方便理解上述第二响应码流，可参考表1和表2。其中，表1示例出了在不同传输速率 下，第一芯片系统500的本地参考时钟，比特时间，以及Symbol占用的时间和脉宽检测周期P(在表1中以数据包发送的时间T替代)。表2示例出了在表1中不同传输速率下，携带不同指令的第二响应码流的高电平和低电平占用的比特数。
表1
Figure PCTCN2021120781-appb-000001
表2
Bit patterns 唤醒1 唤醒2 复位1 复位2 休眠1 休眠2
Bit[0:k-1] 1 1 1 1 0 0
Bit[k:2k-1] 0 1 1 1 1 1
Bit[2k:3k-1] 1 0 1 1 1 0
Bit[3k:4k-1] 0 0 0 1 0 0
Bit[4k:5k-1] 1 1 0 0 1 1
Bit[5k:6k-1] 0 1 0 0 0 1
Bit[6k:7k-1] 1 0 1 0 0 1
Bit[7k:8k-1] 0 0 1 0 1 0
Bit[8k:9k-1] 1 1 1 1 0 1
Bit[9k:10k-1] 0 1 0 1 1 1
Bit[10k:11k-1] 1 0 0 1 1 0
Bit[11k:12k-1] 0 0 0 1 0 0
Bit[12k:13k-1] 1 1 1 0 1 0
Bit[13k:14k-1] 0 1 1 0 0 1
Bit[14k:15k-1] 1 0 1 0 0 0
Bit[15k:16k-1] 0 0 0 0 1 0
Bit[16k:17k-1] 1 1 0 1 0 1
Bit[17k:18k-1] 0 1 0 1 1 1
Bit[18k:19k-1] 1 0 1 1 1 1
Bit[19k:20k-1] 0 0 1 1 0 0
Bit[20k:21k-1] 1 1 1 0 1 1
Bit[21k:22k-1] 0 1 0 0 0 1
Bit[22k:23k-1] 1 0 0 0 0 0
Bit[23k:24k-1] 0 0 0 0 1 0
示例性的，如表1中的fb为48M时，本地参考时钟为24M，每个比特的传输时间为20.83ns，k为4，每个符号的传输时间为83.33ns，每个数据包的传输时间为2us。对应的第一响应码流为唤醒1时，第二响应码流中的“1”占用的比特为Bit0～Bit(k-1)，即Bit0～Bit3，共占用4个比特，“0”占用Bitk～Bit(2k-1)，即Bit4～Bit7，占用4个比特。以唤醒1为例，第一响应码流为“10”在形成第二响应码流时，第一响应码流中的“1”连续出现4次，“0”持续出现4次，形成“11110000”的第二响应码流。
示例性的，如表1所示，在fb为76.8M时，本地参考时钟为38.4M，每个比特的传输时间为13.02ms，k为6，每个符号的传输时间为78.13ns，每个数据包的传输时间为1.875us。在第一响应码流为唤醒1时，第二响应码流“1”占用的比特为Bit0～Bit(k-1)，即Bit0～Bit5，共占用6个比特，“0”占用Bitk～Bit(2k-1)，即Bit6～Bit11，占用6个比特。以唤醒1为例，第一响应码流为“10”在形成第二响应码流时，第一响应码流中的“1”连续出现6次，“0”持续出现6次，形成“111111000000”的第二响应码流。
第二检测电路604具备识别放大后波形的能力，示例性的，第二检测电路604可为脉宽检测电路，用于检测电平的持续时间。在检测第二响应码流时，第二响应码流在将第一响应码流中的每个比特持续k次后，相当于将第一响应码流对应形成的波形放大，第二检测电路604可识别放大后的波形。在当前技术中，需要识别的对象是第一响应码流，由于 第一响应码流的被发送的速率较高，周期较小，所以需要借助于PLL和CDR，识别第一响应码流包含的信息。在本实施例中，第二响应码流对应的波形可以被理解为是对第一响应码流对应的波形进行K倍放大后得到的，该波形能够被第二芯片系统的脉宽检测电路识别，不需要再借助于PLL和CDR识别了，因此能够极大减少通信系统中芯片系统的功率。示例性的，第二响应码流形成的放大后的波形可与低速码流(与第二响应码流携带有相同指令)形成的波形相同，可通过脉宽检测电路直接检测第二响应码流形成的波形即可获取第二响应码流携带的指令。
在上述方案中，k的取值影响到“1”和“0”连续出现的次数，即“1”和“0”占用的比特数，进而影响第二响应码流形成的波形的脉宽。在第一发送端口502的传输速率改变时，可通过对应调整k值改变第二响应码流中每个“0”和“1”占用的比特数，使得不同传输速率下，“1”和“0”持续时间相同，从而实现在不同传输速率下可形成相同的波形，第一发送端口502在未切换工作模式时的传输速率对形成的波形不会造成影响。第二芯片系统600可通过识别第二响应码流中交替的“0”和“1”脉宽信号占空比(占用的比特数)进行检测，以获得第二接收端口603切换后的工作模式。
另外，在采用本申请实施例提供的第二响应码流时，可将不同传输速率下的第二响应码流归一形成相同的波形。另外，在低速码流形成的波形中，也是通过“1”和“0”形成波形，由于低速码流的传输速率比较低，每个比特的传输时间比较长，因此可形成通过脉宽检测电路识别的波形。而在本申请实施例中，通过调整“1”和“0”的脉宽信号连续出现的次数(K次)，使得高速码流的“1”和“0”与低速码流中的“1”和“0”持续相同的时间，从而使得高速码流形成的波形等效形成低速码流形成的波形，在第二芯片系统600识别时，无需采用PLL和CDR锁定第一响应码流中每个比特中的“0”和“1”以进行识别，只需采用脉宽检测电路识别“1”和“0”的持续时间即对第二响应码流可进行识别，减少了对端芯片系统的功耗。
作为一个可选的方案，在本申请实施例中的第一响应码流可包含不同的指令，示例性的，第一响应码流可包含但不限定用于携带唤醒、复位、休眠等指令的码流，从而可通过第一响应码流实现不同的功能。作为一个示例，第一响应码流(唤醒、复位、休眠)分别设计有两种方案，且假定每种第一响应码流的数据包都为24个Symbol(符号)组合。为了保证第一响应码流有足够的高低电平跳变，按照后一比特周期为前一比特周期取反的思路，此时两个比特周期之间的Bit(Bite，比特)满足最大的汉明距离(汉明距离是使用在数据传输差错控制编码里面的，汉明距离是一个概念，它表示两个(相同长度)字对应位不同的数量，我们以d(x，y)表示两个字x，y之间的汉明距离。对两个字符串进行异或运算，并统计结果为1的个数，那么这个数就是汉明距离)。
为方便理解第一响应码流形成的波形，以示例出第一响应码流包含唤醒、休眠、复位为例，说明第一响应码流形成的波形。
1)唤醒指令，包括但不限定：唤醒1：“1 0”；唤醒2：“11 00”。参考图7，图7示出了唤醒1对应的波形图，在第二芯片系统600检测到图7所示的波形时，第二芯片系统600可根据图7所示的波形获取到唤醒1对应的指令。参考图8，图8示出了唤醒2对应的波形图，在第二芯片系统600检测到图8所示的波形时，第二芯片系统600可根据图8所示的波形获取到唤醒2对应的指令。
2)复位指令，包括但不限定：复位1：“111 000”；复位2：“1111 0000”。参考图9，图9示出了复位1对应的波形图，在第二芯片系统600检测到图9所示的波形时，第二芯 片系统600可根据图9所示的波形获取到复位1对应的指令。参考图10，图10示出了复位2对应的波形图，在第二芯片系统600检测到图10所示的波形时，第二芯片系统600可根据图10所示的波形获取到复位2对应的指令。
3)休眠指令，包括但不限定：休眠1：“0110 1001”；休眠2：“010011 101100”。参考图11，图11示出了休眠1对应的波形图，在第二芯片系统600检测到图11所示的波形时，第二芯片系统600可根据图11所示的波形获取到休眠1对应的指令。参考图12，图12示出了休眠2对应的波形图，在第二芯片系统600检测到图12所示的波形时，第二芯片系统600可根据图12所示的波形获取到休眠2对应的指令。
第一芯片系统500在包括协议层时，通过协议层发送控制第一发送端口502的指令，第一控制器501用以接收协议层的指令，并根据指令形成相应的第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次。本申请实施例提供的第一响应码流包括但不限定携带唤醒、复位、休眠等指令的码流。示例性的，当协议层发出唤醒指令时，第一控制器501接收到唤醒指令后，确定第一发送端口502在未切换工作模式时的传输速率、本地参考时钟，以确定第一发送端口502形成波形的脉宽系数，并根据该脉宽系数确定第二响应码流中的“0”和“1”连续出现的次数。
为方便理解本申请实施例提供的上述第一芯片系统和第二芯片系统通过第二响应码流实现信息交互的情景，结合图13所示的流程图对其进行说明。
步骤001：第一芯片系统获取第一发送端口在其未切换工作模式时的传输速率fb；
具体的，通过第一控制器获取当前第一发送端口未切换工作模式时所在的工作模式，并获取在该工作模式下的第一发送端口发送码流的传输速率。第一发送端口未切换工作模式时所在的工作模式也可称为第一发送端口的当前工作模式。
步骤002：第一芯片系统获取第一发送端口在其当前工作模式的参考时钟Refclk；
具体的，通过第一控制器获取当前第一发送端口的本地参考时钟Refclk。
步骤003：第一芯片系统根据传输速率fb以及本地参考时钟Refclk确定脉宽系数k；
具体的，通过第一控制器根据传输速率fb，参考时钟Refclk确定脉宽系数k，以使得在不同工作模式下，可形成归一化的脉宽检测。示例性的，上述归一化的脉宽检测指代的是，无论第一发送端口所处的当前工作模式为何种工作模式，在形成的第二响应码流时，第二响应码流形成的波形与低速码流形成的波形相同，且包含有相同响应指令的第二响应码流形成的波形完全相同。示例性的，以唤醒指令对应的波形为第一波形，则在第一发送端口处于第一速率时，第一控制器根据上述条件调整k值，使得形成的第二响应码流对应的波形为第一波形；在第一发送端口处于第二速率时，第一控制器根据上述条件调整k值，使得第二响应码流对应的波形为第一波形，可参考表1和表2中的相关示例。
步骤004：第一芯片系统生成对应的第二响应码流；
具体的，在第一发送端口的工作模式发生切换时，第一控制器生成第一响应码流；并利用确定的脉宽系数K，对第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，第一响应码流内的每一个比特均在第二响应码流内连续出现K次。
步骤005：第一芯片系统向第二芯片系统发送第二响应码流；
具体的，第一发送端口向第二接收端口以当前模式的传输速率发送第二响应码流。其中，传输速率fb为第一芯片系统和第二芯片系统当前工作模式的传输速率。例如当前工作 模式为高速传输模式(此模式存在不同的速率档位)，第一芯片系统以当前高速传输模式发送第二响应码流。
步骤006：第二芯片系统接收第二响应码流；
具体的，第二芯片系统在接收第二响应码流时，也是处于高速传输模式来接收第一芯片系统发送过来的第二响应码流，这过程中第一芯片系统和第二芯片系统之间的传输速率即为fb。
步骤007：第二芯片系统识别第二响应码流；
具体的，第二芯片系统通过第二检测电路识别第一发送端口发送的第二响应码流。具体为通过脉宽检测电路识别第二响应码流中的“0”和“1”Bit持续的时间来识别波形，第二控制器通过读取第二响应码流获得第二接收端口切换后的工作模式。
步骤008：第二芯片系统根据第二响应码流的指令进行工作模式切换；
具体的，第二控制器根据第二响应码流控制第二接收端口进行切换为所述切换后的工作模式，并向上层的协议层反馈切换的信息。
在采用本申请实施例提供的第二响应码流时，可将不同传输速率下的第二响应码流归一形成相同的波形。另外，在低速码流形成的波形中，也是通过“1”和“0”形成波形，由于低速码流的传输速率比较低，每个比特的传输时间比较长，因此可形成通过脉宽检测电路识别的波形。而在本申请实施例中，通过调整“1”和“0”的脉宽信号连续出现的次数(K次)，使得高速码流的“1”和“0”与低速码流中的“1”和“0”持续相同的时间，从而使得高速码流形成的波形等效形成低速码流形成的波形，在第二芯片系统600识别时，无需采用PLL和CDR锁定第一响应码流中每个比特中的“0”和“1”以进行识别，只需采用脉宽检测电路识别“1”和“0”的持续时间即对第二响应码流可进行识别，减少了对端芯片系统的功耗。
另外，对于DC耦合电路的场景通常采用拉电平进行响应操作，而AC耦合电路的场景通常采用发送高速码流给对方进行具体识别。而在本申请实施例提供的第一响应码流可同时兼容AC和DC耦合的物理电路，场景应用广泛。
在上述方法流程中，以第一芯片系统向第二芯片系统发送信息为例。第一芯片系统的PHY层收到协议层传下来的指令(唤醒、复位或休眠)。若是唤醒指令，则第一芯片系统的PHY层先通过其第一控制器向本端(第一芯片系统)的TX进行唤醒操作，待TX唤醒后发送唤醒码流(第二响应码流的一种)给第二芯片系统的RX。若协议层传递下来的指令为复位或休眠指令，则第一芯片系统的PHY层通过第一控制器控制本端的TX发送复位或者休眠码流，当本端的TX发送X次复位或休眠码流后，本端的TX进行复位或者休眠。
第二芯片系统的RX收到的唤醒、复位或休眠码流后，通过第二检测电路进行码流的识别，由于上述第二响应码流可在第二芯片系统的脉宽检测周期内可识别出波形。因此第二检测电路仅采用脉宽检测电路即可检测第二响应码流。脉宽检测电路通过检测第二响应码流中“0”和“1”的Bit持续时间来识别第二响应码流。通过第二检测电路识别出第二接收端口切换后的工作模式，将信息传递给第二芯片系统的第二控制器，第二控制器在收到信息后对第二接收端口进行相应的操作。并且在第二控制器进行操作的同时，也会告知协议层第二接收端口要进入一个对应的工作模式状态。
作为一个可选的方案，在第一芯片系统与第二芯片系统配合时，即可采用上述的先发送第二响应码流，之后再控制发送端口切换工作模式；或者，也可先切换工作模式，之后在发送第二响应码流。上述不同的方式可通过第一控制器实现。第一控制器可控制第一发 送端口切换工作模式后，向第二芯片系统发送第二响应码流；或，第一控制器还可用于向第二芯片系统发送第二响应码流后，控制第一发送端口切换工作模式。两种方式均可应用在本申请实施例提供的通信系统中。
在上述流程中，第一响应码流若为唤醒指令，则第一芯片系统和第二芯片系统可以处于低功耗或超低功耗等工作模式，传输速率非常低，第二芯片系统的第二接收端口收到唤醒指令后进行快速唤醒操作。若为休眠指令，则第一芯片系统和第二芯片系统可工作在高速、低速传输模式或低功耗模式，第一芯片系统在发送休眠指令一段时间之后进入超低功耗模式，第二芯片系统在规定的时间内收到休眠指令后进入超低功耗模式。若为复位指令，第一第二芯片系统可工作在高速传输或者低速传输模式，第一芯片系统在发送指令一段时间之后进入重置模式，第二芯片系统在规定的时间内收到复位指令后进入重置模式。
应理解，在上述描述中，以LANE1为例进行的说明。在LANE2中，也可实现上述功能，可参考上述第一芯片系统的第一发送端口向第二芯片系统的第二接收端口发送响应码流的方式。另外，第一芯片系统中的第一检测电路和第一接收端口的功能可参考上述第二芯片系统中第二接收端口和第二检测电路的功能，在此不再赘述。第二芯片系统的第二控制器和第二发送端口的功能可参考第一芯片系统的第一控制器和第一发送端口的功能，在此不再赘述。
为方便理解本申请实施例提供的上述通信系统，本申请实施例还提供了一种通信方法。该通信方法包括以下步骤：
步骤01：在所述发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；
具体的，第二响应码流在发送端口未切换工作模式时的传输速率下可形成与低速码流相同的波形。在形成第二响应码流时，获取本端芯片系统的第一发送端口未切换工作模式时的传输速率；获取第一发送端口在未切换工作模式时的本地参考时钟；根据传输速率、本地参考时钟确定脉宽系数K；根据确定的K值生成对应的第二响应码流。具体的可参考图7中的步骤001～步骤004，在此不再赘述。另外，在发送第二响应码流时，芯片系统以发送端口未切换工作模式时的传输速率发送第二响应码流。
步骤02：通过所述发送端口将第二响应码流发送给接收端口；
具体的，可参考图7所示流程的步骤005。第一发送端口可以当前工作模式下的传输速率传输第二响应码流。
步骤03：通过所述接收端口接收第二响应码流，并通过读取第二响应码流获得接收端口切换后的工作模式；
具体的，对端芯片系统通过第二接收端口接收第二响应码流，其中，对端芯片系统接收第二响应码流时，以本端芯片系统在未切换工作模式时的传输速率下接收第二响应码流。另外，对端芯片系统可通过第二检测电路检测第二响应码流。具体可参考图7中所示流程的步骤006～007，在此不再赘述。
步骤04：将所述接收端口的工作模式切换为所述切换后的工作模式。
具体的，第二控制器根据获取的第二响应码流确定接收端口切换后的工作模式，并控制接收端口切换成切换后的工作模式，具体可参考图7中所示流程的步骤008。
通过上述描述可看出，在采用本申请实施例提供的第二响应码流时，可将不同传输速 率下的第二响应码流归一形成相同的波形。另外，在低速码流形成的波形中，也是通过“1”和“0”形成波形，由于低速码流的传输速率比较低，每个比特的传输时间比较长，因此可形成通过脉宽检测电路识别的波形。而在本申请实施例中，通过调整“1”和“0”的脉宽信号连续出现的次数(K次)，使得高速码流的“1”和“0”与低速码流中的“1”和“0”持续相同的时间，从而使得高速码流形成的波形等效形成低速码流形成的波形，在第二芯片系统600识别时，无需采用PLL和CDR锁定第一响应码流中每个比特中的“0”和“1”以进行识别，只需采用脉宽检测电路识别“1”和“0”的持续时间即对第二响应码流可进行识别，减少了对端芯片系统的功耗。
另外，由上述的通信系统以及方法可看出，在上述方案中，采用的响应码流不限定具体bit组合形式，因此可根据不同的指令信息可规定具体的比特组合。
同时，对于改变“0”和“1”持续的脉宽时间方法不限定为上述方法，亦可采用PWM或者其他改变脉宽的形式。
本申请实施例还提供了一种芯片系统，芯片系统为上述的第一芯片系统或者第二芯片系统。本申请实施例提供的芯片系统包括发送端口、控制器、接收端口和检测电路等部件中的部分部件或所有部件。示例性的，该芯片系统仅包含发送端口和控制器，此时芯片系统仅具有发送数据的功能，不具备接收功能。或者芯片系统包括发送端口、控制器、接收端口和检测电路等所有部件。芯片系统具有发送数据和接收数据的功能。
应理解，该芯片系统中的发送端口、控制器、接收端口和检测电路可参考上述第一芯片系统或第二芯片系统中相同类型部件的功能，在此不再赘述。
本申请实施例还提供了芯片系统工作步骤，具体如下。
在芯片系统作为本端芯片时，其用于发送响应码流控制对端芯片进行切换。其具体流程如下：
步骤1：在发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，第一响应码流内的每一个比特均在第二响应码流内连续出现K次；
具体的，第二响应码流在发送端口未切换工作模式时的传输速率下可形成与低速码流相同的波形。在形成第二响应码流时，获取本端芯片系统的第一发送端口未切换工作模式时的传输速率；获取第一发送端口在未切换工作模式时的本地参考时钟；根据传输速率、本地参考时钟确定脉宽系数K；根据确定的K值生成对应的第二响应码流。具体的可参考图7中的步骤001～步骤004，在此不再赘述。另外，在发送第二响应码流时，芯片系统以发送端口未切换工作模式时的传输速率发送第二响应码流。
步骤2：将第二响应码流发送给对端芯片系统的接收端口，以使对端芯片系统通过接收端口接收第二响应码流，并根据第二响应码流获得接收端口切换后的工作模式，以及将接收端口的工作模式切换为切换后的工作模式。
具体的，通过脉宽检测电路识别对端芯片系统发送的第二响应码流形成的波形。可参考图7中所示的步骤006～步骤008。
步骤3：根据第一检测电路识别的对端芯片系统发送的第二响应码，控制第一接收端口进行切换。
在芯片系统为对端芯片系统时，其工作流程如下：
步骤10：通过接收端口接收第二响应码流，第二响应码流是利用脉宽系数K对第一响 应码流内的每一个比特进行处理得到的，其中，第一响应码流内的每一个比特均在第二响应码流内连续出现K次，且第一响应码流是与接收端口之间具有链路关系的发送端口的工作模式发生变化时，发送端口所在的芯片系统生成的；
具体可参考图7所示流程中的步骤001～步骤006中具体的操作步骤。
步骤20:读取第二响应码流并获取切换后的工作模式；
具体可参考图7所示流程中的步骤007中具体的操作步骤。
步骤30：将接收端口切换到切换后的工作模式。
具体可参考图7所示流程中的步骤008中具体的操作步骤。
本申请实施例还提供了一种移动终端，该移动终端包括第一芯片系统和第二芯片系统，其中，第一芯片系统和第二芯片系统均为上述任一项的芯片系统；其中第一芯片系统和第二芯片系统中，发送端口和接收端口一一对应连接。在采用上述方案中，实现了将高频信息低频化且不需要使用PLL和CDR，极大减少芯片系统的功率，促进芯片系统在不同的工作模式下进行快速进行响应操作。
如图14所示，本申请实施例还提供了通信装置1000用于实现上述方法的功能。该通信装置1000可以是通信系统，也可以是通信系统中的装置。通信装置1000包括至少一个处理器1001，用于实现上述方法中装置的功能。示例地，处理器1001可以用于根据获取的第一芯片系统的发送码流的指令，并根据该指令改变，具体参见方法中的详细描述，此处不再说明。
在一些实施例中，该通信装置1000还可以包括至少一个存储器1002，用于存储程序指令和/或数据。存储器1002和处理器1001耦合。本申请实施例中的耦合是装置、单元或模块之间的间隔耦合或通信连接，可以是电性，机械或其它的形式，用于装置、单元或模块之间的信息交互。作为另一种实现，存储器1002还可以位于通信装置1000之外。处理器1001可以和存储器1002协同操作。处理器1001可能执行存储器1002中存储的程序指令。所述至少一个存储器中的至少一个可以包括于处理器中。
在一些实施例中，通信装置1000包括通信接口1003，用于通过传输介质和其它设备进行通信，从而用于通信装置1000中的装置可以和其它设备进行通信。示例性地，通信接口1003可以是收发器、电路、总线、模块或其它类型的通信接口，该其它设备可以是网络设备或其它终端设备等。处理器1001利用通信接口1003收发数据，并用于实现上述实施例中的方法。示例性的，通信接口1003可以用于传递信号。
本申请实施例中不限定上述通信接口1003、处理器1001以及存储器1002之间的连接介质。例如，本申请实施例在图12中以存储器1002、处理器1001以及通信接口1003之间可以通过总线连接，所述总线可以分为地址总线、数据总线、控制总线等。
在本申请实施例中，处理器可以是通用处理器、数字信号处理器、专用集成电路、现场可编程门阵列或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件，可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。
在本申请实施例中，存储器可以是非易失性存储器，比如硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)等，还可以是易失性存储器(volatile memory)，例如随机存取存储器(random-access memory，RAM)。存储器是能够用于携带或存储具有指令 或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。本申请实施例中的存储器还可以是电路或者其它任意能够实现存储功能的装置，用于存储程序指令和/或数据。
本申请实施例提供的方法中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、用户设备或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，简称DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机可以存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，数字视频光盘(digital video disc，简称DVD))、或者半导体介质(例如，SSD)等。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (22)

  1. 一种改变工作模式的方法，其特征在于，应用于包括第一芯片系统和第二芯片系统的通信系统中，所述第一芯片系统具有发送端口，所述第二芯片系统具有接收端口，所述发送端口与所述接收端口之间具有通信链路；
    在所述发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；
    通过所述发送端口将所述第二响应码流发送给所述接收端口；
    通过所述接收端口接收所述第二响应码流，并通过读取所述第二响应码流获得所述接收端口切换后的工作模式；
    将所述接收端口的工作模式切换为所述切换后的工作模式。
  2. 根据权利要求1所述的改变工作模式的方法，其特征在于，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
  3. 根据权利要求1或2所述的改变工作模式的方法，其特征在于，所述脉宽系数K满足：K＝2*fb/Refclk。
  4. 根据权利要求1～3任一项所述的改变工作模式的方法，其特征在于，所述读取所述第二响应码流，具体是指：在脉宽检测周期内读取所述第二响应码流。
  5. 根据权利要求1～4任一项所述的改变工作模式的方法，其特征在于，所述工作模式包括高速传输模式、低速传输模式、低功耗模式、超低功耗模式和重置模式。
  6. 根据权利要求1～5任一项所述的改变工作模式的方法，其特征在于，所述生成第一响应码流发生在所述发送端口的工作模式发生切换之前，或者发生切换之后。
  7. 一种改变工作模式的方法，其特征在于，
    在发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；
    将所述第二响应码流发送给对端芯片系统的接收端口，以使所述对端芯片系统通过所述接收端口接收所述第二响应码流，并根据所述第二响应码流获得所述接收端口切换后的工作模式，以及将所述接收端口的工作模式切换为所述切换后的工作模式。
  8. 根据权利要求7所述的改变工作模式的方法，其特征在于，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
  9. 根据权利要求7或8所述的改变工作模式的方法，其特征在于，所述脉宽系数K满足：K＝2*fb/Refclk。
  10. 一种改变工作模式的方法，其特征在于，
    通过接收端口接收第二响应码流，所述第二响应码流是利用脉宽系数K对第一响应码流内的每一个比特进行处理得到的，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次，且所述第一响应码流是与所述接收端口之间具有链路关系的发送端口的工作模式发生变化时，所述发送端口所在的芯片系统生成的；
    读取所述第二响应码流并获取切换后的工作模式；
    将所述接收端口切换到所述切换后的工作模式。
  11. 根据权利要求10所述的改变工作模式的方法，其特征在于，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
  12. 根据权利要求10或11所述的改变工作模式的方法，其特征在于，所述脉宽系数K满足：K＝2*fb/Refclk。
  13. 根据权利要求10～12任一项所述的改变工作模式的方法，其特征在于，所述读取所述第二响应码流并获取切换后的工作模式具体为：通过脉宽检测电路读取所述第二响应码流，并根据所述脉宽检测电路识别的所述第二响应码流，获取所述第二响应码流携带的切换后的工作模式。
  14. 一种芯片系统，其特征在于，包括发送端口及控制器；
    所述控制器用于在所述发送端口的工作模式发生切换时，生成第一响应码流，并利用脉宽系数K对所述第一响应码流内的每一个比特进行处理，得到第二响应码流，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次；
    所述控制器还用于控制所述发送端口将所述第二响应码流发送到对端芯片系统。
  15. 根据权利要求14所述的芯片系统，其特征在于，所述控制器还用于根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定所述脉宽系数K。
  16. 根据权利要求14或15所述的芯片系统，其特征在于，所述脉宽系数K满足：K＝2*fb/Refclk。
  17. 一种芯片系统，其特征在于，包括接收端口、检测电路和控制器；其中，所述芯片具有接收端口，
    所述接收端口用于接收对端芯片系统发送的第二响应码流；所述第二响应码流是利用脉宽系数K对第一响应码流内的每一个比特进行处理得到的，其中，所述第一响应码流内的每一个比特均在所述第二响应码流内连续出现K次，且所述第一响应码流是与所述接收端口之间具有链路关系的发送端口的工作模式发生变化时，所述发送端口所在的芯片系统生成的；
    所述检测电路，用于读取所述第二响应码流；
    所述控制器还用于根据所述检测电路读取的所述第二响应码流获取所述接收端口切换后的工作模式，并控制所述接收端口切换到所述切换后的工作模式。
  18. 根据权利要求17所述的芯片系统，其特征在于，所述脉宽系数K是根据所述发送端口的工作模式发生切换前，所述发送端口的传输速率fb以及所述发送端口的本地参考时钟Refclk确定的。
  19. 根据权利要求17或18所述的芯片系统，其特征在于，所述脉宽系数K满足：K＝2*fb/Refclk。
  20. 根据权利要求17～19任一项所述的芯片系统，其特征在于，所述检测电路为脉宽检测电路。
  21. 一种通信系统，其特征在于，包括第一芯片系统和第二芯片系统，其中，所述第一芯片系统为如权利要求14～16任一项所述的芯片系统，所述第二芯片系统为如权利要求 17～20任一项所述的芯片系统；
    所述发送端口与所述接收端口之间具有通信链路。
  22. 一种移动终端，其特征在于，包括第一芯片系统和第二芯片系统，其中，所述第一芯片系统为如权利要求14～16任一项所述的芯片系统，所述第二芯片系统为如权利要求17～20任一项所述的芯片系统；
    所述发送端口与所述接收端口之间具有通信链路。
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