WO2022064662A1 - Transformer and converter - Google Patents

Transformer and converter Download PDF

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Publication number
WO2022064662A1
WO2022064662A1 PCT/JP2020/036459 JP2020036459W WO2022064662A1 WO 2022064662 A1 WO2022064662 A1 WO 2022064662A1 JP 2020036459 W JP2020036459 W JP 2020036459W WO 2022064662 A1 WO2022064662 A1 WO 2022064662A1
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Prior art keywords
voltage side
coil
low
pattern layers
conductor pattern
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PCT/JP2020/036459
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French (fr)
Japanese (ja)
Inventor
俊悟 平谷
和嗣 草別
成治 高橋
Original Assignee
住友電気工業株式会社
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Priority to PCT/JP2020/036459 priority Critical patent/WO2022064662A1/en
Publication of WO2022064662A1 publication Critical patent/WO2022064662A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F30/00—Fixed transformers not covered by group H01F19/00
    • H01F30/06—Fixed transformers not covered by group H01F19/00 characterised by the structure
    • H01F30/10—Single-phase transformers

Definitions

  • This disclosure relates to transformers and converters.
  • Patent Document 1 discloses a transformer in which a coil on the exciting side and a coil on the power receiving side are provided on a multilayer board.
  • the coil pattern constituting the coil on the exciting side and the coil pattern constituting the coil on the power receiving side are alternately laminated in the thickness direction of the multilayer board.
  • the coil on the exciting side and the coil on the power receiving side one is a high-voltage side coil used at a high voltage and the other is a low-voltage side coil used at a low voltage.
  • the transformers in this disclosure are High pressure side coil and Low pressure side coil and A transformer including a high-voltage side coil and a core penetrating the low-voltage side coil.
  • a multilayer substrate including a plurality of conductor pattern layers to be laminated and an insulating layer arranged between two conductor pattern layers adjacent to each other in the stacking direction is provided.
  • the plurality of conductor pattern layers are A plurality of high-voltage side pattern layers having coil patterns constituting the high-voltage side coil, A plurality of low pressure side pattern layers having a coil pattern constituting the low pressure side coil are included.
  • At least two low-voltage side pattern layers of the plurality of low-voltage side pattern layers are arranged between two high-voltage side pattern layers electrically connected in series.
  • the converters of the present disclosure are The transformer of the present disclosure is provided.
  • FIG. 1 is a circuit diagram of the converter shown in the first embodiment.
  • FIG. 2 is a schematic top view of the transformer shown in the first embodiment.
  • FIG. 3 is a schematic side view of the transformer shown in the first embodiment.
  • FIG. 4 is an explanatory diagram schematically showing a laminated state of the high-voltage side coil and the low-voltage side coil in the multilayer board of the transformer shown in the first embodiment.
  • FIG. 5 is a schematic plan view of the coil pattern of the high-voltage side coil in the transformer shown in the first embodiment.
  • FIG. 6 is an explanatory diagram schematically showing a laminated state of the high-voltage side coil and the low-voltage side coil in the multilayer board of the transformer shown in the second embodiment.
  • FIG. 7 is a schematic plan view of the coil pattern of the high-voltage side coil in the transformer shown in the second embodiment.
  • FIG. 8 is an explanatory diagram schematically showing a laminated state of the high-voltage side coil and the low-voltage side coil in the multilayer board of the transformer shown in the third embodiment.
  • FIG. 9 is a diagram summarizing the results of the test examples in a table.
  • a parasitic capacitance is formed between the two coil patterns arranged in the stacking direction. The smaller the distance between the two coil patterns, the larger the parasitic capacitance. Parasitic capacitance can reduce the conversion efficiency of the transformer.
  • One of the purposes of the present disclosure is to provide a transformer capable of suppressing a decrease in conversion efficiency due to parasitic capacitance, and a converter including the transformer.
  • Three parasitic capacitances are formed on the multilayer board. -The first parasitic capacitance formed between the two coil patterns that make up the high-voltage side coil. -A second parasitic capacitance formed between the two coil patterns that make up the low pressure side coil. -A third parasitic capacitance formed between the coil pattern of the low pressure side coil and the coil pattern of the high pressure side coil.
  • the first parasitic capacitance and the second parasitic capacitance can increase the loss of the switching device provided in the transformer. Of these three parasitic capacitances, the first parasitic capacitance has a great influence on the decrease in conversion efficiency.
  • the present inventors have completed the transformer and converter according to the present disclosure based on the above findings.
  • embodiments of the present disclosure will be described in a list.
  • the transformer according to the embodiment is High pressure side coil and Low pressure side coil and A transformer including a high-voltage side coil and a core penetrating the low-voltage side coil.
  • a multilayer substrate including a plurality of conductor pattern layers to be laminated and an insulating layer arranged between two conductor pattern layers adjacent to each other in the stacking direction is provided.
  • the plurality of conductor pattern layers are A plurality of high-voltage side pattern layers having coil patterns constituting the high-voltage side coil, A plurality of low pressure side pattern layers having a coil pattern constituting the low pressure side coil are included.
  • At least two low-voltage side pattern layers of the plurality of low-voltage side pattern layers are arranged between two high-voltage side pattern layers electrically connected in series.
  • the transformer according to the embodiment can suppress a decrease in conversion efficiency due to parasitic capacitance.
  • at least two low voltage side pattern layers are arranged between two high voltage side pattern layers electrically connected in series. That is, the distance between the two high-voltage side pattern layers connected in series is large. Therefore, the first parasitic capacitance formed between the two high-pressure side pattern layers becomes small. The first parasitic capacitance has a great influence on the decrease in the conversion efficiency of the transformer. Therefore, the transformer of the first embodiment having a small parasitic capacitance is excellent in conversion efficiency.
  • the coil pattern of the high-voltage side coil and the coil pattern of the low-voltage side coil are alternately laminated. That is, the configuration of Patent Document 1 is a configuration in which one low-voltage side pattern layer is arranged between two high-voltage side pattern layers electrically connected in series. In this configuration, the distance between the two high-pressure pattern layers is narrow and the first parasitic capacitance is large. Therefore, the transformer of Patent Document 1 tends to have lower conversion efficiency than the transformer of the embodiment.
  • the low-voltage side coil may be of a center tap type including a first low-voltage side coil and a second low-voltage side coil.
  • the center tap type transformer can build a full-wave rectification type converter.
  • the full-wave rectified converter can reduce the ripple of the rectified output.
  • At least a part of the high-voltage side pattern layers in the plurality of high-voltage side pattern layers may be electrically connected in parallel.
  • the configuration of the above form ⁇ 3> is a configuration in which one turn provided in the high-voltage side coil is distributed to different layers in the multilayer board. By distributing one turn to a plurality of layers, the width of the coil pattern in each layer can be narrowed. As a result, the plane area of the multilayer board seen from the thickness direction of the multilayer board becomes smaller, and the transformer becomes smaller.
  • the plurality of high-voltage side pattern layers electrically connected in parallel may be continuous in the stacking direction of the multilayer board.
  • the low-voltage side pattern layer does not have to exist between the plurality of high-voltage side pattern layers electrically connected in parallel.
  • At least a part of the low-voltage side pattern layers in the plurality of low-voltage side pattern layers may be electrically connected in parallel.
  • the configuration of the above form ⁇ 4> is a configuration in which one turn of the low-voltage side coil is distributed to different layers in the multilayer board. By distributing one turn to a plurality of layers, the width of the coil pattern in each layer can be narrowed. As a result, the plane area of the multilayer board seen from the thickness direction of the multilayer board becomes smaller, and the transformer becomes smaller.
  • ⁇ 5> As one form of the transformer according to the embodiment, Examples thereof include a form in which the first layer and the final layer in the plurality of conductor pattern layers are layers included in the plurality of low-voltage side pattern layers.
  • the low pressure side pattern layer By arranging the low pressure side pattern layer on the layer closest to the surface side of the multilayer board, it is easy to secure insulation between the multilayer board and the member close to the multilayer board. For example, when the multilayer board is fixed to the housing, it is easy to secure the insulation between the multilayer board and the housing.
  • the plurality of high-voltage side pattern layers may include a layer having a plurality of turns arranged in a spiral shape.
  • the number of turns of the high pressure side coil is larger than the number of turns of the low pressure side coil.
  • the configuration of ⁇ 6> above is a configuration that can solve such a problem.
  • the configuration of ⁇ 6> is a configuration in which a plurality of turns provided in the high-voltage side coil are arranged in one high-voltage side pattern layer. By arranging a plurality of turns in one high-voltage side pattern layer, the number of high-voltage side pattern layers in the transformer is reduced. If the number of high-voltage side pattern layers is small, two or more low-voltage side pattern layers are likely to be arranged between the high-voltage side pattern layers.
  • ⁇ 7> As one form of the transformer according to the embodiment, Examples thereof include a form in which the thickness of each of the plurality of insulating layers is 0.1 mm or more and 1.0 mm or less.
  • the thickness of the insulating layer is 0.1 mm or more, the parasitic capacitance formed between the two coil patterns arranged in the stacking direction becomes sufficiently small. If the thickness of the insulating layer is 1.0 mm or less, the thickness of the multilayer board does not become too thick.
  • the converter according to the embodiment is The transformer according to any one of ⁇ 1> to ⁇ 7> is provided.
  • the converter according to the embodiment includes a transformer capable of suppressing a decrease in conversion efficiency due to parasitic capacitance. Therefore, the converter according to the embodiment is excellent in conversion efficiency.
  • the converter 100 of this example includes a first circuit 1, a second circuit 2, and a transformer 3. Direct current is input to the first circuit 1 of this example.
  • the first circuit 1 of this example includes a low potential line 11 connected to the ground potential input terminal 1A and a high potential line 12 connected to the positive potential input terminal 1B.
  • the low potential line 11 extends from the input terminal 1A to one end of the high voltage side coil 31 of the transformer 3.
  • the high potential line 12 extends from the input terminal 1B to the other end of the high voltage side coil 31 of the transformer 3.
  • the first circuit 1 of this example includes a capacitor 1C on the input side and a switching circuit 1D.
  • the capacitor 1C on the input side is a device provided between the low potential line 11 and the high potential line 12, and reduces feedback noise.
  • the switching circuit 1D of this example provided between the low-potential line 11 and the high-potential line 12 is a conversion circuit that converts direct current into alternating current.
  • a known configuration can be used for the switching circuit 1D.
  • the switching circuit 1D of this example is composed of four rectifying elements 13 connected by a bridge.
  • the rectifying element 13 is a device that constitutes a part of the first circuit 1.
  • the rectifying element 13 of this example is a field effect transistor.
  • the rectifying element 13 may be a diode.
  • the transformer 3 converts the AC voltage.
  • the transformer 3 includes a high-voltage side coil 31, a low-voltage side coil 32, and a core 33.
  • the high pressure side coil 31 is a primary coil
  • the low pressure side coil is a secondary coil.
  • the high voltage side coil 31 is connected to the first circuit 1.
  • the low voltage side coil 32 is connected to the second circuit 2 described later.
  • the core 33 is penetrated by the high pressure side coil 31 and the low pressure side coil 32.
  • the transformer 3 in this example is a center tap type.
  • the low voltage side coil 32 includes a first low voltage side coil 321 and a second low voltage side coil 322.
  • the second conductive line 22 of the second circuit 2 which will be described later, is connected between the first low-voltage side coil 321 and the second low-voltage side coil 322.
  • the second circuit 2 of this example includes a first conductive line 21 and a second conductive line 22.
  • the first conductive line 21 is connected from both ends of the low voltage side coil 32 of the transformer 3 to the output terminal 2A which is the ground potential. More specifically, there is a first conductive line 21 from the first low-voltage side coil 321 to the output terminal 2A, and a first conductive line 21 from the second low-voltage side coil 322 to the output terminal 2A. Both conductive lines 21 are connected at a contact 21b. The first conductive line 21 is grounded by the ground 29.
  • the second conductive line 22 that functions as a center tap reaches the output terminal 2B, which has a positive potential, from the low-voltage side coil 32 of the transformer 3 by a path different from that of the first conductive line 21.
  • the first conductive line 21 and the second conductive line 22 are not connected from the low-voltage side coil 32 to the output terminals 2A and 2B.
  • a rectifier circuit 2C and a filter circuit 2D are provided between the first conductive line 21 and the second conductive line 22.
  • the rectifier circuit 2C of this example a known conversion circuit that converts alternating current into direct current can be used.
  • the rectifier circuit 2C of this example includes two rectifier elements 211 and 212.
  • the rectifying elements 211 and 212 are devices included in the first conductive line 21.
  • the rectifying element 211 is provided between the first low-voltage side coil 321 and the contact 21b.
  • the rectifying element 212 is provided between the second low-voltage side coil 322 and the contact 21b.
  • the rectifying elements 211 and 212 of this example are field effect transistors. Unlike this example, the rectifying elements 211 and 212 may be diodes.
  • the filter circuit 2D of this example is a low-pass filter.
  • the filter circuit 2D includes an inductor 23 and a capacitor 24 on the output side as devices.
  • the inductor 23 is provided on the second conductive line 22.
  • the capacitor 24 is provided between a portion of the first conductive line 21 downstream of the contact 21b and a portion of the second conductive line 22 downstream of the inductor 23.
  • the filter circuit 2D of this example is an L-type filter, but may be a ⁇ -type filter or a T-type filter.
  • the structure of the transformer 3 of this example will be described with reference to FIGS. 2 to 5.
  • the transformer 3 of this example includes a core 33 having a substantially eight-shaped shape (see FIG. 3) and a multilayer substrate 4 including a high-voltage side coil 31 and a low-voltage side coil 32 (see FIG. 4).
  • the core 33 may be annular.
  • the core 33 of this example is an assembly of a first core member 331 and a second core member 332 (see FIG. 3).
  • the first core member 331 is a magnetic material having a substantially E-shape.
  • the three leg pieces of the first core member 331 are arranged inside the through holes 41, 42, and 43 provided in the multilayer board 4, respectively.
  • the second core member 332 is a magnetic material having a substantially I-shape.
  • the second core member 332 is arranged so as to connect the three leg pieces of the first core member 331.
  • the core 33 is a sintered body such as a ferrite core.
  • the core 33 may be a powder compact, a composite material molded body, or a laminated steel plate.
  • the compaction compact is a magnetic member obtained by compression molding soft magnetic powder.
  • the molded body of the composite material is a magnetic member obtained by curing a fluid resin in which soft magnetic powder is dispersed.
  • the laminated steel sheet is a laminated body in which electromagnetic steel sheets are laminated.
  • the multilayer board 4 is an insulating layer arranged between a plurality of conductor pattern layers L1 to L6 to be laminated and two conductor pattern layers L1 to L6 adjacent to each other in the stacking direction. Includes 40 and.
  • FIG. 4 schematically shows a laminated state of the conductor pattern layers L1 to L6 and the insulating layer 40, and is not a cross-sectional view of FIGS. 2 and 3.
  • the conductor pattern layers L2 and L5 of this example are high-voltage side pattern layers 5 having a coil pattern 50 constituting the high-voltage side coil 31.
  • the coil pattern 50 is composed of a thin film.
  • a metal such as copper, which has excellent conductivity, is suitable for the thin film.
  • the portions of the conductor pattern layers L2 and L5 other than the coil pattern 50 are made of an insulating material integrated with the insulating layer 40.
  • the coil patterns 50 of the conductor pattern layers L2 and L5 of this example are arranged so as to surround the through holes 42 of the multilayer board 4.
  • the central leg piece of the first core member 331 is arranged in the through hole 42.
  • the coil pattern 50 is configured by arranging a plurality of turns of the high-voltage side coil 31 in a spiral shape.
  • the three turns of the high-voltage side coil 31 constitute one coil pattern 50.
  • one turn may constitute one coil pattern 50.
  • the coil pattern 50 in the conductor pattern layer L2 is composed of three spiral turns whose diameters gradually decrease from the outside to the inside. The three turns orbit counterclockwise from the outside to the inside.
  • the outer peripheral end of the coil pattern 50 arranged on the upper left of the paper surface corresponds to one end of the high-voltage side coil 31.
  • the upper left end of the coil pattern 50 is connected to the first circuit 1 in FIG.
  • the coil pattern 50 in the conductor pattern layer L5 is composed of three spiral turns whose diameters gradually increase from the inside to the outside. The three turns orbit counterclockwise from the inside to the outside.
  • the outer peripheral end of the coil pattern 50 arranged on the upper right of the paper surface corresponds to the other end of the high-voltage side coil 31.
  • the upper right end of the coil pattern 50 is connected to the first circuit 1 in FIG.
  • the coil pattern 50 of the conductor pattern layer L2 and the coil pattern 50 of the conductor pattern layer L5 are electrically connected via the via 51. That is, the conductor pattern layer L2 which is the high-voltage side pattern layer 5 and the conductor pattern layer L5 which is the high-voltage side pattern layer 5 are electrically connected in series. Therefore, the number of turns of the high-voltage side coil 31 in this example is 6.
  • the conductor pattern layers L1 and L4 of this example are low-voltage side pattern layers 6 having a coil pattern 60 constituting the first low-voltage side coil 321.
  • the conductive pattern layers L3 and L6 are low-voltage side pattern layers 6 having a coil pattern 60 constituting the second low-voltage side coil 322.
  • the coil pattern 60 is composed of a thin metal film having excellent conductivity.
  • the portions of the conductive pattern layers L1, L3, L4, and L6 other than the coil pattern 60 are made of an insulating material integrated with the insulating layer 40.
  • the conductor pattern layer L1 is arranged so as to surround the through hole 42 of the multilayer board 4.
  • Other conductor pattern layers L3, L4, and L6 (FIG. 4) are also arranged so as to surround the through hole 42.
  • These conductor pattern layers L1, L3, L4, and L6, which are the low-pressure side pattern layers 6, are arranged at overlapping positions when the multilayer substrate 4 is viewed in a plan view.
  • these conductor pattern layers L1, L3, L4, and L6 are arranged at positions overlapping with the conductor pattern layers L2 and L5, which are the high-voltage side pattern layers 5, when the multilayer substrate 4 is viewed in a plan view.
  • the coil pattern 60 in the conductor pattern layer L1 is composed of one turn of the first low pressure side coil 321 (see FIG. 2). Unlike this example, the coil pattern 60 may be composed of a plurality of turns arranged in a spiral shape.
  • the conductor pattern layer L1 and the conductor pattern layer L4 constituting the first low-voltage side coil 321 are electrically connected in parallel via a via 61 (see FIG. 2). Therefore, the number of turns of the first low-pressure side coil 321 of this example is 1. Further, the conductor pattern layer L3 and the conductor pattern layer L6 constituting the second low-voltage side coil 322 are electrically connected in parallel via vias (not shown). Therefore, the number of turns of the second low pressure side coil 322 is 1.
  • one turn of the first low-voltage side coil 321 and the second low-voltage side coil 322 is distributed to a plurality of layers, so that the coil pattern 60 of each conductor pattern layer L1, L3, L4, L6
  • the width of the strip-shaped thin film becomes smaller.
  • the plane area of the multilayer board 4 becomes smaller.
  • the coil pattern 60 of the conductor pattern layers L1 and L4 and the coil pattern 60 of the conductor pattern layers L3 and L6 are electrically connected. Both ends of the coil pattern 60 of the conductor pattern layers L1 and L4 are connected to the first conductive line 21 on the upper side of FIG. Both ends of the coil pattern 60 of the conductor pattern layers L3 and L6 are connected to the lower first conductive line 21 in FIG.
  • the second conductive line 22, which is a center tap, is electrically connected to the conductor patterns L1, L3, L4, and L6.
  • a parasitic capacitance 7 is formed between the coil patterns 50 and 60 of the conductor pattern layers L1 to L6 in the above-mentioned laminated state.
  • the parasitic capacitance 7 formed between the two coil patterns 50 electrically connected in series is referred to as the first parasitic capacitance 71.
  • the parasitic capacitance 7 formed between the two coil patterns 60 electrically connected in series is the second parasitic capacitance.
  • the parasitic capacitance 7 formed between the coil pattern 50 and the coil pattern 60 is referred to as a third parasitic capacitance 73.
  • the first parasitic capacitance 71 increases the switching loss and greatly affects the decrease in the conversion efficiency of the transformer 3. That is, when the first parasitic capacitance 71 becomes small, the decrease in the conversion efficiency of the transformer 3 is likely to be suppressed.
  • the insulation layer 40 is made of an epoxy resin or the like.
  • the thickness of the insulating layer 40 is a thickness that can secure insulation between the coil patterns 50 and 50 adjacent to each other in the stacking direction, between the coil patterns 50 and 60, and between the coil patterns 60 and 60.
  • the thickness of the insulating layer 40 is 0.1 mm or more and 1.0 mm or less.
  • the thickness of the insulating layer 40 is 0.1 mm or more, the parasitic capacitance 7 formed between the coil patterns arranged in the stacking direction is sufficiently small.
  • the thickness of the insulating layer 40 is 1.0 mm or less, the thickness of the multilayer board 4 does not become too thick.
  • a more preferable thickness of the insulating layer 40 is 0.2 mm or more and 0.5 mm or less.
  • a more preferable thickness of the insulating layer 40 is 0.25 mm or more and 0.4 mm or less.
  • the conductor pattern layer L1 which is the first layer and the conductor pattern layer L6 which is the final layer are the low voltage side pattern layer 6.
  • the transformer 3 of this example when the transformer 3 of this example is fixed to a housing or the like, it is easy to secure insulation between the multilayer board 4 and the housing.
  • an insulating member (not shown) is interposed between the multilayer board 4 and the housing.
  • the insulating layer 40 may be arranged on at least one of the outside of the conductor pattern layer L1 and the outside of the conductor pattern layer L8. In this case, when fixing the multilayer board 4 to a housing or the like, it is not necessary to separately prepare an insulating member.
  • two low-voltage side pattern layers 6 and 6 are arranged between two high-voltage side pattern layers 5 and 5 electrically connected in series, that is, between conductor pattern layers L2 and L5. ing.
  • the distance between the conductor pattern layers L2 and L5 is the same as the sum of the thicknesses of the three insulating layers 40 and the thicknesses of the two low-voltage side pattern layers 6 and 6. Therefore, the first parasitic capacitance 71 formed between the conductor pattern layers L2 and L5 is sufficiently small. Therefore, the transformer 3 of this example can suppress the decrease in conversion efficiency due to the parasitic capacitance 7.
  • the high-voltage side pattern layer 5 includes a coil pattern 50 in which a plurality of turns of the high-voltage side coil 31 are arranged in a spiral shape (FIG. 5).
  • a coil pattern 50 in which a plurality of turns of the high-voltage side coil 31 are arranged in a spiral shape (FIG. 5).
  • the conductor pattern layer L1 and the conductor pattern layer L4, which are the low-voltage side pattern layers 6, are electrically connected in parallel, and the conductor pattern layer L3 and the conductor pattern layer L6 are electrically connected in parallel.
  • the number of the low pressure side pattern layer 6 is larger than the number of turns of the low pressure side coil 32. If the number of the low-voltage side pattern layers 6 is large, two or more low-voltage side pattern layers 6 are likely to be arranged between the two high-voltage side pattern layers 5 and 5 connected in series.
  • the converter 100 of FIG. 1 including the transformer 3 of this example can suppress a decrease in conversion efficiency due to the first parasitic capacitance 71.
  • the transformer 3 of the second embodiment includes eight conductor pattern layers L1 to L8.
  • the conductor pattern layers L2, L3, L6, and L7 are high-voltage side pattern layers 5 constituting the high-voltage side coil 31.
  • each of the coil patterns 50 of the conductor pattern layers L2, L3, L6, and L7 has a configuration in which a plurality of turns are arranged in a spiral shape.
  • the coil pattern 50 of the conductor pattern layer L2 and the coil pattern 50 of the conductor pattern layer L3 have the same shape.
  • the winding direction is counterclockwise from the outside to the inside.
  • the coil pattern 50 of the conductor pattern layer L6 and the coil pattern 50 of the conductor pattern layer L7 have the same shape.
  • the winding direction is clockwise from the outside to the inside.
  • the outer peripheral ends of the coil patterns 50 of the conductor patterns L2 and L3 are both electrically connected via the via 52. Further, the outer peripheral ends of the coil patterns 50 of the conductor patterns L6 and L7 are both electrically connected via the via 53.
  • the central ends of the four spiral coil patterns 50 are electrically connected via vias 51.
  • the conductor pattern layer L2 and the conductor pattern layer L3 having the same shape are electrically connected in parallel.
  • the conductor pattern layer L6 having the same shape and the conductor pattern layer L7 are electrically connected in parallel.
  • the conductor pattern layers L2 and L3 and the conductor pattern layers L6 and L7 are electrically connected in series. No parasitic capacitance is formed between the conductor pattern layer L2 and the conductor pattern layer L3 electrically connected in parallel, and between the conductor pattern layer L6 and the conductor pattern layer L7.
  • the conductor pattern layers L1, L4, L5, and L8 are low-voltage side pattern layers 6 constituting the low-voltage side coil 32 (see FIG. 1). More specifically, the conductor pattern layers L1 and L5 are low-voltage side pattern layers 6 constituting the first low-voltage side coil 321 and are electrically connected in parallel. The conductor pattern layers L4 and L8 are low-voltage side pattern layers 6 constituting the second low-voltage side coil 322, and are electrically connected in parallel.
  • two low-voltage side pattern layers 6 and 6 are arranged between the high-voltage side pattern layers 5 and 5 electrically connected in series.
  • the conductor pattern layer L4 and the conductor pattern layer L5 are arranged between the conductor pattern layer L3 and the conductor pattern layer L6. Therefore, the first parasitic capacitance 71 in the transformer 3 of this example is small.
  • the turn of the high-voltage side coil 31 is distributed to a plurality of layers, so that the width of the coil pattern 50 of each conductor pattern layer L2, L3, L6, L7 becomes smaller. As a result, the plane area of the multilayer board 4 becomes smaller.
  • the transformer 3 of the third embodiment includes eight conductor pattern layers L1 to L8.
  • the conductor pattern layers L2 and L7 are high-voltage side pattern layers 5 constituting the high-voltage side coil 31.
  • the configurations of the conductor pattern layers L2 and L7 are the same as the configurations of the conductor pattern layers L2 and L5 (see FIG. 5) of the first embodiment.
  • the conductor pattern layers L1, L3, L4, L5, L6, and L8 are low-voltage side pattern layers 6 constituting the low-voltage side coil 32 (see FIG. 1). More specifically, the conductor pattern layers L1, L4, and L6 are low-voltage side pattern layers 6 constituting the first low-voltage side coil 321 and are electrically connected in parallel. The conductor pattern layers L3, L5, and L8 are low-voltage side pattern layers 6 constituting the second low-voltage side coil 322, and are electrically connected in parallel. The first low-voltage side coil 321 and the second low-voltage side coil 322 are electrically connected in series.
  • the conductor pattern layers L3, L4, L5, and L6 are arranged between the conductor pattern layer L2 and the conductor pattern layer L7. Therefore, the first parasitic capacitance 71 in the transformer 3 of this example is small.
  • the magnitude of parasitic capacitance in three transformers with different stacked states was determined by simulation. The configuration of the transformer used as a sample is as follows.
  • the multilayer board 4 of the transformer 3 of 1 includes eight conductor pattern layers L1 to L8.
  • the conductor pattern layers L2, L4, L5 and L7 are high-voltage side pattern layers 5, and the conductor pattern layers L1, L6, L3 and L8 are low-voltage side pattern layers 6.
  • a schematic diagram showing the arrangement state of each layer is shown in the table of FIG.
  • the conductor pattern layer L2 and the conductor pattern layer L4, the conductor pattern layer L5 and the conductor pattern layer L7, the conductor pattern layer L1 and the conductor pattern layer L6, and the conductor pattern layer L3 and the conductor pattern layer L8 are electrically connected in parallel. There is. Only the insulating layer is arranged between the conductor pattern layer L4 and the conductor pattern layer L5, which are the high-voltage side pattern layers 5 connected in series.
  • Sample No. 2 The thickness, size, and number of layers of the multilayer board 4 of 2 are the sample No. It is the same as the multilayer board 4 of 1.
  • the conductor pattern layers L2, L3, L6, and L7 are high-voltage side pattern layers 5, and the conductor pattern layers L1, L4, L5, and L8 are low-voltage side pattern layers 6.
  • the conductor pattern layer L2 and the conductor pattern layer L3, the conductor pattern layer L6 and the conductor pattern layer L7, the conductor pattern layer L1 and the conductor pattern layer L4, and the conductor pattern layer L5 and the conductor pattern layer L8 are electrically connected in parallel.
  • the conductor pattern layers L4 and L5, which are the low-voltage side pattern layers 6, are arranged between the conductor pattern layer L3, which is the high-voltage side pattern layer 5 connected in series, and the conductor pattern layer L6.
  • Sample No. 3 Sample No.
  • the thickness, size, and number of layers of the multilayer board 4 of 3 are the sample No. It is the same as the multilayer board 4 of 1.
  • the conductor pattern layers L2, L3, L6, and L7 are high-voltage side pattern layers 5, and the conductor pattern layers L1, L4, L5, and L8 are low-voltage side pattern layers 6.
  • the conductor pattern layer L2 and the conductor pattern layer L3, the conductor pattern layer L6 and the conductor pattern layer L7, the conductor pattern layer L1 and the conductor pattern layer L5, and the conductor pattern layer L4 and the conductor pattern layer L8 are electrically connected in parallel. There is.
  • the conductor pattern layers L4 and L5, which are the low-voltage side pattern layers 6, are arranged between the conductor pattern layer L3, which is the high-voltage side pattern layer 5 connected in series, and the conductor pattern layer L6.
  • This sample No. Reference numeral 3 is the above-mentioned sample No.
  • the positions of the conductor pattern layer L4 and the conductor pattern layer L5 of 2 are exchanged. Therefore, the sample No. In the configuration of 3, the conductor pattern layer L4 of the second low-voltage side coil 322 is arranged between the conductor pattern layer L1 of the first low-voltage side coil 321 and the conductor pattern layer L5 connected in parallel. Further, the conductor pattern layer L5 of the first low-voltage side coil 321 is arranged between the conductor pattern layer L4 of the second low-voltage side coil 322 and the conductor pattern layer L8 connected in parallel.
  • the sample No. The first parasitic capacitance 71 of a few is the sample No. It was 30% or less of the first parasitic capacitance 71 of 1. The reason for this result is the sample No. This is because, in 2 and 3, two low-voltage side pattern layers 6 are arranged between the high-voltage side pattern layers 5 connected in series.
  • the second parasitic capacitance 72 of 3 is the sample No. It was larger than the second parasitic capacitance 72 of 1.
  • the reason for this result is that among the plurality of conductor pattern layers L1, L4, L5 and L8 which are the low pressure side pattern layers 6, the conductor pattern layers L4 and L5 adjacent to each other in the stacking direction exist.
  • the third parasitic capacitance 73 of a few is the sample No. It was 60% or less of the third parasitic capacitance 73 of 1. The reason for this result is that among the plurality of conductor pattern layers L1, L4, L5, L8 which are the low-voltage side pattern layers 6, there are conductor pattern layers L4, L5 that do not sandwich the high-voltage side pattern layer 5.
  • the first parasitic capacitance 71 has the greatest effect on the decrease in the conversion efficiency of the transformer 3. Therefore, the sample No.
  • the transformers 3 of 2 and 3 are the sample No. It is superior in conversion efficiency to the transformer 3 of 1.

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Abstract

This transformer comprises a high-voltage coil, a low-voltage coil, and a core that passes through the high-voltage coil and the low-voltage coil, the transformer comprising a multilayer substrate including a plurality of stacked conductor pattern layers and insulating layers each disposed between two adjacent conductor pattern layers in the stacking direction, wherein: the plurality of stacked conductor pattern layers includes a plurality of high-voltage pattern layers that have coil patterns that constitute the high-voltage coil, and a plurality of low-voltage pattern layers that have coil patterns that constitute the low-voltage coil; and at least two low-voltage pattern layers among the plurality of low-voltage pattern layers are disposed between two high-voltage pattern layers electrically connected in series among the plurality of high-voltage pattern layers.

Description

トランス及びコンバータTransformers and converters
　本開示は、トランス及びコンバータに関する。 This disclosure relates to transformers and converters.
　特許文献１には、励磁側のコイルと受電側のコイルとが多層基板上に設けられたトランスが開示されている。特許文献１では、励磁側のコイルを構成するコイルパターンと、受電側のコイルを構成するコイルパターンとが、多層基板の厚み方向に交互に積層されている。励磁側のコイルと受電側のコイルのうち、一方は高電圧で使用される高圧側コイル、他方は低電圧で使用される低圧側コイルである。 Patent Document 1 discloses a transformer in which a coil on the exciting side and a coil on the power receiving side are provided on a multilayer board. In Patent Document 1, the coil pattern constituting the coil on the exciting side and the coil pattern constituting the coil on the power receiving side are alternately laminated in the thickness direction of the multilayer board. Of the coil on the exciting side and the coil on the power receiving side, one is a high-voltage side coil used at a high voltage and the other is a low-voltage side coil used at a low voltage.
特開２０１０－９３１７４号公報Japanese Unexamined Patent Publication No. 2010-93174
　本開示のトランスは、
　高圧側コイルと、
　低圧側コイルと、
　前記高圧側コイル及び前記低圧側コイルを貫通するコアとを備えるトランスであって、
　積層される複数の導体パターン層と、積層方向に隣接する二つの導体パターン層の間に配置される絶縁層とを含む多層基板を備え、
　前記複数の導体パターン層は、
　　前記高圧側コイルを構成するコイルパターンを有する複数の高圧側パターン層と、
　　前記低圧側コイルを構成するコイルパターンを有する複数の低圧側パターン層とを含み、
　前記複数の高圧側パターン層のうち、電気的に直列に接続される二つの高圧側パターン層の間に、前記複数の低圧側パターン層のうちの少なくとも二つの低圧側パターン層が配置される。 The transformers in this disclosure are
High pressure side coil and
Low pressure side coil and
A transformer including a high-voltage side coil and a core penetrating the low-voltage side coil.
A multilayer substrate including a plurality of conductor pattern layers to be laminated and an insulating layer arranged between two conductor pattern layers adjacent to each other in the stacking direction is provided.
The plurality of conductor pattern layers are
A plurality of high-voltage side pattern layers having coil patterns constituting the high-voltage side coil,
A plurality of low pressure side pattern layers having a coil pattern constituting the low pressure side coil are included.
Of the plurality of high-voltage side pattern layers, at least two low-voltage side pattern layers of the plurality of low-voltage side pattern layers are arranged between two high-voltage side pattern layers electrically connected in series.
　本開示のコンバータは、
　本開示のトランスを備える。 The converters of the present disclosure are
The transformer of the present disclosure is provided.
図１は、実施形態１に示されるコンバータの回路図である。FIG. 1 is a circuit diagram of the converter shown in the first embodiment. 図２は、実施形態１に示されるトランスの概略上面図である。FIG. 2 is a schematic top view of the transformer shown in the first embodiment. 図３は、実施形態１に示されるトランスの概略側面図である。FIG. 3 is a schematic side view of the transformer shown in the first embodiment. 図４は、実施形態１に示されるトランスの多層基板における高圧側コイルと低圧側コイルの積層状態を模式的に示す説明図である。FIG. 4 is an explanatory diagram schematically showing a laminated state of the high-voltage side coil and the low-voltage side coil in the multilayer board of the transformer shown in the first embodiment. 図５は、実施形態１に示されるトランスにおける高圧側コイルのコイルパターンの概略平面図である。FIG. 5 is a schematic plan view of the coil pattern of the high-voltage side coil in the transformer shown in the first embodiment. 図６は、実施形態２に示されるトランスの多層基板における高圧側コイルと低圧側コイルの積層状態を模式的に示す説明図である。FIG. 6 is an explanatory diagram schematically showing a laminated state of the high-voltage side coil and the low-voltage side coil in the multilayer board of the transformer shown in the second embodiment. 図７は、実施形態２に示されるトランスにおける高圧側コイルのコイルパターンの概略平面図である。FIG. 7 is a schematic plan view of the coil pattern of the high-voltage side coil in the transformer shown in the second embodiment. 図８は、実施形態３に示されるトランスの多層基板における高圧側コイルと低圧側コイルの積層状態を模式的に示す説明図である。FIG. 8 is an explanatory diagram schematically showing a laminated state of the high-voltage side coil and the low-voltage side coil in the multilayer board of the transformer shown in the third embodiment. 図９は、試験例の結果を表にまとめた図である。FIG. 9 is a diagram summarizing the results of the test examples in a table.
［本開示が解決しようとする課題］
　高圧側コイルのコイルパターンと、低圧側コイルのコイルパターンとが交互に積層されるトランスでは、積層方向に並ぶ二つのコイルパターンの間に寄生容量が形成される。前記二つのコイルパターンの間隔が小さいほど、寄生容量は大きくなる。寄生容量は、トランスの変換効率を低下させる恐れがある。 [Problems to be solved by this disclosure]
In a transformer in which the coil pattern of the high-voltage side coil and the coil pattern of the low-voltage side coil are alternately laminated, a parasitic capacitance is formed between the two coil patterns arranged in the stacking direction. The smaller the distance between the two coil patterns, the larger the parasitic capacitance. Parasitic capacitance can reduce the conversion efficiency of the transformer.
　本開示は、寄生容量に起因する変換効率の低下を抑制できるトランス、及びそのトランスを備えるコンバータを提供することを目的の一つとする。 One of the purposes of the present disclosure is to provide a transformer capable of suppressing a decrease in conversion efficiency due to parasitic capacitance, and a converter including the transformer.
［本開示の実施形態の説明］
　本発明者らが上記課題について鋭意検討した結果、以下の知見を得た。
　多層基板において、三つの寄生容量が形成される。
・高圧側コイルを構成する二つのコイルパターンの間に形成される第一の寄生容量。
・低圧側コイルを構成する二つのコイルパターンの間に形成される第二の寄生容量。
・低圧側コイルのコイルパターンと高圧側コイルのコイルパターンとの間に形成される第三の寄生容量。
　第一の寄生容量と第二の寄生容量は、トランスに備わるスイッチングデバイスの損失を増加させる恐れがある。これらの三つの寄生容量のうち、特に第一の寄生容量が変換効率の低下に大きな影響を与える。 [Explanation of Embodiments of the present disclosure]
As a result of diligent studies by the present inventors on the above problems, the following findings were obtained.
Three parasitic capacitances are formed on the multilayer board.
-The first parasitic capacitance formed between the two coil patterns that make up the high-voltage side coil.
-A second parasitic capacitance formed between the two coil patterns that make up the low pressure side coil.
-A third parasitic capacitance formed between the coil pattern of the low pressure side coil and the coil pattern of the high pressure side coil.
The first parasitic capacitance and the second parasitic capacitance can increase the loss of the switching device provided in the transformer. Of these three parasitic capacitances, the first parasitic capacitance has a great influence on the decrease in conversion efficiency.
　本発明者らは、上記知見に基づいて本開示に係るトランス及びコンバータを完成させた。以下、本開示の実施態様を列記して説明する。 The present inventors have completed the transformer and converter according to the present disclosure based on the above findings. Hereinafter, embodiments of the present disclosure will be described in a list.
＜１＞実施形態に係るトランスは、
　高圧側コイルと、
　低圧側コイルと、
　前記高圧側コイル及び前記低圧側コイルを貫通するコアとを備えるトランスであって、
　積層される複数の導体パターン層と、積層方向に隣接する二つの導体パターン層の間に配置される絶縁層とを含む多層基板を備え、
　前記複数の導体パターン層は、
　　前記高圧側コイルを構成するコイルパターンを有する複数の高圧側パターン層と、
　　前記低圧側コイルを構成するコイルパターンを有する複数の低圧側パターン層とを含み、
　前記複数の高圧側パターン層のうち、電気的に直列に接続される二つの高圧側パターン層の間に、前記複数の低圧側パターン層のうちの少なくとも二つの低圧側パターン層が配置される。 <1> The transformer according to the embodiment is
High pressure side coil and
Low pressure side coil and
A transformer including a high-voltage side coil and a core penetrating the low-voltage side coil.
A multilayer substrate including a plurality of conductor pattern layers to be laminated and an insulating layer arranged between two conductor pattern layers adjacent to each other in the stacking direction is provided.
The plurality of conductor pattern layers are
A plurality of high-voltage side pattern layers having coil patterns constituting the high-voltage side coil,
A plurality of low pressure side pattern layers having a coil pattern constituting the low pressure side coil are included.
Of the plurality of high-voltage side pattern layers, at least two low-voltage side pattern layers of the plurality of low-voltage side pattern layers are arranged between two high-voltage side pattern layers electrically connected in series.
　実施形態に係るトランスは、寄生容量に起因する変換効率の低下を抑制できる。
　実施形態に係るトランスでは、電気的に直列に接続される二つの高圧側パターン層の間に、少なくとも二つの低圧側パターン層が配置されている。つまり、直列に接続される二つの高圧側パターン層の間隔が大きくなっている。従って、二つの高圧側パターン層の間に形成される第一の寄生容量が小さくなる。第一の寄生容量はトランスの変換効率の低下に大きな影響を与える。そのため、第一の寄生容量が小さい実施形態のトランスは、変換効率に優れる。 The transformer according to the embodiment can suppress a decrease in conversion efficiency due to parasitic capacitance.
In the transformer according to the embodiment, at least two low voltage side pattern layers are arranged between two high voltage side pattern layers electrically connected in series. That is, the distance between the two high-voltage side pattern layers connected in series is large. Therefore, the first parasitic capacitance formed between the two high-pressure side pattern layers becomes small. The first parasitic capacitance has a great influence on the decrease in the conversion efficiency of the transformer. Therefore, the transformer of the first embodiment having a small parasitic capacitance is excellent in conversion efficiency.
　ここで、特許文献１の構成では、高圧側コイルのコイルパターンと、低圧側コイルのコイルパターンとが交互に積層されている。つまり、特許文献１の構成は、電気的に直列に接続される二つの高圧側パターン層の間に、一つの低圧側パターン層が配置される構成である。この構成では、二つの高圧側パターン層の間隔が狭く、第一の寄生容量が大きい。従って、特許文献１のトランスは、実施形態のトランスよりも変換効率が低下し易い。 Here, in the configuration of Patent Document 1, the coil pattern of the high-voltage side coil and the coil pattern of the low-voltage side coil are alternately laminated. That is, the configuration of Patent Document 1 is a configuration in which one low-voltage side pattern layer is arranged between two high-voltage side pattern layers electrically connected in series. In this configuration, the distance between the two high-pressure pattern layers is narrow and the first parasitic capacitance is large. Therefore, the transformer of Patent Document 1 tends to have lower conversion efficiency than the transformer of the embodiment.
＜２＞実施形態に係るトランスの一形態として、
　前記低圧側コイルは、第一の低圧側コイルと第二の低圧側コイルとを備えるセンタータップ型である形態が挙げられる。 <2> As one form of the transformer according to the embodiment,
The low-voltage side coil may be of a center tap type including a first low-voltage side coil and a second low-voltage side coil.
　センタータップ型のトランスは、全波整流型のコンバータを構築できる。全波整流型のコンバータは、整流出力のリップルを小さくできる。 The center tap type transformer can build a full-wave rectification type converter. The full-wave rectified converter can reduce the ripple of the rectified output.
＜３＞実施形態に係るトランスの一形態として、
　前記複数の高圧側パターン層における少なくとも一部の高圧側パターン層は、電気的に並列に接続される形態が挙げられる。 <3> As one form of the transformer according to the embodiment,
At least a part of the high-voltage side pattern layers in the plurality of high-voltage side pattern layers may be electrically connected in parallel.
　上記形態＜３＞の構成は、高圧側コイルに備わる一つのターンを、多層基板における異なる層に分配した構成である。一つのターンを複数の層に分配することで、各層におけるコイルパターンの幅を狭くできる。その結果、多層基板の厚み方向から見た多層基板の平面面積が小さくなり、トランスが小型化する。 The configuration of the above form <3> is a configuration in which one turn provided in the high-voltage side coil is distributed to different layers in the multilayer board. By distributing one turn to a plurality of layers, the width of the coil pattern in each layer can be narrowed. As a result, the plane area of the multilayer board seen from the thickness direction of the multilayer board becomes smaller, and the transformer becomes smaller.
　ここで、電気的に並列に接続される導体パターン層の間には寄生容量は形成されない。従って、電気的に並列に接続される複数の高圧側パターン層は、多層基板の積層方向に連続していても良い。別の言い方をすれば、電気的に並列に接続される複数の高圧側パターン層の間に、低圧側パターン層が存在しなくても良い。 Here, no parasitic capacitance is formed between the conductor pattern layers that are electrically connected in parallel. Therefore, the plurality of high-voltage side pattern layers electrically connected in parallel may be continuous in the stacking direction of the multilayer board. In other words, the low-voltage side pattern layer does not have to exist between the plurality of high-voltage side pattern layers electrically connected in parallel.
＜４＞実施形態に係るトランスの一形態として、
　前記複数の低圧側パターン層における少なくとも一部の低圧側パターン層は、電気的に並列に接続される形態が挙げられる。 <4> As one form of the transformer according to the embodiment,
At least a part of the low-voltage side pattern layers in the plurality of low-voltage side pattern layers may be electrically connected in parallel.
　上記形態＜４＞の構成は、低圧側コイルの一つのターンを、多層基板における異なる層に分配した構成である。一つのターンを複数の層に分配することで、各層におけるコイルパターンの幅を狭くできる。その結果、多層基板の厚み方向から見た多層基板の平面面積が小さくなり、トランスが小型化する。 The configuration of the above form <4> is a configuration in which one turn of the low-voltage side coil is distributed to different layers in the multilayer board. By distributing one turn to a plurality of layers, the width of the coil pattern in each layer can be narrowed. As a result, the plane area of the multilayer board seen from the thickness direction of the multilayer board becomes smaller, and the transformer becomes smaller.
　上記形態＜４＞の構成では、低圧側コイルを構成する低圧側パターン層が増える。従って、直列接続される二つの高圧側パターン層の間に、二つ以上の低圧側パターン層を配置することが容易になる。 In the configuration of the above form <4>, the number of low-voltage side pattern layers constituting the low-voltage side coil increases. Therefore, it becomes easy to arrange two or more low-voltage side pattern layers between the two high-voltage side pattern layers connected in series.
＜５＞実施形態に係るトランスの一形態として、
　前記複数の導体パターン層における第一層と最終層とが、前記複数の低圧側パターン層に含まれる層である形態が挙げられる。 <5> As one form of the transformer according to the embodiment,
Examples thereof include a form in which the first layer and the final layer in the plurality of conductor pattern layers are layers included in the plurality of low-voltage side pattern layers.
　多層基板の表面側に最も近い層に低圧側パターン層が配置されることで、多層基板と、多層基板に近接する部材との絶縁を確保し易い。例えば、多層基板が筐体に固定される場合、多層基板と筐体との絶縁を確保し易い。 By arranging the low pressure side pattern layer on the layer closest to the surface side of the multilayer board, it is easy to secure insulation between the multilayer board and the member close to the multilayer board. For example, when the multilayer board is fixed to the housing, it is easy to secure the insulation between the multilayer board and the housing.
＜６＞実施形態に係るトランスの一形態として、
　前記複数の高圧側パターン層は、渦巻き状に配置される複数のターンを有する層を含む形態が挙げられる。 <6> As one form of the transformer according to the embodiment,
The plurality of high-voltage side pattern layers may include a layer having a plurality of turns arranged in a spiral shape.
　高圧側コイルのターン数は、低圧側コイルのターン数よりも多い。高圧側コイルのターン数と低圧側コイルのターン数によっては、高圧側パターン層の間に二つ以上の低圧側パターン層を配置することが難しい場合がある。上記＜６＞の構成は、このような問題を解消し得る構成である。上記＜６＞の構成は、高圧側コイルに備わる複数のターンが一つの高圧側パターン層に配置される構成である。一つの高圧側パターン層に複数のターンが配置されることで、トランスにおける高圧側パターン層の数が少なくなる。高圧側パターン層の数が少なければ、高圧側パターン層の間に二つ以上の低圧側パターン層が配置され易い。 The number of turns of the high pressure side coil is larger than the number of turns of the low pressure side coil. Depending on the number of turns of the high-voltage side coil and the number of turns of the low-voltage side coil, it may be difficult to arrange two or more low-voltage side pattern layers between the high-voltage side pattern layers. The configuration of <6> above is a configuration that can solve such a problem. The configuration of <6> is a configuration in which a plurality of turns provided in the high-voltage side coil are arranged in one high-voltage side pattern layer. By arranging a plurality of turns in one high-voltage side pattern layer, the number of high-voltage side pattern layers in the transformer is reduced. If the number of high-voltage side pattern layers is small, two or more low-voltage side pattern layers are likely to be arranged between the high-voltage side pattern layers.
＜７＞実施形態に係るトランスの一形態として、
　前記複数の絶縁層のそれぞれの厚みは０．１ｍｍ以上１．０ｍｍ以下である形態が挙げられる。 <7> As one form of the transformer according to the embodiment,
Examples thereof include a form in which the thickness of each of the plurality of insulating layers is 0.1 mm or more and 1.0 mm or less.
　絶縁層の厚みが０．１ｍｍ以上であれば、積層方向に並ぶ二つのコイルパターンの間に形成される寄生容量が十分に小さくなる。絶縁層の厚みが１．０ｍｍ以下であれば、多層基板の厚さが厚くなり過ぎない。 If the thickness of the insulating layer is 0.1 mm or more, the parasitic capacitance formed between the two coil patterns arranged in the stacking direction becomes sufficiently small. If the thickness of the insulating layer is 1.0 mm or less, the thickness of the multilayer board does not become too thick.
＜８＞実施形態に係るコンバータは、
　上記＜１＞から＜７＞のいずれかのトランスを備える。 <8> The converter according to the embodiment is
The transformer according to any one of <1> to <7> is provided.
　実施形態に係るコンバータは、寄生容量に起因する変換効率の低下を抑制できるトランスを備える。従って、実施形態に係るコンバータは、変換効率に優れる。 The converter according to the embodiment includes a transformer capable of suppressing a decrease in conversion efficiency due to parasitic capacitance. Therefore, the converter according to the embodiment is excellent in conversion efficiency.
［本開示の実施形態の詳細］
　以下、本開示の実施形態に係るトランス及びコンバータの具体例を図面に基づいて説明する。図中の同一符号は同一又は相当部分を示す。なお、本発明はこれらの例示に限定されるものではなく、請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 [Details of Embodiments of the present disclosure]
Hereinafter, specific examples of the transformer and the converter according to the embodiment of the present disclosure will be described with reference to the drawings. The same reference numerals in the figure indicate the same or corresponding parts. It should be noted that the present invention is not limited to these examples, and is indicated by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.
＜実施形態１＞
　実施形態１では、コンバータとして、センタータップを用いた全波整流型のＤＣ／ＤＣコンバータを説明する。本例のコンバータ１００の電気的な回路構成を図１の回路図に基づいて説明する。次いで、本例のコンバータ１００に備わるトランス３の構造を図２から図５に基づいて説明する。 <Embodiment 1>
In the first embodiment, a full-wave rectification type DC / DC converter using a center tap will be described as the converter. The electrical circuit configuration of the converter 100 of this example will be described with reference to the circuit diagram of FIG. Next, the structure of the transformer 3 provided in the converter 100 of this example will be described with reference to FIGS. 2 to 5.
　≪コンバータ≫
　本例のコンバータ１００は、第一回路１と第二回路２とトランス３とを備える。本例の第一回路１には直流が入力される。本例の第一回路１は、接地電位の入力端子１Ａにつながる低電位ライン１１と、正電位の入力端子１Ｂにつながる高電位ライン１２とを備える。低電位ライン１１は、入力端子１Ａからトランス３の高圧側コイル３１の一方の端部に至る。高電位ライン１２は、入力端子１Ｂからトランス３の高圧側コイル３１の他方の端部に至る。 ≪Converter≫
The converter 100 of this example includes a first circuit 1, a second circuit 2, and a transformer 3. Direct current is input to the first circuit 1 of this example. The first circuit 1 of this example includes a low potential line 11 connected to the ground potential input terminal 1A and a high potential line 12 connected to the positive potential input terminal 1B. The low potential line 11 extends from the input terminal 1A to one end of the high voltage side coil 31 of the transformer 3. The high potential line 12 extends from the input terminal 1B to the other end of the high voltage side coil 31 of the transformer 3.
　本例の第一回路１は、入力側のコンデンサ１Ｃと、スイッチング回路１Ｄとを備える。入力側のコンデンサ１Ｃは、低電位ライン１１と高電位ライン１２との間に設けられるデバイスであって、帰還ノイズを低減する。 The first circuit 1 of this example includes a capacitor 1C on the input side and a switching circuit 1D. The capacitor 1C on the input side is a device provided between the low potential line 11 and the high potential line 12, and reduces feedback noise.
　低電位ライン１１と高電位ライン１２との間に設けられる本例のスイッチング回路１Ｄは、直流を交流に変換する変換回路である。スイッチング回路１Ｄには公知の構成が利用できる。本例のスイッチング回路１Ｄは、ブリッジ接続される４つの整流素子１３によって構成される。整流素子１３は、第一回路１の一部を構成するデバイスである。本例の整流素子１３は、電界効果トランジスタ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）である。整流素子１３はダイオードであっても良い。 The switching circuit 1D of this example provided between the low-potential line 11 and the high-potential line 12 is a conversion circuit that converts direct current into alternating current. A known configuration can be used for the switching circuit 1D. The switching circuit 1D of this example is composed of four rectifying elements 13 connected by a bridge. The rectifying element 13 is a device that constitutes a part of the first circuit 1. The rectifying element 13 of this example is a field effect transistor. The rectifying element 13 may be a diode.
　トランス３は、交流の電圧を変換する。トランス３は、高圧側コイル３１と低圧側コイル３２とコア３３とを備える。高圧側コイル３１は一次コイルであり、低圧側コイルは二次コイルである。高圧側コイル３１は、第一回路１に接続される。低圧側コイル３２は、後述する第二回路２に接続される。コア３３は、高圧側コイル３１と低圧側コイル３２とに貫通される。 The transformer 3 converts the AC voltage. The transformer 3 includes a high-voltage side coil 31, a low-voltage side coil 32, and a core 33. The high pressure side coil 31 is a primary coil, and the low pressure side coil is a secondary coil. The high voltage side coil 31 is connected to the first circuit 1. The low voltage side coil 32 is connected to the second circuit 2 described later. The core 33 is penetrated by the high pressure side coil 31 and the low pressure side coil 32.
　本例のトランス３はセンタータップ型である。センタータップ型のトランス３では、低圧側コイル３２が、第一の低圧側コイル３２１と、第二の低圧側コイル３２２とを備える。本例では、第一の低圧側コイル３２１と第二の低圧側コイル３２２との間に、後述する第二回路２の第二導電ライン２２が接続されている。 The transformer 3 in this example is a center tap type. In the center tap type transformer 3, the low voltage side coil 32 includes a first low voltage side coil 321 and a second low voltage side coil 322. In this example, the second conductive line 22 of the second circuit 2, which will be described later, is connected between the first low-voltage side coil 321 and the second low-voltage side coil 322.
　本例の第二回路２は、第一導電ライン２１と第二導電ライン２２とを備える。第一導電ライン２１は、トランス３の低圧側コイル３２の両端から接地電位である出力端子２Ａにつながる。より具体的には、第一の低圧側コイル３２１から出力端子２Ａに至る第一導電ライン２１と、第二の低圧側コイル３２２から出力端子２Ａに至る第一導電ライン２１とがある。両導電ライン２１は接点２１ｂにおいてつながる。第一導電ライン２１はアース２９によって接地されている。一方、センタータップとして機能する第二導電ライン２２は、第一導電ライン２１とは異なる経路で、トランス３の低圧側コイル３２から正電位である出力端子２Ｂに至る。低圧側コイル３２から出力端子２Ａ，２Ｂに至るまでの間、第一導電ライン２１と第二導電ライン２２とはつながっていない。 The second circuit 2 of this example includes a first conductive line 21 and a second conductive line 22. The first conductive line 21 is connected from both ends of the low voltage side coil 32 of the transformer 3 to the output terminal 2A which is the ground potential. More specifically, there is a first conductive line 21 from the first low-voltage side coil 321 to the output terminal 2A, and a first conductive line 21 from the second low-voltage side coil 322 to the output terminal 2A. Both conductive lines 21 are connected at a contact 21b. The first conductive line 21 is grounded by the ground 29. On the other hand, the second conductive line 22 that functions as a center tap reaches the output terminal 2B, which has a positive potential, from the low-voltage side coil 32 of the transformer 3 by a path different from that of the first conductive line 21. The first conductive line 21 and the second conductive line 22 are not connected from the low-voltage side coil 32 to the output terminals 2A and 2B.
　本例の第二回路２では、第一導電ライン２１と第二導電ライン２２との間に整流回路２Ｃとフィルタ回路２Ｄとが設けられている。本例の整流回路２Ｃは、交流を直流に変換する公知の変換回路が利用できる。本例の整流回路２Ｃは、二つの整流素子２１１，２１２を備える。整流素子２１１，２１２は、第一導電ライン２１に含まれるデバイスである。整流素子２１１は、第一の低圧側コイル３２１から接点２１ｂの間に設けられている。整流素子２１２は、第二の低圧側コイル３２２から接点２１ｂの間に設けられている。本例の整流素子２１１，２１２は、電界効果トランジスタである。本例とは異なり、整流素子２１１，２１２はダイオードでも良い。 In the second circuit 2 of this example, a rectifier circuit 2C and a filter circuit 2D are provided between the first conductive line 21 and the second conductive line 22. As the rectifier circuit 2C of this example, a known conversion circuit that converts alternating current into direct current can be used. The rectifier circuit 2C of this example includes two rectifier elements 211 and 212. The rectifying elements 211 and 212 are devices included in the first conductive line 21. The rectifying element 211 is provided between the first low-voltage side coil 321 and the contact 21b. The rectifying element 212 is provided between the second low-voltage side coil 322 and the contact 21b. The rectifying elements 211 and 212 of this example are field effect transistors. Unlike this example, the rectifying elements 211 and 212 may be diodes.
　本例のフィルタ回路２Ｄは、ローパスフィルタである。フィルタ回路２Ｄは、デバイスとしてインダクタ２３と出力側のコンデンサ２４とを備える。インダクタ２３は、第二導電ライン２２に設けられている。コンデンサ２４は、第一導電ライン２１における接点２１ｂよりも下流側の部分と、第二導電ライン２２におけるインダクタ２３よりも下流側の部分との間に設けられている。本例のフィルタ回路２Ｄは、Ｌ形フィルタであるが、π形フィルタであっても良いし、Ｔ形フィルタであっても良い。 The filter circuit 2D of this example is a low-pass filter. The filter circuit 2D includes an inductor 23 and a capacitor 24 on the output side as devices. The inductor 23 is provided on the second conductive line 22. The capacitor 24 is provided between a portion of the first conductive line 21 downstream of the contact 21b and a portion of the second conductive line 22 downstream of the inductor 23. The filter circuit 2D of this example is an L-type filter, but may be a π-type filter or a T-type filter.
　≪トランス≫
　本例のトランス３の構造を図２から図５に基づいて説明する。本例のトランス３は、概略８の字形状のコア３３（図３参照）と、高圧側コイル３１及び低圧側コイル３２を含む多層基板４とを備える（図４参照）。本例とは異なり、コア３３は環状であっても良い。 ≪Transformer≫
The structure of the transformer 3 of this example will be described with reference to FIGS. 2 to 5. The transformer 3 of this example includes a core 33 having a substantially eight-shaped shape (see FIG. 3) and a multilayer substrate 4 including a high-voltage side coil 31 and a low-voltage side coil 32 (see FIG. 4). Unlike this example, the core 33 may be annular.
　・コア
　本例のコア３３は、第一コア部材３３１と第二コア部材３３２との組物である（図３参照）。第一コア部材３３１は、概略Ｅ字形状の磁性体である。第一コア部材３３１の三つの脚片はそれぞれ、多層基板４に設けられる貫通孔４１，４２，４３の内部に配置されている。第二コア部材３３２は、概略Ｉ字形状の磁性体である。第二コア部材３３２は、第一コア部材３３１の三つの脚片をつなぐように配置される。 -Core The core 33 of this example is an assembly of a first core member 331 and a second core member 332 (see FIG. 3). The first core member 331 is a magnetic material having a substantially E-shape. The three leg pieces of the first core member 331 are arranged inside the through holes 41, 42, and 43 provided in the multilayer board 4, respectively. The second core member 332 is a magnetic material having a substantially I-shape. The second core member 332 is arranged so as to connect the three leg pieces of the first core member 331.
　コア３３は、例えばフェライトコアなどの焼結体である。その他、コア３３は、圧粉成形体、複合材料の成形体、又は積層鋼板であっても良い。圧粉成形体は、軟磁性粉末が圧縮成形されてなる磁性部材である。複合材料の成形体は、軟磁性粉末が分散された流動性の樹脂を硬化させた磁性部材である。積層鋼板は、電磁鋼板が積層された積層体である。 The core 33 is a sintered body such as a ferrite core. In addition, the core 33 may be a powder compact, a composite material molded body, or a laminated steel plate. The compaction compact is a magnetic member obtained by compression molding soft magnetic powder. The molded body of the composite material is a magnetic member obtained by curing a fluid resin in which soft magnetic powder is dispersed. The laminated steel sheet is a laminated body in which electromagnetic steel sheets are laminated.
　・多層基板
　図４に示されるように、多層基板４は、積層される複数の導体パターン層Ｌ１～Ｌ６と、積層方向に隣接する二つの導体パターン層Ｌ１～Ｌ６の間に配置される絶縁層４０とを含む。ここで、図４は、導体パターン層Ｌ１～Ｌ６と絶縁層４０との積層状態を模式的に示すものであり、図２，３の断面図ではない。 Multilayer board As shown in FIG. 4, the multilayer board 4 is an insulating layer arranged between a plurality of conductor pattern layers L1 to L6 to be laminated and two conductor pattern layers L1 to L6 adjacent to each other in the stacking direction. Includes 40 and. Here, FIG. 4 schematically shows a laminated state of the conductor pattern layers L1 to L6 and the insulating layer 40, and is not a cross-sectional view of FIGS. 2 and 3.
　・・高圧側パターン層
　本例の導体パターン層Ｌ２，Ｌ５は、高圧側コイル３１を構成するコイルパターン５０を有する高圧側パターン層５である。コイルパターン５０は薄膜によって構成される。薄膜には導電性に優れる銅などの金属が好適である。導体パターン層Ｌ２，Ｌ５におけるコイルパターン５０を除く部分は、絶縁層４０と一体になった絶縁材料によって構成されている。 High-voltage side pattern layer The conductor pattern layers L2 and L5 of this example are high-voltage side pattern layers 5 having a coil pattern 50 constituting the high-voltage side coil 31. The coil pattern 50 is composed of a thin film. A metal such as copper, which has excellent conductivity, is suitable for the thin film. The portions of the conductor pattern layers L2 and L5 other than the coil pattern 50 are made of an insulating material integrated with the insulating layer 40.
　本例の導体パターン層Ｌ２，Ｌ５のコイルパターン５０は、図５に示されるように、多層基板４の貫通孔４２を取り囲むように配置されている。図２，３を参照して既に説明したように、貫通孔４２には、第一コア部材３３１の中央の脚片が配置されている。コイルパターン５０は、高圧側コイル３１の複数のターンが渦巻状に配置されることで構成されている。本例では高圧側コイル３１の三つのターンが、一つのコイルパターン５０を構成している。本例とは異なり、一つのターンが一つのコイルパターン５０を構成していても良い。 As shown in FIG. 5, the coil patterns 50 of the conductor pattern layers L2 and L5 of this example are arranged so as to surround the through holes 42 of the multilayer board 4. As already described with reference to FIGS. 2 and 3, the central leg piece of the first core member 331 is arranged in the through hole 42. The coil pattern 50 is configured by arranging a plurality of turns of the high-voltage side coil 31 in a spiral shape. In this example, the three turns of the high-voltage side coil 31 constitute one coil pattern 50. Unlike this example, one turn may constitute one coil pattern 50.
　導体パターン層Ｌ２におけるコイルパターン５０は、外側から内側に向かって徐々に径が小さくなる渦巻状の三つのターンによって構成されている。三つのターンは、外側から内側に向かって反時計回りに周回する。紙面左上に配置されるコイルパターン５０の外周端部は、高圧側コイル３１の一方の端部に相当する。このコイルパターン５０の左上端部は、図１の第一回路１に接続される。 The coil pattern 50 in the conductor pattern layer L2 is composed of three spiral turns whose diameters gradually decrease from the outside to the inside. The three turns orbit counterclockwise from the outside to the inside. The outer peripheral end of the coil pattern 50 arranged on the upper left of the paper surface corresponds to one end of the high-voltage side coil 31. The upper left end of the coil pattern 50 is connected to the first circuit 1 in FIG.
　導体パターン層Ｌ５におけるコイルパターン５０は、内側から外側に向かって徐々に径が大きくなる渦巻状の三つのターンによって構成されている。三つのターンは、内側から外側に向かって反時計回りに周回する。紙面右上に配置されるコイルパターン５０の外周端部は、高圧側コイル３１の他方の端部に相当する。このコイルパターン５０の右上の端部は、図１の第一回路１に接続される。 The coil pattern 50 in the conductor pattern layer L5 is composed of three spiral turns whose diameters gradually increase from the inside to the outside. The three turns orbit counterclockwise from the inside to the outside. The outer peripheral end of the coil pattern 50 arranged on the upper right of the paper surface corresponds to the other end of the high-voltage side coil 31. The upper right end of the coil pattern 50 is connected to the first circuit 1 in FIG.
　導体パターン層Ｌ２のコイルパターン５０と、導体パターン層Ｌ５のコイルパターン５０とはビア５１を介して電気的に接続されている。つまり、高圧側パターン層５である導体パターン層Ｌ２と、高圧側パターン層５である導体パターン層Ｌ５とは電気的に直列に接続されている。従って、本例の高圧側コイル３１のターン数は６である。 The coil pattern 50 of the conductor pattern layer L2 and the coil pattern 50 of the conductor pattern layer L5 are electrically connected via the via 51. That is, the conductor pattern layer L2 which is the high-voltage side pattern layer 5 and the conductor pattern layer L5 which is the high-voltage side pattern layer 5 are electrically connected in series. Therefore, the number of turns of the high-voltage side coil 31 in this example is 6.
　・・低圧側パターン層
　本例の導体パターン層Ｌ１，Ｌ４は、図４に示されるように、第一の低圧側コイル３２１を構成するコイルパターン６０を有する低圧側パターン層６である。一方、導電パターン層Ｌ３，Ｌ６は、第二の低圧側コイル３２２を構成するコイルパターン６０を有する低圧側パターン層６である。コイルパターン６０は、導電性に優れる金属の薄膜によって構成される。また、導電パターン層Ｌ１，Ｌ３，Ｌ４，Ｌ６におけるコイルパターン６０を除く部分は、絶縁層４０と一体になった絶縁材料によって構成される。 Low-voltage side pattern layer As shown in FIG. 4, the conductor pattern layers L1 and L4 of this example are low-voltage side pattern layers 6 having a coil pattern 60 constituting the first low-voltage side coil 321. On the other hand, the conductive pattern layers L3 and L6 are low-voltage side pattern layers 6 having a coil pattern 60 constituting the second low-voltage side coil 322. The coil pattern 60 is composed of a thin metal film having excellent conductivity. Further, the portions of the conductive pattern layers L1, L3, L4, and L6 other than the coil pattern 60 are made of an insulating material integrated with the insulating layer 40.
　導体パターン層Ｌ１は、図２に示されるように、多層基板４の貫通孔４２を取り囲むように配置されている。他の導体パターン層Ｌ３，Ｌ４，Ｌ６（図４）も貫通孔４２を取り囲むように配置されている。低圧側パターン層６であるこれら導体パターン層Ｌ１，Ｌ３，Ｌ４，Ｌ６は、多層基板４を平面視したとき重複する位置に配置されている。また、これら導体パターン層Ｌ１，Ｌ３，Ｌ４，Ｌ６は、多層基板４を平面視したときに、高圧側パターン層５である導体パターン層Ｌ２，Ｌ５と重複する位置に配置されている。 As shown in FIG. 2, the conductor pattern layer L1 is arranged so as to surround the through hole 42 of the multilayer board 4. Other conductor pattern layers L3, L4, and L6 (FIG. 4) are also arranged so as to surround the through hole 42. These conductor pattern layers L1, L3, L4, and L6, which are the low-pressure side pattern layers 6, are arranged at overlapping positions when the multilayer substrate 4 is viewed in a plan view. Further, these conductor pattern layers L1, L3, L4, and L6 are arranged at positions overlapping with the conductor pattern layers L2 and L5, which are the high-voltage side pattern layers 5, when the multilayer substrate 4 is viewed in a plan view.
　導体パターン層Ｌ１におけるコイルパターン６０は、第一の低圧側コイル３２１の一つのターンによって構成されている（図２参照）。本例とは異なり、コイルパターン６０は、渦巻状に配置される複数のターンによって構成されていても良い。 The coil pattern 60 in the conductor pattern layer L1 is composed of one turn of the first low pressure side coil 321 (see FIG. 2). Unlike this example, the coil pattern 60 may be composed of a plurality of turns arranged in a spiral shape.
　第一の低圧側コイル３２１を構成する導体パターン層Ｌ１と導体パターン層Ｌ４とは、ビア６１（図２参照）を介して電気的に並列に接続されている。従って、本例の第一の低圧側コイル３２１のターン数は１である。また、第二の低圧側コイル３２２を構成する導体パターン層Ｌ３と導体パターン層Ｌ６とは、図示しないビアを介して電気的に並列に接続されている。従って、第二の低圧側コイル３２２のターン数は１である。このように、第一の低圧側コイル３２１及び第二の低圧側コイル３２２の一つのターンが複数の層に分配されることで、各導体パターン層Ｌ１，Ｌ３，Ｌ４，Ｌ６のコイルパターン６０の帯状の薄膜の幅が小さくなる。コイルパターン６０の幅が小さくなれば、多層基板４の平面面積が小さくなる。 The conductor pattern layer L1 and the conductor pattern layer L4 constituting the first low-voltage side coil 321 are electrically connected in parallel via a via 61 (see FIG. 2). Therefore, the number of turns of the first low-pressure side coil 321 of this example is 1. Further, the conductor pattern layer L3 and the conductor pattern layer L6 constituting the second low-voltage side coil 322 are electrically connected in parallel via vias (not shown). Therefore, the number of turns of the second low pressure side coil 322 is 1. In this way, one turn of the first low-voltage side coil 321 and the second low-voltage side coil 322 is distributed to a plurality of layers, so that the coil pattern 60 of each conductor pattern layer L1, L3, L4, L6 The width of the strip-shaped thin film becomes smaller. As the width of the coil pattern 60 becomes smaller, the plane area of the multilayer board 4 becomes smaller.
　導体パターン層Ｌ１，Ｌ４のコイルパターン６０と、導体パターン層Ｌ３，Ｌ６のコイルパターン６０とは電気的に接続されている。導体パターン層Ｌ１，Ｌ４のコイルパターン６０の端部は共に、図１の上側の第一導電ライン２１に接続される。導体パターン層Ｌ３，Ｌ６のコイルパターン６０の端部は共に、図１の下側の第一導電ライン２１に接続される。センタータップである第二導電ライン２２は、導体パターンＬ１，Ｌ３，Ｌ４，Ｌ６に電気的に接続される。 The coil pattern 60 of the conductor pattern layers L1 and L4 and the coil pattern 60 of the conductor pattern layers L3 and L6 are electrically connected. Both ends of the coil pattern 60 of the conductor pattern layers L1 and L4 are connected to the first conductive line 21 on the upper side of FIG. Both ends of the coil pattern 60 of the conductor pattern layers L3 and L6 are connected to the lower first conductive line 21 in FIG. The second conductive line 22, which is a center tap, is electrically connected to the conductor patterns L1, L3, L4, and L6.
　・・寄生容量
　上述した積層状態にある導体パターン層Ｌ１～Ｌ６のコイルパターン５０，６０の間には寄生容量７が形成される。本明細書では、高圧側コイル３１を構成する複数のコイルパターン５０のうち、電気的に直列に接続される二つのコイルパターン５０の間に形成される寄生容量７を第一の寄生容量７１と呼ぶ。また、低圧側コイル３２（図１参照）を構成する複数のコイルパターン６０のうち、電気的に直列に接続される二つのコイルパターン６０の間に形成される寄生容量７を第二の寄生容量７２と呼ぶ。更に、コイルパターン５０とコイルパターン６０との間に形成される寄生容量７を第三の寄生容量７３と呼ぶ。 Parasitic capacitance A parasitic capacitance 7 is formed between the coil patterns 50 and 60 of the conductor pattern layers L1 to L6 in the above-mentioned laminated state. In the present specification, among the plurality of coil patterns 50 constituting the high-voltage side coil 31, the parasitic capacitance 7 formed between the two coil patterns 50 electrically connected in series is referred to as the first parasitic capacitance 71. Call. Further, among the plurality of coil patterns 60 constituting the low-voltage side coil 32 (see FIG. 1), the parasitic capacitance 7 formed between the two coil patterns 60 electrically connected in series is the second parasitic capacitance. Call it 72. Further, the parasitic capacitance 7 formed between the coil pattern 50 and the coil pattern 60 is referred to as a third parasitic capacitance 73.
　本発明者らの検討の結果によると、第一の寄生容量７１はスイッチング損失を増大させ、トランス３の変換効率の低下に大きな影響を与えることが分かった。つまり、第一の寄生容量７１が小さくなると、トランス３の変換効率の低下が抑制され易い。 According to the results of the studies by the present inventors, it was found that the first parasitic capacitance 71 increases the switching loss and greatly affects the decrease in the conversion efficiency of the transformer 3. That is, when the first parasitic capacitance 71 becomes small, the decrease in the conversion efficiency of the transformer 3 is likely to be suppressed.
　・・絶縁層
　絶縁層４０は、エポキシ樹脂などで構成されている。絶縁層４０の厚さは、積層方向に隣接するコイルパターン５０，５０の間、コイルパターン５０，６０の間、及びコイルパターン６０，６０の間の絶縁を確保できる厚さである。例えば、絶縁層４０の厚さは０．１ｍｍ以上１．０ｍｍ以下である。絶縁層４０の厚さが０．１ｍｍ以上であれば、積層方向に並ぶコイルパターンの間に形成される寄生容量７が十分に小さくなる。絶縁層４０の厚さが１．０ｍｍ以下であれば、多層基板４の厚さが厚くなり過ぎない。より好ましい絶縁層４０の厚さは０．２ｍｍ以上０．５ｍｍ以下である。更に好ましい絶縁層４０の厚さは０．２５ｍｍ以上０．４ｍｍ以下である。 -Insulation layer The insulation layer 40 is made of an epoxy resin or the like. The thickness of the insulating layer 40 is a thickness that can secure insulation between the coil patterns 50 and 50 adjacent to each other in the stacking direction, between the coil patterns 50 and 60, and between the coil patterns 60 and 60. For example, the thickness of the insulating layer 40 is 0.1 mm or more and 1.0 mm or less. When the thickness of the insulating layer 40 is 0.1 mm or more, the parasitic capacitance 7 formed between the coil patterns arranged in the stacking direction is sufficiently small. If the thickness of the insulating layer 40 is 1.0 mm or less, the thickness of the multilayer board 4 does not become too thick. A more preferable thickness of the insulating layer 40 is 0.2 mm or more and 0.5 mm or less. A more preferable thickness of the insulating layer 40 is 0.25 mm or more and 0.4 mm or less.
　複数の導体パターン層Ｌ１～Ｌ６のうち、第一層である導体パターン層Ｌ１と、最終層である導体パターン層Ｌ６とは、低圧側パターン層６である。この場合、本例のトランス３を筐体などに固定する場合、多層基板４と筐体との絶縁を確保し易い。本例のトランス３を筐体に固定する場合、多層基板４と筐体との間に図示しない絶縁部材が介在される。 Of the plurality of conductor pattern layers L1 to L6, the conductor pattern layer L1 which is the first layer and the conductor pattern layer L6 which is the final layer are the low voltage side pattern layer 6. In this case, when the transformer 3 of this example is fixed to a housing or the like, it is easy to secure insulation between the multilayer board 4 and the housing. When the transformer 3 of this example is fixed to the housing, an insulating member (not shown) is interposed between the multilayer board 4 and the housing.
　本例の構成とは異なり、導体パターン層Ｌ１の外側、及び導体パターン層Ｌ８の外側の少なくとも一方に絶縁層４０が配置されていても良い。この場合、多層基板４を筐体などに固定する際、別途絶縁部材を用意する必要がない。 Unlike the configuration of this example, the insulating layer 40 may be arranged on at least one of the outside of the conductor pattern layer L1 and the outside of the conductor pattern layer L8. In this case, when fixing the multilayer board 4 to a housing or the like, it is not necessary to separately prepare an insulating member.
　≪効果≫
　本例のトランス３では、電気的に直列に接続される二つの高圧側パターン層５，５の間、即ち導体パターン層Ｌ２，Ｌ５の間に、二つの低圧側パターン層６，６が配置されている。導体パターン層Ｌ２，Ｌ５の間の距離は、三つの絶縁層４０の厚みと、二つの低圧側パターン層６，６の厚みの合計と同じである。そのため、導体パターン層Ｌ２，Ｌ５の間に形成される第一の寄生容量７１が十分に小さい。従って、本例のトランス３は、寄生容量７に起因する変換効率の低下を抑制できる。 ≪Effect≫
In the transformer 3 of this example, two low-voltage side pattern layers 6 and 6 are arranged between two high-voltage side pattern layers 5 and 5 electrically connected in series, that is, between conductor pattern layers L2 and L5. ing. The distance between the conductor pattern layers L2 and L5 is the same as the sum of the thicknesses of the three insulating layers 40 and the thicknesses of the two low-voltage side pattern layers 6 and 6. Therefore, the first parasitic capacitance 71 formed between the conductor pattern layers L2 and L5 is sufficiently small. Therefore, the transformer 3 of this example can suppress the decrease in conversion efficiency due to the parasitic capacitance 7.
　本例のトランス３では、高圧側パターン層５が、高圧側コイル３１の複数のターンを渦巻き状に配置したコイルパターン５０を備える（図５）。一つの高圧側パターン層５に複数のターンが配置されることで、トランス３における高圧側パターン層５の数が少なくなる。高圧側パターン５の数が少なければ、高圧側パターン層５の間に二つ以上の低圧側パターン層６が配置され易い。 In the transformer 3 of this example, the high-voltage side pattern layer 5 includes a coil pattern 50 in which a plurality of turns of the high-voltage side coil 31 are arranged in a spiral shape (FIG. 5). By arranging a plurality of turns in one high-voltage side pattern layer 5, the number of high-voltage side pattern layers 5 in the transformer 3 is reduced. If the number of high-voltage side patterns 5 is small, two or more low-voltage side pattern layers 6 are likely to be arranged between the high-voltage side pattern layers 5.
　本例のトランス３では、低圧側パターン層６である導体パターン層Ｌ１と導体パターン層Ｌ４とが電気的に並列に接続され、導体パターン層Ｌ３と導体パターン層Ｌ６とが電気的に並列に接続されている。従って、低圧側コイル３２のターン数よりも低圧側パターン層６の数が多くなる。低圧側パターン層６の数が多ければ、直列に接続される二つの高圧側パターン層５，５の間に、二つ以上の低圧側パターン層６が配置され易い。 In the transformer 3 of this example, the conductor pattern layer L1 and the conductor pattern layer L4, which are the low-voltage side pattern layers 6, are electrically connected in parallel, and the conductor pattern layer L3 and the conductor pattern layer L6 are electrically connected in parallel. Has been done. Therefore, the number of the low pressure side pattern layer 6 is larger than the number of turns of the low pressure side coil 32. If the number of the low-voltage side pattern layers 6 is large, two or more low-voltage side pattern layers 6 are likely to be arranged between the two high-voltage side pattern layers 5 and 5 connected in series.
　本例のトランス３を備える図１のコンバータ１００は、第一の寄生容量７１に起因する変換効率の低下を抑制できる。 The converter 100 of FIG. 1 including the transformer 3 of this example can suppress a decrease in conversion efficiency due to the first parasitic capacitance 71.
＜実施形態２＞
　実施形態２では、複数の高圧側パターン層５における少なくとも一部の高圧側パターン層５が電気的に並列に接続される構成を図６、図７に基づいて説明する。 <Embodiment 2>
In the second embodiment, a configuration in which at least a part of the high-voltage side pattern layers 5 in the plurality of high-voltage side pattern layers 5 are electrically connected in parallel will be described with reference to FIGS. 6 and 7.
　実施形態２のトランス３は、図６に示されるように、８層の導体パターン層Ｌ１～Ｌ８を備える。導体パターン層Ｌ２，Ｌ３，Ｌ６，Ｌ７は、高圧側コイル３１を構成する高圧側パターン層５である。図７に示されるように、導体パターン層Ｌ２，Ｌ３，Ｌ６，Ｌ７のコイルパターン５０はいずれも、複数のターンが渦巻状に配置される構成である。 As shown in FIG. 6, the transformer 3 of the second embodiment includes eight conductor pattern layers L1 to L8. The conductor pattern layers L2, L3, L6, and L7 are high-voltage side pattern layers 5 constituting the high-voltage side coil 31. As shown in FIG. 7, each of the coil patterns 50 of the conductor pattern layers L2, L3, L6, and L7 has a configuration in which a plurality of turns are arranged in a spiral shape.
　導体パターン層Ｌ２のコイルパターン５０と、導体パターン層Ｌ３のコイルパターン５０とは同一形状となっている。その巻方向は、外側から内側に向かって反時計回りである。また、導体パターン層Ｌ６のコイルパターン５０と、導体パターン層Ｌ７のコイルパターン５０とは同一形状となっている。その巻方向は、外側から内側に向かって時計回りである。導体パターンＬ２，Ｌ３のコイルパターン５０の外周端部は共に、ビア５２を介して電気的に接続される。また、導体パターンＬ６，Ｌ７のコイルパターン５０の外周端部は共に、ビア５３を介して電気的に接続される。四つの渦巻き状のコイルパターン５０の中心側の端部はビア５１を介して電気的につながっている。 The coil pattern 50 of the conductor pattern layer L2 and the coil pattern 50 of the conductor pattern layer L3 have the same shape. The winding direction is counterclockwise from the outside to the inside. Further, the coil pattern 50 of the conductor pattern layer L6 and the coil pattern 50 of the conductor pattern layer L7 have the same shape. The winding direction is clockwise from the outside to the inside. The outer peripheral ends of the coil patterns 50 of the conductor patterns L2 and L3 are both electrically connected via the via 52. Further, the outer peripheral ends of the coil patterns 50 of the conductor patterns L6 and L7 are both electrically connected via the via 53. The central ends of the four spiral coil patterns 50 are electrically connected via vias 51.
　同一形状の導体パターン層Ｌ２と導体パターン層Ｌ３とは電気的に並列に接続される。同様に、同一形状の導体パターン層Ｌ６と導体パターン層Ｌ７とは電気的に並列に接続される。一方、導体パターン層Ｌ２，Ｌ３と、導体パターン層Ｌ６，Ｌ７とは電気的に直列に接続される。電気的に並列に接続される導体パターン層Ｌ２と導体パターン層Ｌ３との間、及び導体パターン層Ｌ６と導体パターン層Ｌ７との間には寄生容量は形成されない。 The conductor pattern layer L2 and the conductor pattern layer L3 having the same shape are electrically connected in parallel. Similarly, the conductor pattern layer L6 having the same shape and the conductor pattern layer L7 are electrically connected in parallel. On the other hand, the conductor pattern layers L2 and L3 and the conductor pattern layers L6 and L7 are electrically connected in series. No parasitic capacitance is formed between the conductor pattern layer L2 and the conductor pattern layer L3 electrically connected in parallel, and between the conductor pattern layer L6 and the conductor pattern layer L7.
　導体パターン層Ｌ１，Ｌ４，Ｌ５，Ｌ８は、低圧側コイル３２（図１参照）を構成する低圧側パターン層６である。より具体的には、導体パターン層Ｌ１，Ｌ５は、第一の低圧側コイル３２１を構成する低圧側パターン層６であり、電気的に並列に接続されている。導体パターン層Ｌ４，Ｌ８は、第二の低圧側コイル３２２を構成する低圧側パターン層６であり、電気的に並列に接続されている。 The conductor pattern layers L1, L4, L5, and L8 are low-voltage side pattern layers 6 constituting the low-voltage side coil 32 (see FIG. 1). More specifically, the conductor pattern layers L1 and L5 are low-voltage side pattern layers 6 constituting the first low-voltage side coil 321 and are electrically connected in parallel. The conductor pattern layers L4 and L8 are low-voltage side pattern layers 6 constituting the second low-voltage side coil 322, and are electrically connected in parallel.
　本例の構成においても、電気的に直列に接続される高圧側パターン層５，５の間に、二つの低圧側パターン層６，６が配置されている。具体的には、導体パターン層Ｌ３と導体パターン層Ｌ６との間に、導体パターン層Ｌ４と導体パターン層Ｌ５が配置されている。従って、本例のトランス３における第一の寄生容量７１は小さい。 Also in the configuration of this example, two low-voltage side pattern layers 6 and 6 are arranged between the high-voltage side pattern layers 5 and 5 electrically connected in series. Specifically, the conductor pattern layer L4 and the conductor pattern layer L5 are arranged between the conductor pattern layer L3 and the conductor pattern layer L6. Therefore, the first parasitic capacitance 71 in the transformer 3 of this example is small.
　本例の構成では、高圧側コイル３１のターンが複数の層に分配されることで、各導体パターン層Ｌ２，Ｌ３，Ｌ６，Ｌ７のコイルパターン５０の幅が小さくなる。その結果、多層基板４の平面面積が小さくなる。 In the configuration of this example, the turn of the high-voltage side coil 31 is distributed to a plurality of layers, so that the width of the coil pattern 50 of each conductor pattern layer L2, L3, L6, L7 becomes smaller. As a result, the plane area of the multilayer board 4 becomes smaller.
＜実施形態３＞
　実施形態３では、三つの低圧側パターン層６が電気的に並列に接続される構成を図８に基づいて説明する。 <Embodiment 3>
In the third embodiment, a configuration in which the three low-voltage side pattern layers 6 are electrically connected in parallel will be described with reference to FIG.
　実施形態３のトランス３は、図８に示されるように、八層の導体パターン層Ｌ１～Ｌ８を備える。導体パターン層Ｌ２，Ｌ７は、高圧側コイル３１を構成する高圧側パターン層５である。導体パターン層Ｌ２，Ｌ７の構成は、実施形態１の導体パターン層Ｌ２，Ｌ５（図５参照）の構成と同じである。 As shown in FIG. 8, the transformer 3 of the third embodiment includes eight conductor pattern layers L1 to L8. The conductor pattern layers L2 and L7 are high-voltage side pattern layers 5 constituting the high-voltage side coil 31. The configurations of the conductor pattern layers L2 and L7 are the same as the configurations of the conductor pattern layers L2 and L5 (see FIG. 5) of the first embodiment.
　導体パターン層Ｌ１，Ｌ３，Ｌ４，Ｌ５，Ｌ６，Ｌ８は、低圧側コイル３２（図１参照）を構成する低圧側パターン層６である。より具体的には、導体パターン層Ｌ１，Ｌ４，Ｌ６は、第一の低圧側コイル３２１を構成する低圧側パターン層６であり、電気的に並列に接続されている。導体パターン層Ｌ３，Ｌ５，Ｌ８は、第二の低圧側コイル３２２を構成する低圧側パターン層６であり、電気的に並列に接続されている。第一の低圧側コイル３２１と第二の低圧側コイル３２２とは電気的に直列に接続される。 The conductor pattern layers L1, L3, L4, L5, L6, and L8 are low-voltage side pattern layers 6 constituting the low-voltage side coil 32 (see FIG. 1). More specifically, the conductor pattern layers L1, L4, and L6 are low-voltage side pattern layers 6 constituting the first low-voltage side coil 321 and are electrically connected in parallel. The conductor pattern layers L3, L5, and L8 are low-voltage side pattern layers 6 constituting the second low-voltage side coil 322, and are electrically connected in parallel. The first low-voltage side coil 321 and the second low-voltage side coil 322 are electrically connected in series.
　本例の構成では、電気的に直列に接続される高圧側パターン層５，５の間に、４層の低圧側パターン層６が配置されている。具体的には、導体パターン層Ｌ２と導体パターン層Ｌ７との間に、導体パターン層Ｌ３，Ｌ４，Ｌ５，Ｌ６が配置されている。従って、本例のトランス３における第一の寄生容量７１は小さい。
＜試験例＞
　試験例では、積層状態の異なる三つのトランスにおける寄生容量の大きさをシミュレーションによって求めた。試料となるトランスの構成は以下のとおりである。 In the configuration of this example, four low-voltage side pattern layers 6 are arranged between the high-voltage side pattern layers 5 and 5 electrically connected in series. Specifically, the conductor pattern layers L3, L4, L5, and L6 are arranged between the conductor pattern layer L2 and the conductor pattern layer L7. Therefore, the first parasitic capacitance 71 in the transformer 3 of this example is small.
<Test example>
In the test example, the magnitude of parasitic capacitance in three transformers with different stacked states was determined by simulation. The configuration of the transformer used as a sample is as follows.
　≪試料Ｎｏ．１≫
　試料Ｎｏ．１のトランス３の多層基板４は、８層の導体パターン層Ｌ１～Ｌ８を備える。導体パターン層Ｌ２，Ｌ４，Ｌ５，Ｌ７は高圧側パターン層５、導体パターン層Ｌ１，Ｌ６，Ｌ３，Ｌ８は低圧側パターン層６である。各層の配置状態を示す模式図は、図９の表中に示されている。導体パターン層Ｌ２と導体パターン層Ｌ４、導体パターン層Ｌ５と導体パターン層Ｌ７、導体パターン層Ｌ１と導体パターン層Ｌ６、及び導体パターン層Ｌ３と導体パターン層Ｌ８はそれぞれ電気的に並列に接続されている。直列に接続される高圧側パターン層５である導体パターン層Ｌ４と導体パターン層Ｌ５の間には絶縁層のみが配置されている。 << Sample No. 1 >>
Sample No. The multilayer board 4 of the transformer 3 of 1 includes eight conductor pattern layers L1 to L8. The conductor pattern layers L2, L4, L5 and L7 are high-voltage side pattern layers 5, and the conductor pattern layers L1, L6, L3 and L8 are low-voltage side pattern layers 6. A schematic diagram showing the arrangement state of each layer is shown in the table of FIG. The conductor pattern layer L2 and the conductor pattern layer L4, the conductor pattern layer L5 and the conductor pattern layer L7, the conductor pattern layer L1 and the conductor pattern layer L6, and the conductor pattern layer L3 and the conductor pattern layer L8 are electrically connected in parallel. There is. Only the insulating layer is arranged between the conductor pattern layer L4 and the conductor pattern layer L5, which are the high-voltage side pattern layers 5 connected in series.
　≪試料Ｎｏ．２≫
　試料Ｎｏ．２の多層基板４の厚み・大きさ・積層数は、試料Ｎｏ．１の多層基板４と同じである。図９の表中に示されるように、導体パターン層Ｌ２，Ｌ３，Ｌ６，Ｌ７は高圧側パターン層５、導体パターン層Ｌ１，Ｌ４，Ｌ５，Ｌ８は低圧側パターン層６である。導体パターン層Ｌ２と導体パターン層Ｌ３、導体パターン層Ｌ６と導体パターン層Ｌ７、導体パターン層Ｌ１と導体パターン層Ｌ４、及び導体パターン層Ｌ５と導体パターン層Ｌ８はそれぞれ電気的に並列に接続されている。直列に接続される高圧側パターン層５である導体パターン層Ｌ３と導体パターン層Ｌ６の間には、低圧側パターン層６である導体パターン層Ｌ４，Ｌ５が配置されている。 << Sample No. 2 >>
Sample No. The thickness, size, and number of layers of the multilayer board 4 of 2 are the sample No. It is the same as the multilayer board 4 of 1. As shown in the table of FIG. 9, the conductor pattern layers L2, L3, L6, and L7 are high-voltage side pattern layers 5, and the conductor pattern layers L1, L4, L5, and L8 are low-voltage side pattern layers 6. The conductor pattern layer L2 and the conductor pattern layer L3, the conductor pattern layer L6 and the conductor pattern layer L7, the conductor pattern layer L1 and the conductor pattern layer L4, and the conductor pattern layer L5 and the conductor pattern layer L8 are electrically connected in parallel. There is. The conductor pattern layers L4 and L5, which are the low-voltage side pattern layers 6, are arranged between the conductor pattern layer L3, which is the high-voltage side pattern layer 5 connected in series, and the conductor pattern layer L6.
　≪試料Ｎｏ．３≫
　試料Ｎｏ．３の多層基板４の厚み・大きさ・積層数は、試料Ｎｏ．１の多層基板４と同じである。図９の表中に示されるように、導体パターン層Ｌ２，Ｌ３，Ｌ６，Ｌ７は高圧側パターン層５、導体パターン層Ｌ１，Ｌ４，Ｌ５，Ｌ８は低圧側パターン層６である。導体パターン層Ｌ２と導体パターン層Ｌ３、導体パターン層Ｌ６と導体パターン層Ｌ７、導体パターン層Ｌ１と導体パターン層Ｌ５、及び導体パターン層Ｌ４と導体パターン層Ｌ８はそれぞれ電気的に並列に接続されている。直列に接続される高圧側パターン層５である導体パターン層Ｌ３と導体パターン層Ｌ６の間には、低圧側パターン層６である導体パターン層Ｌ４，Ｌ５が配置されている。この試料Ｎｏ．３は、前述の試料Ｎｏ．２の導体パターン層Ｌ４と導体パターン層Ｌ５の位置を入れ替えたものである。そのため、試料Ｎｏ．３の構成では、並列に接続される第一の低圧側コイル３２１の導体パターン層Ｌ１と導体パターン層Ｌ５との間に、第二の低圧側コイル３２２の導体パターン層Ｌ４が配置されている。また、並列に接続される第二の低圧側コイル３２２の導体パターン層Ｌ４と導体パターン層Ｌ８との間に、第一の低圧側コイル３２１の導体パターン層Ｌ５が配置されている。 << Sample No. 3 ≫
Sample No. The thickness, size, and number of layers of the multilayer board 4 of 3 are the sample No. It is the same as the multilayer board 4 of 1. As shown in the table of FIG. 9, the conductor pattern layers L2, L3, L6, and L7 are high-voltage side pattern layers 5, and the conductor pattern layers L1, L4, L5, and L8 are low-voltage side pattern layers 6. The conductor pattern layer L2 and the conductor pattern layer L3, the conductor pattern layer L6 and the conductor pattern layer L7, the conductor pattern layer L1 and the conductor pattern layer L5, and the conductor pattern layer L4 and the conductor pattern layer L8 are electrically connected in parallel. There is. The conductor pattern layers L4 and L5, which are the low-voltage side pattern layers 6, are arranged between the conductor pattern layer L3, which is the high-voltage side pattern layer 5 connected in series, and the conductor pattern layer L6. This sample No. Reference numeral 3 is the above-mentioned sample No. The positions of the conductor pattern layer L4 and the conductor pattern layer L5 of 2 are exchanged. Therefore, the sample No. In the configuration of 3, the conductor pattern layer L4 of the second low-voltage side coil 322 is arranged between the conductor pattern layer L1 of the first low-voltage side coil 321 and the conductor pattern layer L5 connected in parallel. Further, the conductor pattern layer L5 of the first low-voltage side coil 321 is arranged between the conductor pattern layer L4 of the second low-voltage side coil 322 and the conductor pattern layer L8 connected in parallel.
　≪シミュレーション≫
　上記試料Ｎｏ．１から試料Ｎｏ．３のトランス３における寄生容量７１，７２，７３をシミュレーションによって求めた。寄生容量７１，７２，７３は、試料Ｎｏ．１の数値を１００としたパーセンテージで示す。その結果を図９の表に示す。 ≪Simulation≫
The sample No. Sample No. 1 to sample No. The parasitic capacitances 71, 72, 73 in the transformer 3 of 3 were obtained by simulation. Parasitic capacitances 71, 72, 73 are sample Nos. It is shown as a percentage with the value of 1 as 100. The results are shown in the table of FIG.
　図９の表に示されるように、試料Ｎｏ．２，３の第一の寄生容量７１は、試料Ｎｏ．１の第一の寄生容量７１の３０％以下であった。この結果の理由は、試料Ｎｏ．２，３において、直列に接続される高圧側パターン層５の間に、二つの低圧側パターン層６が配置されるからである。 As shown in the table of FIG. 9, the sample No. The first parasitic capacitance 71 of a few is the sample No. It was 30% or less of the first parasitic capacitance 71 of 1. The reason for this result is the sample No. This is because, in 2 and 3, two low-voltage side pattern layers 6 are arranged between the high-voltage side pattern layers 5 connected in series.
　試料Ｎｏ．２及び試料Ｎｏ．３の第二の寄生容量７２は、試料Ｎｏ．１の第二の寄生容量７２よりも大きかった。この結果の理由は、低圧側パターン層６である複数の導体パターン層Ｌ１，Ｌ４，Ｌ５，Ｌ８のうち、積層方向に隣接する導体パターン層Ｌ４，Ｌ５が存在するからである。 Sample No. 2 and sample No. The second parasitic capacitance 72 of 3 is the sample No. It was larger than the second parasitic capacitance 72 of 1. The reason for this result is that among the plurality of conductor pattern layers L1, L4, L5 and L8 which are the low pressure side pattern layers 6, the conductor pattern layers L4 and L5 adjacent to each other in the stacking direction exist.
　試料Ｎｏ．２，３の第三の寄生容量７３は、試料Ｎｏ．１の第三の寄生容量７３の６０％以下であった。この結果の理由は、低圧側パターン層６である複数の導体パターン層Ｌ１，Ｌ４，Ｌ５，Ｌ８のうち、高圧側パターン層５を挟まない導体パターン層Ｌ４，Ｌ５が存在するからである。 Sample No. The third parasitic capacitance 73 of a few is the sample No. It was 60% or less of the third parasitic capacitance 73 of 1. The reason for this result is that among the plurality of conductor pattern layers L1, L4, L5, L8 which are the low-voltage side pattern layers 6, there are conductor pattern layers L4, L5 that do not sandwich the high-voltage side pattern layer 5.
　既に述べたように、トランス３の変換効率の低下に及ぼす影響は、第一の寄生容量７１が最も大きい。従って、試料Ｎｏ．２，３のトランス３は、試料Ｎｏ．１のトランス３よりも変換効率に優れる。 As already mentioned, the first parasitic capacitance 71 has the greatest effect on the decrease in the conversion efficiency of the transformer 3. Therefore, the sample No. The transformers 3 of 2 and 3 are the sample No. It is superior in conversion efficiency to the transformer 3 of 1.
１００　コンバータ
１　第一回路
　１Ａ，１Ｂ　入力端子、１Ｃ　入力側のコンデンサ、１Ｄ　スイッチング回路
　１１　低電位ライン、１２　高電位ライン
　１３　整流素子
２　第二回路
　２Ａ，２Ｂ　出力端子、２Ｃ　整流回路、２Ｄ　フィルタ回路
　２１　第一導電ライン、２１ｂ　接点、２１１，２１２　整流素子
　２２　第二導電ライン、２３　インダクタ
　２４　出力側のコンデンサ、２９　アース
３　トランス
　３１　高圧側コイル
　３２　低圧側コイル、３２１　第一の低圧側コイル、３２２　第二の低圧側コイル
　３３　コア、３３１　第一コア部材、３３２　第二コア部材
４　多層基板
　４０　絶縁層、４１，４２，４３　貫通孔
　Ｌ１，Ｌ２，Ｌ３，Ｌ４，Ｌ５，Ｌ６，Ｌ７，Ｌ８　導体パターン層
５　高圧側パターン層
　５０　コイルパターン、５１，５２，５３　ビア
６　低圧側パターン層
　６０　コイルパターン、６１　ビア
７　寄生容量
　７１　第一の寄生容量、７２　第二の寄生容量、７３　第三の寄生容量 100 Converter 1 1st circuit 1A, 1B input terminal, 1C input side capacitor, 1D switching circuit 11 low potential line, 12 high potential line 13 rectifying element 2 2nd circuit 2A, 2B output terminal, 2C rectifying circuit, 2D filter circuit 21 1st conductive line, 21b contact, 211,212 rectifying element 22 2nd conductive line, 23 inductor 24 Output side capacitor, 29 Earth 3 transformer 31 High pressure side coil 32 Low pressure side coil, 321 First low pressure side coil 322 Second low-voltage side coil 33 core, 331 first core member, 332 second core member 4 multilayer substrate 40 insulation layer, 41, 42, 43 through hole L1, L2, L3, L4, L5, L6, L7, L8 conductor Pattern layer 5 High-pressure side pattern layer 50 Coil pattern, 51, 52, 53 Via 6 Low-pressure side pattern layer 60 Coil pattern, 61 Via 7 Parasitic capacitance 71 First parasitic capacitance, 72 Second parasitic capacitance, 73 Third parasitic capacitance capacity

Claims (8)

  1. 　高圧側コイルと、
    　低圧側コイルと、
    　前記高圧側コイル及び前記低圧側コイルを貫通するコアとを備えるトランスであって、
    　積層される複数の導体パターン層と、積層方向に隣接する二つの導体パターン層の間に配置される絶縁層とを含む多層基板を備え、
    　前記複数の導体パターン層は、
    　　前記高圧側コイルを構成するコイルパターンを有する複数の高圧側パターン層と、
    　　前記低圧側コイルを構成するコイルパターンを有する複数の低圧側パターン層とを含み、
    　前記複数の高圧側パターン層のうち、電気的に直列に接続される二つの高圧側パターン層の間に、前記複数の低圧側パターン層のうちの少なくとも二つの低圧側パターン層が配置される、
    トランス。     High pressure side coil and
    Low pressure side coil and
    A transformer including a high-voltage side coil and a core penetrating the low-voltage side coil.
    A multilayer substrate including a plurality of conductor pattern layers to be laminated and an insulating layer arranged between two conductor pattern layers adjacent to each other in the stacking direction is provided.
    The plurality of conductor pattern layers are
    A plurality of high-voltage side pattern layers having coil patterns constituting the high-voltage side coil,
    A plurality of low pressure side pattern layers having a coil pattern constituting the low pressure side coil are included.
    At least two low-voltage side pattern layers of the plurality of low-voltage side pattern layers are arranged between two high-voltage side pattern layers electrically connected in series among the plurality of high-voltage side pattern layers.
    Trance.
  2. 　前記低圧側コイルは、第一の低圧側コイルと第二の低圧側コイルとを備えるセンタータップ型である請求項１に記載のトランス。 The transformer according to claim 1, wherein the low-voltage side coil is a center tap type including a first low-voltage side coil and a second low-voltage side coil.
  3. 　前記複数の高圧側パターン層における少なくとも一部の高圧側パターン層は、電気的に並列に接続される請求項１又は請求項２に記載のトランス。 The transformer according to claim 1 or 2, wherein at least a part of the high-voltage side pattern layers in the plurality of high-voltage side pattern layers are electrically connected in parallel.
  4. 　前記複数の低圧側パターン層における少なくとも一部の低圧側パターン層は、電気的に並列に接続される請求項１から請求項３のいずれか１項に記載のトランス。 The transformer according to any one of claims 1 to 3, wherein at least a part of the low voltage side pattern layers in the plurality of low voltage side pattern layers are electrically connected in parallel.
  5. 　前記複数の導体パターン層における第一層と最終層とが、前記複数の低圧側パターン層に含まれる層である請求項１から請求項４のいずれか１項に記載のトランス。 The transformer according to any one of claims 1 to 4, wherein the first layer and the final layer in the plurality of conductor pattern layers are layers included in the plurality of low-voltage side pattern layers.
  6. 　前記複数の高圧側パターン層は、渦巻き状に配置される複数のターンを有する層を含む請求項１から請求項５のいずれか１項に記載のトランス。 The transformer according to any one of claims 1 to 5, wherein the plurality of high-voltage side pattern layers include a layer having a plurality of turns arranged in a spiral shape.
  7. 　前記複数の絶縁層のそれぞれの厚みは０．１ｍｍ以上１．０ｍｍ以下である請求項１から請求項６のいずれか１項に記載のトランス。 The transformer according to any one of claims 1 to 6, wherein the thickness of each of the plurality of insulating layers is 0.1 mm or more and 1.0 mm or less.
  8. 　請求項１から請求項７のいずれか１項に記載のトランスを備える、
    コンバータ。     The transformer according to any one of claims 1 to 7 is provided.
    converter.
PCT/JP2020/036459 2020-09-25 2020-09-25 Transformer and converter WO2022064662A1 (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799123A (en) * 1993-06-10 1995-04-11 Yokogawa Electric Corp Printed coil
JP2008177486A (en) * 2007-01-22 2008-07-31 Matsushita Electric Works Ltd Transformer
JP2009289879A (en) * 2008-05-28 2009-12-10 Fuji Electric Systems Co Ltd Laminated transformer
WO2013046259A1 (en) * 2011-09-28 2013-04-04 三菱電機株式会社 Light source lighting device
JP2013247155A (en) * 2012-05-23 2013-12-09 Fdk Corp Lamination transformer
JP2015050391A (en) * 2013-09-03 2015-03-16 パナソニックＩｐマネジメント株式会社 Lighting device, lamp fitting and vehicle
JP2016506624A (en) * 2012-12-19 2016-03-03 テレフオンアクチーボラゲット エル エム エリクソン（パブル） Planar transformer
JP2019146359A (en) * 2018-02-21 2019-08-29 新電元工業株式会社 Switching power supply device
JP2020021885A (en) * 2018-08-02 2020-02-06 富士電機株式会社 Transformer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799123A (en) * 1993-06-10 1995-04-11 Yokogawa Electric Corp Printed coil
JP2008177486A (en) * 2007-01-22 2008-07-31 Matsushita Electric Works Ltd Transformer
JP2009289879A (en) * 2008-05-28 2009-12-10 Fuji Electric Systems Co Ltd Laminated transformer
WO2013046259A1 (en) * 2011-09-28 2013-04-04 三菱電機株式会社 Light source lighting device
JP2013247155A (en) * 2012-05-23 2013-12-09 Fdk Corp Lamination transformer
JP2016506624A (en) * 2012-12-19 2016-03-03 テレフオンアクチーボラゲット エル エム エリクソン（パブル） Planar transformer
JP2015050391A (en) * 2013-09-03 2015-03-16 パナソニックＩｐマネジメント株式会社 Lighting device, lamp fitting and vehicle
JP2019146359A (en) * 2018-02-21 2019-08-29 新電元工業株式会社 Switching power supply device
JP2020021885A (en) * 2018-08-02 2020-02-06 富士電機株式会社 Transformer

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