WO2022062925A1 - 通信方法、设备、系统及计算机可读存储介质 - Google Patents

通信方法、设备、系统及计算机可读存储介质 Download PDF

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Publication number
WO2022062925A1
WO2022062925A1 PCT/CN2021/117847 CN2021117847W WO2022062925A1 WO 2022062925 A1 WO2022062925 A1 WO 2022062925A1 CN 2021117847 W CN2021117847 W CN 2021117847W WO 2022062925 A1 WO2022062925 A1 WO 2022062925A1
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Prior art keywords
data
bit
target
signal line
data packet
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PCT/CN2021/117847
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English (en)
French (fr)
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高宽
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华为技术有限公司
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Priority to EP21871296.6A priority Critical patent/EP4207643A4/en
Publication of WO2022062925A1 publication Critical patent/WO2022062925A1/zh
Priority to US18/187,173 priority patent/US20230231940A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/22—Parsing or analysis of headers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a communication method, a communication device, a communication system, and a computer-readable storage medium.
  • the signal transmission between different chips in the server usually adopts serial communication, for example, serial universal input and output (serial universal input and output) , SGPIO) protocol.
  • serial universal input and output serial universal input and output
  • SGPIO serial universal input and output
  • 4 signal lines need to be configured between two chips that communicate based on the SGPIO protocol to realize signal transmission, and the 4 signal lines need to occupy 8 input/output (input/output, I/O) of the chip. ) port, obviously, this configuration does not save the hardware resources of the chip very well. Therefore, how to save hardware resources and reduce hardware costs under the condition that the function and performance of the server remain unchanged is still an urgent problem to be solved at present.
  • the present application discloses a communication method, device, system, and computer-readable storage medium, which can effectively save hardware resources of a communication device when performing communication, thereby reducing hardware costs.
  • the present application provides a communication method, which is applied to data communication between a first device and a second device, and the first device and the second device realize data communication through a target signal line, and the method includes the following steps :
  • the first device constructs the multi-bit target data to be sent into at least one target data packet according to a preset format, each target data packet includes at least one bit of target data and multi-bit identification data, and the multi-bit identification data in each target data packet The data is used to indicate the quantity and location of the target data in the corresponding target data packet;
  • the first device packs each bit of data in the at least one target data packet, so that different data have different signal waveforms after being packed;
  • the first device sequentially sends each bit of the packaged data to the second device through the target signal line.
  • the first device constructs the multi-bit target data to be sent to the second device into at least one target data packet according to a preset format, and then packages each bit of data in the at least one target data packet , and finally, each bit of the packaged data is sent to the second device through the target signal line, so as to realize data communication between the first device and the second device.
  • target signal line only one signal line (ie, target signal line) is needed between the first device and the second device to realize the data communication between the first device and the second device, then the method is applied to When implementing data communication in server products, it can effectively save hardware resources and reduce hardware costs.
  • the signal waveform corresponding to the above-mentioned one bit of data includes a signal rising edge and a signal falling edge ;
  • the signal waveform corresponding to the above-mentioned one bit of data includes a signal rising edge and does not include a signal falling edge.
  • binary data 0 and binary data 1 have different signal waveforms, so the first device can pack one bit of data in one data cycle, so that different data can have different signals after being packed waveform, so that the second device can determine whether the data sent by the first device is binary data 0 or binary data 1 according to the signal waveform.
  • the multi-bit identification data includes multi-bit first identification data and multi-bit second identification data, and the first identification data and the second identification data are different;
  • the preset format includes: the target data packet includes a data packet header and at least one data segment, the packet header includes multiple consecutive first identification data and at least one second identification data, and each data segment in the at least one data segment includes at least one target data and at least one second identification data , the quantity of multiple consecutive bits of first identification data in the data packet header is greater than the quantity of at least one bit of target data in each data segment.
  • the data packet header and the data segment can be distinguished, so that the data packet header is unique, so that when parsing the target data packet, the second device can be based on the uniqueness of the data packet header. properties, determine the position of the data packet header, and further determine the corresponding data segment and the target data in the data segment, so as to realize data communication between the first device and the second device.
  • the above method is applied to data communication between chips, the first device includes a first chip, and the second device includes a second chip.
  • the above method is applied to determine whether the target signal line between the first device and the second device is correctly connected, and the multi-bit target data sent by the first device to the second device includes the target signal line.
  • Identification information the identification information of the target signal line is used to indicate the target signal line, so that the second device can judge whether the target signal line is connected correctly according to the obtained identification information of the target signal line.
  • the first device can send the identification information of the target signal line to the second device, so that the second device can effectively determine whether the target signal line is connected correctly.
  • the second device determines that the target signal line is connected incorrectly , the second device can send alarm information, so that the user can reconnect the wrongly connected target signal line in time, thereby improving the security and accuracy of data communication.
  • the present application provides a communication method, which is applied to data communication between a first device and a second device.
  • the first device and the second device implement data communication through a target signal line, and the method includes the following steps :
  • the second device receives each bit of data after packaging sent by the first device through the target signal line, and determines each bit of data according to the signal waveform corresponding to each bit of data after packaging, thereby obtaining at least one target data packet;
  • the second device parses the at least one target data packet according to the preset format, thereby obtaining multi-bit target data in the at least one target data packet.
  • the second device can determine, according to the signal waveform corresponding to the received packaged data, each bit of data sent by the first device to the second device. One bit of data to get at least one target packet. Then, by parsing the at least one target data packet, the second device can obtain multi-bit target data included in the at least one target data packet, thereby implementing data communication between the first device and the second device.
  • the second device determines each bit of data according to the signal waveform corresponding to each bit of data after packaging, including: when the second device detects the signal waveform corresponding to each bit of data after packaging When it is on the rising edge, the second device starts timing and collects data at a preset time; when the second device collects a low level, the second device determines that the collected data is binary data 0; when the second device collects In the case of reaching a high level, the second device determines that the collected data is binary data 1.
  • the second device can accurately obtain every bit of data sent by the first device.
  • the above method is applied to data communication between chips, the first device includes a first chip, and the second device includes a second chip.
  • the above method is applied to determine whether the target signal line between the first device and the second device is correctly connected, and the multi-bit target data includes identification information of the target signal line, and the identification information of the target signal line is used
  • the method further includes: the second device determines the identification information and preset information of the target signal line included in the multi-bit target data. Whether it matches; if the identification information of the target signal line matches the preset information, the second device determines that the connection of the target signal line is correct; in the case that the identification information of the target signal line does not match the preset information, the second device determines The target signal line is connected incorrectly.
  • the present application provides a first device, the first device and the second device implement data communication through a target signal line, and the first device includes a data packet construction unit, a data packaging unit, and a data transceiver unit,
  • the data packet construction unit is used to construct the multi-bit target data to be sent into at least one target data packet according to a preset format, and each target data packet includes at least one bit of target data and multiple bits of identification data.
  • the multi-bit identification data is used to indicate the quantity and position of the target data in the corresponding target data packet;
  • the data packing unit is used to pack each bit of data in the at least one target data packet, so that different data have different signal waveforms after being packed;
  • the data transceiver unit is used for sending each bit of data packaged to the second device in turn through the target signal line.
  • the signal waveform corresponding to one bit of data when one bit of data in at least one target data packet is binary data 0, in one data cycle, the signal waveform corresponding to one bit of data includes a signal rising edge and a signal falling edge; When one bit of data in at least one target data packet is binary data 1, in one data period, the signal waveform corresponding to one bit of data includes a signal rising edge and does not include a signal falling edge.
  • the multi-bit identification data includes multi-bit first identification data and multi-bit second identification data, and the first identification data and the second identification data are different;
  • the preset format includes: the target data packet includes a data packet header and at least one data segment, the data packet header includes multiple consecutive first identification data and at least one second identification data, and each data segment in the at least one data segment includes at least one data segment.
  • the number of bits of target data and at least one bit of second identification data, the number of multiple consecutive bits of first identification data in the data packet header is greater than the number of at least one bit of target data in each data segment.
  • the present application provides a second device, the first device and the second device implement data communication through a target signal line, and the second device includes a data transceiver unit and a data packet analysis unit,
  • the data transceiver unit is used to receive each bit of data after packaging sent by the first device through the target signal line, and determine each bit of data according to the signal waveform corresponding to each bit of data after packaging, so as to obtain at least one target data packet ;
  • the data packet parsing unit is configured to parse the at least one target data packet according to a preset format, so as to obtain multi-bit target data in the at least one target data packet.
  • the data transceiver unit is specifically configured to: start timing when it is detected that the signal waveform corresponding to each bit of data after packaging is on a rising edge, and collect data at a preset time; In the case of a high level, it is determined that the collected data is binary data 0; in the case of a high level, it is determined that the collected data is binary data 1.
  • the first device includes a first chip
  • the second device includes a second chip
  • the second device further includes a judging unit, and the judging unit is configured to judge whether the identification information of the target signal line included in the multi-bit target data matches the preset information, wherein the identification information of the target signal line It is used to indicate the target signal line; in the case that the identification information of the target signal line matches the preset information, it is determined that the target signal line is connected correctly; in the case that the identification information of the target signal line does not match the preset information, it is determined that the target signal line is connected Line connection error.
  • the present application provides another first device, the first device includes a processor and a memory, and the processor executes codes in the memory to implement some or all of the steps described in the first aspect.
  • the present application provides another second device, the second device includes a processor and a memory, and the processor executes codes in the memory to implement some or all of the steps described in the second aspect.
  • the present application provides a computer-readable storage medium storing computer instructions, where the computer instructions are used to implement some or all of the steps described in the first aspect.
  • the present application provides a computer-readable storage medium storing computer instructions, where the computer instructions are used to implement some or all of the steps described in the second aspect.
  • the present application provides a communication system, the communication system includes a first device and a second device, the first device is configured to perform some or all of the steps described in the first aspect, and the second device is configured to perform the second aspect some or all of the steps described.
  • Fig. 1 is the topology diagram of a kind of SGPIO protocol provided by the embodiment of the present application
  • FIG. 2 is a schematic diagram of a principle for identifying whether a cable is connected correctly according to an embodiment of the present application
  • FIG. 3 is a topology diagram of a single-wire asynchronous serial communication protocol provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a communication method provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a possible preset format of a target data packet provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of another possible preset format of a target data packet provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of signal waveforms corresponding to different data in the same data period provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a data packaging method provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a first device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a second device provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another first device provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another second device provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • the applicable application scenarios of the embodiments of the present application are first introduced: communication between chips, which may specifically include data transmission between chips, cable mis-insertion prevention, and hard disk lighting.
  • serial communication is usually used in current server products to implement communication between different chips (for example, complex programmable logic device (CPLD)) inside the server, for example, the SGPIO protocol.
  • CPLD complex programmable logic device
  • Figure 1 shows a topology diagram of the SGPIO protocol.
  • chip A is a master device
  • chip B is a slave device.
  • Communication between chip A and chip B is implemented through the SGPIO protocol (ie, a set of SGPIO buses).
  • a group of SGPIO buses may specifically include 4 signal lines, namely: a clock line, a signal loading line, a data output line, and a data input line.
  • the clock line is used to transmit the clock signal (CLK) sent from chip A to chip B, so that chip A and chip B can realize synchronous communication
  • the signal loading line is used to transmit the data loading and Synchronization signal (Load), data loading and synchronization signals are used to indicate that a new frame of data is about to start transmission
  • the data output line is used to transmit the data signal (DataOut) sent from chip A to chip B
  • the data input line is used to transmit from The data signal (DataIn) sent by chip B to chip A.
  • chip A is connected to one side of the 4 signal lines through 4 I/O ports (eg, port 1-port 4), and chip B is connected to one side of 4 signal lines through 4 I/O ports (eg, port 5- Port 8) is connected to the other side of the 4 signal lines, that is to say, it needs to occupy 4 I/O ports of chip A and 4 I/O ports of chip B to realize the communication between chip A and chip B. communication.
  • chip A sends data to chip B, but chip B does not need to send data to chip A
  • the signal lines included in a group of SGPIO bus can be correspondingly reduced to three, namely clock line, signal loading line and data output line.
  • the SGPIO bus occupies a lot of hardware resources (I/O resources), so the SGPIO protocol is not applicable in the application scenario where the I/O ports of chip A and/or chip B are short.
  • FIG. 2 shows a schematic diagram of the principle of identifying whether the cable is connected correctly by using the PWM signal.
  • port 1 of chip A sends a PWM signal (PWM 1) to port 5 of chip B through a clock line
  • port 2 of chip A sends a PWM signal (PWM 2) to port 6 of chip B through a signal loading line
  • the chip Port 3 of A sends a PWM signal (PWM 3) to port 7 of chip B through a data output line
  • port 4 of chip A sends a PWM signal (PWM 4) to port 8 of chip B through a data input line.
  • the duty cycle of PWM 1 is 3/7
  • the duty cycle of PWM 2 is 2/3
  • the duty cycle of PWM 3 is 1
  • the duty cycle of PWM 4 is 3/2.
  • chip B can determine whether the signal line is connected correctly according to the duty cycle of the PWM signal sent by chip A. Specifically, taking the clock line as an example, when port 5 of chip B receives PWM 1 sent by port 1 of chip A, , detects that the duty cycle of PWM 1 is 3/7, and then judges whether the duty cycle of PWM 1 is the same as the preset duty cycle. When the duty cycle of PWM 1 is the same as the preset duty cycle, chip B determines The clock line is connected correctly, that is, the clock line is the cable connected between port 1 of chip A and port 5 of chip B. It should be understood that the manner in which the chip B judges whether the signal loading line, the data output line and the data input line are connected correctly is similar to the above-mentioned way of judging whether the clock line is connected correctly, and will not be repeated here.
  • FIG. 2 shows the use of 4 PWM signals with different duty ratios to determine whether the four signal lines are connected correctly.
  • this method can only judge whether the corresponding cable is connected correctly through only one signal line, this method It is not suitable for scenarios with too many cables.
  • the duty cycle of the PWM signal is a rough calculation, that is to say, the data that can be carried on the PWM signal is limited and imprecise, and in the actual server product, chip B may not only be related to the chip A communicates, and may also be connected to multiple other chips or devices. At this time, chip B (for example, port 5) is plugged with a large number of cables, so port 5 will also receive a large number of PWM signals.
  • port 5 When port 5 receives these PWM signals, it is possible to obtain a plurality of approximately equal duty cycles by calculating the duty cycles of these PWM signals. At this time, port 5 will not be able to accurately determine the corresponding PWM signals with approximately equal duty cycles. the cable is connected correctly.
  • port 5 of chip B receives two PWM signals with a duty cycle of approximately 3/7, one of which is sent by port 1 of chip A, and the other is sent by port 9 of chip C. At this time, Chip B will not be able to determine whether the other end of the clock line is connected to port 1 of chip A or port 9 of chip C, so it cannot determine whether the clock line is connected correctly.
  • FIG. 3 shows a topology diagram of the single-wire asynchronous serial communication protocol provided by the embodiment of the present application. From FIG. 3 It can be seen that the protocol only needs one signal line (target signal line) to realize data communication between the first device and the second device. Therefore, using the single-wire asynchronous serial communication protocol provided by the embodiments of the present application for data communication can effectively save hardware resources. In addition, when the cable information is transmitted using the single-wire asynchronous serial communication protocol provided by the embodiments of the present application, it can also be effectively determined whether the cable (including the target signal line) between the first device and the second device is correctly connected. In order to more clearly understand the single-wire asynchronous serial communication protocol provided by the embodiments of the present application, the following will take the data communication between the first device and the second device in FIG. 3 as an example to introduce the protocol in detail.
  • FIG. 4 shows a schematic flowchart of a communication method provided by an embodiment of the present application.
  • the communication method provided by the embodiment of the present application includes but is not limited to the following steps:
  • the first device constructs the multi-bit target data to be sent into at least one target data packet according to a preset format.
  • the multi-bit target data to be sent are all binary data, specifically including binary data 0 and binary data 1.
  • Each target data packet in the at least one target data packet includes at least one bit of target data and multi-bit identification data, and the multi-bit identification data in each target data packet is used to indicate the quantity and location of target data in the corresponding target data.
  • the multiple bits of identification data include multiple bits of first identification data and multiple bits of second identification data, and the first identification data and the second identification data are different.
  • the preset format includes: the target data packet includes a data packet header and at least one data segment, the data packet header includes multiple consecutive first identification data and at least one second identification data, and in at least one data segment Each data segment includes at least one bit of target data and at least one bit of second identification data, and the number of multiple consecutive bits of first identification data in the data packet header is greater than the number of at least one bit of target data in each data segment.
  • the number of consecutive first identification data in the data packet header is greater than the number of at least one bit of target data in each data segment: in the target data packet,
  • the data packet header can be distinguished from the data segment, so that the data packet header is unique, so that when the data packet is subsequently parsed, the position of the data packet header can be determined according to the uniqueness of the data packet header, so as to determine the corresponding data segment and the data segment in the data segment. target data.
  • FIG. 5 shows a possible preset format of the target data packet.
  • the target data packet includes a data packet header and M data segments.
  • the packet header includes N+1 bits of continuous binary data 1 and one bit of binary data 0 from left to right, and each of the M data segments includes N bits of target data and one bit of binary data 0 from left to right.
  • M and N are both preset by the user, and both M and N are positive integers.
  • the data packet header includes 5 consecutive binary data 1 and one binary data 0 from left to right, that is, "111110", and each data segment in the 3 data segments starts from From left to right, it includes 4 bits of target data and one bit of binary data 0, that is, "xxxx0", that is, the target data packet is "111110 xxxx0 xxxx0 xxxx0".
  • the first identification data is binary data 1
  • the second identification data is binary data 0.
  • the first identification data can also be binary data 0
  • the second identification data can also be is binary data 1, which is not specifically limited here.
  • the data packet header includes 5 consecutive binary data 0 and one binary data 1 from left to right, that is, "000001”
  • Each of the 3 data segments includes 4 bits of target data and one bit of binary data 1 from left to right, that is, "xxxx1”, that is, the target data packet is "000001 xxxx1 xxxx1 xxxx1”.
  • the packet header includes N+1 consecutive first identification data, and each of the M data segments includes N-bit target data, but in practical applications, the The number of consecutive first identification data may also be N+K, which is not specifically limited here.
  • K>1 and K is a positive integer.
  • the data packet header includes 6 consecutive binary data 1 and one binary data 0 in sequence from left to right, namely "1111110”, each of the 3 data segments
  • Each data segment includes 4 bits of target data and one bit of binary data 0 from left to right, namely "xxxx0", that is to say, the target data packet is "1111110 xxxx0 xxxx0 xxxx0".
  • the preset structure of the target data packet may also be: the target data packet includes a data packet header and M data segments.
  • the packet header includes N+1 bits of continuous binary data 1 and one bit of binary data 0 from right to left, and each of the M data segments includes N bits of target data and one bit of binary data from right to left.
  • M and N are both preset by the user, and both M and N are positive integers.
  • the data packet header includes 5 consecutive binary data 1 and one binary data 0 in sequence from right to left, that is, "011111”, and each data segment in the 3 data segments starts from From right to left, it includes 4 bits of target data and one bit of binary data 0, that is, "0xxxx", that is, the target data packet is "011111 0xxxx 0xxxx 0xxxx”.
  • the first identification data is binary data 1
  • the second identification data is binary data 0.
  • the first identification data can also be binary data 1
  • the second identification data can also be It is binary data 1, which is not specifically limited here.
  • the data packet header includes 5 consecutive binary data 0 and one binary data 1 in sequence from right to left, that is, "100000”, each data in the 3 data segments
  • the segment includes 4 bits of target data and one bit of binary data 1 in sequence from right to left, that is, "1xxxx", that is, the target data packet is "100000 1xxxx 1xxxx 1xxxx".
  • the packet header includes N+1 consecutive first identification data, and each of the M data segments includes N-bit target data, but in practical applications, the The number of consecutive first identification data may also be N+K, which is not specifically limited here.
  • K>1 and K is a positive integer.
  • the data packet header includes 6 consecutive binary data 1 and one binary data 0 in sequence from right to left, namely "0111111", each of the 3 data segments
  • Each data segment includes 4 bits of target data and one bit of binary data 0 in sequence from right to left, that is, "0xxxx", that is, the target data packet is "0111111 0xxxx 0xxxx 0xxxx".
  • S102 The first device packs each bit of data in the at least one target data packet, so that different data have different signal waveforms after being packed.
  • the signal waveform corresponding to the one bit of data when one bit of data in at least one target data packet is binary data 0, in one data cycle, the signal waveform corresponding to the one bit of data includes a signal rising edge and a signal falling edge. .
  • the signal waveform corresponding to the one bit of data in one data period, includes a signal rising edge and does not include a signal falling edge. Since binary data 0 and binary data 1 have different signal waveforms in one data cycle, the first device can pack one bit of data in one data cycle, so that different data can have different signal waveforms after being packed.
  • FIG. 7 shows the waveform corresponding to binary data 0 and the waveform corresponding to binary data 1 in one data period. It can be seen from Figure 7 that binary data 0 and binary data 1 present different waveforms in one data period. Specifically, taking FIG. 7 as an example, a data cycle is a period from time t1 to time t4.
  • time t1 to time t2 is a low level signal
  • time t2 jumps from low level to high level (that is, the rising edge of the signal)
  • the time t2 to the time t3 is a high level signal
  • the time t3 jumps from a high level to a low level (that is, the signal falling edge)
  • the time t3 to time t4 is a low level signal
  • the signal waveform corresponding to the binary data 0 includes a signal rising edge and a signal falling edge.
  • time t1 to time t2 is a low level signal
  • time t2 jumps from low level to high level (ie, the rising edge of the signal)
  • time t2 to time t4 is a high level signal
  • the signal waveform corresponding to binary data 0 includes a signal rising edge, but does not include a signal falling edge.
  • the data cycle is preset by the user, and the data cycle can be obtained as follows: the user determines, according to the internal master clocks of the first device and the second device, that the The working clock for realizing communication (hereinafter referred to as working clock), and then it is determined that at least S working clocks are required to ensure that the signal waveform corresponding to binary data 0 is different from the signal waveform corresponding to binary data 1, that is, at least S working clocks are required.
  • the clock can ensure that the signal waveform corresponding to binary data 0 includes a signal rising edge and a signal falling edge, and the signal waveform corresponding to binary data 1 includes a signal rising edge, but does not include a signal falling edge.
  • the value of one data period is equal to the duration corresponding to the S operating clocks, where S>0 and S is a positive integer.
  • the signal waveform corresponding to binary data 0 includes a signal rising edge and a signal falling edge. It should also include the waveform corresponding to a segment of low-level signal before the rising edge of the signal, and the waveform corresponding to a segment of low-level signal after the falling edge of the signal; the waveform corresponding to binary data 1 should include a rising edge of the signal as well as the rising edge of the signal.
  • the waveform corresponding to a segment of low-level signal before the edge, and the waveform corresponding to a segment of high-level signal after the rising edge of the signal please refer to the data packing method shown in FIG. 8 later for details.
  • the internal master clock of the CPLD chip is 25 megahertz (mega Hertz, MHz), so the first device and the second device can use the 25MHz internal master clock as the work of communication clock.
  • the binary data 0 is low level in the 1st to 3rd main clock cycle (ie 25MHz), high level in the 4th main clock cycle, and in the 5th to 16th main clock cycle.
  • the clock cycle is low; binary data 1 is low on the 1st-3rd master clock cycle and high on the 4th-16th master clock cycle.
  • the internal master clock of the first device and the second device can be selected as the working clock.
  • the working clock of the first device and the working clock of the second device can be made approximately equal by frequency multiplication, and the approximately equal working clock can be used as the working clock for communication between the first device and the second device.
  • the purpose of the working clocks of the first device and the second device being approximately equal or completely equal is: since the first device packs one bit of data in one data cycle, the second device needs to collect one bit of data in one data cycle, so that Only the second device can accurately receive the data sent by the first device.
  • S103 The first device sequentially sends each bit of the packaged data to the second device through the target signal line.
  • the packed binary data 0 is a signal including a signal rising edge and a signal falling edge.
  • the packed binary data 1 is a signal that includes a rising edge of a signal, but does not include a falling edge of the signal.
  • the second device receives each bit of data after packaging sent by the first device through the target signal line, and determines each bit of data according to the signal waveform corresponding to each bit of data after packaging, so as to obtain the above-mentioned at least one target data Bag.
  • the second device when the second device detects that the signal waveform corresponding to a certain bit of data after packaging is on the rising edge, the second device starts. time and collect data at preset moments. When the second device collects a low level, the second device determines that the collected data is binary data 0; when the second device collects a high level, the second device determines that the collected data is binary data 1. In the above manner, the second device can determine each bit of data sent by the first device, thereby obtaining the at least one target data packet.
  • the preset time is a preset working clock cycle. Taking FIG. 8 as an example, the preset time may be any one of the main clock cycles from the 5th main clock cycle to the 16th main clock cycle shown in FIG. 8 .
  • the second device detects the rising edge of the signal through the target signal line, the second device starts the internal master clock to start timing, and starts to collect data after timing X master clock cycles. If the second device collects a low level, then The second device determines that the collected data is binary data 0, and if the second device collects a high level, the second device determines that the collected data is binary data 1. Among them, 2 ⁇ X ⁇ 13, and X is a positive integer.
  • the second device parses the at least one target data packet according to the preset format, thereby obtaining multi-bit target data in the at least one target data packet.
  • the second device After the first device sends all the at least one target data packet to the second device through the target signal line, the second device will obtain multi-bit data. Then, according to the preset format, the second device determines which data in the multi-bit data constitutes the data packet header, so as to determine which data in the multi-bit data is the target data.
  • the second device determines the positions of the plurality of data packet headers in the multi-bit data according to the data packet header including the multi-bit consecutive first identification data in the preset format, and then according to each The position of the data packet header is determined corresponding to each data segment in the target data packet and the target data in each data segment, so as to obtain the target data in each target data packet, and further obtain multi-bit target data.
  • the second device first determines the position of the data packet header and the data packet header as "111110" according to the position of five consecutive binary data 1s in the multi-bit data. Then, extract the 4-bit data after the data packet header, that is, the target data "0101" in the first data segment, and determine that the first data segment is "01010". Then, extract the 4-bit data after the first data segment, that is, the target data "1011” in the second data segment, and determine that the second data segment is "10110". Then, extract the 4-bit data after the second data segment, that is, the target data "1110" in the third data segment, and determine that the third data segment is "11100". Thus, the valid data in the target data packet is "0101 1011 1110".
  • the communication method shown in FIG. 4 can be applied to data communication between chips.
  • the first device includes a first chip
  • the second device includes a second chip.
  • the first chip may be of the same type as the second chip, for example, both the first chip and the second chip are CPLD chips.
  • the type of the first chip may also be different from that of the second chip, for example, the first chip is a CPLD chip, the second chip is a digital signal processing (digital signal processing, DSP) chip, and so on.
  • DSP digital signal processing
  • the communication method shown in FIG. 4 can also be applied to the scenario of preventing mis-insertion of cables, that is, judging whether the target signal line between the first device and the second device is correctly connected.
  • the first device and the second device may be chips, single boards, etc., which are not specifically limited here.
  • the specific process please refer to the detailed description in steps 21 to 23 later.
  • Step 11 Design the board schematic.
  • one or two signal lines are designed between the first chip and the second chip.
  • a signal line can be designed between chip A and chip B; when the first chip and the second chip When sending data to each other, two signal lines can be designed between the first chip and the second chip.
  • the first chip and the second chip may be disposed on the same single board, or may be disposed on different single boards, which are not specifically limited here.
  • Step 12 Write the logic code of the board.
  • the relevant code for data transmission and reception between the first chip and the second chip is written.
  • Step 13 Making the Veneer.
  • the written logic code is burned into the first chip and the second chip as required.
  • Step 14 Test the board.
  • the program is run to test and improve the signal waveform on the signal line between the first chip and the second chip, so as to ensure the stability of the hardware link between the first chip and the second chip. After that, verify whether the data communication between the first chip and the second chip is normal by sending and receiving data (for example, judging whether the sent data is consistent with the received data), when the data communication between the first chip and the second chip is normal , indicating that data communication can be realized between the first chip and the second chip.
  • Step 21 The first device sends at least one target data packet to the second device.
  • At least one target data packet includes multi-bit target data
  • the multi-bit target data includes identification information of the target signal line
  • the identification information of the target signal line is used to indicate the target signal line.
  • the identification information of the target signal line includes the cable number of the target signal line.
  • Step 22 The second device receives at least one target data packet sent by the first device, and parses the at least one target data packet to obtain multi-bit target data included in the at least one target data packet.
  • Step 23 The second device determines whether the identification information of the target signal line included in the multi-bit target data matches the preset information. If the identification information of the target signal line matches the preset information, the second device determines that the connection of the target signal line is correct; if the identification information of the target signal line does not match the preset information, the second device determines that the connection of the target signal line is incorrect.
  • preset information is stored on the second device, and the preset information includes identification information of at least one signal line and connection information of at least one signal line, and the identification information of at least one signal line and the connection information of at least one signal line exist one by one. corresponding relationship.
  • the identification information of the signal line and the connection information of the signal line are both used to indicate the signal line.
  • the identification information of the signal line may be the cable number of the signal line, and the connection information of the signal line may include the information of the two ports connected with the signal line, or may be one of the two ports connected with the signal line ( The port is not the information of the port on which the preset information is stored on the second device), which is not specifically limited here.
  • the identification information of the at least one signal line includes the identification information of the target signal line
  • the connection information of the at least one signal line includes the connection information of the target signal line
  • the connection information of the target signal line includes the information of the port 1 of the first device and the The information of the port 2 of the second device or the connection information of the target signal line is the information of the port 1 of the first device.
  • the matching of the identification information of the target signal line with the preset information means that the identification information of the target signal line is consistent with the identification information of any one of the signal lines in the preset information, and the port indicated by the connection information of the corresponding signal line includes the first Port 1 of the device (the port that sends the identification information of the target signal line).
  • the second device when the second device determines that the target signal line is connected incorrectly, the second device can send out an alarm message to inform the user that the target signal line is connected incorrectly, so that the user can discover the target signal line connection error in time, and Reconnect the target signal line, thereby making the data communication between the first device and the second device more accurate and secure.
  • the data packet header of the target data packet is "111110", and the data segment is "00010" ", that is, the target packet is "111110 00010”.
  • port 2 of the second device will receive the target data packet, thereby obtaining the target data (ie, the number of the target signal line) as "0001".
  • the second device matches the target data with the preset information, and determines that the target data is consistent with the number of the target signal line in the preset information, and the target data is sent by port 1 of the first device, which matches the target signal in the preset information. line connection information. At this time, the second device determines that the target signal line is connected correctly.
  • steps 21 to 23 only describe how to determine whether a cable (that is, the target signal line) between the first device and the second device is connected correctly.
  • the first device and the For other cables between the second devices it can also be determined whether the cables are connected correctly by using the methods described in step 21 to step 23 .
  • the number of cables between the first device and the second device is too large (for example, 100 cables), compared with the method for judging whether the cables are connected correctly shown in FIG.
  • the method described in step 23 can effectively and accurately determine whether all cables are connected correctly, so as to realize the function of preventing wrong insertion of cables.
  • FIG. 9 shows a schematic structural diagram of a first device provided by an embodiment of the present application.
  • the first device includes a data packet construction unit 110, a data packaging unit 120, and a data transceiver unit 130, wherein,
  • the data packet construction unit 110 is configured to construct the multi-bit target data to be sent into at least one target data packet according to a preset format, and each target data packet includes at least one bit of target data and multiple bits of identification data.
  • the multi-bit identification data is used to indicate the quantity and location of the target data in the corresponding target data packet.
  • the data packing unit 120 is configured to pack each bit of data in the at least one target data packet, so that different data have different signal waveforms after being packed.
  • the data transceiving unit 130 is configured to send each bit of the packaged data to the second device in sequence through the target signal line.
  • the signal waveform corresponding to one bit of data when one bit of data in at least one target data packet is binary data 0, within one data cycle, the signal waveform corresponding to one bit of data includes a signal rising edge and a signal falling edge; when one bit of data in at least one target data packet is binary data 1, in one data period, the signal waveform corresponding to one bit of data includes a signal rising edge and does not include a signal falling edge.
  • the multi-bit identification data includes multi-bit first identification data and multi-bit second identification data, and the first identification data and the second identification data are different;
  • the preset format includes: the target data packet includes a data packet header and at least one data segment, the packet header includes multiple consecutive first identification data and at least one second identification data, each data segment in the at least one data segment includes at least one target data and at least one second identification data, The quantity of the multiple consecutive first identification data in the data packet header is greater than the quantity of at least one bit of target data in each data segment.
  • the first device may be a chip, or may be a single board including a chip, etc., which is not specifically limited here.
  • the second device may be a chip, or a single board including a chip, etc., which is not specifically limited here.
  • the first device and the second device are the same device, or may be different devices.
  • the embodiments of the present application do not describe in detail the preset format, the signal waveform corresponding to each bit of data after packaging, and the like.
  • the description of the relevant content in S101-S102 please refer to the description of the relevant content in S101-S102, which will not be repeated here.
  • the above-mentioned embodiment also does not describe in detail the process of constructing the target data packet by the data packet construction unit 110 in the first device and the process of packaging the data by the data packaging unit 120.
  • S101-S102 which will not be repeated here.
  • the first device in this embodiment of the present application is only illustrated by the division of the above-mentioned functional modules.
  • the above-mentioned function allocation may be completed by different functional modules as required, that is, the internal structure of the first device is divided into different functional modules.
  • Function modules to complete all or part of the functions described above.
  • the first device provided in the foregoing embodiment and the first device in the foregoing method embodiment belong to the same concept, and the specific implementation process thereof is detailed in the foregoing method embodiment, which will not be repeated here.
  • FIG. 10 shows a schematic structural diagram of a second device provided by an embodiment of the present application, where the second device includes a data transceiver unit 210 and a data packet analysis unit 220 .
  • the data transceiver unit 210 is configured to receive each bit of data after packaging sent by the first device through the target signal line, and determine each bit of data according to the signal waveform corresponding to each bit of data after packaging, so as to obtain at least one target data Bag;
  • the data packet parsing unit 220 is configured to parse at least one target data packet according to a preset format, so as to obtain multi-bit target data in the at least one target data packet.
  • the data transceiver unit 210 is specifically configured to: start timing when it is detected that the signal waveform corresponding to each bit of data after packaging is on a rising edge, and collect data at a preset time; In the case of a high level, it is determined that the collected data is binary data 0; in the case of a high level, it is determined that the collected data is binary data 1.
  • the second device further includes a judging unit 230, and the judging unit 230 is configured to judge whether the identification information of the target signal line included in the multi-bit target data matches the preset information, wherein the identification information of the target signal line The identification information is used to indicate the target signal line; if the identification information of the target signal line matches the preset information, it is determined that the connection of the target signal line is correct; if the identification information of the target signal line does not match the preset information, it is determined The target signal line is connected incorrectly.
  • the first device may be a chip, or may be a single board including a chip, etc., which is not specifically limited here.
  • the second device may be a chip, or a single board including a chip, etc., which is not specifically limited here.
  • the first device and the second device are the same device, or may be different devices.
  • the embodiment of the present application does not describe in detail the signal waveform, preset format, preset information, etc. corresponding to each bit of data after packaging. No further description is given here.
  • the above embodiment also does not describe in detail the process of parsing the target data packet by the data packet parsing unit 220 in the second device. For details, please refer to the relevant description of S105, which will not be repeated here.
  • the second device in this embodiment of the present application is only illustrated by the division of the above-mentioned functional modules.
  • the above-mentioned function allocation may be completed by different functional modules as required, that is, the internal structure of the second device is divided into different functional modules.
  • Function modules to complete all or part of the functions described above.
  • the second device provided in the foregoing embodiment and the second device in the foregoing method embodiment belong to the same concept, and the specific implementation process thereof is detailed in the foregoing method embodiment, which will not be repeated here.
  • FIG. 11 shows a schematic structural diagram of another first device provided by an embodiment of the present application, where the first device includes a processor 310 , a communication interface 320 , and a memory 330 .
  • the processor 310 , the communication interface 320 and the memory 330 are coupled through the bus 340 .
  • the processor 310 may be a central processing unit (CPU), a general-purpose processor, a DSP, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other available processor.
  • the processor 310 may implement or execute various exemplary methods described in conjunction with the embodiments of the present application. Specifically, the processor 310 reads the program code stored in the memory 330, and cooperates with the communication interface 320 to execute part or all of steps S101-S103 and step 21.
  • the communication interface 320 can be a wired interface or a wireless interface for communicating with other modules or devices.
  • the wired interface can be an Ethernet interface, a controller area network interface, a local interconnect network (LIN), and a FlexRay interface.
  • the interface may be a cellular network interface or use a wireless local area network interface or the like.
  • the communication interface 220 may be connected to other devices, for example, the communication interface 320 may be connected to other electronic devices 350 (eg, a second device) to implement data communication between the first device and the second device.
  • the memory 330 may include volatile memory, such as random access memory (RAM); the memory 330 may also include non-volatile memory, such as read only memory (ROM), flash memory, hard disk (hard disk drive, HDD) or solid state drive (solid state drive, SSD), the memory 330 may also include a combination of the above-mentioned types of memory.
  • RAM random access memory
  • ROM read only memory
  • HDD hard disk drive
  • SSD solid state drive
  • the memory 330 may store program codes and program data.
  • the program code is composed of codes of some or all of the units in the first device shown in FIG.
  • the program data is data generated by the first device shown in FIG. 9 in the process of running the program, for example, target data, first identification data, second identification data, and so on.
  • Bus 340 may be a controller area network (CAN) or other implementation internal bus.
  • the bus 340 can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is shown in FIG. 11, but it does not mean that there is only one bus or one type of bus.
  • the first device in this embodiment of the present application is configured to execute the method executed by the first device in the foregoing method embodiment, which belongs to the same concept as the foregoing method embodiment, and the specific implementation process is detailed in the foregoing method embodiment, which will not be repeated here.
  • FIG. 12 shows a schematic structural diagram of another second device provided by an embodiment of the present application, where the second device includes a processor 410 , a communication interface 420 , and a memory 430 .
  • the processor 410 , the communication interface 420 and the memory 430 are coupled through the bus 440 .
  • the processor 410 may be a CPU, a general purpose processor, a DSP, an ASIC, an FPGA, a PLD, a CPLD, a transistor logic device, a hardware component, or any combination thereof.
  • the processor 410 may implement or execute various exemplary methods described in connection with the present disclosure. Specifically, the processor 410 reads the program code stored in the memory 430, and cooperates with the communication interface 420 to execute part or all of steps S104-S105 and steps 22-23.
  • the communication interface 420 can be a wired interface or a wireless interface for communicating with other modules or devices, the wired interface can be an Ethernet interface, a controller area network interface, a LIN and FlexRay interface, and the wireless interface can be a cellular network interface or use a wireless local area network interface, etc.
  • the communication interface 420 can be connected with other electronic devices 450 (eg, the first device), so as to realize data communication between the first device and the second device.
  • Memory 430 may include volatile memory, such as RAM; memory 430 may also include non-volatile memory, such as ROM, flash memory, HDD, or SSD, and may also include a combination of the foregoing types of memory.
  • the memory 430 may store program codes and program data.
  • the program code consists of code of some or all of the units in the second device shown in FIG.
  • the program data is data generated by the second device shown in FIG. 10 in the process of running the program, for example, target data, first identification data, second identification data, preset information, and the like.
  • Bus 440 may be a CAN or other implementing internal bus.
  • the bus 440 can be divided into an address bus, a data bus, a control bus, and the like. For ease of presentation, only one thick line is shown in FIG. 12, but it does not mean that there is only one bus or one type of bus.
  • the second device in the embodiment of the present application is configured to execute the method executed by the second device in the foregoing method embodiment, which belongs to the same concept as the foregoing method embodiment, and the specific implementation process is detailed in the foregoing method embodiment, which will not be repeated here.
  • An embodiment of the present application further provides a communication system, as shown in FIG. 13 , the communication system shown in FIG. 13 , the communication system shown in FIG. 13 includes a first device 510 and a second device 520 , the first device 510 and the first device 510 The two devices 520 are connected through a target signal line.
  • the first device 510 may be the first device shown in FIG. 9 or the first device shown in FIG. 11 .
  • the first device 510 is configured to execute the method executed by the first device in the above method embodiments, and its specific implementation process is For details, refer to the above method embodiments, which will not be repeated here.
  • the second device 520 may be the second device shown in FIG. 10 or the second device shown in FIG. 12 .
  • the second device 520 is configured to execute the method performed by the second device in the above method embodiments, and its specific implementation is For details of the process, please refer to the above method embodiments, which will not be repeated here.
  • the present application also provides a computer-readable storage medium, where the computer-readable storage medium stores computer instructions, when the computer instructions are executed on a computing device (for example, the first device shown in FIG. 9 or FIG. 11 ), make the computer
  • the device executes the method executed by the first device in the foregoing method embodiments.
  • the present application also provides another computer-readable storage medium, where the computer-readable storage medium stores computer instructions that, when executed on a computing device (for example, the second device shown in FIG. 10 or FIG. 12 ), cause the computer instructions to The computing device executes the method executed by the second device in the above method embodiments.
  • a computing device for example, the second device shown in FIG. 10 or FIG. 12
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product described above includes one or more computer instructions.
  • the aforementioned computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • the above-mentioned computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the above-mentioned computer instructions may be transmitted from a website site, computer, server or data center via wired communication. (eg, coaxial cable, optical fiber, digital subscriber line) or wireless (eg, infrared, wireless, microwave, etc.) to another website site, computer, server or data center.
  • the above-mentioned computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, etc. that includes one or more available media integrated.
  • the above-mentioned usable media may be magnetic media (eg, floppy disks, memory disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, SSD), and the like.
  • magnetic media eg, floppy disks, memory disks, magnetic tapes
  • optical media eg, DVD
  • semiconductor media eg, SSD
  • the disclosed apparatus may also be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored or not implemented.
  • the indirect coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solutions in the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated units are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art, or all or part of the technical solution, and the computer software product is stored in a storage medium.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the aforementioned storage medium may include, for example, various media that can store program codes, such as a U disk, a removable hard disk, a read-only memory, a random access memory, a magnetic disk or an optical disk.

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Abstract

公开了一种通信方法、设备、系统及计算机可读存储介质，其中，方法应用于第一设备和第二设备，第一设备和第二设备通过目标信号线实现数据通信，方法包括：第一设备将待发送的多位目标数据按照预设格式构建成至少一个目标数据包，每个目标数据包包括至少一位目标数据和多位标识数据，每个目标数据包中的多位标识数据用于指示对应的目标数据包中目标数据的数量及位置；第一设备将至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形；第一设备将打包后的每一位数据通过目标信号线依次发送给第二设备。利用该方法进行通信时可有效节省第一设备和第二设备的硬件资源，从而降低第一设备和第二设备的开发成本。

Description

通信方法、设备、系统及计算机可读存储介质
本申请要求于2020年9月22日提交中国专利局、申请号为202011003324.2、发明名称为“通信方法、设备、系统及计算机可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种通信方法、通信设备、通信系统以及计算机可读存储介质。
背景技术
随着云计算的快速发展，人们对服务器产品的功能及性能的需求越来越高，这导致服务器的配置越来越复杂，服务器单板的规模也越来越大。在这一情况下，为了尽可能地节省硬件资源，降低硬件资源的成本，服务器中不同芯片之间的信号传输通常采用串行通信的方式，例如，串行通用输入输出(serial universal input and output,SGPIO)协议。如图1所示，两个基于SGPIO协议进行通信的芯片之间需要配置4根信号线才能实现信号传输，而4根信号线需要占用芯片的8个输入/输出(input/output,I/O)端口，显而易见的，这一配置并不能很好地节省芯片的硬件资源。因此，如何在保证服务器功能及性能不变的情况下，节省硬件资源，降低硬件的成本，仍是当前亟需解决的问题。
发明内容
本申请公开了一种通信方法、设备、系统及计算机可读存储介质，利用该通信方法进行通信时可有效节省通信设备的硬件资源，从而降低硬件的成本。
第一方面，本申请提供了一种通信方法，该方法应用于第一设备和第二设备之间的数据通信，第一设备和第二设备通过目标信号线实现数据通信，该方法包括如下步骤：
第一设备将待发送的多位目标数据按照预设格式构建成至少一个目标数据包，每个目标数据包包括至少一位目标数据和多位标识数据，每个目标数据包中的多位标识数据用于指示对应的目标数据包中目标数据的数量及位置；
第一设备将至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形；
第一设备将打包后的每一位数据通过目标信号线依次发送给第二设备。
实施第一方面描述的方法，第一设备按照预设格式将待发送给第二设备的多位目标数据构建成至少一个目标数据包，然后将至少一个目标数据包中的每一位数据进行打包，最后将打包后的每一位数据通过目标信号线发送给第二设备，从而实现第一设备和第二设备之间的数据通信。可以看出，通过上述方法第一设备和第二设备之间仅需一根信号线(即目标信号线)即可实现第一设备和第二设备之间的数据通信，那么将该方法应用于服务器产品中以实现数据通信时，可以有效地节省硬件资源，降低硬件成本。
在一种可能的实现方式中，当至少一个目标数据包中的一位数据为二进制数据0时，在 一个数据周期内，上述一位数据对应的信号波形包括一个信号上升沿和一个信号下降沿；当至少一个目标数据包中的一位数据为二进制数据1时，在一个数据周期内，上述一位数据对应的信号波形包括一个信号上升沿，且不包括信号下降沿。
可以看出，在一个数据周期内，二进制数据0和二进制数据1具有不同的信号波形，那么第一设备可以在一个数据周期打包一位数据，这样可以使得不同的数据在打包后具有不同的信号波形，从而方便第二设备可以根据信号波形来确定第一设备发送的是数据为二进制数据0还是二进制数据1。
在一种可能的实现方式中，多位标识数据包括多位第一标识数据和多位第二标识数据，第一标识数据和第二标识数据不同；预设格式包括：目标数据包包括数据包头和至少一个数据段，数据包头包括多位连续的第一标识数据和至少一位第二标识数据，至少一个数据段中的每个数据段包括至少一位目标数据和至少一位第二标识数据，数据包头中的多位连续的第一标识数据的数量大于每个数据段中的至少一位目标数据的数量。
可以看出，通过上述预设方式构建目标数据包时，可以将数据包头与数据段进行区分，使得数据包头是唯一的，从而使得第二设备在解析目标数据包时，可以根据数据包头的唯一性，确定数据包头的位置，进一步确定对应的数据段及数据段中的目标数据，从而实现第一设备与第二设备之间的数据通信。
在一种可能的实现方式中，上述方法应用于芯片之间的数据通信，第一设备包括第一芯片，第二设备包括第二芯片。
可以看出，由于上述方法仅需一根信号线便可实现数据通信，因此将上述方法应用于芯片之间的数据通信时，可以有效地节省芯片的硬件资源，从而降低硬件的成本。
在一种可能的实现方式中，上述方法应用于判断第一设备与第二设备之间的目标信号线是否连接正确，第一设备发送给第二设备的多位目标数据中包括目标信号线的标识信息，目标信号线的标识信息用于指示目标信号线，使得第二设备可以根据获得的目标信号线的标识信息判断目标信号线是否连接正确。
可以看出，利用上述方法第一设备可以将目标信号线的标识信息发送给第二设备，使得第二设备能够有效地判断目标信号线是否连接正确，当第二设备确定目标信号线连接错误时，第二设备可以发出告警信息，使得用户能够及时将连接错误的目标信号线重新进行连接，从而提高数据通信的安全性以及准确性。
第二方面，本申请提供了一种通信方法，该方法应用于第一设备和第二设备之间的数据通信，第一设备和第二设备通过目标信号线实现数据通信，该方法包括如下步骤：
第二设备通过目标信号线接收第一设备发送的打包后的每一位数据，并根据打包后的每一位数据对应的信号波形，确定每一位数据，从而获得至少一个目标数据包；
第二设备根据预设格式对至少一个目标数据包进行解析，从而得到至少一个目标数据包中的多位目标数据。
实施第二方面描述的方法，由于打包后的每一位数据具有不同的信号波形，因此第二设备可以根据接收到的打包后的数据对应的信号波形确定第一设备发送给第二设备的每一位数据，从而得到至少一个目标数据包。然后，第二设备通过解析至少一个目标数据包，可以获得至少一个目标数据包中包括的多位目标数据，从而实现第一设备和第二设备之间的数据通信。
在一种可能的实现方式中，第二设备根据打包后的每一位数据对应的信号波形，确定每一位数据，包括：当第二设备检测到打包后的每一位数据对应的信号波形处于上升沿时，第 二设备开始计时，并在预设时刻采集数据；在第二设备采集到低电平的情况下，第二设备确定采集到的数据为二进制数据0；在第二设备采集到高电平的情况下，第二设备确定采集到的数据为二进制数据1。通过上述方式，第二设备能够准确获得第一设备发送的每一位数据。
在一种可能的实现方式中，上述方法应用于芯片之间的数据通信，第一设备包括第一芯片，第二设备包括第二芯片。
在一种可能的实现方式中，上述方法应用于判断第一设备与第二设备之间的目标信号线是否连接正确，多位目标数据包括目标信号线的标识信息，目标信号线的标识信息用于指示目标信号线，在第二设备得到目标数据包中的多位目标数据之后，上述方法还包括：第二设备判断多位目标数据中包括的所述目标信号线的标识信息与预设信息是否匹配；在目标信号线的标识信息与预设信息匹配的情况下，第二设备确定目标信号线连接正确；在目标信号线的标识信息与预设信息不匹配的情况下，第二设备确定目标信号线连接错误。
第三方面，本申请提供了一种第一设备，第一设备与第二设备通过目标信号线实现数据通信，第一设备包括数据包构建单元、数据打包单元以及数据收发单元，
数据包构建单元用于将待发送的多位目标数据按照预设格式构建成至少一个目标数据包，每个目标数据包包括至少一位目标数据和多位标识数据，每个目标数据包中的多位标识数据用于指示对应的目标数据包中目标数据的数量及位置；
数据打包单元用于将至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形；
数据收发单元用于将打包后的每一位数据通过目标信号线依次发送给第二设备。
在一种可能的实现方式中，当至少一个目标数据包中的一位数据为二进制数据0时，在一个数据周期内，一位数据对应的信号波形包括一个信号上升沿和一个信号下降沿；当至少一个目标数据包中的一位数据为二进制数据1时，在一个数据周期内，一位数据对应的信号波形包括一个信号上升沿，且不包括信号下降沿。
在一种可能的实现方式中，多位标识数据包括多位第一标识数据和多位第二标识数据，第一标识数据和第二标识数据不同；
预设格式包括：目标数据包包括数据包头和至少一个数据段，数据包头包括多位连续的第一标识数据和至少一位第二标识数据，至少一个数据段中的每个数据段包括至少一位目标数据和至少一位第二标识数据，数据包头中的多位连续的第一标识数据的数量大于每个数据段中的至少一位目标数据的数量。
第四方面，本申请提供了一种第二设备，第一设备和第二设备通过目标信号线实现数据通信，第二设备包括数据收发单元和数据包解析单元，
数据收发单元用于通过目标信号线接收第一设备发送的打包后的每一位数据，并根据打包后的每一位数据对应的信号波形，确定每一位数据，从而获得至少一个目标数据包；
数据包解析单元用于根据预设格式对至少一个目标数据包进行解析，从而得到至少一个目标数据包中的多位目标数据。
在一种可能的实现方式中，数据收发单元具体用于：当检测到打包后的每一位数据对应的信号波形处于上升沿时，开始计时，并在预设时刻采集数据；在采集到低电平的情况下，确定采集到的数据为二进制数据0；在采集到高电平的情况下，确定采集到的数据为二进制数据1。
在一种可能的实现方式中，第一设备包括第一芯片，第二设备包括第二芯片。
在一种可能的实现方式中，第二设备还包括判断单元，判断单元用于判断多位目标数据 中包括的目标信号线的标识信息与预设信息是否匹配，其中，目标信号线的标识信息用于指示目标信号线；在目标信号线的标识信息与预设信息匹配的情况下，确定目标信号线连接正确；在目标信号线的标识信息与预设信息不匹配的情况下，确定目标信号线连接错误。
第五方面，本申请提供了另一种第一设备，第一设备包括处理器和存储器，处理器执行存储器中的代码以实现第一方面所描述的部分或全部步骤。
第六方面，本申请提供了另一种第二设备，第二设备包括处理器和存储器，处理器执行存储器中的代码以实现第二方面所描述的部分或全部步骤。
第七方面，本申请提供了一种计算机可读存储介质，存储有计算机指令，计算机指令用于实现第一方面所描述的部分或全部步骤。
第八方面，本申请提供了一种计算机可读存储介质，存储有计算机指令，计算机指令用于实现第二方面所描述的部分或全部步骤。
第九方面，本申请提供了一种通信系统，通信系统包括第一设备和第二设备，第一设备用于执行第一方面所描述的部分或全部步骤，第二设备用于执行第二方面所描述的部分或全部步骤。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种SGPIO协议的拓扑图；
图2是本申请实施例提供的一种识别线缆是否连接正确的原理示意图；
图3是本申请实施例提供的一种单线异步串行通信协议的拓扑图；
图4是本申请实施例提供的一种通信方法的流程示意图；
图5是本申请实施例提供的一种可能的目标数据包的预设格式的示意图；
图6是本申请实施例提供的另一种可能的目标数据包的预设格式的示意图；
图7是本申请实施例提供的一种不同数据在同一数据周期内对应的信号波形的示意图；
图8是本申请实施例提供的一种数据打包方式的示意图；
图9是本申请实施例提供的一种第一设备的结构示意图；
图10是本申请实施例提供的一种第二设备的结构示意图；
图11是本申请实施例提供的另一种第一设备的结构示意图；
图12是本申请实施例提供的另一种第二设备的结构示意图；
图13是本申请实施例提供的一种通信系统的结构示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为了便于理解本申请实施例提供的技术方案，首先介绍本申请实施例适用的应用场景：芯片之间的通信，具体可以包括芯片之间的数据传输、线缆防误插、硬盘点灯等。
近年来，云计算产业迅猛发展，使得人们对服务器产品的功能及性能的需求越来越高，这也进一步导致了服务器的配置越来越复杂，服务器单板的规模也越来越大，服务器产品的制作成本也越来越高。因此，如何在保证服务器产品功能及性能不变的情况下，尽可能地节省硬件资源，降低硬件资源的成本，是当前亟需解决的问题之一。
设备间的通信方式包括串行通信和并行通信，相较于并行通信，串行通信具有结构简单、信号线少、容易实现远距离的信号传输以及成本低等优点。因此，当前的服务器产品中通常采用串行通信的方式来实现服务器内部不同芯片(例如，复杂可编程逻辑器件(complex programming logic device,CPLD))之间的通信，例如，SGPIO协议。如图1所示，图1示出了SGPIO协议的拓扑图。图1中芯片A为主设备(master)，芯片B为从设备(slave)，芯片A和芯片B之间通过SGPIO协议(即一组SGPIO总线)实现通信。
一组SGPIO总线具体可以包括4根信号线，分别是：时钟线、信号加载线、数据输出线以及数据输入线。其中，时钟线用于传输从芯片A发往芯片B的时钟信号(CLK)，从而使得芯片A和芯片B能够实现同步通信；信号加载线用于传输从芯片A发往芯片B的数据加载和同步信号(Load)，数据加载和同步信号用于指示一帧新的数据即将开始传输；数据输出线用于传输从芯片A发往芯片B的数据信号(DataOut)；数据输入线用于传输从芯片B发往芯片A的数据信号(DataIn)。
从图1可以看出，芯片A通过4个I/O端口(例如，端口1-端口4)与4根信号线的一侧相连，芯片B通过4个I/O端口(例如，端口5-端口8)与4根信号线的另一侧相连，也就是说，需要占用芯片A的4个I/O端口以及芯片B的4个I/O端口，才能实现芯片A和芯片B之间的通信。可以理解的，在芯片A向芯片B发送数据，但芯片B不用向芯片A发送数据的情况下，一组SGPIO总线包括的信号线可以相应地减少为3根，即时钟线、信号加载线以及数据输出线。但在这种情况下，仍需要占用的芯片A的3个I/O端口，芯片B的3个I/O端口。总的来说，SGPIO总线占用的硬件资源(I/O资源)较多，因此在芯片A和/或芯片B的I/O端口短缺的应用场景中SGPIO协议并不适用。
当图1中的芯片A和芯片B通过SGPIO总线建立连接后，芯片A和芯片B之间可以进行数据传输。但是为了避免数据传输出现错误，在数据传输之前，需要判断芯片A和芯片B之间的信号线(线缆)是否连接正确。为了节省芯片A和芯片B的硬件资源，通常基于脉冲宽度调制(pulse width modulation,PWM)信号的波形来识别线缆是否连接正确。如图2所示，图2示出了利用PWM信号识别线缆是否连接正确的原理示意图。图2中，芯片A的端口1通过时钟线向芯片B的端口5发送PWM信号(PWM 1)，芯片A的端口2通过信号加载线向芯片B的端口6发送PWM信号(PWM 2)，芯片A的端口3通过数据输出线向芯片B的端口7发送PWM信号(PWM 3)，芯片A的端口4通过数据输入线向芯片B的端口8发送PWM信号(PWM 4)。其中，PWM 1的占空比为3/7，PWM 2的占空比为2/3，PWM 3的占空比为1，PWM 4的占空比为3/2。因此，芯片B可以根据芯片A发送的PWM信号的占空比确定信号线是否连接正确，具体地，以时钟线为例，当芯片B的端口5接收到芯片A的端口1发送的PWM 1后，检测到PWM 1的占空比为3/7，然后判断PWM 1的占空比与预设占空比是否相同，当PWM 1的占空比与预设占空比相同时，芯片B确定时钟线连接正确，即时钟线为连接在芯片A的端口1和芯片B的端口5之间的线缆。应理解，芯片B判断信号加载线、数据输出线以及数据输入线的是否连接正确方式与上述判断时钟线的是否连接正确的方式类似，此处不再展开赘述。
图2示出的利用4个不同占空比的PWM信号来判断4根信号线是否连接正确，这种方 法虽然仅通过一根信号线便可判断对应的线缆是否连接正确，但这种方法并不适用于线缆数量过多的场景。这是因为：PWM信号的占空比是一种粗略性地计算，也就是说，PWM信号上能承载的数据是有限且不精确的，而在实际的服务器产品中，芯片B可能不仅与芯片A通信，还可能还与其他多个芯片或设备相连，这时芯片B(例如，端口5)上插接了大量的线缆，那么端口5也会接收到大量的PWM信号。当端口5接收到这些PWM信号后，通过计算这些PWM信号的占空比可能得到多个近似相等的占空比，这时端口5将无法准确地判断出这些占空比近似相等的PWM信号对应的线缆是否连接正确。例如，芯片B的端口5上接收到了2个占空比近似为3/7的PWM信号，其中，一个为芯片A的端口1发送的，另一个为芯片C的端口9发送的，此时，芯片B将无法判断出时钟线的另一端是连接在芯片A的端口1上，还是连接在芯片C的端口9上，从而无法判断出时钟线是否连接正确。
为了解决上述问题，本申请实施例提供了一种单线异步串行通信协议，如图3所示，图3示出了本申请实施例提供的单线异步串行通信协议的拓扑图，从图3可以看出，该协议仅需1根信号线(目标信号线)便可以实现第一设备和第二设备之间的数据通信。因此，利用本申请实施例提供的单线异步串行通信协议进行数据通信能够有效地节省硬件资源。另外，利用本申请实施例提供的单线异步串行通信协议传输线缆信息时，还能够有效地判断第一设备和第二设备之间的线缆(包括目标信号线)是否连接正确。为了更加清晰地了解本申请实施例提供的单线异步串行通信协议，下面将以图3中的第一设备和第二设备之间的数据通信为例，对该协议进行详细介绍。
请参见图4，图4示出了本申请实施例提供的一种通信方法的流程示意图，本申请实施例提供的通信方法包括但不限于如下步骤：
S101：第一设备将待发送的多位目标数据按照预设格式构建成至少一个目标数据包。
其中，待发送的多位目标数据均为二进制数据，具体包括二进制数据0和二进制数据1。至少一个目标数据包中的每个目标数据包包括至少一位目标数据和多位标识数据，每个目标数据包中的多位标识数据用于指示对应的目标数据中目标数据的数量及位置。
在一具体的实施例中，多位标识数据包括多位第一标识数据和多位第二标识数据，且第一标识数据和第二标识数据不同。
在一具体的实施例中，预设格式包括：目标数据包包括数据包头和至少一个数据段，数据包头包括多位连续的第一标识数据和至少一位第二标识数据，至少一个数据段中的每个数据段包括至少一位目标数据和至少一位第二标识数据，且数据包头中的多位连续的第一标识数据的数量大于每个数据段中的至少一位目标数据的数量。可以理解的，本申请设计的预设格式中数据包头中的多位连续的第一标识数据的数量大于每个数据段中的至少一位目标数据的数量的目的是：在目标数据包中，可以将数据包头与数据段进行区分，使得数据包头是唯一的，从而使得后续解析数据包时，可以根据数据包头的唯一性，确定数据包头的位置，从而确定对应的数据段及数据段中的目标数据。
在一更具体的实施例中，以图5为例，图5示出了一种可能的目标数据包的预设格式。图5中，目标数据包包括数据包头和M个数据段。数据包头从左往右依次包括N+1位连续的二进制数据1和一位二进制数据0，M个数据段中的每个数据段从左往右依次包括N位目标数据和一位二进制数据0。其中，M和N均为用户预先设定的，M和N均为正整数。例如，假设M＝3，N＝4，则数据包头从左往右依次包括5位连续的二进制数据1和一位二进制数据0，即“111110”，3个数据段中的每个数据段从左往右依次包括4位目标数据和一位二进制数 据0，即“xxxx0”，也就是说，目标数据包为“111110 xxxx0 xxxx0 xxxx0”。
可以理解的，以图5为例，第一标识数据为二进制数据1，第二标识数据为二进制数据0，在实际应用中，第一标识数据还可以为二进制数据0，第二标识数据还可以为二进制数据1，此处不作具体限定，例如，假设M＝3，N＝4，则数据包头从左往右依次包括5位连续的二进制数据0和一位二进制数据1，即“000001”，3个数据段中的每个数据段从左往右依次包括4位目标数据和一位二进制数据1，即“xxxx1”，也就是说，目标数据包为“000001 xxxx1 xxxx1 xxxx1”。
另外，以图5为例，数据包头中包括N+1位连续的第一标识数据，M个数据段中的每个数据段中包括N位目标数据，但在实际应用中，数据包头中的连续的第一标识数据的数量还可以为N+K，此处不作具体限定。其中，K>1且K为正整数。例如，假设M＝3，N＝4，K＝2，则数据包头从左往右依次包括6位连续的二进制数据1和一位二进制数据0，即“1111110”，3个数据段中的每个数据段从左往右依次包括4位目标数据和一位二进制数据0，即“xxxx0”，也就是说，目标数据包为“1111110 xxxx0 xxxx0 xxxx0”。
可选的，以图6为例，目标数据包的预设结构还可以是：目标数据包包括数据包头和M个数据段。数据包头从右往左依次包括N+1位连续的二进制数据1和一位二进制数据0，M个数据段中的每个数据段从右往左依次包括N位目标数据和一位二进制数据0。其中，M和N均为用户预先设定的，M和N均为正整数。例如，假设M＝3，N＝4，则数据包头从右往左依次包括5位连续的二进制数据1和一位二进制数据0，即“011111”，3个数据段中的每个数据段从右往左依次包括4位目标数据和一位二进制数据0，即“0xxxx”，也就是说，目标数据包为“011111 0xxxx 0xxxx 0xxxx”。
可以理解的，以图6为例，第一标识数据为二进制数据1，第二标识数据为二进制数据0，在实际应用中，第一标识数据还可以为二进制数据0，第二标识数据还可以为二进制数据1，此处不作具体限定。例如，例如，假设M＝3，N＝4，则数据包头从右往左依次包括5位连续的二进制数据0和一位二进制数据1，即“100000”，3个数据段中的每个数据段从右往左依次包括4位目标数据和一位二进制数据1，即“1xxxx”，也就是说，目标数据包为“100000 1xxxx 1xxxx 1xxxx”。
另外，以图6为例，数据包头中包括N+1位连续的第一标识数据，M个数据段中的每个数据段中包括N位目标数据，但在实际应用中，数据包头中的连续的第一标识数据的数量可以还可以为N+K，此处不作具体限定。其中，K>1且K为正整数。例如，假设M＝3，N＝4，K＝2，则数据包头从右往左依次包括6位连续的二进制数据1和一位二进制数据0，即“0111111”，3个数据段中的每个数据段从右往左依次包括4位目标数据和一位二进制数据0，即“0xxxx”，也就是说，目标数据包为“0111111 0xxxx 0xxxx 0xxxx”。
S102：第一设备将至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形。
在一具体的实施例中，当至少一个目标数据包中的一位数据为二进制数据0时，在一个数据周期内，所述一位数据对应的信号波形包括一个信号上升沿和一个信号下降沿。当至少一个目标数据包中的一位数据为二进制数据1时，在一个数据周期内，所述一位数据对应的信号波形包括一个信号上升沿，且不包括信号下降沿。由于在一个数据周期内，二进制数据0和二进制数据1具有不同的信号波形，因此第一设备可以在一个数据周期打包一位数据，这样可以使得不同的数据在打包后具有不同的信号波形。
如图7所示，图7示出在一个数据周期内，二进制数据0对应的波形以及二进制数据1 对应的波形。从图7可以看出，二进制数据0和二进制数据1在一个数据周期内呈现出不同的波形。具体地，以图7为例，一个数据周期为时刻t1～时刻t4这一段时长，对于二进制数据0来说，时刻t1～时刻t2为低电平信号，时刻t2从低电平跳变为高电平(即信号上升沿)，时刻t2～时刻t3为高电平信号，时刻t3从高电平跳变为低电平(即信号下降沿)，时刻t3～时刻t4为低电平信号，那么，在一个数据周期内，二进制数据0对应的信号波形中包括一个信号上升沿和一个信号下降沿。对于二进制数据1来说，时刻t1～时刻t2为低电平信号，时刻t2从低电平跳变为高电平(即信号上升沿)，时刻t2～时刻t4为高电平信号，那么，在一个数据周期内，二进制数据0对应的信号波形中包括一个信号上升沿，但不包括信号下降沿。
需要说明的，图7中，在一个数据周期内，二进制数据0和二进制数据1对应的信号波形都存在一个信号上升沿，这是因为：在目标信号线开始传输数据之前，目标信号线处于断电空闲状态，此时相当于输出低电平，即在时刻t1～时刻t2为低电平信号；当目标信号线开始传输数据时，目标信号线处于通电工作状态，此时相当于输出高电平。因此，在一个数据周期内，无论是二进制数据0对应的信号波形还是二进制数据1对应的信号波形都会存在从低电平到高电平的跳变，即在时刻t2出现信号上升沿。可以理解的，在目标信号线传输数据后，对于传输二进制数据0，相当于输出低电平，因此在时刻t3出现从高电平跳变为低电平(即信号下降沿)，在时刻t3～时刻t4为低电平信号。对于传输二进制数据1，相当于输出高电平，因此在时刻t2～时刻t4均为高电平信号。
在一具体的实施例中，数据周期为用户预先设定的，数据周期可以是这样得到的：用户根据第一设备和第二设备的内部主时钟，确定第一设备和第二设备之间能够实现通信的工作时钟(以下简称为工作时钟)，然后确定至少需要S个工作时钟才能够保证二进制数据0对应的信号波形和二进制数据1对应的信号波形不同，也就是说，至少需要S个工作时钟才能够保证二进制数据0对应的信号波形包括一个信号上升沿和一个信号下降沿，二进制数据1对应的信号波形包括一个信号上升沿，但不包括信号下降沿。那么，一个数据周期的数值等于S个工作时钟对应的时长，其中，S>0且S为正整数。需要说明的是，在实际应用中，为了保证数据打包的准确性，在S个工作时钟(即一个数据周期)内，二进制数据0对应的信号波形除了包括一个信号上升沿和一个信号下降沿，还应包括信号上升沿前的一段低电平信号对应的波形，以及信号下降沿后的一段低电平信号对应的波形；二进制数据1对应的波形除了包括一个信号上升沿，还应包括信号上升沿前的一段低电平信号对应的波形，以及信号上升沿后的一段高电平信号对应的波形，具体可参见后文中图8示出的数据打包方式。
例如，假设第一设备和第二设备为CPLD芯片，CPLD芯片的内部主时钟为25兆赫兹(mega Hertz,MHz)，因此第一设备和第二设备可以将25MHz的内部主时钟作为通信的工作时钟。经测试发现，如图8所示，二进制数据0在第1-3个主时钟周期(即25MHz)为低电平，在第4个主时钟周期为高电平，在第5-16个主时钟周期为低电平；二进制数据1在第1-3个主时钟周期为低电平，在第4-16个主时钟周期为高电平。那么，第一设备可以选取16个主时钟周期作为一个数据周期，一个数据周期为16/25M＝0.64μs。因此，第一设备可以每16个主时钟周期打包一位数据，这样打包后的二进制数据0和打包后的二进制数据1具有不同的信号波形。可以理解的，打包后的二进制数据0为一个时长为0.64μs的信号。打包后的二进制数据1为时长为0.64μs的信号。
需要说明的，当第一设备和第二设备具有相同的内部主时钟时，可选用第一设备和第二设备的内部主时钟作为工作时钟，当第一设备和第二设备的内部主时钟不同时，可通过倍频的方式使得第一设备的工作时钟与第二设备的工作时钟近似相等，并将近似相等的工作时钟 作为第一设备与第二设备之间进行通信的工作时钟。本申请中第一设备和第二设备的工作时钟近似相等或完全相等的目的是：由于第一设备在一个数据周期打包一位数据，那么第二设备需要在一个数据周期采集一位数据，这样第二设备才能准确接收到第一设备发送的数据。
S103：第一设备将打包后的每一位数据通过目标信号线依次发送给第二设备。
其中，对于二进制数据0来说，打包后的二进制数据0为一段包括有一个信号上升沿和一个信号下降沿的信号。对于二进制数据1来说，打包后的二进制数据1为一段包括有一个信号上升沿，但不包括信号下降沿的信号。
S104：第二设备通过目标信号线接收第一设备发送的打包后的每一位数据，并根据打包后的每一位数据对应的信号波形，确定每一位数据，从而获得上述至少一个目标数据包。
在一具体的实施例中，以第一设备发送的打包后的任一位数据为例，当第二设备检测到打包后的某一位数据对应的信号波形处于上升沿时，第二设备开始计时，并在预设时刻采集数据。在第二设备采集到低电平的情况下，第二设备确定采集到的数据为二进制数据0；在第二设备采集到高电平的情况下，第二设备确定采集到的数据为二进制数据1。通过上述方式，第二设备可以确定出第一设备发送的每一位数据，从而获得上述至少一个目标数据包。
在一具体的实施例中，预设时刻为预设的工作时钟周期。以图8为例，预设时刻可以是图8示出的第5个主时钟周期至第16个主时钟周期中的任一个主时钟周期。具体地，当第二设备通过目标信号线检测到信号上升沿时，第二设备启动内部主时钟开始计时，计时X个主时钟周期后开始采集数据，如果第二设备采集到低电平，则第二设备确定采集到的数据为二进制数据0，如果第二设备采集到高电平，则第二设备确定采集到的数据为二进制数据1。其中，2<X<13，且X为正整数。可以理解的，当第二设备检测到信号上升沿时，第二设备开始计时，相当于第二设备从图8中的第4个主时钟周期开始计时，那么2<X<13相当于图8中的第5个主时钟周期至第16个主时钟周期中的任一个主时钟周期。
S105：第二设备根据预设格式对至少一个目标数据包进行解析，从而得到至少一个目标数据包中的多位目标数据。
具体实现中，当第一设备通过目标信号线将上述至少一个目标数据包全部发送至第二设备后，第二设备会得到多位数据。然后，第二设备根据预设格式，确定多位数据中有哪些数据构成了数据包头，从而确定多位数据中哪些数据为目标数据。
在一具体的实施例中，第二设备获得多位数据后，根据预设格式中数据包头包括多位连续的第一标识数据，确定多位数据中多个数据包头的位置，然后根据每个数据包头的位置确定对应目标数据包中每个数据段以及每个数据段中的目标数据，从而得到每个目标数据包中的目标数据，进一步得到多位目标数据。
例如，假设第二设备接收到的多位数据为“111110 01010 10110 11100”，目标数据包的格式为图5示出的结构，且M＝3，N＝4。那么第二设备接收到多位数据后，首先根据确定多位数据中的连续5个二进制数据1的位置，从而确定数据包头的位置以及数据包头为“111110”。然后，提取出数据包头后的4位数据，即第一数据段中的目标数据“0101”，并确定第一数据段为“01010”。然后，提取出第一数据段后的4位数据，即第二数据段中的目标数据“1011”，并确定第二数据段为“10110”。然后，提取出第二数据段后的4位数据，即第三数据段中的目标数据“1110”，并确定第三数据段为“11100”。从而得到目标数据包中的有效数据为“0101 1011 1110”。
在一具体的实施例中，图4示出的通信方法可应用于芯片之间的数据通信，那么，第一设备包括第一芯片，第二设备包括第二芯片。第一芯片可以与第二芯片的类型相同，例如， 第一芯片和第二芯片均为CPLD芯片。第一芯片也可以与第二芯片的类型不同，例如，第一芯片为CPLD芯片，第二芯片为数字信号处理(digital signal processing,DSP)芯片等等。芯片之间的具体的数据通信过程请参见后文的步骤11-步骤13中的详细叙述。
在另一具体的实施例中，图4示出的通信方法还可应用于线缆防误插的场景中，即判断第一设备与第二设备之间的目标信号线是否连接正确。可选的，第一设备和第二设备可以是芯片，也可以是单板等等，此处不作具体限定。具体过程请参见后文的步骤21-步骤23中的详细叙述。
下面将通过步骤11-步骤13以及步骤21-步骤23分别介绍图4示出的通信方法的2种应用场景。
应用场景一：实现芯片之间的数据传输
步骤11：设计单板原理图。
具体地，根据第一芯片和第二芯片之间的通信要求，在第一芯片和第二芯片之间设计一根或两根信号线。其中，当第一芯片需向第二芯片发送数据，但第二芯片无需向第一芯片发送数据时，可以在芯片A和芯片B之间设计一根信号线；当第一芯片与第二芯片之间互相发送数据时，可以在第一芯片与第二芯片之间设计两根信号线。其中，第一芯片和第二芯片可以设置在同一个单板上，也可以设置在不同的单板上，此处不作具体限定。
步骤12：编写单板的逻辑代码。
具体地，按照前述内容中涉及的通信协议(包括数据打包、数据包结构、数据接收等)编写第一芯片和第二芯片之间进行数据收发的相关代码。
步骤13：制作单板。
具体地，按照单板原理图制成单板后，将编写好的逻辑代码按照需求烧录到第一芯片和第二芯片中。
步骤14：测试单板。
具体地，运行程序，测试并改进第一芯片和第二芯片之间的信号线上的信号波形，以保证第一芯片和第二芯片之间的硬件链路稳定。之后，通过收发数据(例如，判断发送的数据与接收到的数据是否一致)验证第一芯片和第二芯片之间的数据通信是否正常，当第一芯片和第二芯片之间的数据通信正常时，说明第一芯片和第二芯片之间可实现数据通信。
应用场景二：实现线缆防误插
步骤21：第一设备向第二设备发送至少一个目标数据包。
其中，至少一个目标数据包中包括多位目标数据，多位目标数据包括目标信号线的标识信息，目标信号线的标识信息用于指示目标信号线。可选的，目标信号线的标识信息包括目标信号线的线缆编号。
步骤22：第二设备接收第一设备发送的至少一个目标数据包，并对至少一个目标数据包进行解析，得到至少一个目标数据包中包括的多位目标数据。
步骤23：第二设备判断多位目标数据中包括的目标信号线的标识信息与预设信息是否匹配。如果目标信号线的标识信息与预设信息匹配，则第二设备确定目标信号线连接正确；如果目标信号线的标识信息与预设信息不匹配，则第二设备确定目标信号线连接错误。
其中，第二设备上存储有预设信息，预设信息包括至少一条信号线的标识信息以及至少一条信号线的连接信息，至少一条信号线的标识信息与至少一条信号线的连接信息存在一一对应的关系。信号线的标识信息和信号线的连接信息都用于指示该信号线。信号线的标识信 息可以是信号线的线缆编号，信号线的连接信息可以包括连接有该信号线的两个端口的信息，也可以是连接有该信号线的两个端口中的一个端口(该端口不是第二设备上存储有预设信息的端口)的信息，此处不作具体限定。至少一条信号线的标识信息包括目标信号线的标识信息，至少一条信号线的连接信息包括目标信号线的连接信息，可选的，目标信号线的连接信息包括第一设备的端口1的信息和第二设备的端口2的信息，或目标信号线的连接信息为第一设备的端口1的信息。目标信号线的标识信息与预设信息匹配指的是：目标信号线的标识信息与预设信息中任一个的信号线的标识信息一致，且对应的信号线的连接信息指示的端口包括第一设备的端口1(发送目标信号线的标识信息的端口)。
在一具体的实施例中，当第二设备确定目标信号线连接错误时，第二设备可以发出告警信息，以告知用户目标信号线连接错误，使得用户可以及时地发现目标信号线连接错误，并重新连接目标信号线，从而使得第一设备与第二设备之间的数据通信更加准确且安全。
举例说明，假设目标线缆的编号为0001，以图5示出的预设格式为例，若M＝1，N＝4，则目标数据包的数据包头为“111110”，数据段为“00010”，即目标数据包为“111110 00010”。第一设备通过目标信号线将目标数据包发送给第二设备后，第二设备的端口2会接收到该目标数据包，从而得到目标数据(即目标信号线的编号)为“0001”。第二设备将目标数据与预设信息进行匹配，确定目标数据与预设信息中的目标信号线的编号一致，且目标数据为第一设备的端口1发送的，符合预设信息中的目标信号线的连接信息。此时，第二设备确定目标信号线连接正确。
可以理解的，上述步骤21-步骤23仅仅介绍了第一设备和第二设备之间的一条线缆(即目标信号线)是如何判断是否连接正确的方法，在实际应用中，第一设备和第二设备之间的其他线缆也可以通过步骤21-步骤23中叙述的方法来判断线缆是否连接正确。尤其是当第一设备和第二设备之间的线缆的数量过多(例如，100条线缆)时，相较于图2示出的判断线缆连接是否正确的方法，通过步骤21-步骤23中叙述的方法可以有效且准确地判断出所有线缆是否连接正确，从而实现线缆防误插功能。
前述内容详细阐述了本申请实施例的方法，为了更好地实施本申请实施例提供的方法，接下来将介绍本申请实施例提供的用于配合实施上述方法的相关设备及系统。
如图9所示，图9示出了本申请实施例提供的一种第一设备的结构示意图，第一设备包括数据包构建单元110、数据打包单元120以及数据收发单元130，其中，
数据包构建单元110用于将待发送的多位目标数据按照预设格式构建成至少一个目标数据包，每个目标数据包包括至少一位目标数据和多位标识数据，每个目标数据包中的多位标识数据用于指示对应的目标数据包中目标数据的数量及位置。
数据打包单元120用于将至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形。
数据收发单元130用于将打包后的每一位数据通过目标信号线依次发送给第二设备。
在一具体的实施例中，当至少一个目标数据包中的一位数据为二进制数据0时，在一个数据周期内，一位数据对应的信号波形包括一个信号上升沿和一个信号下降沿；当至少一个目标数据包中的一位数据为二进制数据1时，在一个数据周期内，一位数据对应的信号波形包括一个信号上升沿，且不包括信号下降沿。
在一具体的实施例中，多位标识数据包括多位第一标识数据和多位第二标识数据，第一标识数据和第二标识数据不同；预设格式包括：目标数据包包括数据包头和至少一个数据段， 数据包头包括多位连续的第一标识数据和至少一位第二标识数据，至少一个数据段中的每个数据段包括至少一位目标数据和至少一位第二标识数据，数据包头中的多位连续的第一标识数据的数量大于每个数据段中的至少一位目标数据的数量。
在一具体的实施例中，第一设备可以是芯片，也可以是包括芯片的单板等等，此处不作具体限定。第二设备可以是芯片，也可以是包括芯片的单板等等，此处不作具体限定。第一设备和第二设备为同一设备，也可以为不同的设备。
为了简便陈述，本申请实施例并没有对预设格式、打包后的每一位数据对应的信号波形、等进行详细说明，具体请参见S101-S102中的相关内容叙述，此处不再进行赘述。上述实施例也没有对第一设备中数据包构建单元110构建目标数据包的过程、数据打包单元120打包数据的过程进行详细说明，具体请参见S101-S102的相关叙述，此处不再展开赘述。
本申请实施例的第一设备仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将第一设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的第一设备与上述方法实施例中的第一设备属于同一构思，其具体实现过程详见上述方法实施例，这里不再赘述。
如图10所示，图10示出了本申请实施例提供的一种第二设备的结构示意图，第二设备包括数据收发单元210和数据包解析单元220。
数据收发单元210用于通过目标信号线接收第一设备发送的打包后的每一位数据，并根据打包后的每一位数据对应的信号波形，确定每一位数据，从而获得至少一个目标数据包；
数据包解析单元220用于根据预设格式对至少一个目标数据包进行解析，从而得到至少一个目标数据包中的多位目标数据。
在一具体的实施例中，数据收发单元210具体用于：当检测到打包后的每一位数据对应的信号波形处于上升沿时，开始计时，并在预设时刻采集数据；在采集到低电平的情况下，确定采集到的数据为二进制数据0；在采集到高电平的情况下，确定采集到的数据为二进制数据1。
在一种可能的实现方式中，第二设备还包括判断单元230，判断单元230用于判断多位目标数据中包括的目标信号线的标识信息与预设信息是否匹配，其中，目标信号线的标识信息用于指示目标信号线；在目标信号线的标识信息与预设信息匹配的情况下，确定目标信号线连接正确；在目标信号线的标识信息与预设信息不匹配的情况下，确定目标信号线连接错误。
在一具体的实施例中，第一设备可以是芯片，也可以是包括芯片的单板等等，此处不作具体限定。第二设备可以是芯片，也可以是包括芯片的单板等等，此处不作具体限定。第一设备和第二设备为同一设备，也可以为不同的设备。
为了简便陈述，本申请实施例并没有对打包后的每一位数据对应的信号波形、预设格式、预设信息等进行详细说明，具体请参见S101-S102、步骤23中的相关内容叙述，此处不再进行赘述。上述实施例也没有对第二设备中数据包解析单元220解析目标数据包的过程进行详细说明，具体请参见S105的相关叙述，此处不再展开赘述。
本申请实施例的第二设备仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将第二设备的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的第二设备与上述 方法实施例中的第二设备属于同一构思，其具体实现过程详见上述方法实施例，这里不再赘述。
如图11所示，图11示出了本申请实施例提供的另一种第一设备的结构示意图，第一设备包括处理器310、通信接口320和存储器330。其中，处理器310、通信接口320以及存储器330通过总线340进行耦合。
处理器310可以是中央处理器(central processing unit,CPU)，通用处理器、DSP、专用集成电路(application specific integrated circuit,ASIC)、现场可编程门阵列(field programmable gate array,FPGA)或者其他可编程逻辑器件(programmable logic device,PLD)、CPLD、晶体管逻辑器件、硬件部件或者其任意组合。处理器310可以实现或执行结合本申请实施例所描述的各种示例性的方法。具体的，处理器310读取存储器330中存储的程序代码，并与通信接口320配合执行S101-S103以及步骤21的部分或者全部步骤。
通信接口320可以为有线接口或无线接口，用于与其他模块或设备进行通信，有线接口可以是以太接口、控制器局域网络接口、局域互联网络(local interconnect network,LIN)以及FlexRay接口，无线接口可以是蜂窝网络接口或使用无线局域网接口等。具体的，通信接口220可以与其他设备连接，例如，通信接口320可以与其他电子设备350(例如，第二设备)相连，以便实现第一设备和第二设备之间的数据通信。
存储器330可以包括易失性存储器，例如随机存取存储器(random access memory,RAM)；存储器330也可以包括非易失性存储器，例如只读存储器(read only memory,ROM)、快闪存储器、硬盘(hard disk drive,HDD)或固态硬盘(solid state drive,SSD)，存储器330还可以包括上述种类的存储器的组合。存储器330可以存储有程序代码以及程序数据。其中，程序代码由图9示出的第一设备中的部分或者全部单元的代码组成，例如，数据包构建单元110的代码、数据打包单元120的代码以及数据收发单元130。程序数据由图9示出的第一设备在运行程序的过程中产生的数据，例如，目标数据、第一标识数据、第二标识数据等等。
总线340可以是控制器局域网络(controller area network,CAN)或其他实现内部总线。总线340可以分为地址总线、数据总线、控制总线等。为了便于表示，图11中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
本申请实施例中的第一设备用于执行上述方法实施例中的第一设备执行的方法，与上述方法实施例属于同一构思，其具体实现过程详见上述方法实施例，这里不再赘述。
如图12所示，图12示出了本申请实施例提供的另一种第二设备的结构示意图，第二设备包括处理器410、通信接口420和存储器430。其中，处理器410、通信接口420以及存储器430通过总线440进行耦合。
处理器410可以是CPU，通用处理器、DSP、ASIC、FPGA、PLD、CPLD、晶体管逻辑器件、硬件部件或者其任意组合。处理器410可以实现或执行结合本申请公开内容所描述的各种示例性的方法。具体的，处理器410读取存储器430中存储的程序代码，并与通信接口420配合执行S104-S105以及步骤22-步骤23的部分或者全部步骤。
通信接口420可以为有线接口或无线接口，用于与其他模块或设备进行通信，有线接口可以是以太接口、控制器局域网络接口、LIN以及FlexRay接口，无线接口可以是蜂窝网络接口或使用无线局域网接口等。具体的，通信接口420可以与其他电子设备450(例如，第一设备)连接，以便实现第一设备和第二设备之间的数据通信。
存储器430可以包括易失性存储器，例如RAM；存储器430也可以包括非易失性存储器，例如ROM、快闪存储器、HDD或SSD，存储器430还可以包括上述种类的存储器的组合。存储器430可以存储有程序代码以及程序数据。其中，程序代码由图10示出的第二设备中的部分或者全部单元的代码组成，例如，数据收发单元210的代码、数据包解析单元220的代码以及判断单元230中的代码。程序数据由图10示出的第二设备在运行程序的过程中产生的数据，例如，目标数据、第一标识数据、第二标识数据、预设信息等。
总线440可以是CAN或其他实现内部总线。总线440可以分为地址总线、数据总线、控制总线等。为了便于表示，图12中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
本申请实施例中的第二设备用于执行上述方法实施例中的第二设备执行的方法，与上述方法实施例属于同一构思，其具体实现过程详见上述方法实施例，这里不再赘述。
本申请实施例还提供了一种通信系统，如图13所示，图13示出的通信系统，图13示出的通信系统包括第一设备510和第二设备520，第一设备510和第二设备520之间通过目标信号线连接。第一设备510可以是图9示出的第一设备，也可是图11示出的第一设备，第一设备510用于执行上述方法实施例中的第一设备执行的方法，其具体实现过程详见上述方法实施例，这里不再赘述。第二设备520可以是图10示出的第二设备，也可以是图12示出的第二设备，第二设备520用于执行上述方法实施例中的第二设备执行的方法，其具体实现过程详见上述方法实施例，这里不再赘述。
本申请还提供了一种计算机可读存储介质，计算机可读存储介质存储有计算机指令，当计算机指令在计算设备(例如，图9或图11示出的第一设备)上运行时，使得计算设备执行上述方法实施例中的第一设备执行的方法。
本申请还提供了另一种计算机可读存储介质，计算机可读存储介质存储有计算机指令，当计算机指令在计算设备(例如，图10或图12示出的第二设备)上运行时，使得计算设备执行上述方法实施例中的第二设备执行的方法。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。上述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行上述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。上述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。上述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，上述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(如，同轴电缆、光纤、数字用户线)或无线(如，红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。上述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。上述可用介质可以是磁性介质，(如，软盘、存储盘、磁带)、光介质(如，DVD)、或者半导体介质(如，SSD)等。在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，也可以通过其它的方式实现。例如以上所描述的装置实施例仅是示意性的，例如所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可结合或者可以集成到 另一个系统，或一些特征可以忽略或不执行。另一点，所显示或讨论的相互之间的间接耦合或者直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者，也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例的方案的目的。
另外，在本申请各实施例中的各功能单元可集成在一个处理单元中，也可以是各单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质例如可包括：U盘、移动硬盘、只读存储器、随机存取存储器、磁碟或光盘等各种可存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种通信方法，其特征在于，应用于第一设备和第二设备，所述第一设备和所述第二设备通过目标信号线实现数据通信，所述方法包括：
    所述第一设备将待发送的多位目标数据按照预设格式构建成至少一个目标数据包，每个目标数据包包括至少一位所述目标数据和多位标识数据，所述每个目标数据包中的多位标识数据用于指示对应的目标数据包中目标数据的数量及位置；
    所述第一设备将所述至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形；
    所述第一设备将打包后的每一位数据通过所述目标信号线依次发送给所述第二设备。
  2. 根据权利要求1所述的方法，其特征在于，当所述至少一个目标数据包中的一位数据为二进制数据0时，在一个数据周期内，所述一位数据对应的信号波形包括一个信号上升沿和一个信号下降沿；当所述至少一个目标数据包中的一位数据为二进制数据1时，在一个数据周期内，所述一位数据对应的信号波形包括一个信号上升沿，且不包括信号下降沿。
  3. 根据权利要求1或2所述的方法，其特征在于，所述多位标识数据包括多位第一标识数据和多位第二标识数据，所述第一标识数据和所述第二标识数据不同；
    所述预设格式包括：所述目标数据包包括数据包头和至少一个数据段，所述数据包头包括多位连续的所述第一标识数据和至少一位所述第二标识数据，所述至少一个数据段中的每个数据段包括至少一位目标数据和至少一位第二标识数据，所述数据包头中的多位连续的第一标识数据的数量大于所述每个数据段中的至少一位目标数据的数量。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述方法还包括：
    所述第二设备通过所述目标信号线接收所述第一设备发送的所述打包后的每一位数据，并根据所述打包后的每一位数据对应的信号波形，确定所述每一位数据，从而获得所述至少一个目标数据包；
    所述第二设备根据所述预设格式对所述至少一个目标数据包进行解析，从而得到所述多位目标数据。
  5. 根据权利要求4所述的方法，其特征在于，所述第二设备根据所述打包后的每一位数据对应的信号波形，确定所述每一位数据，包括：
    当所述第二设备检测到所述打包后的每一位数据对应的信号波形处于上升沿时，所述第二设备开始计时，并在预设时刻采集数据；
    在所述第二设备采集到低电平的情况下，所述第二设备确定采集到的数据为二进制数据0；
    在所述第二设备采集到高电平的情况下，所述第二设备确定采集到的数据为二进制数据1。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述方法应用于芯片之间的数据通信，所述第一设备包括第一芯片，所述第二设备包括第二芯片。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述方法应用于判断所述目标信号线是否连接正确，所述多位目标数据包括所述目标信号线的标识信息，所述目标信号线的标识信息用于指示所述目标信号线，在所述第二设备得到所述目标数据包中的多位目标数据之后，所述方法还包括：
    所述第二设备判断所述多位目标数据中包括的所述目标信号线的标识信息与预设信息是否匹配；
    在所述目标信号线的标识信息与所述预设信息匹配的情况下，所述第二设备确定所述目标信号线连接正确；
    在所述目标信号线的标识信息与所述预设信息不匹配的情况下，所述第二设备确定所述目标信号线连接错误。
  8. 一种第一设备，其特征在于，所述第一设备与第二设备通过目标信号线实现数据通信，所述第一设备包括数据包构建单元、数据打包单元以及数据收发单元，
    所述数据包构建单元用于将待发送的多位目标数据按照预设格式构建成至少一个目标数据包，每个目标数据包包括至少一位所述目标数据和多位标识数据，所述每个目标数据包中的多位标识数据用于指示对应的目标数据包中目标数据的数量及位置；
    所述数据打包单元用于将所述至少一个目标数据包中的每一位数据进行打包，以使得不同的数据在打包后具有不同的信号波形；
    所述数据收发单元用于将打包后的每一位数据通过所述目标信号线依次发送给第二设备。
  9. 根据权利要求8所述的设备，其特征在于，当所述至少一个目标数据包中的一位数据为二进制数据0时，在一个数据周期内，所述一位数据对应的信号波形包括一个信号上升沿和一个信号下降沿；当所述至少一个目标数据包中的一位数据为二进制数据1时，在一个数据周期内，所述一位数据对应的信号波形包括一个信号上升沿，且不包括信号下降沿。
  10. 根据权利要求8或9所述的设备，其特征在于，所述多位标识数据包括多位第一标识数据和多位第二标识数据，所述第一标识数据和所述第二标识数据不同；
    所述预设格式包括：所述目标数据包包括数据包头和至少一个数据段，所述数据包头包括多位连续的所述第一标识数据和至少一位所述第二标识数据，所述至少一个数据段中的每个数据段包括至少一位所述目标数据和至少一位所述第二标识数据，所述数据包头中的多位连续的第一标识数据的数量大于所述每个数据段中的至少一位目标数据的数量。
  11. 根据权利要求8-10任一项所述的设备，其特征在于，所述第一设备还包括数据包解析单元，
    所述数据包收发单元还用于通过所述目标信号线接收所述第二设备发送的打包后的多位数据，并根据所述打包后的多位数据中的每一位数据对应的信号波形，确定所述打包后的多位数据中的每一位数据，从而获得至少一个数据包；
    所述数据包解析单元用于根据所述预设格式对所述至少一个数据包进行解析，从而得到所述至少一个数据包中的目标数据。
  12. 根据权利要求11所述的设备，其特征在于，所述数据收发单元具体用于：
    当检测到所述打包后的每一位数据对应的信号波形处于上升沿时，开始计时，并在预设时刻采集数据；
    在采集到低电平的情况下，确定采集到的数据为二进制数据0；
    在采集到高电平的情况下，确定采集到的数据为二进制数据1。
  13. 根据权利要求11或12任一项所述的设备，其特征在于，所述第一设备用于判断所述目标信号线是否连接正确，所述至少一个数据包中的目标数据包括所述目标信号线的标识信息，所述目标信号线的标识信息用于指示所述目标信号线，所述第一设备还包括线缆判断单元，所述线缆判断单元用于：
    判断所述至少一个数据包中的目标数据中包括的所述目标信号线的标识信息与预设信息是否匹配；
    在所述目标信号线的标识信息与所述预设信息匹配的情况下，确定所述目标信号线连接正确；
    在所述目标信号线的标识信息与所述预设信息不匹配的情况下，确定所述目标信号线连接错误。
  14. 一种第一设备，其特征在于，所述第一设备包括处理器和存储器，所述处理器执行所述存储器中的代码以实现权利要求1至7中第一设备执行的方法。
  15. 一种计算机可读存储介质，其特征在于，存储有计算机指令，所述计算机指令用于实现权利要求1至7中第一设备执行的方法。
  16. 一种通信系统，所述通信系统包括第一设备和第二设备，所述第一设备用于实现权利要求1至7中第一设备执行的方法，所述第二设备执行权利要求1至7中第二设备执行的方法。
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