WO2022062708A1 - 显示面板及其显示装置和制造方法 - Google Patents

显示面板及其显示装置和制造方法 Download PDF

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Publication number
WO2022062708A1
WO2022062708A1 PCT/CN2021/110794 CN2021110794W WO2022062708A1 WO 2022062708 A1 WO2022062708 A1 WO 2022062708A1 CN 2021110794 W CN2021110794 W CN 2021110794W WO 2022062708 A1 WO2022062708 A1 WO 2022062708A1
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WIPO (PCT)
Prior art keywords
area
display panel
display
circuit
shift register
Prior art date
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PCT/CN2021/110794
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English (en)
French (fr)
Inventor
周宏军
杜丽丽
魏锋
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/789,996 priority Critical patent/US11942012B2/en
Publication of WO2022062708A1 publication Critical patent/WO2022062708A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to a display panel, a display device, and a manufacturing method thereof.
  • OLED Organic Light-Emitting Diode
  • display panels have been gradually applied in many fields such as smartphones, wearable devices, tablet computers, TVs, and virtual reality devices.
  • various special-shaped designs have also appeared on the display panel, including Liu Haiping, water drop screen, circular screen, etc.
  • User demands for narrow bezels of display panels are increasing.
  • Embodiments of the present disclosure provide display panels and related display devices and manufacturing methods.
  • a display panel has a display area and a non-display area surrounding the display area.
  • the display panel includes an array of pixels. The edges of the pixel array define the boundary between the display area and the non-display area.
  • the non-display area includes a first area and a second area that are sequentially arranged in a direction away from the pixel array.
  • the display panel also includes a compensation circuit.
  • the compensation circuit is configured to compensate for the parasitic capacitance of the pixels in the pixel array.
  • the compensation circuit includes a first portion located in the first region and a second portion located in the second region.
  • the display panel further includes a first shift register located in the second area. The second portion of the compensation circuit is aligned with the first shift register circuit in the circumferential direction of the pixel array.
  • the pixel array has a profiled profile.
  • the first shift register circuit and the second part of the compensation circuit are alternately arranged in the circumferential direction.
  • the non-display area includes a first half area and a second half area divided by a center line of the pixel array.
  • the display panel further includes a pad area. The pad area is adjacent to the first half area.
  • the second portion of the compensation circuit and the first shift register circuit are located in the second half area.
  • the center line is perpendicular to the line connecting the center of the pad region and the center of the pixel array.
  • a power line located in the second area and located in the first half area is further included.
  • a reset signal line is further included.
  • the reset signal line is configured to provide a reset signal to the pixel.
  • the reset signal line is located in the second area and surrounds the first area.
  • a second shift register circuit and a multiplexing circuit that are located in the first half area and located on a side of the power supply line away from the first area are further included.
  • the multiplexing circuit is configured to multiplex the data signal lines of the pixels.
  • the second shift register circuit and the multiplexing circuit are alternately arranged along the circumferential direction.
  • a wiring area is further included.
  • the wiring area is located in the first half area and on a side of the second shift register circuit and the multiplexing circuit away from the first area.
  • a ground line is further included, which is located in the third area of the non-display area.
  • the third region surrounds the second region and is located between the second region and the pad region.
  • the display device includes the display panel according to any one of the first aspects.
  • a method for manufacturing a display panel includes providing a substrate, forming at least one display panel on the substrate, forming a test circuit on the substrate for testing the display panel, testing the display panel through the test circuit, and cutting the substrate to singulate the display panel display panel, and separate the display panel from the test circuit.
  • FIG. 1 shows a schematic diagram of a related art display panel.
  • FIG. 2 shows a partial schematic view of a non-displayed upper half of the display panel shown in FIG. 1 .
  • FIG. 3 shows a partial schematic view of a non-displayed lower half of the display panel shown in FIG. 1 .
  • FIG. 4 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 5 shows a partial schematic view of the non-displayed second half of the display panel shown in FIG. 4 .
  • FIG. 6 shows a partial schematic view of the first half of the non-display area of the display panel shown in FIG. 4 .
  • FIG. 7 shows a schematic diagram of the design of a compensation circuit according to an embodiment of the present disclosure.
  • FIG. 8 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 9 illustrates a flowchart of a method for manufacturing a display panel according to any embodiment of the present disclosure, according to an embodiment of the present disclosure.
  • FIG. 10 illustrates a schematic diagram of the layout of a plurality of display panels formed on the same substrate according to an embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of a design for forming a test circuit outside of a cut line according to an embodiment of the present disclosure.
  • FIG. 1 shows a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel 10 includes a circular display area AA, a non-display area BB surrounding the circular display area AA, and a pad area CC adjacent to the non-display area BB.
  • the compensation circuit COM is required to compensate the parasitic capacitance of the pixel to improve uniformity.
  • the display panel 10 includes a pixel array, a compensation circuit COM, a reset signal line VIN for supplying reset signals to the pixels, a power supply line VDD, a first shift register circuit GOA1 for supplying gate control signals to the pixels, and a test display A test circuit CT of the panel, a second shift register circuit GOA2 for supplying gate control signals to pixels, a multiplexing circuit MUX for multiplexing data signal lines of pixels, a wiring area FAN, and a ground line VSS.
  • the compensation circuit COM in the upper half of the non-display area BB, the compensation circuit COM, the reset signal line VIN, the power supply line VDD, the first shift register circuit GOA1, the test circuit CT, and the ground line are sequentially included along the direction away from the display area AA. VSS.
  • the reset signal line VIN, the second shift register circuit GOA2 and the multiplexing circuit MUX, the wiring area FAN, and the ground line VSS are sequentially included in the direction away from the display area AA.
  • cutting lines (not shown) are also included at the periphery of the non-display area BB and the pad area CC.
  • the cutting line is cut along the cutting line to separate the display panel.
  • the reset signal line VIN, the power supply line VDD, the ground line VSS, and the cutting line CT in the first half and the second half of the non-display area BB are continuous in the circumferential direction.
  • the regions where each electrical component is located are shown as arcs or rings, but this is only schematic and not limitative.
  • the relative positions of the reset signal line VIN, the power supply line VDD, and the first shift register circuit GOA1 and the test circuit CT are illustrative and not restrictive.
  • the reset signal line VIN, the second shift register circuit GOA2 and the multiplexing circuit MUX are also illustrative and not restrictive. Those skilled in the art can design it according to the specific implementation. The upper and lower halves of the non-display area BB will be described below with reference to FIGS. 2 and 3 .
  • FIG. 2 shows a partial schematic view of the upper half of the non-display area BB of the display panel shown in FIG. 1 .
  • the edge of the pixel array is stepped.
  • the stepped edge defines the boundary between the display area AA and the non-display area BB.
  • the compensation circuit COM is only provided adjacent to the stepped edge of the pixel array.
  • the first shift register GOA1 and the test circuit CT are alternately arranged in the circumferential direction.
  • FIG. 2 only shows a manner in which one first shift register GOA1 and one test circuit CT are alternately arranged. Other alternate arrangements are also possible.
  • FIG. 3 shows a partial schematic view of the lower half of the non-display area BB of the display panel shown in FIG. 1 .
  • the second shift register GOA2 and the multiplexing circuit MUX are alternately arranged in the circumferential direction. Similar to FIG. 2 , FIG. 3 only shows a manner in which one second shift register GOA2 and one multiplexing circuit MUX are alternately arranged. Other alternate arrangements are also possible.
  • the compensation circuit COM needs to compensate the pixel. Parasitic capacitance is compensated.
  • the compensation circuit COM increases the area of the non-display area BB, which is not conducive to realizing a narrow frame.
  • the difference in the number of pixels between the center pixel column and the edge pixel column is relatively large, and the parasitic capacitance difference between the center pixel column and the edge pixel column is also relatively large.
  • the area occupied by the compensation circuit COM is also relatively large. Therefore, the upper half of the non-display area BB where the compensation circuit COM is located limits the width of the frame of the circular display panel.
  • the present disclosure proposes a display panel, which does not include a test circuit CT, and rearranges the electrical components in the non-display area BB.
  • the non-display area BB includes a first area BB1 and a second area BB2 that are sequentially arranged in a direction away from the pixel array. All or part of the compensation circuit COM is arranged in the second area BB2. Thereby, a part of the space saved by removing the test circuit CT can be used to arrange all or part of the compensation circuit COM, so that the width of the bezel can be reduced as a whole.
  • Embodiments of the present disclosure provide a display panel, a display device, and a manufacturing method thereof.
  • the embodiments of the present disclosure and examples thereof will be described in detail below with reference to the accompanying drawings.
  • FIG. 4 shows a schematic diagram of a display panel according to other embodiments of the present disclosure.
  • Figure 4 only shows an embodiment in which the pixel array in display area AA has a circular profile, however it should be understood that other profiles are possible.
  • the compensation circuit COM includes a first part located in the first area BB1 and a second part located in the second area BB2.
  • the compensation circuits COM are all used to compensate the parasitic capacitance of the pixels.
  • the display panel 20 includes a reset signal line VIN.
  • the reset signal line VIN is located in the second area BB2 and surrounds the first area BB1.
  • the reset signal line VIN is used to provide a reset voltage signal to the pixel during the reset phase.
  • the first part or the second part of the compensation circuit COM may be a complete circuit with a compensation function, or may be some electrical components or parts of electrical components in the compensation circuit COM.
  • the non-display area BB includes the first half area HB1 divided by the center line L1 of the pixel array.
  • the center line L1 may form any angle with the line L2 connecting the center of the pad area CC and the center of the pixel array.
  • the center line L1 may be perpendicular to the line L2 connecting the center of the pad area CC and the center of the pixel array.
  • the center refers to the center of the geometry.
  • the center of the pixel array refers to the center of the geometry of the pixel array.
  • the first half area HB1 is also referred to as the lower half of the non-display area BB
  • the second half area is also referred to as the upper half of the non-display area BB.
  • the first half area HB1 and the second half area HB2 of the display panel 20 in FIG. 4 will be described in detail below with reference to FIGS. 5 and 6 .
  • FIG. 5 shows a partial schematic view of the second half HB2 of the non-display area BB of the display panel 20 shown in FIG. 4 .
  • the second portion of the compensation circuit COM is aligned with the first shift register circuit GOA1 in the circumferential direction of the pixel array.
  • "the element A and the element B are aligned in a certain direction” means that the element A and the element B at least partially overlap in a certain direction.
  • the first shift register circuit GOA1 and the second part of the compensation circuit COM are alternately arranged in the circumferential direction, not with the test circuit CT.
  • the first shift register circuit GOA1 is used to provide reset driving signals to the pixels in the reset stage, and to provide gate driving signals to the pixels in the display stage.
  • the test circuit CT is used, for example, to test the display panel in the production stage of the display panel, and is no longer used during the use process of the display panel after it leaves the factory.
  • the pad area CC is disposed adjacent to the first half area HB1. As shown, the second part of the compensation circuit COM and the first shift register circuit GOA1 are located in the second half area HB2.
  • FIG. 6 shows a partial schematic view of the first half HB1 of the non-display area BB of the display panel 20 shown in FIG. 4 .
  • the power line VDD may be located in the second region BB2 and in the first half region HB1.
  • the power line VDD is used to provide power voltage signals to the electrical components on the display panel.
  • no corresponding power supply line VDD is provided in the upper half of the non-display area. This embodiment will be described below with reference to FIG. 7 .
  • FIG. 7 shows a schematic diagram of the design of the compensation circuit COM according to an embodiment of the present disclosure.
  • the data signal line DL and the power supply line VDD are respectively arranged on two adjacent metal layers in the step area of the pixel to form a compensation capacitance, thereby compensating the inductive capacitance of the corresponding pixel.
  • the farther the pixel column is from the center pixel column the larger the parasitic capacitance that needs to be compensated, and the larger the area of the non-display area BB occupied by the corresponding compensation circuit COM.
  • the area occupied by the compensation circuit COM of the pixel row R3 that is farther from the center pixel row R1 is larger than that of the pixel row R2 that is closer to the center pixel row R1.
  • the power supply lines VDD lines corresponding to the respective pixel columns are connected in series with each other.
  • the power line VDD has the function of reducing the voltage drop and improving the uniformity of the display panel. Therefore, the power supply line VDD in the upper half of the non-display area shown in FIG. 2 is. This can reduce the bezel of the display panel by tens to hundreds of microns.
  • the display panel 20 may further include a second shift register circuit GOA2 and a multiplexing circuit MUX located in the first half area HB1 and located on a side of the power supply line VDD away from the first area BB1 .
  • the second shift register circuit GOA2 is used to provide light-emitting signals to the pixels during the display phase.
  • the multiplexing circuit MUX is used for multiplexing the data signal lines of the pixels. In an embodiment of the present disclosure, the multiplexing circuit may supply power to six columns of pixels through one data signal line.
  • the second shift register circuit GOA2 may be alternately arranged with the multiplexing circuit MUX in the circumferential direction.
  • the display panel 20 further includes a wiring area FAN. The wiring area is located in the first half area HB1, and is located on a side of the second shift register circuit GOA2 and the multiplexing circuit MUX away from the first area BB1.
  • the display panel 20 includes a ground line VSS.
  • the ground line VSS is located in the third area BB3 of the non-display area.
  • the ground line VSS is used to provide a ground voltage signal to the electrical components on the display panel 20 .
  • the third area BB3 surrounds the second area BB2 and is located between the second area BB2 and the pad area CC.
  • Embodiments of the present disclosure also provide a display device including the display panel according to any of the embodiments of the present disclosure.
  • FIG. 8 shows a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device 80 may include the display panel 10 or 20 according to any embodiment of the present disclosure.
  • the display device 80 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided by the embodiment of the present disclosure has the same or similar beneficial effects as the display panel provided by the foregoing embodiment of the present disclosure. Since the display panel has been described in detail in the foregoing embodiment, it will not be repeated here.
  • Embodiments of the present disclosure also provide a manufacturing method for manufacturing the display panel 10 or 20 according to any embodiment of the present disclosure. The manufacturing method will be described in detail below with reference to FIG. 9 .
  • a substrate is provided.
  • the substrate may be glass, flexible material, or special plastic.
  • the electrical components required for the display panel may be formed on the substrate through processes such as depositing metal materials, depositing insulating materials, depositing semiconductor materials, and patterning on the substrate.
  • multiple display panels may be formed on the same substrate, as shown in FIG. 10 .
  • 10 illustrates a schematic diagram of the layout of a plurality of display panels formed on the same substrate according to an embodiment of the present disclosure.
  • Figure 10 shows 8 display panels. Other numbers of display panels can also be simultaneously formed on the same substrate.
  • a test circuit CT for testing the display panel is formed on the substrate.
  • the test circuit is formed outside the cutting line, as shown in FIG. 11 .
  • 11 shows a schematic diagram of a design of a test circuit that forms the test circuit outside the cut line according to an embodiment of the present disclosure.
  • the test circuit CT is coupled to the display panel via the pad area CC, and is coupled to the test pad PAD.
  • the display panel is tested by the test circuit CT.
  • a test signal can be provided to the test circuit CT through the test pad PAD, so that the CT can drive the display panel 10 or 20 according to the test signal, so as to perform the test.
  • the substrate is cut to separate the display panel and separate the display panel from the test circuit CT.
  • one display panel may be separated from the test circuit on the substrate and other display panels along the cutting line as shown in FIG. 1 or FIG. 4 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)

Abstract

提供了一种显示面板(10)，具有显示区(AA)和围绕显示区(AA)的非显示区(BB)，显示面板(10)包括：像素阵列，其边缘限定了显示区(AA)与非显示区(BB)之间的边界，非显示区(BB)包括沿远离像素阵列方向依次设置的第一区域(BB1)和第二区域(BB2)；补偿电路(COM)，被配置为对像素阵列中的像素的寄生电容进行补偿，补偿电路(COM)包括位于第一区域（BB1）的第一部分，位于第二区域(BB2)的第二部分；以及位于第二区域(BB2)的第一移位寄存器(GOA1)，补偿电路(COM)的第二部分与第一移位寄存器(GOA1)电路沿像素阵列的周向对准。

Description

显示面板及其显示装置和制造方法
相关申请的交叉引用
本申请要求于2020年9月24日递交的申请号为202011015612.X的中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及显示技术领域，特别地，涉及一种显示面板及其显示装置和制造方法。
背景技术
近年，随着液晶和有机发光二极管(Organic Light-Emitting Diode,OLED)技术的发展，显示面板已逐步应用于智能手机、穿戴设备、平板电脑、电视、虚拟现实设备等诸多领域。同时，显示面板也出现了各式各样的异形设计，包括刘海屏、水滴屏、圆形屏等。用户对显示面板的窄边框的需求日益增加。
发明内容
本公开的实施例提供了显示面板及相关的显示装置和制造方法。
根据本公开的第一方面，提供了一种显示面板。该显示面板具有显示区和围绕该显示区的非显示区。该显示面板包括像素阵列。该像素阵列的边缘限定了显示区与非显示区之间的边界。该非显示区包括沿远离像素阵列的方向依次设置的第一区域和第二区域。该显示面板还包括补偿电路。该补偿电路被配置为对像素阵列中的像素的寄生电容进行补偿。该补偿电路包括位于第一区域的第一部分和位于所述第二区域的第二部分。以及该 显示面板还包括位于所述第二区域的第一移位寄存器。该补偿电路的第二部分与第一移位寄存器电路沿像素阵列的周向对准。
在本公开的实施例中，像素阵列具有异形轮廓。
在本公开的实施例中，第一移位寄存器电路与补偿电路的第二部分沿周向交替设置。
在本公开的实施例中，非显示区包括由像素阵列的中心线划分的第一半区域和第二半区域。显示面板进一步包括衬垫区。该衬垫区邻近第一半区域。补偿电路的第二部分和第一移位寄存器电路位于第二半区域。
在本公开的实施例中，中心线与衬垫区的中心与像素阵列的中心的连线垂直。
在本公开的实施例中，进一步包括位于第二区域且位于第一半区域的电源线。
在本公开的实施例中，进一步包括复位信号线。该复位信号线被配置为用于向像素提供复位信号。该复位信号线位于第二区域并围绕第一区域。
在本公开的实施例中，进一步包括位于第一半区域且位于电源线的远离第一区域的一侧的第二移位寄存器电路和复用电路。该复用电路被配置为复用像素的数据信号线。
在本公开的实施例中，第二移位寄存器电路与复用电路沿所述周向交替设置。
在本公开的实施例中，进一步包括布线区域。该布线区域位于第一半区域且位于所述第二移位寄存器电路与所述复用电路的远离第一区域的一侧。
在本公开的实施例中，进一步包括接地线，其位于非显示区的第三区域。该第三区域围绕第二区域且位于第二区域和衬垫区之间。
根据本公开的第二方面，提供了一种显示装置。该显示装置包括根据第一方面中的任一项的显示面板。
根据本公开的第三方面，提供了一种用于制造根据第一方面中的任一项的显示面板的方法。该方法包括提供基板，在该基板上形成至少一个显 示面板，在该基板上形成用于测试该显示面板的测试电路，通过该测试电路对该显示面板进行测试，以及切割该基板以单独化该显示面板，并将该显示面板与该测试电路分离。
适应性的进一步的方面和范围从本文中提供的描述变得明显。应当理解，本申请的各个方面可以单独或者与一个或多个其他方面组合实施。还应当理解，本文中的描述和特定实施例旨在仅说明的目的并不旨在限制本申请的范围。
附图说明
本文中描述的附图用于仅对所选择的实施例的说明的目的，并不是所有可能的实施方式，并且不旨在限制本申请的范围，其中：
图1示出了一种相关技术的显示面板的示意图。
图2示出了图1所示的显示面板的非显示的上半部分的局部示意图。
图3示出了图1所示的显示面板的非显示的下半部分的局部示意图。
图4示出了根据本公开的实施例的显示面板的示意图。
图5示出了图4所示的显示面板的非显示的第二半部分的局部示意图。
图6示出了图4所示的显示面板的非显示区的第一半部分的局部示意图。
图7示出了根据本公开的实施例的补偿电路的设计的示意图。
图8示出了根据本公开的实施例的一种显示装置的结构示意图。
图9示出根据本公开的实施例的用于制造根据本公开的任一实施例所述的显示面板的方法的流程图。
图10示出了根据本公开的实施例的在同一基板上形成的多个显示面板的布局的示意图。
图11示出了根据本公开的实施例的将测试电路形成在切割线外侧的设计的示意图。
贯穿这些附图的各个视图，相应的参考编号指示相应的部件或特征。
具体实施方式
首先，需要说明的是，除非上下文中另外明确地指出，否则在本文和所附权利要求中所使用的词语的单数形式包括复数，反之亦然。因而，当提及单数时，通常包括相应术语的复数。相似地，措辞“包含”和“包括”将解释为包含在内而不是独占性地。同样地，术语“包括”和“或”应当解释为包括在内的，除非本文中另有说明。在本文中使用术语“实例”之处，特别是当其位于一组术语之后时，所述“实例”仅仅是示例性的和阐述性的，且不应当被认为是独占性的或广泛性的。
另外，还需要说明的是，当介绍本申请的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素；除非另有说明，“多个”的含义是两个或两个以上；用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素；术语“第一”、“第二”、“第三”等仅用于描述的目的，而不能理解为指示或暗示相对重要性及形成顺序。
此外，在附图中，为了清楚起见夸大了各层的厚度及区域。应当理解的是，当提到层、区域、或组件在别的部分“上”时，指其直接位于别的部分上，或者也可能有别的组件介于其间。相反，当某个组件被提到“直接”位于别的组件上时，指并无别的组件介于其间。
如前所述，随着技术的发展，人们对显示面板的边框的窄化提出更高的要求。因此，为满足该要求，需要对显示面板的非显示区的布局进行持续改进。特别地，对于具有异形轮廓的显示面板，相比于常规矩形显示面板，实现窄边框需要付出更多的设计努力以获得更紧密、更合理的布局。
下面参照图1至图3对一种相关技术的显示面板的布局进行说明。在本说明书中，具有异形轮廓的显示面板指轮廓是非正规矩形的，例如具有圆角的矩形、圆形等。图1示出了根据本公开的实施例的显示面板的示意图。如图1所示，显示面板10包括圆形显示区AA、围绕圆形显示区AA的非显示区BB、和与非显示区BB邻近的衬垫区CC。由于圆形显示装置的每列像素的数量不完全相同，因此每一列像素的寄生电容不完全同，影 响显示装置的显示的均一性。因此，需要补偿电路COM对像素的寄生电容进行补偿以提高均一性。显示面板10包括像素阵列、补偿电路COM、用于向像素提供复位信号的复位信号线VIN、电源线VDD、用于向像素提供栅极控制信号的第一移位寄存器电路GOA1、用于测试显示面板的测试电路CT、用于向像素提供栅极控制信号的第二移位寄存器电路GOA2、用于复用像素的数据信号线的复用电路MUX、布线区域FAN、以及接地线VSS。具体地，在非显示区BB的上半部分，沿远离显示区AA的方向依次包括补偿电路COM、复位信号线VIN、电源线VDD、第一移位寄存器电路GOA1及测试电路CT、和接地线VSS。在非显示区BB的下半部分，沿远离显示区AA的方向依次包括复位信号线VIN、第二移位寄存器电路GOA2及复用电路MUX、布线区域FAN、和接地线VSS。另外，在非显示区BB和衬垫区CC的外围还包括切割线(为示出)。在制造显示面板的过程中，沿该切割线切割以单独化显示面板。处于非显示区BB的第一半部分和第二半部分的复位信号线VIN、电源线VDD、接地线VSS、和切割线CT沿周向是连续的。为了便于说明和方便制图，将各电器元件所在的区域示出为圆弧或圆环，但这仅是示意性的而非限制性的。另外，在非显示区BB的上半部分中，复位信号线VIN、电源线VDD、和第一移位寄存器电路GOA1及测试电路CT的相对位置是示意性的而非限制性的。类似地，在非显示区BB的下半部分中，复位信号线VIN、第二移位寄存器电路GOA2及复用电路MUX也是示意性的而非限制性的。本领域的技术人员可以根据具体实施方式对其进行设计。下面参照图2和图3对非显示区BB的上半部分和下半部分进行说明。
图2示出了图1所示的显示面板的非显示区BB的上半部分的局部示意图。如图2所示，像素阵列的边缘成台阶状。该台阶状的边缘限定了显示区AA和非显示区BB之间的边界。补偿电路COM仅被邻近像素阵列的台阶状边缘设置。第一移位寄存器GOA1与测试电路CT沿周向交替设置。图2中仅示出了一个第一移位寄存器GOA1与一个测试电路CT交替设置的方式。其他交替设置的方式也是可行的。
图3示出了图1所示的显示面板的非显示区BB的下半部分的局部示意图。如图所示，第二移位寄存器GOA2与复用电路MUX沿周向交替设置。与图2类似，图3中仅示出了一个第二移位寄存器GOA2与一个复用电路MUX交替设置的方式。其他交替设置的方式也是可行的。
如前所述，由于异形显示面板的每个像素行和像素列中的像素数量是不完全相同的，每行和每列像素的寄生电容也是不完全相同的，因此需要补偿电路COM对像素的寄生电容进行补偿。然而，补偿电路COM增加了非显示区BB的面积，因而不利于实现窄边框。特别是对于圆形显示面板，中心像素列与边缘像素列之间的像素数量差比较大，中心像素列与边缘像素列之间的寄生电容差也比较大，用于像素数量最少的像素列的补偿电路COM所占的面积也比较大。因此，补偿电路COM所在的非显示区BB的上半部分限制了圆形显示面板边框的宽。
针对这一技术问题，本公开提出了一种显示面板，其不包括测试电路CT，将非显示区BB内的电器元件重新布局。在本公开的实施例中，非显示区BB包括沿远离像素阵列的方向依次设置的第一区域BB1和第二区域BB2。补偿电路COM的全部或部分被设置在第二区域BB2内。由此，移除测试电路CT所节省的空间的一部分可用于设置补偿电路COM的全部或部分，从而能够整体上减少边框的宽度。
本公开的实施例提供了一种显示面板及其显示装置和制造方法。下面结合附图对本公开的实施例及其示例进行详细说明。
图4示出了根据本公开的另一些实施例的显示面板的示意图。图4仅示出了显示区AA中的像素阵列具有圆形轮廓的实施例，然而应该理解其它轮廓也是可行的。如图4所示，补偿电路COM包括位于第一区域BB1的第一部分和位于第二区域BB2的第二部分。该补偿电路COM均用于对像素的寄生电容进行补偿。与图1类似，显示面板20包括复位信号线VIN。该复位信号线VIN位于第二区域BB2并围绕第一区域BB1。该复位信号线VIN用于在复位阶段向像素提供复位电压信号。在本公开的实施例中，补偿电路COM的第一部分或第二部分可以是具有补偿功能的完整的电路， 也可以是补偿电路COM中的部分电器元件或电器元件的部分。在本公开的实施例中，非显示区BB包括由像素阵列的中心线L1划分的第一半区域HB1。中心线L1可以与衬垫区CC的中心和像素阵列的中心的连线L2成任一角度。在本公开的实施例中，中心线L1可以与衬垫区CC的中心和像素阵列的中心的连线L2垂直。在本公开的实施例中，中心指几何形状的中心。具体地，像素阵列的中心指像素阵列的几何形状的中心。在这种情况下，第一半区域HB1也称为非显示区BB的下半部分，而第二半区域也称为非显示区BB的上半部分。下面参考图5和图6对图4中的显示面板20的第一半区域HB1和第二半区域HB2进行详细说明。
图5示出了图4所示的显示面板20的非显示区BB的第二半部分HB2的局部示意图。在本公开的实施例中，补偿电路COM的第二部分与第一移位寄存器电路GOA1沿像素阵列的周向对准。在本公开的实施例中，“元素A与元素B沿某一方向对准”是指元素A与元素B沿某一方向至少部分重叠。如图5所示，与图2相比，第一移位寄存器电路GOA1与补偿电路COM的第二部分沿周向交替设置，而不是与测试电路CT沿周向交替设置。这可以将显示面板的宽度减少几百微米，例如0.2毫米。该第一移位寄存器电路GOA1用于在复位阶段向像素提供复位驱动信号，并在显示阶段向像素提供栅极驱动信号。该测试电路CT用于例如在显示面板的生产阶段对显示面板进行测试，在显示面板出厂后的使用过程中不再被使用。衬垫区CC邻近第一半区域HB1设置。如图所示，补偿电路COM的第二部分和第一移位寄存器电路GOA1位于第二半区域HB2。
图6示出了图4所示的显示面板20的非显示区BB的第一半部分HB1的局部示意图。电源线VDD可以位于第二区域BB2，且位于第一半区域HB1。该电源线VDD用于向显示面板上的电器元件提供电源电压信号。与图1相比，本实施例未在非显示区的上半部分设置相应的电源线VDD。下面参考图7对该实施例进行说明。
图7示出了根据本公开的实施例的补偿电路COM的设计的示意图。如图所示，在像素的台阶区数据信号线DL与电源线VDD分别设置在两个 相邻的金属层上以形成补偿电容，从而对相应的像素的感应电容进行补偿。如前所述，距中心像素列距离越远的像素列，所需补偿的寄生电容越大，且所对应的补偿电路COM所占的非显示区BB的面积越大。如图所示，距离中心像素列R1较远的像素列R3的补偿电路COM所占的面积比距中心像素列R1较近的像素列R2的大。与各个像素列对应的电源线VDD线彼此串联。该电源线VDD具有降低压降，改善显示面板的均一性的作用。因此，图2所示的处于非显示区上半部分的电源线VDD。这可以使显示面板的边框减少几十到上百微米。
继续参考图4，显示面板20可以进一步包括位于第一半区域HB1且位于电源线VDD远离第一区域BB1一侧的第二移位寄存器电路GOA2和复用电路MUX。该第二移位寄存器电路GOA2用于在显示阶段向像素提供发光信号。该复用电路MUX用于对像素的数据信号线进行复用。在本公开的实施例中，复用电路可以通过一个数据信号线向六列像素供电。如图6所示第二移位寄存器电路GOA2可以与复用电路MUX沿周向交替设置。显示面板20进一步包括布线区域FAN。该布线区域位于第一半区域HB1，且位于第二移位寄存器电路GOA2与复用电路MUX远离第一区域BB1的一侧。
如图4所示，显示面板20包括接地线VSS。该接地线VSS位于非显示区的第三区域BB3。该接地线VSS用于向显示面板20上的电器元件提供接地电压信号。在本公开的实施例中，该第三区域BB3围绕第二区域BB2，并位于第二区域BB2和衬垫区CC之间。
本公开的实施例还提供一种显示装置，该显示装置包括根据本公开的任一实施例所述的显示面板。
图8示出了根据本公开的实施例的一种显示装置的结构示意图。如图8所示，显示装置80可以包括根据本公开的任一实施例所述的显示面板10或20。
显示装置80可以是于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供的显示装置具有与本公开前述实施例提供的显示面板相同或相似的有益效果，由于显示面板在前述实施例中已经进行了详细说明，此处不再赘述。
本公开的实施例还提供一种制造方法，该制造方法用于制造根据本公开的任一实施例所述的显示面板10或20。下面参照图9对该制造方法进行详细说明。
图9示出根据本公开的实施例的用于制造根据本公开的任一实施例所述的显示面板的方法的流程图。如图9所示，在步骤910，提供基板。在本公开的实施例中，基板可以是玻璃、柔性材料、或特殊塑料。
在步骤920，在基板上形成至少一个显示面板。在本实施例中，可以通过在基板上沉积金属材料、沉积绝缘材料、沉积半导体材料、和构图等工艺，在基板上形成显示面板所需的电器元件。在本公开的实施例中，可以在同一基板上形成多个显示面板，如图10所示。图10示出了根据本公开的实施例的在同一基板上形成的多个显示面板的布局的示意图。图10示出了8个显示面板。在同一基板上也可以同时形成其他数量的显示面板。
在步骤930，在基板上形成用于测试显示面板的测试电路CT。在本公开的实施例中，测试电路被形成在切割线外侧，如图11所示。图11示出了根据本公开的实施例的将测试电路形成在切割线外侧的测试电路的设计的示意图。如图11所示，测试电路CT经由衬垫区CC与显示面板耦接，并与测试焊盘PAD耦接。
在步骤940，通过测试电路CT对显示面板进行测试。在本公开的实施例中，可以通过测试焊盘PAD向测试电路CT提供测试信号以使CT根据测试信号驱动显示面板10或20，从而进行测试。
在步骤950，切割基板以单独化显示面板，并将该显示面板与测试电路CT分离。在本公开的实施例中，可以沿如图1或图4所示的切割线将一个显示面板与基板上的测试电路和其它显示面板分离。
以上为了说明和描述的目的提供了实施例的前述描述。其并不旨在是穷举的或者限制本申请。特定实施例的各个元件或特征通常不限于特定的 实施例，但是，在合适的情况下，这些元件和特征是可互换的并且可用在所选择的实施例中，即使没有具体示出或描述。同样也可以以许多方式来改变。这种改变不能被认为脱离了本申请，并且所有这些修改都包含在本申请的范围内。

Claims (13)

  1. 一种显示面板，具有显示区和围绕所述显示区的非显示区，所述显示面板包括：
    像素阵列，其边缘限定了所述显示区与所述非显示区之间的边界，所述非显示区包括沿远离所述像素阵列的方向依次设置的第一区域和第二区域；
    补偿电路，被配置为对所述像素阵列中的像素的寄生电容进行补偿，且所述补偿电路包括位于所述第一区域的第一部分和位于所述第二区域的第二部分；以及
    位于所述第二区域的第一移位寄存器；
    其中，所述补偿电路的所述第二部分与所述第一移位寄存器电路沿所述像素阵列的周向对准。
  2. 根据权利要求1所述的显示面板，其中，所述像素阵列具有异形轮廓。
  3. 根据权利要求1至2中任一项所述的显示面板，其中，所述第一移位寄存器电路与所述补偿电路的第二部分沿所述周向交替设置。
  4. 根据权利要求3所述的显示面板，其中，所述非显示区包括由所述像素阵列的中心线划分的第一半区域和第二半区域，所述显示面板进一步包括衬垫区，所述衬垫区邻近所述第一半区域设置，其中，所述补偿电路的第二部分和所述第一移位寄存器电路位于所述第二半区域。
  5. 根据权利要求4所述的显示面板，其中，所述中心线与所述衬垫区的中心与所述像素阵列的中心的连线垂直。
  6. 根据权利要求1、2、4和5中任一项所述的显示面板，进一步包括位于所述第二区域且位于所述第一半区域的电源线。
  7. 根据权利要求6所述的显示面板，进一步包括复位信号线，其被配置为用于向所述像素提供复位电压信号，所述复位信号线位于所述第二区域并围绕所述第一区域。
  8. 根据权利要求7所述的显示面板，进一步包括位于所述第一半区域 且位于所述电源线的远离所述第一区域的一侧的第二移位寄存器电路和复用电路，所述复用电路被配置为复用所述像素的数据信号线。
  9. 根据权利要求8所述的显示面板，其中，所述第二移位寄存器电路与所述复用电路沿所述周向交替设置。
  10. 根据权利要求8至9中任一项所述的显示面板，进一步包括布线区域，所述布线区域位于所述第一半区域且位于所述第二移位寄存器电路与所述复用电路的远离所述第一区域的一侧。
  11. 根据权利要求10所述的显示面板，进一步包括接地线，其位于所述非显示区的第三区域，其中，所述第三区域围绕所述第二区域且位于所述第二区域和所述衬垫区之间。
  12. 一种显示装置，所述显示装置包括权利要求1至11中任一项所述的显示面板。
  13. 一种用于制造根据权利要求1至11中任一项所述的显示面板的方法：
    提供基板；
    在所述基板上形成至少一个所述显示面板；
    在所述基板上形成用于测试所述显示面板的测试电路；
    通过所述测试电路对所述显示面板进行测试；以及
    切割所述基板以单独化所述显示面板，并将所述显示面板与所述测试电路分离。
PCT/CN2021/110794 2020-09-24 2021-08-05 显示面板及其显示装置和制造方法 WO2022062708A1 (zh)

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