WO2022062646A1

WO2022062646A1 - Power saving method and apparatus for core cluster, and chip, device and storage medium

Info

Publication number: WO2022062646A1
Application number: PCT/CN2021/109332
Authority: WO
Inventors: 刘君
Original assignee: 哲库科技(北京)有限公司
Priority date: 2020-09-24
Filing date: 2021-07-29
Publication date: 2022-03-31
Also published as: CN112114651B; CN112114651A

Abstract

Disclosed are a power saving method and apparatus for a core cluster, and a chip, a device and a storage medium. The core cluster comprises at least two cores. The method comprises: when any core in a core cluster completes each distributed non-idle task, the any core entering an idle state; the any core determining whether same is the last core, in the core cluster, which enters the idle state; and if the any core is not the last core, in the core cluster, which enters the idle state, the any core entering a sleep state.

Description

Power saving method and device, chip, device and storage medium for processor cluster

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent application with the application number of 202011019751.X and the application date of September 24, 2020, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated by way of full-text introduction this application.

technical field

The present application relates to electronic technology, and relates to, but is not limited to, power saving methods and devices, chips, devices, and storage media for processor clusters.

Background technique

At present, in the field of electronic technology, from early single-core processors, to multi-core processors, to cluster structures, the purpose is to improve the processing capability of the system under a limited main frequency. The introduction of cluster structure also provides the basis for the realization of multi-task parallelism. A cluster structure is a more sophisticated approach that groups several processor cores into a group called a cluster. Typically, several such clusters can be set up within a slice. Since each cluster contains multiple processor cores, it has more processing power.

In portable electronic products such as mobile phones, Ipads, MP3 players, and phone watches that have strict power consumption requirements, the chip solutions mostly use processor clusters (Core Cluster). Therefore, how to save the power consumption of the processor cluster, It is particularly important in these electronic products that require high low power consumption.

SUMMARY OF THE INVENTION

The power saving method and device, chip, device, and storage medium of a processor cluster provided by this application are implemented as follows:

The present application provides a power saving method for a processor cluster, wherein the processor cluster includes at least two processor cores, and the method includes: completing, in any one of the processor cores in the processor cluster, each of the allocated processor cores. When a non-idle task occurs, any of the processor cores enters an idle state; the any processor core determines whether it is the last processor core in the processor cluster to enter the idle state; if any of the processor cores enter the idle state The processor core is not the last processor core in the processor cluster to enter the idle state, and any of the processor cores enters the sleep state.

A processing device provided by the present application, the processing device is any processing device in a processor cluster, and the processing device includes: a determining module, configured to enter an idle state when each assigned non-idle task is completed , determine whether it is the last processing device in the processor cluster to enter the idle state; the control module is configured to control the processing device if it is not the last processing device in the processor cluster to enter the idle state Go to sleep.

The present application provides a chip, the chip includes at least two processors, and when any one of the processors executes a computer program, the method described in the present application is implemented.

An electronic device provided by the present application includes a memory and at least two processors, wherein the memory stores a computer program that can be run on the processors, and when any one of the processors executes the program, the computer program described in the present application is implemented. method.

A computer-readable storage medium provided by this application has a computer program stored thereon, and when the computer program is executed by a processor, the method described in this application is implemented.

Description of drawings

The accompanying drawings herein are incorporated into and constitute a part of this specification, and these drawings illustrate embodiments consistent with the present application, and together with the description, serve to explain the technical solutions of the present application.

FIG. 1A is a schematic flowchart of an implementation of a power saving method for a processor cluster provided by the present application;

1B is a schematic diagram of the effect comparison of two technical solutions provided by the application;

2 is a schematic structural diagram of a modem provided by the application;

3 is a schematic flowchart of another implementation of the power saving method for a processor cluster provided by the present application;

4 is a schematic flowchart of another implementation of the power saving method for a processor cluster provided by the present application;

5 is a schematic structural diagram of a processing device provided by the present application;

FIG. 6 is a schematic structural diagram of an electronic device provided by the present application.

detailed description

In order to make the purpose, technical solutions and advantages of the present application clearer, the specific technical solutions of the present application will be further described in detail below with reference to the accompanying drawings in the present application. The following examples are used to illustrate the present application, but are not intended to limit the scope of the present application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terminology used herein is for the purpose of describing the present application only and is not intended to limit the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be pointed out that the term "first\second\third" involved in this application is used to distinguish similar or different objects, and does not represent a specific ordering of objects. It can be understood that "first\second\third" Where permitted, the specific order or sequence may be interchanged to enable the application described herein to be practiced in sequences other than those illustrated or described herein.

The present application provides a power saving method for a processor cluster, where the processor cluster includes at least two processor cores. FIG. 1A is a schematic flowchart of the implementation of the power saving method for the processor cluster of the present application, as shown in FIG. 1A , The method may include the following steps 101 to 103:

Step 101: When any one of the processor cores in the processor cluster completes each non-idle task assigned, the any processor core enters an idle state, and determines whether it is in the processor cluster. The last processor core to enter the idle state; if yes, go to step 102; otherwise, go to step 103.

The processor cluster includes at least two processor cores, for example, including 4 processor cores or 6 processor cores. In this application, the number of processor cores included in the processor cluster is not limited. Each processor core corresponds to a processor. Correspondingly, the component corresponding to the processor cluster may be a multi-core processor. That is to say, in this application, a processor and a multi-core processor correspond to a hardware concept, and a processor cluster and a processor core correspond to a software concept. The number of processors of the multi-core processor is not limited, and may be two or more. There is also no limitation on whether the corresponding processors of these processor cores are of the same model. These processors can be the same model or different.

In some embodiments, after each processor core enters the idle state, or when it is determined that it is about to enter the sleep state, the processor core sends a notification message to each other processor core to notify that it has entered the idle state. Each processor core can determine whether it is the last processor core in the processor cluster to enter the idle state according to the number of received notification messages.

In some embodiments, each processor core in the processor cluster has one or more non-idle tasks and also has one idle task. The priority of the idle task is the lowest, and the processor core enters the idle state after executing each non-idle task, that is, executes the idle task. That is, the step of determining whether it is the last processor core in the processor cluster to enter the idle state is performed; based on this, step 102 or step 103 is performed.

Step 102, the any processor core enters a sleep state, and controls the processor cluster to enter a power saving state.

In some embodiments, the any processor core can control the processor cluster to enter a power saving state before entering the sleep state; in some embodiments, the any processor core can also control the processor cluster to enter the sleep state Controls the processor cluster to enter a power saving state. In this application, this is not limited.

The so-called power saving state means that the power consumption of the processor cluster is reduced compared to the previous working state. For example, the power-saving state is a power-off state or a sleep state. In some embodiments, as the last processor core to enter the idle state, the value of a specific variable in the shared memory may be backed up first; then, the shared memory is controlled to be powered off. In some embodiments, as the last processor core to enter the idle state, peripheral devices of the at least two processor cores can also be controlled to power off, enter the sleep state after the wake-up time is set, and notify the power management Unit (Power Management Unit, PMU), so that the PMU stops supplying power to the processor cluster. For example, the PMU disconnects the power supply circuit between the power supply unit and the components corresponding to the processor cluster, so that the processor cluster enters a power-off state. Of course, the power supply circuit between the power supply unit and the components corresponding to the processor cluster may not be disconnected, but the power supply to some components (such as shared memory and/or peripheral devices, etc.) in the components corresponding to the processor cluster may be stopped. The component can go to sleep.

Understandably, each processor core in the processor cluster has a power management function, that is, any processor core, as the last core to enter the idle state, has the ability to control the processor cluster to enter the power saving state. In this way, there is no need for one main processor core to control the processor cluster to enter the power saving state after waiting for all other processor cores to enter the sleep state, thereby saving unnecessary working time of the main processor core, thereby saving the processor cluster power consumption.

Step 103, any of the processor cores enters a sleep state.

Understandably, each processor core in the processor cluster has a power management function. After completing the assigned non-idle task, each processor core enters the idle state, and then judges whether it is the last one to enter the idle state. If not, it can enter the sleep state without still being in the active state, thereby saving unnecessary power consumption, which is useful for enhancing the endurance of low-power electronic products with strict power consumption requirements. great significance. Especially for mobile phones that people are inseparable from, under the premise of ensuring product functions, low power consumption can greatly extend the battery life of mobile phones, thereby improving user experience.

For example, it is assumed that the processor cluster includes 4 processor cores, that is, 4 cores. In some embodiments, only the main processor core (ie, the main core) has a power management function, and none of core1, core2, and core3 have this function; thus, the main core must wait until the last core even if it is not the last core to enter the idle state. After a core goes to sleep, it can go to sleep by itself. For example, as shown in Timeline 1 in Figure 1B, the main core is the first processor core to enter the idle state. At this time, the main core cannot directly enter the sleep state, but remains in the Active state until core1 to Only when core 3 enters the sleep state can the main core enter the sleep state and control the power-off of the components corresponding to the processor cluster.

In other embodiments, since each processor core has a power management capability, for example, as shown in Timeline 2 in FIG. 1B , once the above-mentioned main core enters the idle state, it is not the last processor core to enter the idle state. , you can directly enter the sleep state without waiting for core1 to core3 to enter the sleep state before entering the sleep state. The task of power management can be completed by other cores. For example, core3 is the last to enter the idle state, so core3 can complete the power management task and control the power-off of the components corresponding to the processor cluster.

It can be seen that, by adopting the latter technical solution, the main core can save the time in the active state (t1 as shown in FIG. 1B ). That is, compared with the previous technical solution (that is, only the main core has the power management function), the main core can enter the sleep state t1 earlier, thereby saving the power consumption of the main core and improving the battery life of the electronic device where it is located. , which is obviously beneficial to improve the user experience.

The application provides a modem, and FIG. 2 is a schematic structural diagram of the modem of the application. As shown in FIG. 2 , the modem 2 includes a multi-core processor 20, a PMU 21, a power supply unit (Power Supply) 22, a shared memory 23 and Peripherals (peripherals) 24; wherein, the multi-core processor 20 includes 4 processors, namely the processor 201, the processor 202, the processor 203 and the processor 204; the PMU 21 includes an AND logic detection circuit (AND) 211.

It should be noted that the fact that the multi-core processor includes 4 processors here is just an example, which should not limit the protection scope of the present application. In this application, the multi-core processor may include any number of processors, which is not limited. The power saving method for a processor cluster provided in this application is applicable to any processor cluster having two or more processor cores, that is, a multi-core processor. Peripherals 24 are peripherals of multi-core processor 20 . For example, peripheral devices 24 are serial devices, timers, and/or interface devices (eg, USB), and the like.

In a low-power consumption scenario of a communication terminal, the modem of the terminal needs to enter a sleep state in a discontinuous reception (Discontinuous Reception, DRX) inactive state or in an airplane (Airplane) mode. In some embodiments, each processor can execute a program instruction to write a sleep bit to a register, thereby triggering the controller to be set, and the PMU detects that all processors have entered sleep through an AND logic detection circuit. After the state, the multi-core processor 20 is controlled to be powered off, that is, the power supply circuit between the power supply unit 22 and the multi-core processor 20 is disconnected.

Understandably, the so-called low-power consumption scenarios of communication terminals refer to portable electronic products with batteries. These products often have relatively high requirements on the battery life of the products. Therefore, how to make these products have lower power consumption on the premise of ensuring functions? become an important issue to be solved.

Based on this, the present application provides a power saving method for a processor cluster, where the processor cluster includes at least two processor cores. FIG. 3 is a schematic flowchart of another implementation of the power saving method for the processor cluster of the present application. , as shown in FIG. 3, the method may include the following steps 301 to 307:

Step 301, when any one of the processor cores in the processor cluster completes each assigned non-idle task, the any processor core enters an idle state, and determines whether it is in the processor cluster. The last processor core to enter the idle state; if yes, go to step 302; otherwise, go to step 307;

Step 302, the any processor core backs up the specific variable value in the shared memory of each of the processor cores.

In some embodiments, the processor core may back up certain variable values in the shared memory of each of the processor cores after entering the idle state and before entering the sleep state. In this way, the related service interruption problem caused by the loss of these data after entering the sleep state can be prevented, thereby effectively improving the communication service quality.

Step 303 , after backing up the specific variable value in the shared memory, the any processor core controls the shared memory to be powered off, and then proceeds to step 304 .

No matter which processor core in the processor cluster finally enters the idle state, it has the ability to control the power-off of the shared memory, so there is no need to tell the main processor core to control the power-off of the shared memory, so that the shared memory can be powered off faster. The memory enters a powered-down state, thereby saving the power consumption of the processor cluster.

The so-called shared memory refers to the cache device shared by each processor core in the processor cluster. For example, the shared memory is the second level cache (L2 Cache).

Step 304 , the one processor core controls the peripheral devices of the at least two processor cores to power off, and then proceeds to step 305 .

It should be noted that the peripheral devices may be part or all of the peripheral devices of the at least two processor cores. That is, the one processor core can control part or all of the peripheral devices of the at least two processor cores to power off. For example, controlling peripheral devices such as serial devices, timers, and/or interface devices (eg, USB) to power off.

Step 305, the any processor core sets the wake-up time of the processor cluster.

Understandably, the communication terminal does not always communicate with the network, but is discontinuous. When the network determines that there is no related service of the terminal, it will tell the terminal when to enter the sleep state, that is, the terminal periodically receives messages sent by the network. The wake-up time setting is for the terminal to wake up after sleeping for a period of time to detect whether the network calls itself.

It should be noted that, in this application, the execution order of step 302 to step 305 is not limited. The processor core can first set the wake-up time of the processor cluster, then back up specific variable values, power off the shared memory, and finally power off the peripheral devices; of course, the processor core can also power off the peripheral devices first , then set the wake-up time of the processor cluster, and finally back up the specific variable values, power off the shared memory, and other execution sequences, which are not exhaustive here.

Step 306, after controlling the power off of the shared memory, controlling the power off of the peripheral devices, and setting the wake-up time of the processor cluster, the any processor core enters a sleep state, and notifies the PMU, so that the PMU When it is detected that each of the processor cores has entered a sleep state, the power supply to the processor cluster is stopped.

In some embodiments, the PMU may disconnect the power supply circuit between the power supply unit and the components corresponding to the processor cluster, thereby stopping power supply to the processor cluster.

Understandably, steps 302 to 306 are an implementation manner of controlling the processor cluster to enter a power saving state. Controlling the processor cluster to enter a power saving state may include at least one of the above steps 302 to 306 . For example, the shared memory is controlled to be powered off after the peripheral device is controlled to be powered off and/or the value of a specific variable in the shared memory is backed up.

The processor core can notify the PMU that it has entered a sleep state in software or hardware. In software, for example, the processor core can send a notification message to the PMU through Bluetooth or other wireless communication methods; in hardware, for example, the processor core can write sleep bits into registers by executing specific program instructions ( sleep bit), thereby informing the PMU that each processor core enters the sleep state when the register stores the sleep bit written by each processor core. In some embodiments, when the sleep bit written by each processor core is stored in the register, the controller can be triggered to set the bit, and the PMU stops the feed after detecting that all the processor cores have entered the sleep state through an AND logic detection circuit. The processor cluster is powered, for example, the power supply circuit between the power supply unit and the components corresponding to the processor cluster is disconnected.

Step 307, any of the processor cores enters a sleep state, and notifies the PMU to enter a sleep state, so that the PMU stops supplying power to the processor cluster when it detects that each of the processor cores has entered a sleep state , to put the processor cluster into a power-saving state.

It should be noted that the processor core may notify the PMU to enter the sleep state before or after entering the sleep state. Understandably, the purpose of informing the PMU is to facilitate the PMU to know in time whether each processor core in the processor cluster has entered the sleep state, so as to quickly disconnect the power supply circuit between the power supply unit and the components corresponding to the processor cluster, thereby Save power consumption.

In some embodiments, a processor core may write sleep bits to a register; wherein the register is used to notify the PMU of each of the processing when the sleep bits written by each of the processor cores are stored The cores are in sleep state. In hardware implementation, when the sleep bit written by each processor core is stored in the register, the controller will be set, so that when the PMU detects that the controller is set through the AND logic detection circuit, it determines Each of the processor cores enters a sleep state. As such, the implementation notifies the PMU to go to sleep.

It can be understood that, in the present application, the PMU processor core is notified by hardware to enter the sleep state, so that a quick notification can be realized, so that the PMU can disconnect the power supply circuit in a more timely manner, thereby saving power consumption.

In practical applications, the software of the modem system uses an operating system (Operating System, OS) to uniformly schedule each processor core in the processor cluster, and the operating system assigns tasks to different processor cores. The software power management scheme determines a processor core in the system as the main processor core, and creates an idle task on the main processor core. The main processor core enters a sleep state after all other processor cores enter an idle state. That is to say, whenever the main processor core enters the idle state, it needs to be the last one to enter the sleep state. After entering the idle state and before entering the sleep state, if all other processor cores enter the sleep state, they are responsible for Manage the power-off process of the entire processor cluster, including controlling the power-off of the L2 Cache and peripheral devices, and backup of system variables, etc. The L2 cache is the shared memory of all processor cores in the processor cluster.

In the process of researching the above process, the inventor found that: the main processor core, as the last processor core to sleep, must always be in the active (Active) state, until all other processor cores confirm that they have returned to sleep before they can sleep. , even if the main processor core has no tasks, the idle state must wait for other processor cores to sleep before entering the sleep state, which prolongs the activation time of the main processor core, resulting in a waste of power. Reasonable arrangement of tasks on each processor core can effectively solve such problems.

Based on this, an exemplary application of the present application in a practical application scenario will be described below.

To put it simply, in this technical solution, by reasonably arranging tasks on each processor core, unnecessary waiting time of the main processor core can be avoided. In this application, the solution in which the power-off process of the processor cluster is centrally managed by one main processor core is changed to distributed power-off management, and the main processor core and other processor cores are no longer distinguished. As shown in Figure 4, an idle task (idle task) is created on each processor core (ie core0 to core3). During the task, you can decide whether to go to sleep alone or to power off the components corresponding to the processor cluster as a whole. The conditions for determining whether to sleep alone or the components corresponding to the processor cluster are powered off as a whole are: to determine whether you are the last to enter the idle state. If it is the last processor core to enter the idle state, the processor core backs up the variables that the system needs to save, turns off the L2 cache (ie the second level cache) and peripheral devices, and sets the processor cluster's Wake up time, and then put yourself to sleep. At this time, the hardware PMU unit detects that all processor cores have been sleeping, and powers off the corresponding components of the processor cluster as a whole; if you are not the last processor core to enter the idle state, only Put yourself into a sleep state, and hand off the work of controlling the overall power-off of the components corresponding to the processor cluster to other processor cores that have not yet been sleeping.

As can be seen from the process shown in Figure 4, the software power management of multi-core processors is improved to distributed management, and the power-off process of the components corresponding to the processor cluster is centrally managed by the main processor core to each processor core. It can be processed on demand, so that tasks that are not activated by each processor core can enter a sleep state, so that there is no unnecessary waiting state for a processor core, which can save power more effectively.

In the present application, the multi-core system can make the processor cluster enter the sleep state faster when it is sleeping, so as to avoid unnecessary waiting time. By changing the task distribution of the operating system, the power management function is distributed to each processor core, thereby reducing the standby power consumption of the system and saving power.

Through the improvement of the software power management scheme, the centralized management is changed to the distributed management, so as to better adapt to the power control of the multi-core system and reduce the standby power consumption of the system.

Based on the foregoing embodiments, the present application provides a processing device, the processing device includes each module included and each unit included in each module; in the process of implementation, the processing device may be a central processing unit (CPU), Microprocessor (MPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA) or Graphics Processing Unit (GPU), etc.

FIG. 5 is a schematic structural diagram of the processing device of the present application. As shown in FIG. 5 , the processing device 50 is any processing device in the processor cluster, and the processing device 50 includes a determination module 501 and a control module 502, wherein:

A determination module 501, configured to enter an idle state when completing each assigned non-idle task, and determine whether it is the last processing device in the processor cluster to enter the idle state;

The control module 502 is configured to control the processing device 50 to enter the sleep state if it is not the last processing device in the processor cluster to enter the idle state.

In some embodiments, the control module 502 is further configured to, if it is the last processing device in the processor cluster to enter the idle state, control the processing device 50 to enter the sleep state, and control the processor cluster to enter the idle state Power saving state.

In some embodiments, the control module 502 is configured to, if it is the last processing device in the processor cluster to enter the idle state, control the processor cluster to enter the idle state before or after the processing device 50 enters the sleep state Power saving state.

In some embodiments, the processing device 50 further includes a notification module, the notification module is configured to notify the PMU processing device 50 to enter the sleep state if the processing device 50 is not the last processing device in the processor cluster to enter the idle state , so that the PMU stops supplying power to the processor cluster when it detects that each of the processing devices has entered a sleep state.

In some embodiments, the notification module is configured to write a sleep bit to a register; wherein the register is configured to notify the PMU of each of the sleep bits written by each of the processing devices when storing the sleep bits written by each of the processing devices. The processing devices all enter the sleep state.

In some embodiments, the control module 502 is configured to back up the specific variable value in the shared memory of each processing device; after backing up the specific variable value in the shared memory, control the shared memory Power off.

In some embodiments, the control module 502 is configured to back up certain variable values in the shared memory of each processing device 50 after the processing device 50 enters the idle state and before entering the sleep state.

In some embodiments, the control module 502 is further configured to control the power-off of peripheral devices of each of the processing devices.

In some embodiments, the processing device 50 further includes a notification module; wherein, the control module 502 is further configured to set the wake-up time of the processor cluster; control the shared memory to power off and control the peripheral device to power off And/or after the wake-up time of the processor cluster is set, the notification module is triggered to notify the PMU, so that the PMU stops supplying power to the processor cluster when it detects that each of the processing devices has entered a sleep state.

The descriptions of the above processing apparatus embodiments are similar to the descriptions of the above method embodiments, and have similar beneficial effects to the method embodiments. For technical details not disclosed in the embodiments of the processing apparatus of the present application, please refer to the description of the method embodiments of the present application for understanding.

It should be noted that, the division of modules in the above embodiments of the processing apparatus is schematic, which is only a logical function division, and other division manners may be used in actual implementation. In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or may exist independently physically, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units. It can also be implemented in the form of a combination of software and hardware.

When part or all of the power saving method for a processor cluster provided by the above embodiments is implemented by software, the present application provides a chip, the chip includes at least two processors, and any one of the processors executes a computer program When implementing the power saving method of the processor cluster described in this application.

The present application provides an electronic device. FIG. 6 is a schematic structural diagram of the electronic device of the present application. As shown in FIG. 6 , the electronic device 60 includes a memory 601 and at least two processors 602 . The running computer program, when any one of the processors executes the program, implements the power saving method of the processor cluster described in this application.

The memory 601 is configured to store instructions and applications executable by the processor 602, and can also cache data to be processed or processed by the processor 602 and various modules in the electronic device 60 (eg, image data, audio data, voice communication data and Video communication data), which can be realized by flash memory (FLASH) or random access memory (Random Access Memory, RAM).

It should be noted that electronic devices can be of various kinds. The electronic device may be a portable device or a non-portable device. For example, the electronic device may be a portable device such as a smartphone, a laptop, a tablet, an e-reader, a phone watch, a smart bracelet, or an MP3 player. For another example, the electronic device may also be a non-portable device such as a computer.

It should be noted that, in the present application, if the above-mentioned power saving method for a processor cluster is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence or the parts that contribute to related technologies. The computer software products are stored in a storage medium and include several instructions for making the electronic device All or part of the methods described in the various embodiments of the present application are performed. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read only memory (Read Only Memory, ROM), a magnetic disk or an optical disk and other media that can store program codes. As such, the present application is not limited to any particular combination of hardware and software.

The present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the power saving method for a processor cluster provided by the foregoing embodiments.

The present application provides a computer program product containing instructions, which, when running on an electronic device such as a computer, enables the electronic device to execute the method for saving power of a processor cluster provided by the foregoing method embodiments.

It should be pointed out here that the descriptions of the above embodiments such as chips, electronic devices, and storage media are similar to the descriptions of the above method embodiments, and have similar beneficial effects to the method embodiments. For technical details that are not disclosed in the embodiments of the chip, electronic device, and storage medium of the present application, please refer to the description of the method embodiments of the present application for understanding.

It is to be understood that reference throughout the specification to "one embodiment" or "an embodiment" or "some embodiments" means that a particular feature, structure or characteristic associated with the embodiment is included in at least one embodiment of the present application. Thus, appearances of "in one embodiment" or "in an embodiment" or "in some embodiments" in various places throughout this specification are not necessarily necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, rather than the implementation of the present application. The process constitutes any qualification. The above serial numbers in the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

The above descriptions of the various embodiments tend to emphasize the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, details are not repeated herein.

The term "and/or" in this article is only an association relationship to describe associated objects, indicating that there can be three kinds of relationships, such as object A and/or object B, it can mean that object A exists alone, and object A and object exist simultaneously B, there are three cases of object B alone.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, article, or device that includes the element.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The embodiments of the touch screen system described above are only illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods, for example, multiple modules or components may be combined , or can be integrated into another system, or some features can be ignored, or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or modules may be electrical, mechanical or other forms. of.

The modules described above as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules; they may be located in one place or distributed to multiple network units; Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional module in each embodiment of the present application may all be integrated in one processing unit, or each module may be separately used as a unit, or two or more modules may be integrated in one unit; the above integration The module can be implemented in the form of hardware, or it can be implemented in the form of hardware plus software functional units.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by program instructions related to hardware, the aforementioned program can be stored in a computer-readable storage medium, and when the program is executed, the execution includes: The steps of the above method embodiments; and the aforementioned storage medium includes: a removable storage device, a read only memory (Read Only Memory, ROM), a magnetic disk or an optical disk and other media that can store program codes.

Alternatively, if the above-mentioned integrated units of the present application are implemented in the form of software function modules and sold or used as independent products, they may also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence or the parts that contribute to related technologies. The computer software products are stored in a storage medium and include several instructions for making the electronic device All or part of the methods described in the various embodiments of the present application are performed. The aforementioned storage medium includes various media that can store program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.

The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined under the condition of no conflict to obtain new method embodiments.

The features disclosed in the several product embodiments provided in this application can be combined arbitrarily without conflict to obtain a new product embodiment.

The features disclosed in several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only the embodiment of the present application, but the protection scope of the present application is not limited to this. Covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

A power saving method for a processor cluster, wherein the processor cluster includes at least two processor cores, and the method includes:

When any one of the processor cores in the processor cluster completes each assigned non-idle task, the any one of the processor cores enters an idle state;

The any processor core determines whether it is the last processor core in the processor cluster to enter the idle state;

If the any processor core is not the last processor core in the processor cluster to enter the idle state, the any processor core enters the sleep state.
The method of claim 1, wherein the method further comprises:

If the any processor core is the last processor core in the processor cluster to enter the idle state, the any processor core enters a sleep state, and controls the processor cluster to enter a power saving state.
The method according to claim 2, wherein controlling the processor cluster to enter a power saving state by any of the processor cores comprises:

The any processor core controls the processor cluster to enter a power saving state before or after entering the sleep state.
The method of claim 1, wherein, if the any processor core is not the last processor core in the processor cluster to enter the idle state, the method further comprises:

The any processor core notifies the power management unit PMU that the any processor core enters the sleep state, so that the PMU stops sending the processor to the processor when it detects that each of the processor cores has entered the sleep state Cluster power.
The method according to claim 4, wherein the any processor core notifies the PMU that the any processor core enters a sleep state, comprising:

The any of the processor cores writes sleep bits to a register; wherein the register is used to notify the PMU that each of the processor cores has a sleep bit stored with the sleep bits written by each of the processor cores. Go to sleep.
The method of claim 5, wherein the informing the PMU that each of the processor cores enters a sleep state comprises:

When the sleep bit written by each processor core is stored in the register, the controller is set, so that when the PMU detects that the controller is set through the AND logic detection circuit, it is determined that each processor is set The cores go to sleep.
The method according to claim 2 or 3, wherein the any processor core controls the processor cluster to enter a power saving state, comprising:

The any processor core controls peripheral devices of the at least two processor cores to power off;

And/or, the any processor core backs up the specific variable value in the shared memory of each processor core; after backing up the specific variable value in the shared memory, the any processor core backs up the specific variable value in the shared memory. The core controls the power down of the shared memory.
The method according to claim 7, wherein the any one of the processor cores backs up the specific variable value in the shared memory of each of the processor cores, comprising:

The specific variable value in the shared memory of each of the processor cores is backed up by any of the processor cores after entering the idle state and before entering the sleep state.
The method of claim 7, wherein the any processor core controls the processor cluster to enter a power saving state, further comprising:

The any processor core sets the wake-up time of the processor cluster;

After controlling the power-off of the shared memory, controlling the power-off of peripheral devices of the at least two processor cores, and/or setting the wake-up time of the processor cluster, the any processor core notifies the PMU to enable the When the PMU detects that each of the processor cores has entered a sleep state, it stops supplying power to the processor cluster.
The method according to claim 9, wherein the stopping of supplying power to the processor cluster comprises: disconnecting a power supply circuit between a power supply unit and a component corresponding to the processor cluster.
A processing device, the processing device is any processing device in a processor cluster, and the processing device includes:

a determining module, configured to enter an idle state when completing each assigned non-idle task, and determine whether it is the last processing device in the processor cluster to enter the idle state;

A control module, configured to control the processing device to enter a sleep state if it is not the last processing device in the processor cluster to enter the idle state.
The processing device according to claim 11, wherein the control module is further configured to control the processing device to enter the sleep state if it is the last processing device in the processor cluster to enter the idle state, and control the processing device to enter the sleep state. The processor cluster enters a power saving state.
The processing device according to claim 12, wherein the control module is configured to control the processing device before or after the processing device enters the sleep state if it is the last processing device in the processor cluster to enter the idle state The processor cluster enters a power saving state.
The processing device according to claim 12 or 13, wherein the control module is configured to: back up specific variable values in the shared memory of each of the processing devices; After the values are backed up, the shared memory is controlled to be powered off; or, it is also used to control the peripheral devices of each of the processing devices to be powered off.
The processing device according to claim 14, further comprising a notification module;

The control module is further configured to: set the wake-up time of the processor cluster; after controlling the power-off of the shared memory, controlling the power-off of the peripheral device and/or setting the wake-up time of the processor cluster , triggering the notification module to notify the PMU, so that the PMU stops supplying power to the processor cluster when it detects that each of the processing devices has entered a sleep state.
The processing device of claim 11, wherein the processing device further comprises a notification module for notifying power management if the processing device is not the last processing device in the processor cluster to enter the idle state The unit PMU puts the processing devices into a sleep state, so that the PMU stops supplying power to the processor cluster when it detects that each of the processing devices has entered a sleep state.
The processing device according to claim 16, wherein the notification module is configured to write a sleep bit into a register; wherein the register is configured to notify the register when the sleep bit written by each processing device is stored. The PMU enters a sleep state for each of the processing devices.
A chip, the chip includes at least two processors, and any one of the processors implements the method according to any one of claims 1 to 10 when executing a computer program.
An electronic device, comprising a memory and at least two processors, the memory stores a computer program that can be run on the processors, and any one of the processors executing the program implements any one of claims 1 to 10 the method described.
A computer-readable storage medium having a computer program stored thereon, the computer program implementing the method according to any one of claims 1 to 10 when executed by a processor.