CN111077976A - Method for realizing idle state low power consumption mode of multi-core processor and processor - Google Patents
Method for realizing idle state low power consumption mode of multi-core processor and processor Download PDFInfo
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- CN111077976A CN111077976A CN201811214744.8A CN201811214744A CN111077976A CN 111077976 A CN111077976 A CN 111077976A CN 201811214744 A CN201811214744 A CN 201811214744A CN 111077976 A CN111077976 A CN 111077976A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
Abstract
The invention discloses a method for realizing an idle state low-power-consumption mode of a multi-core processor and the processor, which are used for at least solving the problems of higher power consumption, poorer performance and delayed response in the low-power-consumption management of the multi-core processor. The method comprises the following steps: a first core in an idle state selects a second core in a running state from the multi-cores, and triggers the second core to execute power-down processing on the first core; the first core and the second core are different cores.
Description
Technical Field
The invention relates to the field of computers, in particular to a method for realizing an idle state low-power-consumption mode of a multi-core processor and the processor.
Background
In order to reduce the power consumption of a multi-core CPU (Central Processing Unit), the prior art has the problem of high power consumption, poor performance and response lag of the prior art; for example, the conventional multi-core CPU low power consumption management method determines whether the next action is to turn on (turn off) a core or maintain the current state by counting the load condition of the CPU in the current time window, and has the following defects:
a) the switch core has a large impact on power consumption and performance. When the core is closed, the execution thread on the closed core needs to be migrated to other cores, and then the core is closed; when the core is opened, the selected execution threads on other cores are migrated to the newly opened core according to the load balancing principle. The main performance losses in this process are: 1. the overhead introduced by thread migration. 2. Cache (Cache) becomes cold after thread migration, needs to be preheated again, and also introduces power consumption and performance loss.
b) The direct basis for the on (off) core action is the CPU load at the current time. And the CPU load at the current time is counted based on the CPU load for a certain period of time before the current time. If the statistical window is too small, frequent core on (off) actions may result, thereby introducing more extra performance loss, resulting in overall performance degradation; if the statistical window is too large, the real-time response is slow, and the user experience is poor.
c) The core idea of the switch core is to determine the future switch core behavior by counting the CPU load condition of 'a period of time in the past', and in principle, there is a time lag, and the sudden real-time high load demand is reflected slowly, thereby causing phenomena such as blocking and the like.
Disclosure of Invention
In order to overcome the above defects, the technical problem to be solved by the present invention is to provide a method for implementing an idle state low power consumption mode of a multi-core processor and a processor, so as to at least solve the problems of high power consumption, poor performance and response lag in low power consumption management of the multi-core processor.
In order to solve the above technical problem, an idle state low power consumption mode implementation method for a multi-core processor in an embodiment of the present invention includes:
a first core in an idle state selects a second core in a running state from the multi-cores, and triggers the second core to execute power-down processing on the first core; the first core and the second core are different cores.
Optionally, the selecting, by a first core in the idle state, a second core in a running state from the multiple cores, and triggering the second core to perform power-down processing on the first core includes:
the first core sends inter-core communication information to the second core, wherein the inter-core communication information is used for instructing the second core to execute power-down processing on the first core;
and when the second core receives the inter-core communication, the first core is powered off.
Optionally, when the second core receives the inter-core communication, before performing power-down processing on the first core, the method includes:
the second core migrating a first interrupt source that the first core is responsible for processing to the second core; and marking the original home core of the first interrupt source.
Optionally, when receiving the inter-core communication, the second core performs power-down processing on the first core, and then includes:
when detecting that a second interrupt source triggers interrupt, the second core judges whether the second interrupt source belongs to the first core according to the original home core of the second interrupt source and the marked original home core of the first interrupt source; and when the first core belongs to the core, performing power-on processing on the first core.
Optionally, the method further comprises:
when the first core determines that no core in the running state exists in the multi-core, whether the multi-core processor is triggered to enter a system sleep process is determined according to the latest wake-up time of the first core and a preset time threshold.
To solve the above technical problem, a processor according to an embodiment of the present invention includes a plurality of cores connected to each other;
the multi-core power-down processing system comprises a first core in an idle state, a second core and a first processor, wherein the first core is used for selecting the second core in a running state from the multi-cores and triggering the second core to execute power-down processing on the first core; the first core and the second core are different cores.
Optionally, the first core is specifically configured to send inter-core communication information to the second core, where the inter-core communication information is used to instruct the second core to perform power-down processing on the first core;
and the second core is used for powering down the first core when the inter-core communication is received.
Optionally, when receiving the inter-core communication, the second core is further configured to migrate, to the second core, the first interrupt source that the first core is responsible for processing, before performing power-down processing on the first core; and marking the original home core of the first interrupt source.
Optionally, when the second core receives the inter-core communication, after the first core is powered off, the second core is further configured to determine, when detecting that a second interrupt source triggers an interrupt, whether the second interrupt source belongs to the first core according to an original home core of the second interrupt source and a marked original home core of the first interrupt source; and when the first core belongs to the core, performing power-on processing on the first core.
Optionally, the first core is further configured to determine, when it is determined that there is no core in a running state among the multiple cores, whether to trigger the multiple core processor to enter a system sleep process according to a latest wake-up time of the first core and a preset time threshold.
The invention has the following beneficial effects:
the embodiments of the invention effectively solve the problems of high power consumption, poor performance and response lag in the low-power-consumption management of the multi-core processor.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart of entering CPUidle in an embodiment of the present invention;
FIG. 2 is a flowchart of exiting the CPUidle in the embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
The use of prefixes such as "first," "second," etc. to distinguish between elements is merely intended to facilitate the description of the invention and has no particular meaning in and of themselves.
Example one
The embodiment of the invention provides a method for realizing an idle state low-power consumption CPUidle mode of a multi-core processor, which comprises the following steps:
a first core in an idle state selects a second core in a running state from the multi-cores, and triggers the second core to execute power-down processing on the first core; the first core and the second core are different cores.
According to the embodiment of the invention, when the core is in an idle state, the core is actively closed, when the core interrupt comes, the core is awakened in real time to perform task processing, and the second core executes power-off processing on the first core, so that various defects in the prior art are ingeniously avoided, and the problems of high power consumption, poor performance and response lag in low-power-consumption management of the multi-core processor are effectively solved.
During specific implementation, the second core can be triggered to perform power-down processing on the first core through inter-core communication, so that extra overhead is not required to be introduced, and the problem is solved more effectively. That is, the selecting, by a first core in the idle state, a second core in a running state from the multi-cores, and triggering the second core to perform power-down processing on the first core may include:
the first core sends inter-core communication information to the second core, wherein the inter-core communication information is used for instructing the second core to execute power-down processing on the first core;
and when the second core receives the inter-core communication, the first core is powered off.
Of course, in the embodiment of the present invention, when an interrupt arrives, it may be determined whether the interrupt belongs to an interrupt of a "closed core". If so, executing the power-on operation of the closed core, and based on this, before the second core performs the power-off processing on the first core when receiving the inter-core communication, the method may also include:
the second core migrating a first interrupt source that the first core is responsible for processing to the second core; and marking the original home core of the first interrupt source.
The powering down processing of the first core by the second core after receiving the inter-core communication may include:
when detecting that an interrupt triggers a second interrupt source, the second core judges whether the second interrupt source belongs to the first core according to the original home core of the second interrupt source and the marked original home core of the first interrupt source; and when the first interrupt source belongs to the second core, performing power-on processing on the first core, and migrating the first interrupt source from the second core to the first core. For example, determining an original home core of the second interrupt source, matching the original home core of the second interrupt source with the original home core of the first interrupt source marked by the second core, and when matching, determining that the second interrupt source belongs to the first core; and when the first interrupt source belongs to the second core, performing power-on processing on the first core, and migrating the first interrupt source from the second core to the first core.
When the first core is powered off, whether other cores in the running state exist is judged firstly. If so, the power-down operation of the core is executed by the core. If not (indirectly indicating that the whole system is in the 'no matter what' state), the system-level standby operation (namely the system sleep flow) is executed according to the situation. That is, the method further comprises:
when the first core determines that no core in the running state exists in the multi-core, whether the multi-core processor is triggered to enter a system sleep process is determined according to the latest wake-up time of the first core and a preset time threshold.
The following describes the embodiments of the present invention in detail by way of examples, which include entering CPUidle flow and exiting CPUidle flow.
As shown in fig. 1, entering the cpuid flow may include:
step 1) a scheduling algorithm in the CPU determines that a first core (called coreA for short) needs to enter a CPUidle mode.
And 2) judging whether other cores in the running state exist in the current system.
And 3) if the core exists, selecting one second core (called coreB for short).
Step a) coreA sends an inter-core communication message to coreB, informing the coreB to power down the coreA.
Step b) coreA enters a wait-to-close (power down) state.
Step c) after receiving the message, coreB knows that coreA needs to power down.
Step d) coreB migrates the interrupt source (first interrupt source) for which coreA is responsible to process to coreB.
Step e) coreB marks the original home core (i.e., coreA) that was interrupted by the migration.
And f) powering down the coreA by the coreB, so that the coreA enters a core power-down state.
And 4) if not, indicating that the system has a need to enter a standby state.
And 5) judging whether the latest awakening time of the system is greater than a time threshold.
And 6) if the value is larger than the preset value, entering a system sleep process.
Step a) DDR enters into a self-refresh mode.
Step b) closing the system clock.
Step c) entering system dormancy.
Step 7) if not, coreA enters the wait for interrupt response mode.
As shown in fig. 2, exiting the cpuid flow may include:
step 1) triggering an interrupt by a certain interrupt source (second interrupt source).
And 2) judging whether the interrupt source is the migrated interrupt source in the step 3 d.
Step 3), if yes, the following steps:
step a) confirms the original home core of the interrupt source (i.e. coreA marked into cpuid flow 3 e).
Step b) power up the coreA.
Step c) migrates the migrated interrupt source back to coreA.
And d) recovering the normal working state of the coreA.
And 4) if not, performing normal interrupt processing.
In the embodiment, the core is actively closed when no matter what the core can do, and the core is awakened in real time to process the task when the interrupt comes, so that the defects in the prior art are ingeniously avoided, each core has an idle thread (kernel thread) in a running state, and the priority is lowest. The idle thread is executed when the other threads have no task requirements. The idle thread judges the power-down state of which level the idle thread enters according to the latest time of the future interrupt of the core, thereby skillfully meeting the requirements of low power consumption and response time.
Example two
An embodiment of the present invention provides a processor, where the processor includes a plurality of cores connected to each other;
the multi-core power-down processing system comprises a first core in an idle state, a second core and a first processor, wherein the first core is used for selecting the second core in a running state from the multi-cores and triggering the second core to execute power-down processing on the first core; the first core and the second core are different cores.
The first core may be specifically configured to send inter-core communication information to the second core, where the inter-core communication information is used to instruct the second core to perform power-down processing on the first core;
and the second core is used for powering down the first core when the inter-core communication is received.
When receiving the inter-core communication, the second core may further be configured to migrate a first interrupt source, which is responsible for processing by the first core, to the second core before performing power-down processing on the first core; and marking the original home core of the first interrupt source.
When the second core receives the inter-core communication, after the first core is powered off, the second core may be further configured to determine whether a second interrupt source belongs to the first core according to an original home core of the second interrupt source and a marked original home core of the first interrupt source when detecting that the second interrupt source triggers an interrupt; and when the first core belongs to the core, performing power-on processing on the first core.
The first core can be further configured to determine whether to trigger the multicore processor to enter a system sleep process according to the latest wake-up time of the first core and a preset time threshold when it is determined that no core in a running state exists in the multicore processor.
The embodiment of the invention is an embodiment of the device of the first embodiment, and can be referred to the first embodiment in concrete implementation, so that the invention has corresponding technical effects.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method for implementing an idle state low power mode of a multi-core processor, the method comprising:
a first core in an idle state selects a second core in a running state from the multi-cores, and triggers the second core to execute power-down processing on the first core; the first core and the second core are different cores.
2. The method of claim 1, wherein a first core of the multiple cores in the idle state selects a second core of the multiple cores in a running state from the multiple cores, triggering the second core to perform power down processing of the first core, comprises:
the first core sends inter-core communication information to the second core, wherein the inter-core communication information is used for instructing the second core to execute power-down processing on the first core;
and when the second core receives the inter-core communication, the first core is powered off.
3. The method of claim 2, wherein the second core, prior to powering down the first core upon receiving the inter-core communication, comprises:
the second core migrating a first interrupt source that the first core is responsible for processing to the second core; and marking the original home core of the first interrupt source.
4. The method of claim 3, wherein the second core, upon receiving the inter-core communication, after powering down the first core, comprises:
when detecting that a second interrupt source triggers interrupt, the second core judges whether the second interrupt source belongs to the first core according to the original home core of the second interrupt source and the marked original home core of the first interrupt source; and when the first core belongs to the core, performing power-on processing on the first core.
5. The method of any one of claims 1-4, further comprising:
when the first core determines that no core in the running state exists in the multi-core, whether the multi-core processor is triggered to enter a system sleep process is determined according to the latest wake-up time of the first core and a preset time threshold.
6. A processor, comprising a plurality of cores connected to each other;
the multi-core power-down processing system comprises a first core in an idle state, a second core and a first processor, wherein the first core is used for selecting the second core in a running state from the multi-cores and triggering the second core to execute power-down processing on the first core; the first core and the second core are different cores.
7. The processor of claim 6, wherein the first core is specifically configured to issue inter-core communication information to the second core, the inter-core communication information being configured to instruct the second core to perform power down processing on the first core;
and the second core is used for powering down the first core when the inter-core communication is received.
8. The processor of claim 7, wherein the second core, upon receiving the inter-core communication, is further to migrate a first interrupt source for which the first core is responsible to process to the second core prior to powering down the first core for processing; and marking the original home core of the first interrupt source.
9. The processor of claim 8, wherein the second core, after powering down the first core upon receiving the inter-core communication, is further configured to, upon detecting that a second interrupt source triggered an interrupt, determine whether the second interrupt source belongs to the first core based on an original home core of the second interrupt source and an original home core of the marked first interrupt source; and when the first core belongs to the core, performing power-on processing on the first core.
10. The processor of any one of claims 6 to 9, wherein the first core is further configured to determine whether to trigger the multicore processor to enter a system sleep process according to a latest wake-up time of the first core and a preset time threshold when it is determined that there is no core in a running state in the multicore processor.
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