WO2022057601A1

WO2022057601A1 - Method and apparatus for sending image data

Info

Publication number: WO2022057601A1
Application number: PCT/CN2021/115285
Authority: WO
Inventors: 汪永浪; 李煜; 王亮; 孙家亮; 高永胜; 余先宇
Original assignee: 华为技术有限公司
Priority date: 2020-09-18
Filing date: 2021-08-30
Publication date: 2022-03-24
Also published as: CN114205485B; CN114205485A

Abstract

The present application relates to the technical field of terminals. Provided are a method and apparatus for sending image data. The method comprises: when a screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, switching a horizontal timing for sending image data to a display module from a first horizontal timing to a second horizontal timing. The first screen refresh rate is greater than the second screen refresh rate; the first horizontal timing comprises a first horizontal blanking region and a first active display region; the second horizontal timing comprises a second horizontal blanking region and a second active display region; a PCLK period in the first horizontal timing is the same as a PCLK period in the second horizontal timing; the duration of the first active display region is the same as the duration of the second active display region; the duration of the first horizontal blanking region is less than the duration of the second horizontal blanking region. According to the technical solution provided in the present application, the phenomenon of abnormal display of an electronic device caused by decrease in screen refresh rate is reduced.

Description

Method and device for sending image data

This application claims the priority of the Chinese patent application with the application number 202010988832.4 and the application title "Method and Device for Sending Image Data", which was submitted to the State Intellectual Property Office on September 18, 2020, the entire contents of which are incorporated into this application by reference middle.

technical field

The present application relates to the field of terminal technologies, and in particular, to a method and apparatus for sending image data.

Background technique

At present, electronic devices such as mobile phones and tablet computers gradually begin to support multiple screen refresh rates. The electronic device can switch different screen refresh rates for different display scenarios. For example, when the electronic device is interacting with the user through the screen or displaying game content, it can be displayed at a higher screen refresh rate, while other The timing can be switched to a lower screen refresh rate for display.

In the prior art, an electronic device includes a system on chip (SOC) and a display module. The SOC can send the image data included in one frame of image to the display module line by line for display based on the horizontal time sequence. The horizontal timing includes multiple pixel clocks (PCLK). When the screen refresh rate is reduced, the SOC can increase the PCLK cycle (hereinafter referred to as the PCLK cycle), so that the time taken to transmit each line of images increases, and accordingly, the speed of sending and displaying each frame of image will also decrease.

However, since PCLK is the clock signal used to control the pixel output, changing the PCLK cycle will make the image data transmission unstable, resulting in abnormal display such as black screen or blurry screen when the screen refresh rate is switched.

SUMMARY OF THE INVENTION

In view of this, the present application provides a method and apparatus for transmitting image data.

In order to achieve the above purpose, in the first aspect, an embodiment of the present application provides a method for sending image data, which is characterized by comprising:

When the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, the horizontal timing sequence for sending image data to the display module is switched from the first horizontal timing sequence to the second horizontal timing sequence, and the first screen refresh rate is greater than the second screen refresh rate;

Wherein, the first horizontal timing sequence includes a first horizontal blank blanking area and a first effective display area;

a second horizontal blank blanking area and a second effective display area included in the second horizontal timing sequence;

The PCLK period in the first horizontal timing sequence is the same as the PCLK period in the second horizontal timing sequence;

The duration of the first effective display area is the same as the duration of the second effective display area;

The duration of the first horizontal blank blanking area is shorter than the duration of the second horizontal blank blanking zone.

Wherein, in the horizontal timing sequence, Hsync may indicate the arrival of one line of image data, and the line of image data includes a plurality of pixels. Hsync may be a pulse signal. When Hsync ends and passes through HBP, the line of image data starts to be transmitted, wherein each pixel may occupy one PCLK. There is no image data transmission between Hsync, HFP and HBP, so this time is called the horizontal blanking area, and there is image data transmission between adjacent HBP and HFP, this time can be called the effective display area.

It should be noted that the first horizontal timing sequence may be the horizontal timing sequence used by the electronic device to send image data to the display module when the screen refresh rate is the first screen refresh rate.

It should also be noted that the embodiments of the present application do not limit the triggering condition or method for switching the screen refresh rate. For example, the electronic device may determine whether a user operation is received based on any window based on the interface manager 212, and if so, determine the higher screen refresh rate as the second screen refresh rate, otherwise determine the lower screen refresh rate as the first screen refresh rate Second screen refresh rate.

In the embodiment of the present application, when the screen refresh rate is switched from a relatively large first screen refresh rate to a relatively small second screen refresh rate, the timing of sending image data by the display module can be switched from the first horizontal timing to the second Two-level timing. The first horizontal timing sequence includes a first horizontal blank blanking area and a first effective display area, and the second horizontal timing sequence includes a second horizontal blank blanking area and a second effective display area. Since the PCLK cycle in the first horizontal timing sequence is the same as the PCLK cycle included in the second horizontal timing sequence, the duration of the first effective display area is the same as the duration of the second effective display area, and the duration of the first horizontal blanking area is smaller than that of the second The duration of the horizontal blanking area, so when the screen refresh rate is reduced, you can increase the horizontal blanking area while keeping the PCLK cycle unchanged, thereby increasing the duration of the horizontal sequence, reducing the electronic equipment due to screen refresh. The phenomenon that the display rate is reduced and the display abnormality occurs, and the reliability of transmitting image data and displaying images based on the image data is improved.

Optionally, the first horizontal blank blanking region includes a first horizontal front porch (HFP), a first horizontal synchronization signal (Hsync) and a first horizontal back porch (HBP) , the second horizontal blank blanking region includes a second HFP, a second Hsync and a second HBP;

The duration of the first HFP is shorter than the duration of the second HFP; and/or the duration of the first Hsync is shorter than the duration of the second Hsync; and/or the duration of the first HBP is shorter than the duration of the first HFP Duration of the second HBP.

For example, the duration of the first HFP, the first Hsync and the first HBP in the first horizontal timing sequence are all 2 PCLK cycles, the duration of the first horizontal blanking area is 6 PCLK cycles, and the duration of the first effective display area is 6 PCLK cycles. for 4 PCLK cycles. The second horizontal timing sequence may include the following four possible implementation manners: manner 1, the durations of the second HFP, the second Hsync and the second HBP are respectively 1 longer than the durations of the first HFP, the first Hsync and the first HBP PCLK cycle, the duration of the second horizontal timing sequence is 3 PCLK cycles longer than the duration of the first horizontal timing sequence, and the duration of the first effective display area is the same as the duration of the second effective display area; The duration of HFP is 3 PCLK cycles longer, the first Hsync, the first HBP and the first effective display area are respectively the same as the duration of the second Hsync, the second HBP and the second effective display area; Mode 3: The duration of the second Hsync 3 PCLK cycles longer than the duration of the first Hsync, the first HFP, the first HBP and the first effective display area are respectively the same as the duration of the second HFP, the second HBP and the second effective display area; The duration of the HBP is 3 PCLKs longer than the duration of the first HBP, and the durations of the first HFP, the first Hsync and the first effective display area are respectively the same as the durations of the second HFP, the second Hsync and the second effective display area.

Optionally, before the switching of the horizontal timing sequence for sending image data to the display module from the first horizontal timing sequence to the second horizontal timing sequence, the method further includes:

based on the first screen refresh rate and the second screen refresh rate, determining an amount of screen refresh rate variation;

Determine the horizontal timing variation based on the screen refresh rate variation, where the horizontal timing variation is N PCLK cycles;

Based on the horizontal timing change amount, the first HFP, the first Hsync and the first HBP are respectively increased by M, P and Q PCLK cycles to obtain the second HFP, the second Hsync and the first HBP. 2HBP;

where N, M, P and Q are integers, and M+P+Q=N.

In some embodiments, based on the second screen refresh rate, the corresponding horizontal timing sequence may be obtained from the corresponding relationship between the screen refresh rate and the horizontal timing sequence as the second horizontal timing sequence.

In some embodiments, when the first screen refresh rate is lower than the second screen refresh rate, that is, when the screen refresh rate is increased, the duration of the first horizontal blanking area may be greater than the duration of the second horizontal blanking area: first HFP The duration of the first HBP is greater than the duration of the second HFP; and/or the duration of the first Hsync is greater than the duration of the second Hsync; and/or the duration of the first HBP is greater than the duration of the second HBP.

Optionally, also include:

When the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, determining a first power consumption parameter corresponding to the second screen refresh rate;

Setting the current power consumption parameter of the display controller DSS as the first power consumption parameter, the power consumption indicated by the first power consumption parameter is lower than that indicated by the second power consumption parameter corresponding to the first screen refresh rate power consumption.

Optionally, also include:

acquiring image composition information corresponding to the image data, the image composition information including at least one of the number of layers and the total number of pixels in the layers;

The determining of the first power consumption parameter corresponding to the second screen refresh rate includes:

The second power consumption parameter is determined based on the second screen refresh rate and the image composition information.

It should be noted that, in practical applications, the image synthesis information may also include other types of information, such as the position of each layer.

Optionally, the current power consumption parameter of the display controller (display subsystem, DSS) is set as the first power consumption parameter, including at least one of the following:

When the second power consumption parameter includes a first physical clock, setting the physical clock of the DSS as the first physical clock;

When the second power consumption parameter includes a first voltage, the voltage of the DSS is set to the first voltage.

Because when the screen refresh rate is higher, the number of layers is larger, and the total number of pixels in the layer is larger, the speed of sending image data to the display module is also faster, and the corresponding power consumption is also larger. Therefore, when the screen is When the refresh rate changes, the power consumption parameter of the DSS can be switched from the second power consumption parameter to the first power consumption parameter, so as to save power consumption when the screen refresh rate decreases, and to reliably send image data when the screen refresh rate increases .

In some embodiments, based on the second screen refresh rate, the corresponding power consumption parameter may be obtained from the correspondence between the screen refresh rate and the power consumption parameter as the first power consumption parameter. In some embodiments, the screen refresh rate change amount may be determined based on the first screen refresh rate and the second screen refresh rate, and based on the screen refresh rate change amount, from the correspondence between the screen refresh rate change amount and the power consumption parameter change amount In the relationship, the corresponding power consumption parameter variation is obtained, and the first power consumption parameter is determined based on the power consumption parameter variation and the second power consumption parameter. In some embodiments, the corresponding power consumption parameter may be obtained from the correspondence between the image composition information and the power consumption parameter based on the image composition information of the current frame image, and determined as the first power consumption parameter.

In some embodiments, when the second screen refresh rate is greater than the first screen refresh rate, the power consumption indicated by the first power consumption parameter may be greater than the power consumption indicated by the second power consumption parameter.

Optionally, also include:

Get at least one layer;

The at least one layer is synthesized to obtain the image data.

Optionally, also include:

A screen refresh rate switching notification is sent to the display module, where the screen refresh rate switching notification is used to instruct the current screen refresh rate to be switched to the second screen refresh rate.

In a second aspect, an embodiment of the present application provides an apparatus for sending image data, including:

The processing module is configured to switch the horizontal timing sequence for sending image data to the display module from the first horizontal timing sequence to the second horizontal timing sequence when the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate. A screen refresh rate is greater than the second screen refresh rate;

Optionally, the first horizontal blank blanking area includes a first HFP, a first Hsync and a first HBP, and the second horizontal blank blanking area includes a second HFP, a second Hsync and a second HBP;

Optionally, the processing module is also used for:

where N, M, P and Q are integers, and M+P+Q=N.

Optionally, the processing module is also used for:

Set the current power consumption parameter of the DSS as the first power consumption parameter, and the power consumption indicated by the first power consumption parameter is lower than the power consumption indicated by the second power consumption parameter corresponding to the first screen refresh rate .

Optionally, the processing module is also used for:

for acquiring image synthesis information corresponding to the image data, the image synthesis information including at least one of the number of layers and the total number of pixels in the layers;

Optionally, the processing module is further configured to perform at least one of the following operations:

Optionally, the processing module is also used for:

Get at least one layer;

The at least one layer is synthesized to obtain the image data.

Optionally, it also includes a sending module for:

In a third aspect, an embodiment of the present application provides an electronic device, including: a memory and a processor, where the memory is used to store a computer program; the processor is used to execute the method described in any one of the first aspects when the computer program is invoked.

In a fourth aspect, an embodiment of the present application provides a chip system, the chip system includes a processor, the processor is coupled to a memory, and the processor executes a computer program stored in the memory, so as to implement any one of the above first aspects. one of the methods described.

Wherein, the chip system may be a single chip or a chip module composed of multiple chips.

In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the method described in any one of the foregoing first aspects.

In a sixth aspect, an embodiment of the present application provides a computer program product that, when the computer program product runs on an electronic device, causes the electronic device to execute the method described in any one of the first aspects above.

It can be understood that, for the beneficial effects of the foregoing second aspect to the sixth aspect, reference may be made to the relevant descriptions in the foregoing first aspect, and details are not described herein again.

Description of drawings

1 is a schematic structural diagram of an electronic device provided by an embodiment of the application;

2 is a block diagram of a software structure of an electronic device provided by an embodiment of the present application;

3 is an abstract diagram of a MIPI timing sequence provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of a vertical timing sequence provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a horizontal sequence provided by an embodiment of the present application;

6 is a sequence diagram of a method for sending image data provided by an embodiment of the present application;

FIG. 7 is another schematic diagram of a horizontal timing sequence provided by an embodiment of the present application;

FIG. 8 is another schematic diagram of a horizontal sequence provided by an embodiment of the present application;

FIG. 9 is another schematic diagram of a horizontal timing sequence provided by an embodiment of the present application;

FIG. 10 is another schematic diagram of a horizontal timing sequence provided by an embodiment of the present application;

FIG. 11 is a schematic structural diagram of an apparatus for sending image data according to an embodiment of the application;

FIG. 12 is a schematic structural diagram of another electronic device provided by an embodiment of the present application.

detailed description

The display method provided by the embodiments of the present application can be applied to mobile phones, tablet computers, wearable devices, in-vehicle devices, augmented reality (AR)/virtual reality (VR) devices, notebook computers, super mobile personal computers ( On electronic devices such as ultra-mobile personal computer, UMPC), netbook, personal digital assistant (personal digital assistant, PDA), the embodiment of the present application does not impose any restrictions on the specific type of the electronic device.

Please refer to FIG. 1 , which is a schematic structural diagram of an electronic device 100 provided by the present application. The electronic device 100 may include an SOC 110 and a liquid crystal display (LCD) display module (LCD module, LCM) 120 .

The SOC 110 may include an application processor (application processor, AP) 111 , a DSS 112 and a mobile industry processor interface (mobile industry processor interface, MIPI) 113 .

AP111 can be an ultra-large-scale integrated circuit that expands audio and video functions and dedicated interfaces on the basis of a central processing unit (CPU), and can be used to process multimedia data such as images and music, including photography, music playback, radio, radio, video playback, etc.

The DSS 112 can be used to obtain image data from the memory (not shown in FIG. 1 ) of the SOC 110 , and send the image data to the DDIC 122 in the LCM 120 through the MIPI interface 113 according to the MIPI timing sequence conforming to the MIPI protocol.

The MIPI interface 113 includes a camera interface, a display interface, a radio frequency interface, a microphone interface and other interfaces. Among them, the display interface can be used for the above-mentioned communication between the DSS112 and the DDIC122, including sending image data through the MIPI timing sequence.

The MIPI timing sequence is used to indicate the time sequence of sending the image data of one frame of image, so that the DDIC 122 receives the image data in an orderly manner and controls the display panel 121 to display the image.

In some embodiments, MIPI interface 113 may be integrated in DSS 112 .

The LCM 120 may include a display panel 121 and a display drive integrated circuit (DDIC) 122 . The DDIC 122 can be used to receive image data sent from the DSS 112 according to a specific timing, and control the display panel 121 to control the corresponding liquid crystal molecules based on each pixel in the image data, so that the display panel 121 displays the image data. In addition, the DDIC 122 may also store the image data in an image register (graphics random-access memory, GRAM) 123 .

The display panel 121 may be used to display image data. The display panel 121 can be an LCD panel, including a twisted nematic (TN) type panel, a vertical nematic (TA) type panel, an in-plane switching (IPS) type panel, a continuous firework-like arrangement (continuous pinwheel alignment, CPA) type panel or advanced super dimension switch (advanced super dimension switch, ADSDS) type panel. Of course, in practical applications, the display panel 121 may also be other types of panels, and the embodiment of the present application does not specifically limit the type of the display panel 121 .

It should be noted that the LCM 120 may further include more components, such as at least one of a connector, a support, a peripheral circuit and a backlight.

In addition, in practical applications, the LCM 120 in the electronic device 100 may be replaced with other display modules, and the embodiment of the present application does not specifically limit the type of the display module.

It can be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100 . In other embodiments of the present application, the electronic device 100 may include more or less components than shown, or combine some components, or separate some components, or arrange different components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware. For example, in some embodiments, the electronic device 100 may further include an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, an antenna, a mobile communication module, At least one of a wireless communication module, an audio module, a speaker, a receiver, a microphone, an earphone jack, a sensor module, a button, a motor, an indicator, a camera, a display screen, and a subscriber identification module (SIM) card interface.

Please refer to FIG. 2 , which is a software structural block diagram of an electronic device 100 provided by an embodiment of the present application.

The layered architecture divides the software into several layers, and each layer has a clear role and division of labor. Layers communicate with each other through software interfaces.

As shown in FIG. 2 , the electronic device 100 includes a display framework layer 210, a hardware abstraction layer 220, a DSS driver layer 230 and an LCD driver layer 240, wherein the display framework layer 210 and the hardware abstraction layer 220 may be located at AP111 in FIG. 1, DSS The driving layer 230 may be located at the DSS 112 in FIG. 1 , and the LCD driving layer 240 may be located at the DDIC 122 in FIG. 1 .

The display frame layer 210 may include a window manager (window manager) 211 and an interface manager (surface flinger) 212. The display panel 121 of the electronic device 100 may display a plurality of windows (window, an abstract class related to display), such as a dialog box, a status bar and a floating window, and the content in each window may serve as a surface. The window manager 211 is an interface class, which defines several interfaces to manage the window, including judging whether there is a status bar, locking the screen, and capturing the screen. The interface manager 212 can obtain the interface in each window, thereby obtaining at least one layer, and send the obtained at least one layer and image composition information to the hardware abstraction layer 220, wherein each layer can include one interface. In addition, the interface manager 212 can also detect whether the corresponding window receives a user operation.

The image synthesis information may include at least one of the number of layers and the total number of pixels in the layers. Of course, in practical applications, the image synthesis information may also include more information, such as the position of each layer.

The hardware abstraction layer 220 may include an image synthesis module 221 and a screen refresh rate switching module 222 . The image synthesis module 221 may be configured to receive at least one layer and image synthesis information sent by the interface manager 212, and according to the image synthesis information, synthesize the at least one layer into a frame of image. The screen refresh rate switching module 222 can determine the current screen refresh rate according to the preset screen refresh rate policy. screen refresh rate.

In some embodiments, the hardware abstraction layer 220 may also include a power consumption module 223 . When the screen refresh rate is reduced, the DSS112 in Figure 1 can reduce the rate of sending image data to the DDIC122 through the MIPI interface 113, and the DSS112 can reduce the power consumption when the rate of sending image data is reduced; conversely, when the screen refresh rate is increased , the DSS112 can increase the rate of sending image data to the DDIC122 through the MIPI interface 113, and the DSS112 can increase the power consumption when increasing the rate of sending image data. Therefore, in order to flexibly set the power consumption parameters of the DSS112 to reduce or increase power consumption, the power consumption module 223 may determine the power consumption parameters of the DSS112 according to the current screen refresh rate, such as at least one of the physical clock and voltage of the DSS112.

The DSS driving layer 230 may include a MIPI timing control module 231 . The MIPI timing control module 231 can determine the MIPI timing for sending image data to the LCD layer 240 according to the current screen refresh rate, and according to the MIPI timing, send the image data of the frame of image synthesized by the hardware abstraction layer 220 to the LCD layer Display unit 241 in 240.

In some embodiments, the DSS driving layer 230 may further include a clock control module 232 and a voltage control module 233 . The clock control module 232 may set the current physical clock of the DSS 112 as the physical clock determined by the power consumption module 223 . The voltage control module 233 may set the current voltage of the DSS 112 to the voltage determined by the power consumption module 223 .

The LCD driving layer 240 may include the display unit 241 . The display unit 241 can be used to control the display panel 121 in FIG. 1 to display based on the received image data, including controlling the liquid crystal molecules corresponding to each pixel to display the pixel.

It should be noted that the electronic device 100 may also include more or less layers, and each layer may include more or less modules. For example, in the hardware abstraction layer 220, the image synthesis module 221 can be switched with the screen refresh rate Module 222 is integrated into one module.

Please refer to FIG. 3 , which is an abstract diagram of a MIPI timing sequence provided by an embodiment of the present application. MIPI timing can be used to indicate the timing of transmitting image data, including vertical timing and horizontal timing. In the vertical timing, the vertical synchronization signal (vertical synchronization, Vsync), can indicate the arrival of a new frame of image, before Vsync, including vertical front porch (vertical front porch, VFP), after Vsync, including vertical trailing edge ( vertical back porch, VBP). The image data of a certain frame of image is between adjacent VBPs and VFPs, and the image data will be transmitted by the SOC 110 to the LCM 120 for display line by line. In horizontal timing, Hsync may indicate the arrival of a line of image data, the line of image data including a plurality of pixels. Before each Hsync, one HFP may be included, after each Hsync, one HBP may be included, and between adjacent HBPs and HFPs, is the line of image data. As can be seen from FIG. 3 , in the process of displaying one frame of image, in addition to the time for actually transmitting image data, it also includes the time occupied by Vsync, VFP, VBP, Hsync, HFP and HBP.

Please refer to FIG. 4 , which is a schematic diagram of a vertical timing sequence provided by an embodiment of the present application. As shown in Figure 4, when a frame of image is transmitted, VFP is first passed, and then the frame of image is instructed to start transmission through Vsync. Vsync may be a pulse signal, and when Vsync ends and VBP passes, the image data of one frame of image starts to be transmitted, wherein each line of image data may be transmitted through a horizontal timing sequence. And it can be seen from Figure 4 that during Vsync, VFP and VBP, there is no image data transmission. This period can be called the vertical blank blanking area, and there is image data transmission between adjacent VFP and VBP. Therefore, The time between adjacent VFPs and VBPs may be referred to as an active display area.

Please refer to FIG. 5 , which is a schematic diagram of a horizontal timing sequence provided by an embodiment of the present application. As shown in FIG. 5 , when a line of image data is transmitted, the HFP is first passed, and then the line of image data is instructed to start transmission through Hsync. Hsync may be a pulse signal. When Hsync ends and passes through HBP, the line of image data starts to be transmitted, wherein each pixel may occupy one PCLK. And it can be seen from Figure 5 that there is no image data transmission between Hsync, HFP and HBP, so this period is called the horizontal blanking area, and there is image data transmission between adjacent HBP and HFP. , this period of time can be called the effective display area.

FIG. 4 and FIG. 5 respectively explain the vertical timing sequence and the horizontal timing sequence of the DSS112 transmitting image data. Correspondingly, the DDIC 122 can receive the image data according to the vertical timing sequence and the horizontal timing sequence and control the display panel 121 to display.

It should be noted that Vsync, VFP, VBP, Hsync, HFP, HBP and PCLK can be generated by the DSS 112 in the aforementioned FIG. 1 . 4 and 5, the durations of Hsync, HFP, and HBP may be several PCLK cycles, and the durations of Vsync, VFP, and VBP may be several horizontal time sequences.

Still taking Figure 4 and Figure 5 as examples, it can be seen from Figure 4 that the currently transmitted image includes 7 lines of image data. From Figure 5, it can be seen that each line of image data includes 4 pixels. It can be seen that the image data includes 7*4 of pixels. It should be noted that the embodiments of the present application only take FIG. 4 and FIG. 5 as examples to describe the MIPI timing sequence for transmitting image data, and do not limit the display panel 121 of the image and the resolution of the image. In practical applications, the panel 121 and the image can be of larger or smaller resolution, for example, the resolution can be 1366*768.

At present, electronic devices can support multiple screen refresh rates and switch the screen refresh rates. In some embodiments, when the SOC 110 sends image data to the LCM 120, the PCLK period can be increased, so that each line of image data is transmitted in a longer time, and the image data of each frame of image will be transmitted more slowly. It also achieves the purpose of reducing the screen refresh rate. In this manner, the horizontal timing sequence is similar to the horizontal timing sequence shown in FIG. 5 , which is only equivalent to extending the horizontal timing sequence shown in FIG. 5 laterally. However, it can be seen from the above that PCLK is the clock signal for transmitting pixels. Changing the PCL cycle will make the image data transmission unstable, which will lead to abnormal display phenomena such as black screen or blurred screen when the screen refresh rate is switched.

To solve the above problems, the present application proposes another method for sending image data. In the embodiment of the present application, when the screen refresh rate is switched from a relatively large first screen refresh rate to a relatively small second screen refresh rate, the timing of sending image data by the display module can be switched from the first horizontal timing to the second Two-level timing. The first horizontal timing sequence includes a first horizontal blank blanking area and a first effective display area, and the second horizontal timing sequence includes a second horizontal blank blanking area and a second effective display area. Since the PCLK cycle in the first horizontal timing sequence is the same as the PCLK cycle included in the second horizontal timing sequence, the duration of the first effective display area is the same as the duration of the second effective display area, and the duration of the first horizontal blanking area is smaller than that of the second The duration of the horizontal blanking area, so when the screen refresh rate is reduced, you can increase the horizontal blanking area while keeping the PCLK cycle unchanged, thereby increasing the duration of the horizontal sequence, reducing the electronic equipment due to screen refresh. The phenomenon that the display rate is reduced and the display abnormality occurs, and the reliability of transmitting image data and displaying images based on the image data is improved.

The technical solutions of the present application will be described in detail below with specific examples. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

Please refer to FIG. 6 , which is a flowchart of a method for sending image data provided by an embodiment of the present application. It should be noted that the method is not limited to the specific sequence shown in FIG. 6 and the following, and it should be understood that in other embodiments, the sequence of some steps of the method may be exchanged according to actual needs, or some steps of the method may be exchanged. It can also be omitted or deleted. The method includes the following steps:

S601 , the interface manager 212 acquires at least one layer and image composition information from the window manager 211 .

In order to facilitate the generation of images displayed in subsequent screens, the interface manager 212 can obtain the interface from at least one window manager 211 respectively when receiving the Vsync to obtain at least one layer, and can also obtain information such as the number of layers and the at least one layer. Image composition information such as the total number of pixels in the layer.

It should be noted that, in practical applications, the interface manager 212 may also acquire at least one layer and image composition information from the window manager 211 based on other trigger conditions. The embodiments of the present application do not specifically limit the triggering conditions for acquiring at least one layer and image synthesis information.

S602, the interface manager 212 sends the at least one layer and the image composition information to the image composition module 221.

Optionally, the interface manager 212 may send the image composition information to the power consumption module 223 .

S603, the image synthesizing module 221 synthesizes the at least one layer into one frame of image according to the image synthesizing information.

Wherein, when the image synthesis information includes the number of layers and the total number of pixels of the layers, the image synthesis module 221 may splicing and stacking the layers of the number of layers based on the total number of pixels of the layers, so as to obtain A frame of image, which is the current image to be displayed. Of course, if the layer synthesis information further includes the positions of the layers, the image synthesis module 221 can also synthesize the layers based on the positions of the layers.

It should be noted that, in practical applications, the image synthesis module 221 may synthesize the at least one layer into one frame of image according to the image synthesis information in other ways, or, in other embodiments, may be managed by the interface The device 212 synthesizes the at least one layer into a frame of image according to the image synthesis information, and the embodiment of the present application does not specifically limit the manner of synthesizing the at least one layer into a frame of image according to the image synthesis information.

S604, the screen refresh rate switching module 222 determines the current second screen refresh rate. After that, S605-S606 and S607-S609 can be executed respectively.

Since the display panel 121 of the electronic device 100 can support multiple screen refresh rates and switch the screen refresh rates, before displaying a new frame of image, the current second screen refresh rate can be determined to ensure that the subsequent display panel 121 has the The image data displays the image correctly.

Optionally, the screen refresh rate switching module 222 may determine the current second screen refresh rate when receiving Vsync or when determining that the image synthesis module 221 has synthesized an image.

Optionally, the display panel 121 of the electronic device 100 may support two screen refresh rates. The screen refresh rate switching module 222 may determine whether a user operation is received based on any window based on the interface manager 212, and if so, determine the higher screen refresh rate as the second screen refresh rate, otherwise determine the lower screen refresh rate for the second screen refresh rate. Of course, in practical applications, the electronic device 100 may support more screen refresh rates, then the screen refresh rate switching module 222 may determine the second screen refresh rate in a similar or more complex manner, such as The frequency of the operation is determined, and the screen refresh rate corresponding to the frequency is determined as the second screen refresh rate.

It should be noted that the screen refresh rate switching module 222 may also determine the second screen refresh rate in other ways based on other trigger conditions. The embodiments of the present application do not specify the trigger conditions and methods for determining the second screen refresh rate. limited.

Optionally, the screen refresh rate switching module 222 may send the second screen refresh rate to the power consumption module 223 .

S605, the power consumption module 223 determines the current first power consumption parameter.

When the screen refresh rate is higher, the number of layers is larger, and the total number of pixels in the layer is larger, the subsequent DSS112 needs to send image data to the DDIC122 faster, and the corresponding power consumption will be larger, so in order to facilitate the subsequent The power consumption parameter of the DSS 112 is adjusted in time to ensure the reliability of sending image data, and the power consumption module 223 can determine the current second power consumption parameter.

Optionally, the second power consumption parameter may include at least one of the second physical clock and the second voltage of the DSS 112 .

Optionally, based on the second screen refresh rate, a corresponding power consumption parameter may be obtained from the correspondence between the screen refresh rate and the power consumption parameter as the first power consumption parameter. Please refer to Table 1 below, the refresh rate of the second screen is 90 Hz (Hertz), then the clock 2 corresponding to 90 Hz can be obtained as the first physical clock, and the voltage 2 corresponding to 90 Hz can be obtained as the first voltage.

Table 1

In addition, in other embodiments, the power consumption module 223 may determine the first screen refresh rate and the second power consumption parameter corresponding to the image of the previous frame adjacent to the image to be displayed. Based on the first screen refresh rate and the second screen refresh rate, determine the screen refresh rate variation, and based on the screen refresh rate variation, obtain the corresponding power from the correspondence between the screen refresh rate variation and the power consumption parameter variation The variation of the power consumption parameter is determined, and the first power consumption parameter is determined based on the variation of the power consumption parameter and the second power consumption parameter. Wherein, when the refresh rate of the second screen is lower than the refresh rate of the first screen, the power consumption indicated by the first power consumption parameter may be smaller than the power consumption indicated by the second power consumption parameter, for example, the second power consumption parameter may include the second physical at least one of the clock and the second voltage, the frequency of the first physical clock may be lower than the frequency of the second physical clock, and the first voltage may be lower than the second voltage. Certainly, when the refresh rate of the second screen is greater than the refresh rate of the first screen, the power consumption indicated by the first power consumption parameter may be greater than the power consumption indicated by the second power consumption parameter.

Optionally, based on the image composition information of the current frame image, the corresponding power consumption parameter may be obtained from the correspondence between the image composition information and the power consumption parameter, and determined as the first power consumption parameter. Please refer to Table 2 below, the image synthesis information includes the number of layers and the total number of pixels in the layer, and the power consumption parameters include the physical clock and voltage of the DSS112. If the image synthesis information corresponding to the current frame image includes 4 layers and the total number of pixels in the layers is 400,000 pixels, the corresponding clock 3 is obtained as the first physical clock, and the corresponding voltage 3 is obtained as the first voltage.

Table 2

It should be noted that, when the first power consumption parameter is determined based on the second screen refresh rate and the image composition information, the parameters between the screen refresh rate, the image composition information and the power consumption parameter may be determined based on the second screen refresh rate and the image composition information. In the corresponding relationship, the corresponding power consumption parameter is obtained as the first power consumption parameter; or, when the first power consumption parameter is determined based on the second screen refresh rate and image composition information, the second screen refresh rate and the image composition information can be determined based on the second screen refresh rate and image composition respectively. The information determines the power consumption parameter, and obtains the average value of the two power consumption parameters as the first power consumption parameter.

It should also be noted that the above-mentioned correspondence between the screen refresh rate and the power consumption parameter, the correspondence between the image synthesis information and the power consumption parameter, or the correspondence between the screen refresh rate, the image synthesis information and the power consumption parameter, It can be obtained by setting in advance.

In some embodiments, the power consumption module 223 may send a physical clock control notification to the clock control module 232, the physical clock control notification carrying the first physical clock; and/or the power consumption module 223 may send a voltage control notification to the voltage control module 233 notification, the voltage control notification carries the first voltage.

S606, the clock control module 232 sets the current physical clock of the DSS 112 as the first physical clock, and/or the voltage control module 233 sets the current voltage of the DSS 112 as the first voltage.

When the screen refresh rate changes, DSS112 can send image data to DDIC122 according to the speed corresponding to the screen refresh rate. The faster the speed of sending image data, the higher the power consumption of DSS112. Matching the refresh rate includes reducing the power consumption of the DSS112 in time when the screen refresh rate decreases, and the clock control module 232 and the voltage control module 233 can respectively control the current physical clock and voltage of the DSS112.

In addition, in other embodiments, the power consumption parameter of the DSS 112 may not be adjusted, that is, S605 and S606 are optional steps.

S607, the MIPI timing control module 231 determines the second horizontal timing corresponding to the second screen refresh.

As can be seen from the foregoing, the DSS 112 transmits the image data line by line to the DDIC 122 through the horizontal timing sequence. Therefore, in order to ensure that the DDIC 122 correctly receives and displays the image, a second horizontal timing corresponding to the second screen refresh rate may be determined.

The second horizontal timing sequence may include a second horizontal blank blanking area and a second effective display area, and the second horizontal blank blanking area may include a second HFP, a second Hsync, and a second HBP. And since the second effective display area is used for each row of pixels in the actual transmission image, and for the same electronic device 100, the width of the display panel 121 is constant, then for different screen refresh rates, the horizontal timing sequence includes: The time duration occupied by the effective display area may be the same. Correspondingly, in S607, determining the second horizontal timing sequence may include determining the second HFP, the second Hsync, and the second HBP.

In addition, in some embodiments, the MIPI timing control module 231 may determine the first screen refresh rate when the image data corresponding to the previous frame image adjacent to the currently to-be-displayed image is sent. The MIPI timing control module 231 may determine the second horizontal timing sequence corresponding to the second screen refresh rate when it is determined that the first screen refresh rate is different from the second screen refresh rate, that is, the current screen refresh rate needs to be switched.

Among them, the PCLK cycle in the second horizontal sequence can be the same as the PCLK cycle in the first horizontal sequence, that is, the PCLK cycle does not need to be changed when the screen refresh rate is switched, which reduces abnormal display phenomena such as black screen and blurred screen, and improves the sending of images. The reliability of the data and subsequent display images based on this image data. The duration of the first effective display area may be the same as the duration of the second effective display area. When the refresh rate of the first screen is greater than the refresh rate of the second screen, that is, when the refresh rate of the screen is reduced, the duration of the first horizontal blanking area can be shorter than that of the second horizontal blanking area: the duration of the first HFP is shorter than that of the second HFP and/or, the duration of the first Hsync is shorter than the duration of the second Hsync; and/or, the duration of the first HBP is shorter than the duration of the second HBP. When the refresh rate of the first screen is lower than the refresh rate of the second screen, that is, when the refresh rate of the screen is increased, the duration of the first horizontal blanking area can be longer than that of the second horizontal blanking area: the duration of the first HFP is longer than that of the second HFP and/or, the duration of the first Hsync is greater than the duration of the second Hsync; and/or the duration of the first HBP is greater than the duration of the second HBP.

Optionally, the MIPI timing control module 231 may obtain the corresponding horizontal timing as the second horizontal timing from the correspondence between the screen refresh rate and the horizontal timing based on the second screen refresh rate. Please refer to Table 3 below, the refresh rate of the second screen is 90Hz, then the corresponding second horizontal timing sequence including the second HFP, the second Hsync and the second HBP can be all 3 PCLK cycles, as shown in Figure 7 Show.

table 3

Optionally, the MIPI timing control module 231 may acquire a first horizontal timing sequence corresponding to the first screen refresh, wherein the first horizontal timing sequence includes a first horizontal blank blanking area and a first effective display area, and the first horizontal blank blanking The zone includes a first HFP, a first Hsync, and a first HBP. Based on the first screen refresh rate and the second screen refresh rate, a screen refresh rate variation is determined, and a horizontal timing variation is determined based on the screen refresh rate variation, where the horizontal timing variation includes N PCLK cycles. Wherein, the amount of screen refresh rate variation = the first screen refresh rate - the second screen refresh rate. If the change of the screen refresh rate is greater than 0, it means that the screen refresh rate is reduced. Based on the horizontal timing change, the first HFP, the first Hsync and the first HBP can be increased by M, P and Q PCLK cycles, respectively, to obtain The second HFP, the second Hsync, and the second HBP, where N, M, P, and Q are integers, and M+P+Q=N. That is, the N PCLK cycles are inserted into at least one of the first HFP, the first Hsync, and the first HBP, thereby increasing the duration of the horizontal blank blanking region. Similarly, if the change in the screen refresh rate is less than 0, it means that the screen refresh rate is increased, and the first HFP, the first Hsync and the first HBP can be reduced by M, P and Q PCLK cycles respectively based on the horizontal timing change. , the second HFP, the second Hsync and the second HBP are obtained, that is, N PCLK cycles are extracted from at least one of the first HFP, the first Hsync and the first HBP, thereby reducing the duration of the horizontal blanking area.

For example, the acquired first horizontal timing sequence is as shown in FIG. 5 above, the durations of the first HFP, the first Hsync and the first HBP are all 2 PCLK cycles, and the duration of the first horizontal blanking area is 6 PCLKs cycle, the duration of the first effective display area is 4 PCLK cycles. Compared with Fig. 7, it can be seen that the duration of the second HFP, the second Hsync and the second HBP is 1 PCLK cycle longer than the duration of the first HFP, the first Hsync and the first HBP respectively, and the duration of the second horizontal sequence is longer than that of the first HFP, the first Hsync and the first HBP respectively. The duration of the horizontal timing sequence is 3 PCLK cycles longer, and the duration of the first effective display area is the same as the duration of the second effective display area. Alternatively, please refer to FIG. 8 to FIG. 10 , which respectively provide a schematic diagram of a horizontal timing sequence. In the second horizontal timing sequence shown in FIG. 8 , the duration of the second HFP is 3 PCLK cycles longer than the duration of the first HFP, and the first Hsync, the first HBP and the first effective display area are The second HBP and the second active display area have the same duration. In the second horizontal timing sequence shown in FIG. 9 , the duration of the second Hsync is longer than the duration of the first Hsync by 3 PCLK cycles, and the first HFP, the first HBP and the first effective display area are the same as the second HFP, The second HBP and the second active display area have the same duration. In the second horizontal timing sequence shown in FIG. 10 , the duration of the second HBP is 3 PCLKs longer than the duration of the first HBP, and the first HFP, the first Hsync and the first effective display area are The duration of the second Hsync and the second effective display area is the same.

S608, the MIPI timing control module 231 sends image data to the display unit 241 based on the second horizontal timing.

Wherein, the MIPI timing control module 231 may, based on the MIPI interface 113, start from the first line of image data of the image, and based on the first horizontal timing, send a plurality of pixels included in the first line of image data to the display unit 241, and then, based on the first line of image data, to the display unit 241 In the horizontal timing sequence, the plurality of pixels included in the image data of the second line are sent to the display unit 241, . . . , until the plurality of pixels included in the image data of the next line are sent.

Optionally, the MIPI timing control module 231 may also send a screen refresh rate switching notification to the display unit 241, where the screen refresh rate switching notification is used to notify the display unit 241 to switch the current screen refresh rate to the second screen refresh rate.

S609, the display unit 241 displays an image based on the received image data.

The display unit 241 may receive a plurality of pixels included in the first line of image data based on the first horizontal timing sequence, and control the display panel 121 to display the first line of image data, . . . , until the last line of image data is displayed, the display panel 121 may completely display the image corresponding to the second image data.

It should be noted that the steps of S605-S606 for setting the current physical clock and voltage of the DSS112 and the steps of S607-S609 for transmitting and displaying image data based on the current screen refresh rate can be performed independently.

Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. Module completion, that is, dividing the internal structure of the device into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment may be integrated in one processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit, and the above-mentioned integrated units may adopt hardware. It can also be realized in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present application. For the specific working processes of the units and modules in the above-mentioned system, reference may be made to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

Based on the same inventive concept, please refer to FIG. 11 , an embodiment of the present application further provides an apparatus 1100 for sending image data, the apparatus 1100 can be set in the SOC 110 of the aforementioned electronic device 100, and the apparatus 1100 includes:

The processing module 1101 is used to switch the horizontal timing sequence of sending image data to the display module from the first horizontal timing sequence to the second horizontal timing sequence when the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate. The screen refresh rate is greater than the second screen refresh rate;

The duration of the first HFP is shorter than the duration of the second HFP; and/or the duration of the first Hsync is shorter than the duration of the second Hsync; and/or the duration of the first HBP is shorter than the duration of the second HBP.

Optionally, the processing module is also used to:

Determine the amount of screen refresh rate change based on the first screen refresh rate and the second screen refresh rate;

Determine the horizontal timing variation based on the screen refresh rate variation, and the horizontal timing variation is N PCLK cycles;

Based on the horizontal timing variation, the first HFP, the first Hsync and the first HBP are respectively increased by M, P and Q PCLK cycles to obtain the second HFP, the second Hsync and the second HBP;

where N, M, P and Q are integers, and M+P+Q=N.

Optionally, the processing module is also used to:

When it is determined that the current screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, determining the first power consumption parameter corresponding to the second screen refresh rate;

The current power consumption parameter of the DSS is set as the first power consumption parameter, and the power consumption indicated by the first power consumption parameter is lower than the power consumption indicated by the second power consumption parameter corresponding to the first screen refresh rate.

Optionally, the processing module is also used to:

for obtaining image synthesis information corresponding to the image data, the image synthesis information includes at least one of the number of layers and the total number of pixels in the layers;

When the second power consumption parameter includes the first physical clock, setting the physical clock of the DSS as the first physical clock;

When the second power consumption parameter includes the first voltage, the voltage of the DSS is set to the first voltage.

Optionally, the processing module is also used to:

Get at least one layer;

Synthesize at least one layer to obtain image data.

Optionally, it also includes a sending module for:

Send a screen refresh rate switching notification to the display module, where the screen refresh rate switching notification is used to instruct the current screen refresh rate to switch to the second screen refresh rate.

The apparatus 1100 for sending image data provided in this embodiment may execute the foregoing method embodiments, and the implementation principles and technical effects thereof are similar, and details are not described herein again.

Based on the same inventive concept, the embodiment of the present application further provides an electronic device 1200 . FIG. 12 is a schematic structural diagram of an electronic device 1200 provided by an embodiment of the present application. As shown in FIG. 12 , the electronic device 1200 provided by this embodiment includes: a memory 1210 and a processor 1220. The memory 1210 is used to store computer programs; The methods described in the above method embodiments are executed when the computer program is invoked.

The electronic device 1200 provided in this embodiment can execute the foregoing method embodiments, and the implementation principles and technical effects thereof are similar, and details are not described herein again.

Based on the same inventive concept, an embodiment of the present application also provides a chip system. The chip system includes a processor coupled with a memory, and the processor executes a computer program stored in the memory, so as to implement the method described in the first aspect or any one of the implementation manners of the first aspect.

Wherein, the chip system may be a single chip, or a chip module composed of multiple chips.

Embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in the foregoing method embodiment is implemented.

The embodiment of the present application further provides a computer program product, when the computer program product runs on the electronic device 1200, the electronic device 1200 implements the method described in the foregoing method embodiments when executed.

If the above-mentioned integrated units are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on this understanding, the present application realizes all or part of the processes in the methods of the above embodiments, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When executed by a processor, the steps of each of the above method embodiments can be implemented. Wherein, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form, and the like. The computer-readable storage medium may include at least: any entity or device capable of carrying computer program codes to the photographing device/terminal device, recording medium, computer memory, read-only memory (ROM), random access Memory (random access memory, RAM), electrical carrier signals, telecommunication signals, and software distribution media. For example, U disk, mobile hard disk, disk or CD, etc. In some jurisdictions, under legislation and patent practice, computer readable media may not be electrical carrier signals and telecommunications signals.

In the foregoing embodiments, the description of each embodiment has its own emphasis. For parts that are not described or described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

In the embodiments provided in this application, it should be understood that the disclosed apparatus/device and method may be implemented in other manners. For example, the apparatus/equipment embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or Components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

It is to be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described feature, integer, step, operation, element and/or component, but does not exclude one or more other The presence or addition of features, integers, steps, operations, elements, components and/or sets thereof.

It will also be understood that, as used in this specification and the appended claims, the term "and/or" refers to and including any and all possible combinations of one or more of the associated listed items.

As used in the specification of this application and the appended claims, the term "if" may be contextually interpreted as "when" or "once" or "in response to determining" or "in response to detecting ". Similarly, the phrases "if it is determined" or "if the [described condition or event] is detected" may be interpreted, depending on the context, to mean "once it is determined" or "in response to the determination" or "once the [described condition or event] is detected. ]" or "in response to detection of the [described condition or event]".

In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the description, and should not be construed as indicating or implying relative importance.

References in this specification to "one embodiment" or "some embodiments" and the like mean that a particular feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in other embodiments," etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean "one or more but not all embodiments" unless specifically emphasized otherwise. The terms "including", "including", "having" and their variants mean "including but not limited to" unless specifically emphasized otherwise.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present application. Scope.

Claims

A method for sending image data, comprising:

When the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, the horizontal timing sequence for sending image data to the display module is switched from the first horizontal timing sequence to the second horizontal timing sequence, and the first screen refresh rate is greater than the second screen refresh rate;

Wherein, the first horizontal timing sequence includes a first horizontal blank blanking area and a first effective display area;

a second horizontal blank blanking area and a second effective display area included in the second horizontal timing sequence;

The pixel clock PCLK period in the first horizontal timing sequence is the same as the PCLK period in the second horizontal timing sequence;

The duration of the first effective display area is the same as the duration of the second effective display area;

The duration of the first horizontal blank blanking area is shorter than the duration of the second horizontal blank blanking zone.
The method according to claim 1, wherein the first horizontal blank blanking region comprises a first horizontal leading edge HFP, a first horizontal synchronization signal Hsync and a first horizontal trailing edge HBP, and the second horizontal blank blanking region comprises a first horizontal blank blanking region. The hidden region includes a second HFP, a second Hsync and a second HBP;

The duration of the first HFP is shorter than the duration of the second HFP; and/or the duration of the first Hsync is shorter than the duration of the second Hsync; and/or the duration of the first HBP is shorter than the duration of the first HFP Duration of the second HBP.
The method according to claim 2, wherein before the switching of the horizontal timing sequence for sending image data to the display module from the first horizontal timing sequence to the second horizontal timing sequence, the method further comprises:

based on the first screen refresh rate and the second screen refresh rate, determining an amount of screen refresh rate variation;

Determine the horizontal timing variation based on the screen refresh rate variation, where the horizontal timing variation is N PCLK cycles;

Based on the horizontal timing change amount, the first HFP, the first Hsync and the first HBP are respectively increased by M, P and Q PCLK cycles to obtain the second HFP, the second Hsync and the first HBP. 2HBP;

where N, M, P and Q are integers, and M+P+Q=N.
The method according to any one of claims 1-3, characterized in that, further comprising:

When the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, determining a first power consumption parameter corresponding to the second screen refresh rate;

Setting the current power consumption parameter of the display controller DSS as the first power consumption parameter, the power consumption indicated by the first power consumption parameter is lower than that indicated by the second power consumption parameter corresponding to the first screen refresh rate power consumption.
The method of claim 4, further comprising:

acquiring image composition information corresponding to the image data, the image composition information including at least one of the number of layers and the total number of pixels in the layers;

The determining of the first power consumption parameter corresponding to the second screen refresh rate includes:

The second power consumption parameter is determined based on the second screen refresh rate and the image composition information.
The method according to claim 4 or 5, wherein the setting the current power consumption parameter of the DSS as the first power consumption parameter comprises at least one of the following:

When the second power consumption parameter includes a first physical clock, setting the physical clock of the DSS as the first physical clock;

When the second power consumption parameter includes a first voltage, the voltage of the DSS is set to the first voltage.
The method according to any one of claims 1-6, further comprising:

Get at least one layer;

The at least one layer is synthesized to obtain the image data.
The method according to any one of claims 1-7, further comprising:

A screen refresh rate switching notification is sent to the display module, where the screen refresh rate switching notification is used to instruct the current screen refresh rate to be switched to the second screen refresh rate.
A device for sending image data, comprising:

The processing module is configured to switch the horizontal timing sequence for sending image data to the display module from the first horizontal timing sequence to the second horizontal timing sequence when the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate. A screen refresh rate is greater than the second screen refresh rate;

Wherein, the first horizontal timing sequence includes a first horizontal blank blanking area and a first effective display area;

a second horizontal blank blanking area and a second effective display area included in the second horizontal timing sequence;

The PCLK period in the first horizontal timing sequence is the same as the PCLK period in the second horizontal timing sequence;

The duration of the first effective display area is the same as the duration of the second effective display area;

The duration of the first horizontal blank blanking area is shorter than the duration of the second horizontal blank blanking zone.
The apparatus according to claim 9, wherein the first horizontal blank blanking area includes a first HFP, a first Hsync and a first HBP, and the second horizontal blank blanking area includes a second HFP, a first Hsync and a first HBP. Second Hsync and Second HBP;

The duration of the first HFP is shorter than the duration of the second HFP; and/or the duration of the first Hsync is shorter than the duration of the second Hsync; and/or the duration of the first HBP is shorter than the duration of the first HBP Duration of the second HBP.
The apparatus according to claim 10, wherein the processing module is further configured to:

based on the first screen refresh rate and the second screen refresh rate, determining an amount of screen refresh rate variation;

Determine a horizontal timing variation based on the screen refresh rate variation, where the horizontal timing variation is N PCLK cycles;

Based on the horizontal timing variation, the first HFP, the first Hsync and the first HBP are respectively increased by M, P and Q PCLK cycles to obtain the second HFP, the second Hsync and the first HBP. 2HBP;

where N, M, P and Q are integers, and M+P+Q=N.
The device according to any one of claims 9-11, wherein the processing module is further configured to:

When the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, determining a first power consumption parameter corresponding to the second screen refresh rate;

Setting the current power consumption parameter of the display controller DSS as the first power consumption parameter, the power consumption indicated by the first power consumption parameter is lower than that indicated by the second power consumption parameter corresponding to the first screen refresh rate power consumption.
The apparatus according to claim 12, wherein the processing module is further configured to:

for acquiring image synthesis information corresponding to the image data, the image synthesis information including at least one of the number of layers and the total number of pixels in the layers;

The second power consumption parameter is determined based on the second screen refresh rate and the image composition information.
The device according to any one of claims 9-13, further comprising a sending module for:

A screen refresh rate switching notification is sent to the display module, where the screen refresh rate switching notification is used to instruct the current screen refresh rate to be switched to the second screen refresh rate.
An electronic device, characterized in that it comprises: a memory and a processor, wherein the memory is used to store a computer program; the processor is used to execute the method according to any one of claims 1-8 when the computer program is invoked method.
A chip system, characterized in that the chip system includes a processor, the processor is coupled with a memory, and the processor executes a computer program stored in the memory, so as to realize any one of claims 1-9 the method described.