CN114205485A

CN114205485A - Method and device for sending image data

Info

Publication number: CN114205485A
Application number: CN202010988832.4A
Authority: CN
Inventors: 汪永浪; 李煜; 王亮; 孙家亮; 高永胜; 余先宇
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-09-18
Filing date: 2020-09-18
Publication date: 2022-03-18
Anticipated expiration: 2040-09-18
Also published as: WO2022057601A1; CN114205485B

Abstract

The application provides a method and a device for sending image data, which relate to the technical field of terminals, wherein the method comprises the step of switching a horizontal time sequence for sending the image data to a display module from a first horizontal time sequence to a second horizontal time sequence when a screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, wherein the first screen refresh rate is greater than the second screen refresh rate, the first horizontal time sequence comprises a first horizontal blank blanking area and a first effective display area, the second horizontal blank blanking area comprises a second horizontal blank blanking area and a second effective display area, a PCLK period in the first horizontal time sequence is the same as that in the second horizontal time sequence, the duration of the first effective display area is the same as that of the second effective display area, and the duration of the first horizontal blanking area is less than that of the second horizontal blank area. The technical scheme provided by the application reduces the phenomenon that the display of the electronic equipment is abnormal due to the reduction of the screen refresh rate.

Description

Method and device for sending image data

Technical Field

The present application relates to the field of terminal technologies, and in particular, to a method and an apparatus for transmitting image data.

Background

At present, electronic devices such as mobile phones and tablet computers are gradually beginning to support various screen refresh rates. The electronic device may switch different screen refresh rates for different display scenarios, for example, when the electronic device is interacting with a user through a screen or displaying game content, the electronic device may display through a higher screen refresh rate, and may switch to a lower screen refresh rate for display at other times.

In the prior art, an electronic device includes a System On Chip (SOC) and a display module. The SOC may send image data included in one frame of image to the display module on a line-by-line basis based on the horizontal timing to display. The horizontal timing includes a plurality of Pixel Clocks (PCLK). When the screen refresh rate is decreased, the SOC may increase a PCLK period (hereinafter, referred to as a PCLK period), so that a time period occupied for transmitting each line of images is increased, and accordingly, a speed of transmitting and displaying each frame of images is also decreased.

However, PCLK is a clock signal for controlling pixel output, and changing the PCLK period can make image data transmission unstable, thereby causing display abnormalities such as black screen display or screen splash display when switching the screen refresh rate.

Disclosure of Invention

In view of the above, the present application provides a method and an apparatus for transmitting image data.

In order to achieve the above object, in a first aspect, an embodiment of the present application provides a method for transmitting image data, including:

when the screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, switching the horizontal time sequence for sending image data to the display module from a first horizontal time sequence to a second horizontal time sequence, wherein the first screen refresh rate is greater than the second screen refresh rate;

wherein the first horizontal timing comprises a first horizontal blank blanking area and a first effective display area;

the second horizontal time sequence comprises a second horizontal blank blanking area and a second effective display area;

the PCLK period in the first horizontal timing is the same as the PCLK period in the second horizontal timing;

the duration of the first effective display area is the same as the duration of the second effective display area;

the duration of the first horizontal blank blanking region is less than the duration of the second horizontal blank blanking region.

Here, in the horizontal timing, Hsync may represent arrival of one line of image data including a plurality of pixels. Hsync can be a pulse signal that starts the transfer of the line of image data when Hsync ends and passes the HBP, where each pixel can occupy one PCLK. There is no image data transfer between Hsync, HFP, and HBP, so this time is called horizontal blank blanking region, while there is image data transfer between adjacent HBP and HFP, this time can be called active display region.

It should be noted that the first horizontal time sequence may be a horizontal time sequence adopted by the electronic device to send the image data to the display module when the screen refresh rate is the first screen refresh rate.

It should be further noted that, in the embodiment of the present application, a trigger condition or a manner for switching a screen refresh rate is not limited. For example, the electronic device may determine whether a user action is received based on either window based on the interface manager 212, and if so, determine a higher screen refresh rate as the second screen refresh rate, otherwise, determine a lower screen refresh rate as the second screen refresh rate.

In the embodiment of the present application, when the screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, the timing for the display module to send the image data can be switched from a first horizontal timing to a second horizontal timing. The first horizontal timing sequence comprises a first horizontal blank blanking area and a first effective display area, and the second horizontal timing sequence comprises a second horizontal blank blanking area and a second effective display area. Because the PCLK period in the first horizontal time sequence is the same as the PCLK period included in the second horizontal time sequence, the time length of the first effective display area is the same as the time length of the second effective display area, and the time length of the first horizontal blank blanking area is less than the time length of the second horizontal blank blanking area, when the screen refresh rate is reduced, the horizontal blank blanking area can be increased under the condition of keeping the PCLK period unchanged, so that the time length of the horizontal time sequence is increased, the phenomenon that the electronic equipment is abnormal in display due to reduction of the screen refresh rate is reduced, and the reliability of image data transmission and image display based on the image data is improved.

Optionally, the first horizontal blank blanking region comprises a first Horizontal Front Porch (HFP), a first horizontal synchronization signal (Hsync), and a first Horizontal Back Porch (HBP), and the second horizontal blank blanking region comprises a second HFP, a second Hsync, and a second HBP;

the duration of the first HFP is less than the duration of the second HFP; and/or the duration of the first Hsync is less than the duration of the second Hsync; and/or the duration of the first HBP is less than the duration of the second HBP.

For example, the durations of the first HFP, the first Hsync, and the first HBP in the first horizontal timing are all 2 PCLK periods, the duration of the first horizontal blank blanking area is 6 PCLK periods, and the duration of the first active display area is 4 PCLK periods. The second horizontal timing may include the following four possible implementations: in the first mode, the time lengths of the second HFP, the second Hsync and the second HBP are respectively 1 PCLK period longer than the time lengths of the first HFP, the first Hsync and the first HBP, the time length of the second horizontal time sequence is 3 PCLK periods longer than the time length of the first horizontal time sequence, and the time length of the first effective display area is the same as the time length of the second effective display area; in a second mode, the duration of the second HFP is 3 PCLK cycles longer than that of the first HFP, and the first Hsync, the first HBP and the first effective display area are respectively the same as the duration of the second Hsync, the second HBP and the second effective display area; the third method comprises the following steps: the duration of the second Hsync is 3 PCLK cycles longer than that of the first Hsync, and the duration of the first HFP, the duration of the first HBP and the duration of the first effective display area are respectively the same as the duration of the second HFP, the duration of the second HBP and the duration of the second effective display area; the method is as follows: the duration of the second HBP is 3 PCLK longer than the duration of the first HBP, and the first HFP, the first Hsync, and the first active display area are respectively the same as the durations of the second HFP, the second Hsync, and the second active display area.

Optionally, before the switching the horizontal timing for sending the image data to the display module from the first horizontal timing to the second horizontal timing, the method further includes:

determining a screen refresh rate variation based on the first screen refresh rate and the second screen refresh rate;

determining a horizontal timing variation based on the screen refresh rate variation, wherein the horizontal timing variation is N PCLK cycles;

increasing M, P cycles and Q cycles of PCLK for the first HFP, the first Hsync and the first HBP respectively based on the horizontal timing variation to obtain a second HFP, a second Hsync and a second HBP;

wherein N, M, P and Q are integers, and M + P + Q ═ N.

In some embodiments, the corresponding horizontal timing may be acquired as the second horizontal timing from the correspondence between the screen refresh rate and the horizontal timing based on the second screen refresh rate.

In some embodiments, when the first screen refresh rate is less than the second screen refresh rate, i.e., the screen refresh rate is increased, the duration of the first horizontal blank blanking region may be greater than the duration of the second horizontal blank blanking region: the duration of the first HFP is greater than the duration of the second HFP; and/or the duration of the first Hsync is greater than the duration of the second Hsync; and/or the duration of the first HBP is greater than the duration of the second HBP.

Optionally, the method further comprises:

when the screen refresh rate is switched from the first screen refresh rate to the second screen refresh rate, determining a first power consumption parameter corresponding to the second screen refresh rate;

setting the current power consumption parameter of the display controller DSS as the first power consumption parameter, wherein the power consumption indicated by the first power consumption parameter is lower than the power consumption indicated by the second power consumption parameter corresponding to the first screen refresh rate.

Optionally, the method further comprises:

acquiring image synthesis information corresponding to the image data, wherein the image synthesis information comprises at least one of the number of layers and the total number of pixels of the layers;

the determining a first power consumption parameter corresponding to the second screen refresh rate includes:

determining the second power consumption parameter based on the second screen refresh rate and the image composition information.

It should be noted that, in practical applications, the image composition information may also include other types of information, such as the positions of the layers.

Optionally, setting a current power consumption parameter of a display controller (DSS) to the first power consumption parameter includes at least one of:

setting a physical clock of the DSS to a first physical clock when the second power consumption parameter comprises the first physical clock;

setting a voltage of the DSS to a first voltage when the second power consumption parameter includes the first voltage.

Since the higher the screen refresh rate, the more the number of layers, and the larger the total number of pixels in the layers, the faster the speed of sending image data to the display module, and the larger the corresponding power consumption, when the screen refresh rate changes, the power consumption parameter of the DSS can be switched from the second power consumption parameter to the first power consumption parameter, so as to save power consumption when the screen refresh rate is reduced, and reliably send image data when the screen refresh rate is increased.

In some embodiments, the corresponding power consumption parameter may be obtained from the correspondence between the screen refresh rate and the power consumption parameter as the first power consumption parameter based on the second screen refresh rate. In some embodiments, the screen refresh rate variation may be determined based on a first screen refresh rate and a second screen refresh rate, a corresponding power consumption parameter variation may be obtained from a correspondence between the screen refresh rate variation and the power consumption parameter variation based on the screen refresh rate variation, and the first power consumption parameter may be determined based on the power consumption parameter variation and the second power consumption parameter. In some embodiments, the corresponding power consumption parameter may be obtained from a correspondence between the image synthesis information and the power consumption parameter based on the image synthesis information of the current frame image, and determined as the first power consumption parameter.

In some embodiments, the power consumption indicated by the first power consumption parameter may be greater than the power consumption indicated by the second power consumption parameter when the second screen refresh rate is greater than the first screen refresh rate.

Optionally, the method further comprises:

acquiring at least one layer;

and synthesizing the at least one image layer to obtain the image data.

Optionally, the method further comprises:

and sending a screen refresh rate switching notice to the display module, wherein the screen refresh rate switching notice is used for indicating that the current screen refresh rate is switched to the second screen refresh rate.

In a second aspect, an embodiment of the present application provides an apparatus for transmitting image data, including:

the processing module is used for switching the horizontal time sequence for sending the image data to the display module from a first horizontal time sequence to a second horizontal time sequence when the screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, wherein the first screen refresh rate is greater than the second screen refresh rate;

Optionally, the first horizontal blank blanking region includes a first HFP, a first Hsync, and a first HBP, and the second horizontal blank blanking region includes a second HFP, a second Hsync, and a second HBP;

Optionally, the processing module is further configured to:

wherein N, M, P and Q are integers, and M + P + Q ═ N.

Optionally, the processing module is further configured to:

setting the current power consumption parameter of the DSS as the first power consumption parameter, wherein the power consumption indicated by the first power consumption parameter is lower than the power consumption indicated by the second power consumption parameter corresponding to the first screen refresh rate.

Optionally, the processing module is further configured to:

the image synthesis information is used for acquiring image synthesis information corresponding to the image data, and the image synthesis information comprises at least one of the number of layers and the total number of pixels of the layers;

Optionally, the processing module is further configured to perform at least one of the following operations:

Optionally, the processing module is further configured to:

acquiring at least one layer;

and synthesizing the at least one image layer to obtain the image data.

Optionally, the apparatus further comprises a sending module, configured to:

In a third aspect, an embodiment of the present application provides an electronic device, including: a memory for storing a computer program and a processor; the processor is adapted to perform the method of any of the first aspect described above when the computer program is invoked.

In a fourth aspect, an embodiment of the present application provides a chip system, where the chip system includes a processor, the processor is coupled with a memory, and the processor executes a computer program stored in the memory to implement the method in any one of the above first aspects.

The chip system can be a single chip or a chip module consisting of a plurality of chips.

In a fifth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to implement the method of any one of the above first aspects.

In a sixth aspect, embodiments of the present application provide a computer program product, which, when run on an electronic device, causes the electronic device to perform the method of any one of the above first aspects.

It is understood that the beneficial effects of the second to sixth aspects can be seen from the description of the first aspect, and are not described herein again.

Drawings

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a block diagram of a software structure of an electronic device according to an embodiment of the present disclosure;

fig. 3 is an abstract diagram of a MIPI timing sequence provided in an embodiment of the present application;

FIG. 4 is a schematic vertical timing diagram provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a horizontal timing sequence provided by an embodiment of the present application;

fig. 6 is a timing diagram of a method for sending image data according to an embodiment of the present disclosure;

FIG. 7 is a schematic horizontal timing diagram according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another horizontal timing sequence provided in the embodiments of the present application;

FIG. 9 is a schematic diagram of another horizontal timing sequence provided in the embodiments of the present application;

FIG. 10 is a schematic diagram of another horizontal timing sequence provided by the embodiments of the present application;

fig. 11 is a schematic structural diagram of an apparatus for sending image data according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of another electronic device according to an embodiment of the present application.

Detailed Description

The display method provided by the embodiment of the application can be applied to electronic devices such as a mobile phone, a tablet personal computer, a wearable device, a vehicle-mounted device, an Augmented Reality (AR)/Virtual Reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a Personal Digital Assistant (PDA), and the like, and the embodiment of the application does not limit the specific types of the electronic devices at all.

Fig. 1 is a schematic structural diagram of an electronic device 100 provided in the present application. The electronic device 100 may include an SOC110 and a Liquid Crystal Display (LCD) module (LCM) 120.

The SOC110 may include an Application Processor (AP) 111, a DSS112, and a Mobile Industry Processor Interface (MIPI) 113.

The AP111 may be a very large scale integrated circuit (vlsi) that extends audio and video functions and a dedicated interface on the basis of a Central Processing Unit (CPU), and may be used to process multimedia data such as images and music, including photography, music playing, radio, video playing, and the like.

DSS112 may be configured to retrieve image data from a memory (not shown in fig. 1) of SOC110 and transmit the image data to DDIC122 in LCM120 via MIPI interface 113 according to MIPI timing in accordance with the MIPI protocol.

The MIPI interface 113 includes various interfaces such as a camera interface, a display interface, a radio frequency interface, and a microphone interface. The display interface may be used for communication between DSS112 and DDIC122, including transmitting image data in MIPI timing.

The MIPI timing is used to indicate the time sequence of transmitting image data of one frame of image, so that the DDIC122 receives the image data in order and controls the display panel 121 to display the image.

In some embodiments, MIPI interface 113 may be integrated in DSS 112.

The LCM120 may include a display panel 121, a Display Driver Integrated Circuit (DDIC) 122. DDIC122 may be configured to receive image data transmitted at a specific timing from DSS112, and control display panel 121 to control corresponding liquid crystal molecules based on each pixel in the image data, so that display panel 121 displays the image data. In addition, the DDIC122 may also store the image data in an image register (GRAM) 123.

The display panel 121 may be used to display image data. The display panel 121 may be an LCD panel including a Twisted Nematic (TN) type panel, a vertical alignment (TA) type panel, an in-plane switching (IPS) type panel, a continuous fireworks alignment (CPA) type panel, or an advanced super dimension switching (ADSDS) type panel. Of course, in practical applications, the display panel 121 may also be another type of panel, and the embodiment of the present application does not specifically limit the type of the display panel 121.

It should be noted that the LCM120 may also include further components, such as at least one of connectors, supports, peripheral circuitry, and a backlight.

In addition, in practical applications, the LCM120 in the electronic device 100 may be replaced by another display module, and the type of the display module is not particularly limited in the embodiment of the present application.

It is to be understood that the illustrated structure of the embodiment of the present application does not specifically limit the electronic device 100. In other embodiments of the present application, electronic device 100 may include more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware. For example, in some embodiments, the electronic device 100 may further include at least one of an external memory interface, an internal memory, a Universal Serial Bus (USB) interface, a charging management module, a power management module, a battery, an antenna, a mobile communication module, a wireless communication module, an audio module, a speaker, a receiver, a microphone, an earphone interface, a sensor module, a key, a motor, an indicator, a camera, a display screen, and a Subscriber Identity Module (SIM) card interface.

Referring to fig. 2, a block diagram of a software structure of an electronic device 100 according to an embodiment of the present disclosure is shown.

The layered architecture divides the software into several layers, each layer having a clear role and division of labor. The layers communicate with each other through a software interface.

As shown in fig. 2, the electronic device 100 includes a display frame layer 210, a hardware abstraction layer 220, a DSS driver layer 230, and an LCD driver layer 240, wherein the display frame layer 210 and the hardware abstraction layer 220 may be located at the AP111 in fig. 1, the DSS driver layer 230 may be located at the DSS112 in fig. 1, and the LCD driver layer 240 may be located at the DDIC122 in fig. 1.

The display framework layer 210 may include a window manager 211 and an interface manager 212. The display panel 121 of the electronic device 100 may display a plurality of windows (abstract classes associated with display), such as a dialog box, a status bar, and a floating window, and the content in each window may be used as an interface (surface). The window manager 211 is an interface class that defines a plurality of interfaces for managing windows, including determining whether there is a status bar, locking a screen, intercepting a screen, etc. The interface manager 212 may obtain an interface in each window, thereby obtaining at least one layer, and send the obtained at least one layer and image composition information to the hardware abstraction layer 220, where each layer may include an interface. In addition, the interface manager 212 may also detect whether the corresponding window receives a user operation.

The image composition information may include at least one of the number of layers and the total number of layers, and of course, in practical applications, the image composition information may also include more information, such as the position of each layer.

The hardware abstraction layer 220 may include an image composition module 221 and a screen refresh rate switching module 222. The image synthesis module 221 may be configured to receive at least one image layer and image synthesis information sent by the interface manager 212, and synthesize the at least one image layer into a frame of image according to the image synthesis information. The screen refresh rate switching module 222 may determine the current screen refresh rate according to a preset screen refresh rate policy, for example, when the interface manager 212 does not receive the user operation within a preset time period closest to the current time, the current screen refresh rate may be decreased.

In some embodiments, the hardware abstraction layer 220 may also include a power consumption module 223. DSS112 in fig. 1 may reduce the rate at which image data is transmitted to DDIC122 over MIPI interface 113 when the screen refresh rate is reduced, while DSS112 may reduce power consumption when the rate at which image data is transmitted is reduced; conversely, when the screen refresh rate is increased, DSS112 may increase the rate of transmitting image data to DDIC122 through MIPI interface 113, and DSS112 may increase power consumption when increasing the rate of transmitting image data. Accordingly, to flexibly set power consumption parameters of DSS112 to reduce power consumption or increase power consumption, power consumption module 223 may determine power consumption parameters of DSS112, such as at least one of a physical clock and a voltage of DSS112, based on the current screen refresh rate.

DSS drive layer 230 may include MIPI timing control module 231. The MIPI timing control module 231 may determine a MIPI timing to transmit image data to the LCD layer 240 according to the current screen refresh rate, and transmit the image data of the frame of image synthesized by the hardware abstraction layer 220 to the display unit 241 in the LCD layer 240 according to the MIPI timing.

In some embodiments, DSS drive layer 230 may further include a clock control module 232 and a voltage control module 233. Clock control module 232 may set the current physical clock of DSS112 to the physical clock determined by power consumption module 223. Voltage control module 233 may set the current voltage of DSS112 to the voltage determined by power consumption module 223.

The LCD driving layer 240 may include a display unit 241. The display unit 241 may be configured to control the display panel 121 in fig. 1 to perform display based on the received image data, including controlling the liquid crystal molecules corresponding to each pixel to display the pixel.

It should be noted that the electronic device 100 may also include more or less layers, and each layer may include more or less modules, for example, in the hardware abstraction layer 220, the image composition module 221 and the screen refresh rate switching module 222 may be integrated into one module.

Fig. 3 is a schematic diagram of an MIPI timing sequence provided in the embodiment of the present application. MIPI timing may be used to indicate the timing of transmitting image data, including vertical timing and horizontal timing. In vertical timing, a vertical synchronization signal (Vsync), which may indicate the arrival of a new image frame, includes a Vertical Front Porch (VFP) before the Vsync and a Vertical Back Porch (VBP) after the Vsync. Between adjacent VBPs and VFPs is image data of a frame of image, which is transmitted line by SOC110 to LCM120 for display. In the horizontal timing, Hsync may represent arrival of one line of image data including a plurality of pixels. Before each Hsync, an HFP may be included, and after each Hsync, an HBP may be included, and between adjacent HBPs and HFP, the line of image data. As can be seen from fig. 3, in the process of displaying one frame of image, besides the time of actually transferring the image data, the time occupied by Vsync, VFP, VBP, Hsync, HFP, and HBP is also included.

Fig. 4 is a schematic vertical timing diagram according to an embodiment of the present disclosure. As shown in fig. 4, when one frame image is transferred, the VFP is first passed, and then the start of transfer of the frame image is instructed by the Vsync. The Vsync may be a pulse signal, and when the Vsync is finished and passes through the VBP, the image data of the one frame image starts to be transmitted, wherein each line of the image data may be transmitted by one horizontal timing. As can be seen from fig. 4, during Vsync, VFP and VBP, no image data is transmitted, and this time may be referred to as a vertical blank blanking area, while image data is transmitted between adjacent VFP and VBP, so that the time between adjacent VFP and VBP may be referred to as an effective display area.

Fig. 5 is a schematic horizontal timing diagram according to an embodiment of the present disclosure. As shown in fig. 5, when a line of image data is transferred, HFP is passed, and then Hsync indicates that the line of image data starts to be transferred. Hsync can be a pulse signal that starts the transfer of the line of image data when Hsync ends and passes the HBP, where each pixel can occupy one PCLK. As can be seen from fig. 5, there is no image data transmission between Hsync, HFP and HBP, so this time is called horizontal blank blanking region, and there is image data transmission between adjacent HBP and HFP, this time can be called active display region.

Fig. 4 and 5 explain a vertical timing and a horizontal timing at which DSS112 transmits image data, respectively, and accordingly DDIC122 may receive image data and control display panel 121 to display according to the vertical timing and the horizontal timing.

It should be noted that Vsync, VFP, VBP, Hsync, HFP, HBP, and PCLK may be generated by DSS112 in fig. 1. As can be seen from fig. 4 and 5, the durations of Hsync, HFP, and HBP may be several PCLK periods, the durations of Vsync, VFP, and VBP, or several horizontal timings.

Still taking fig. 4 and 5 as an example, as can be seen from fig. 4, the currently transmitted image includes 7 lines of image data, and as can be seen from fig. 5, each line of image data includes 4 pixels, and thus, the image data includes 7 × 4 pixels. It should be noted that, in the embodiment of the present application, only fig. 4 and fig. 5 are taken as examples, the MIPI timing sequence for transmitting image data is described, and the resolution of the display panel 121 of an image and the image is not limited, and in practical applications, the panel 121 and the image may have a greater or smaller resolution, for example, the resolution may be 1366 × 768.

Currently, electronic devices can support multiple screen refresh rates and switch the screen refresh rates. In some embodiments, when the SOC110 transmits image data to the LCM120, the PCLK period may be increased, so that image data of each line is transmitted in a longer time, and image data of each frame of image is transmitted more slowly, thereby achieving the purpose of reducing the screen refresh rate. In this manner, the horizontal timing is similar to that shown in fig. 5, which is equivalent to only laterally lengthening the horizontal timing shown in fig. 5. However, as can be seen from the foregoing, PCLK is a clock signal for transmitting pixels, and changing the period of PCL makes image data transmission unstable, and further causes abnormal display phenomena such as black screen or floating screen when the screen refresh rate is switched.

To solve the above problem, the present application proposes another method of transmitting image data. In the embodiment of the present application, when the screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, the timing for the display module to send the image data can be switched from a first horizontal timing to a second horizontal timing. The first horizontal timing sequence comprises a first horizontal blank blanking area and a first effective display area, and the second horizontal timing sequence comprises a second horizontal blank blanking area and a second effective display area. Because the PCLK period in the first horizontal time sequence is the same as the PCLK period included in the second horizontal time sequence, the time length of the first effective display area is the same as the time length of the second effective display area, and the time length of the first horizontal blank blanking area is less than the time length of the second horizontal blank blanking area, when the screen refresh rate is reduced, the horizontal blank blanking area can be increased under the condition of keeping the PCLK period unchanged, so that the time length of the horizontal time sequence is increased, the phenomenon that the electronic equipment is abnormal in display due to reduction of the screen refresh rate is reduced, and the reliability of image data transmission and image display based on the image data is improved.

The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 6 is a flowchart of a method for sending image data according to an embodiment of the present disclosure. It should be noted that the method is not limited by the specific sequence shown in fig. 6 and described below, and it should be understood that in other embodiments, the sequence of some steps in the method may be interchanged according to actual needs, or some steps may be omitted or deleted. The method comprises the following steps:

s601, the interface manager 212 obtains at least one layer and image composition information from the window manager 211.

To facilitate generation of an image to be displayed in a subsequent screen, the interface manager 212 may acquire the interface from the at least one window manager 211 respectively upon receiving the Vsync, obtain at least one layer, and may also acquire image composition information such as the number of layers and the total number of pixels of the layer of the at least one layer.

It should be noted that, in practical applications, the interface manager 212 may also obtain at least one layer and image composition information from the window manager 211 based on other trigger conditions. The embodiment of the present application does not specifically limit the trigger condition for obtaining at least one image layer and image composition information.

S602, the interface manager 212 sends the at least one layer and the image composition information to the image composition module 221.

Alternatively, the interface manager 212 may transmit the image composition information to the power consumption module 223.

S603, the image synthesizing module 221 synthesizes the at least one layer into a frame of image according to the image synthesizing information.

When the image synthesis information includes the number of layers and the total number of pixels of the layers, the image synthesis module 221 may splice and stack the layers of the number of layers based on the total number of pixels of the layers, so as to obtain a frame of image, where the frame of image is a current image to be displayed. Of course, if the image layer synthesis information further includes the position of each image layer, the image synthesis module 221 may also synthesize each image layer based on the position of each image layer.

It should be noted that, in practical applications, the image synthesizing module 221 may synthesize the at least one layer into a frame image according to the image synthesis information in other manners, or in other embodiments, the interface manager 212 may synthesize the at least one layer into a frame image according to the image synthesis information, and the embodiment of the present application is not particularly limited to the manner of synthesizing the at least one layer into a frame image according to the image synthesis information.

S604, the screen refresh rate switching module 222 determines a current second screen refresh rate. Thereafter, S605-S606 and S607-S609 may be performed, respectively.

Since the display panel 121 of the electronic device 100 can support multiple screen refresh rates and switch the screen refresh rates, the current second screen refresh rate can be determined before displaying a new frame of image to ensure that the image data of the subsequent display panel 121 correctly displays the image.

Alternatively, the screen refresh rate switching module 222 may determine the current second screen refresh rate when the Vsync is received or when it is determined that the image is synthesized by the image synthesizing module 221.

Alternatively, the display panel 121 of the electronic device 100 may support two screen refresh rates. The screen refresh rate switching module 222 may determine whether a user action is received based on either window based on the interface manager 212, and if so, determine a higher screen refresh rate as the second screen refresh rate, otherwise, determine a lower screen refresh rate as the second screen refresh rate. Of course, in practical applications, the electronic device 100 may support more screen refresh rates, and the screen refresh rate switching module 222 may determine the second screen refresh rate in a similar or more complicated manner, for example, may determine a frequency of receiving the user operation, and determine a screen refresh rate corresponding to the frequency as the second screen refresh rate.

It should be noted that the screen refresh rate switching module 222 may also determine the second screen refresh rate in other manners based on other triggering conditions, and the triggering conditions and manners for determining the second screen refresh rate in this embodiment of the application are not specifically limited.

Alternatively, the screen refresh rate switching module 222 may send the second screen refresh rate to the power consumption module 223.

S605, the power consumption module 223 determines a current first power consumption parameter.

When the screen refresh rate is higher, the number of layers is greater, and the total number of pixels of a layer is greater, the subsequent DSS112 needs to transmit image data to the DDIC122 faster, and the corresponding power consumption is also greater, so that in order to facilitate subsequent timely adjustment of the power consumption parameter of the DSS112 to ensure reliability of transmitting image data, the power consumption module 223 may determine the current second power consumption parameter.

Optionally, the second power consumption parameter may include at least one of a second physical clock and a second voltage of DSS 112.

Optionally, the corresponding power consumption parameter may be obtained from the correspondence between the screen refresh rate and the power consumption parameter as the first power consumption parameter based on the second screen refresh rate. Referring to table 1 below, if the second screen refresh rate is 90Hz (hertz), the clock 2 corresponding to 90Hz may be obtained as the first physical clock, and the voltage 2 corresponding to 90Hz may be obtained as the first voltage.

TABLE 1

Additionally, in other embodiments, the power consumption module 223 may determine a first screen refresh rate and a second power consumption parameter corresponding to a previous frame image adjacent to the image to be displayed. Determining a screen refresh rate variation based on the first screen refresh rate and the second screen refresh rate, acquiring a corresponding power consumption parameter variation from a correspondence between the screen refresh rate variation and the power consumption parameter variation based on the screen refresh rate variation, and determining a first power consumption parameter based on the power consumption parameter variation and the second power consumption parameter. Wherein when the second screen refresh rate is less than the first screen refresh rate, the power consumption indicated by the first power consumption parameter may be less than the power consumption indicated by the second power consumption parameter, for example, the second power consumption parameter may include at least one of a second physical clock and a second voltage, and then the frequency of the first physical clock may be less than the frequency of the second physical clock, and the first voltage may be less than the second voltage. Of course, when the second screen refresh rate is greater than the first screen refresh rate, the power consumption indicated by the first power consumption parameter may be greater than the power consumption indicated by the second power consumption parameter.

Alternatively, the corresponding power consumption parameter may be obtained from the correspondence between the image synthesis information and the power consumption parameter based on the image synthesis information of the current frame image, and determined as the first power consumption parameter. Referring to table 2 below, the image composition information includes the number of layers and the total number of pixels of the layers, and the power consumption parameters include the physical clock and voltage of DSS 112. If the image synthesis information corresponding to the current frame image includes 4 image layers, and the total number of pixels in the image layers is 40 ten thousand pixels, the corresponding clock 3 is obtained as a first physical clock, and the corresponding voltage 3 is obtained as a first voltage.

TABLE 2

It should be noted that, when the first power consumption parameter is determined based on the second screen refresh rate and the image composition information, the corresponding power consumption parameter may be obtained from the correspondence between the screen refresh rate, the image composition information, and the power consumption parameter as the first power consumption parameter based on the second screen refresh rate and the image composition information; alternatively, when the first power consumption parameter is determined based on the second screen refresh rate and the image composition information, the power consumption parameter may be determined based on the second screen refresh rate and the image composition information, respectively, and an average value of the two power consumption parameters may be acquired as the first power consumption parameter.

It should be noted that the correspondence between the screen refresh rate and the power consumption parameter, the correspondence between the image composition information and the power consumption parameter, or the correspondence between the screen refresh rate and the image composition information and the power consumption parameter may be obtained by setting in advance.

In some embodiments, power consumption module 223 may send a physical clocking notification to clocking module 232, the physical clocking notification carrying the first physical clock; and/or, power consumption module 223 may send a voltage control notification to voltage control module 233, the voltage control notification carrying the first voltage.

S606, clock control module 232 sets the current physical clock of DSS112 to the first physical clock, and/or voltage control module 233 sets the current voltage of DSS112 to the first voltage.

Since DSS112 can transmit image data to DDIC122 at a rate corresponding to the screen refresh rate when the screen refresh rate changes, the faster the image data is transmitted, the higher the power consumption of DSS112, clock control module 232 and voltage control module 233 can control the current physical clock and voltage of DSS112, respectively, in order to match the power consumption of DSS112 to the screen refresh rate, including reducing the power consumption of DSS112 in time when the screen refresh rate is reduced.

In addition, in other embodiments, the power consumption parameter of DSS112 may not be adjusted, i.e., S605 and S606 are optional steps.

S607, the MIPI timing control module 231 determines a second horizontal timing corresponding to the second screen refresh.

As can be seen from the foregoing, DSS112 transmits image data to DDIC122 line by line through horizontal timing. Thus, to ensure that DDIC122 correctly receives and displays an image, a second horizontal timing corresponding to a second screen refresh rate may be determined.

The second horizontal timing may include a second horizontal blank area and a second active display area, and the second horizontal blank area may include a second HFP, a second Hsync, and a second HBP. And since the second effective display area is used for actually transmitting each row of pixels in the image, and the width of the display panel 121 is not changed for the same electronic device 100, the time length occupied by the effective display area included in the horizontal timing may be the same for different screen refresh rates, and accordingly, in S607, determining the second horizontal timing may include determining the second HFP, the second Hsync, and the second HBP.

In addition, in some embodiments, the MIPI timing control module 231 may determine the first screen refresh rate when image data corresponding to a previous frame image adjacent to the current image to be displayed is transmitted. The MIPI timing control module 231 may determine a second horizontal timing corresponding to the second screen refresh rate when it is determined that the first screen refresh rate is different from the second screen refresh rate, that is, when the current screen refresh rate needs to be switched.

The PCLK period in the second horizontal time sequence can be the same as the PCLK period in the first horizontal time sequence, namely, the PCLK period does not need to be changed when the screen refresh rate is switched, display abnormal phenomena such as black screen display and flower screen display are reduced, and reliability of sending image data and displaying images based on the image data subsequently is improved. The duration of the first effective display area may be the same as the duration of the second effective display area. When the first screen refresh rate is greater than the second screen refresh rate, i.e., the screen refresh rate is reduced, the duration of the first horizontal blank blanking area may be less than the duration of the second horizontal blank blanking area: the duration of the first HFP is less than the duration of the second HFP; and/or the duration of the first Hsync is less than the duration of the second Hsync; and/or the duration of the first HBP is less than the duration of the second HBP. When the first screen refresh rate is less than the second screen refresh rate, i.e., the screen refresh rate is increased, the duration of the first horizontal blank blanking area may be greater than the duration of the second horizontal blank blanking area: the duration of the first HFP is greater than the duration of the second HFP; and/or the duration of the first Hsync is greater than the duration of the second Hsync; and/or the duration of the first HBP is greater than the duration of the second HBP.

Alternatively, the MIPI timing control module 231 may obtain, based on the second screen refresh rate, a corresponding horizontal timing from the correspondence between the screen refresh rate and the horizontal timing as the second horizontal timing. Referring to table 3 below, if the second screen refresh rate is 90Hz, the durations of the second HFP, the second Hsync, and the second HBP in the corresponding second horizontal timing sequence may be 3 PCLK periods, as shown in fig. 7.

TABLE 3

Alternatively, the MIPI timing control module 231 may acquire a first horizontal timing corresponding to the first screen refresh, wherein the first horizontal timing includes a first horizontal blank blanking area including the first HFP, the first Hsync, and the first HBP, and a first active display area. Determining a screen refresh rate variation based on the first screen refresh rate and the second screen refresh rate, and determining a horizontal timing variation based on the screen refresh rate variation, the horizontal timing variation including N PCLK cycles. Wherein, the screen refresh rate variation is the first screen refresh rate to the second screen refresh rate. If the screen refresh rate variation amount is greater than 0, indicating that the screen refresh rate is to be decreased, the first HFP, the first Hsync, and the first HBP may be increased by M, P and Q PCLK cycles, respectively, based on the horizontal timing variation amount, resulting in the second HFP, the second Hsync, and the second HBP, where N, M, P and Q are integers, and M + P + Q is equal to N. That is, the N PCLK periods are inserted into at least one of the first HFP, the first Hsync, and the first HBP, thereby increasing the duration of the horizontal blank blanking area. Similarly, if the screen refresh rate variation is less than 0, which indicates that the screen refresh rate is increased, M, P cycles and Q cycles of PCLK may be respectively reduced for the first HFP, the first Hsync and the first HBP based on the horizontal timing variation, so as to obtain the second HFP, the second Hsync and the second HBP, that is, N cycles of PCLK are extracted from at least one of the first HFP, the first Hsync and the first HBP, thereby reducing the duration of the horizontal blank blanking area.

For example, the acquired first horizontal timing sequence is as shown in fig. 5, the durations of the first HFP, the first Hsync, and the first HBP are all 2 PCLK periods, the duration of the first horizontal blank blanking area is 6 PCLK periods, and the duration of the first active display area is 4 PCLK periods. As can be seen from comparison with fig. 7, the durations of the second HFP, the second Hsync, and the second HBP are respectively 1 PCLK cycle longer than the durations of the first HFP, the first Hsync, and the first HBP, the duration of the second horizontal timing is 3 PCLK cycles longer than the duration of the first horizontal timing, and the duration of the first effective display area is the same as the duration of the second effective display area. Still alternatively, referring to fig. 8-10, a horizontal timing diagram is provided. In the second horizontal timing as shown in fig. 8, the duration of the second HFP is 3 PCLK cycles longer than the duration of the first HFP, and the first Hsync, the first HBP, and the first active display area are the same as the durations of the second Hsync, the second HBP, and the second active display area, respectively. In the second horizontal timing shown in fig. 9, the duration of the second Hsync is 3 PCLK cycles longer than the duration of the first Hsync, and the first HFP, the first HBP, and the first effective display area are the same as the durations of the second HFP, the second HBP, and the second effective display area, respectively. In the second horizontal timing shown in fig. 10, the duration of the second HBP is 3 PCLK longer than the duration of the first HBP, and the first HFP, the first Hsync, and the first effective display area are the same as the durations of the second HFP, the second Hsync, and the second effective display area, respectively.

S608, the MIPI timing control module 231 transmits the image data to the display unit 241 based on the second horizontal timing.

Here, the MIPI timing control module 231 may transmit, based on the MIPI interface 113, a plurality of pixels included in the first line of image data to the display unit 241 based on the first horizontal timing, and then transmit a plurality of pixels included in the second line of image data to the display unit 241 based on the first horizontal timing, … …, until a plurality of pixels included in the subsequent line of image data are transmitted.

Optionally, the MIPI timing control module 231 may also send a screen refresh rate switching notification to the display unit 241, the screen refresh rate switching notification being used to notify the display unit 241 that the current screen refresh rate is switched to the second screen refresh rate.

S609, the display unit 241 displays an image based on the received image data.

The display unit 241 may receive a plurality of pixels included in the first line of image data based on the first horizontal timing, and control the display panel 121 to display … … the first line of image data, until the last line of image data is displayed, the display panel 121 may completely display the image corresponding to the second image data.

It should be noted that the steps of S605-S606 setting the current physical clock and voltage of the DSS112 and the steps of S607-S609 performing image data transmission and display based on the current screen refresh rate may be performed independently.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

Based on the same inventive concept, referring to fig. 11, an embodiment of the present application further provides an apparatus 1100 for sending image data, where the apparatus 1100 may be disposed in the SOC110 of the electronic device 100, and the apparatus 1100 includes:

the processing module 1101 is configured to switch a horizontal timing for sending image data to the display module from a first horizontal timing to a second horizontal timing when the screen refresh rate is switched from a first screen refresh rate to a second screen refresh rate, where the first screen refresh rate is greater than the second screen refresh rate;

the first horizontal time sequence comprises a first horizontal blank blanking area and a first effective display area;

Optionally, the first horizontal blank blanking area includes a first HFP, a first Hsync, and a first HBP, and the second horizontal blank blanking area includes a second HFP, a second Hsync, and a second HBP;

Optionally, the processing module is further configured to:

determining a horizontal timing variation based on the screen refresh rate variation, wherein the horizontal timing variation is N PCLK periods;

respectively increasing M, P cycles and Q PCLK cycles of the first HFP, the first Hsync and the first HBP based on the horizontal time sequence variation to obtain a second HFP, a second Hsync and a second HBP;

wherein N, M, P and Q are integers, and M + P + Q ═ N.

Optionally, the processing module is further configured to:

when the current screen refresh rate is determined to be switched from a first screen refresh rate to a second screen refresh rate, determining a first power consumption parameter corresponding to the second screen refresh rate;

and setting the current power consumption parameter of the DSS as a first power consumption parameter, wherein the power consumption indicated by the first power consumption parameter is lower than the power consumption indicated by a second power consumption parameter corresponding to the first screen refresh rate.

Optionally, the processing module is further configured to:

the image synthesis information comprises at least one of the number of layers and the total number of pixels of the layers;

a second power consumption parameter is determined based on the second screen refresh rate and the image composition information.

setting a physical clock of the DSS to the first physical clock when the second power consumption parameter includes the first physical clock;

when the second power consumption parameter includes the first voltage, the voltage of the DSS is set to the first voltage.

Optionally, the processing module is further configured to:

acquiring at least one layer;

and synthesizing at least one image layer to obtain image data.

Optionally, the apparatus further comprises a sending module, configured to:

and sending a screen refresh rate switching notice to the display module, wherein the screen refresh rate switching notice is used for indicating that the current screen refresh rate is switched to a second screen refresh rate.

The apparatus 1100 for sending image data provided in this embodiment can perform the above method embodiments, and the implementation principle and the technical effect are similar, and are not described herein again.

Based on the same inventive concept, the embodiment of the application further provides an electronic device 1200. Fig. 12 is a schematic structural diagram of an electronic device 1200 provided in the embodiment of the present application, and as shown in fig. 12, the electronic device 1200 provided in the embodiment includes: a memory 1210 and a processor 1220, the memory 1210 for storing computer programs; the processor 1220 is used for executing the methods of the above-described method embodiments when calling the computer program.

The electronic device 1200 provided in this embodiment may perform the above method embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.

Based on the same inventive concept, the embodiment of the application also provides a chip system. The chip system comprises a processor coupled to a memory, the processor executing a computer program stored in the memory to implement the method of the first aspect or any of the embodiments of the first aspect.

Embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the method described in the above method embodiments.

The embodiment of the present application further provides a computer program product, which when run on the electronic device 1200, enables the electronic device 1200 to implement the method described in the above method embodiment when executed.

The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable storage medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer memory, read-only memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunication signals, and software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/device and method may be implemented in other ways. For example, the above-described apparatus/device embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of transmitting image data, comprising:

a pixel clock PCLK period in the first horizontal timing is the same as a PCLK period in the second horizontal timing;

2. The method of claim 1, wherein the first horizontal blank blanking region includes a first horizontal leading edge HFP, a first horizontal synchronization signal Hsync, and a first horizontal trailing edge HBP, and wherein the second horizontal blank blanking region includes a second HFP, a second Hsync, and a second HBP;

3. The method according to claim 2, wherein before the switching the horizontal timing of sending the image data to the display module from the first horizontal timing to the second horizontal timing, further comprising:

wherein N, M, P and Q are integers, and M + P + Q ═ N.

4. The method of any of claims 1-3, further comprising:

5. The method of claim 4, further comprising:

6. The method according to claim 4 or 5, wherein the setting of the current power consumption parameter of the DSS as the first power consumption parameter comprises at least one of:

7. The method of any of claims 1-6, further comprising:

acquiring at least one layer;

and synthesizing the at least one image layer to obtain the image data.

8. The method of any of claims 1-7, further comprising:

9. An apparatus for transmitting image data, comprising:

10. The apparatus of claim 9, wherein the first horizontal blank blanking region comprises a first HFP, a first Hsync, and a first HBP, and wherein the second horizontal blank blanking region comprises a second HFP, a second Hsync, and a second HBP;

11. The apparatus of claim 10, wherein the processing module is further configured to:

wherein N, M, P and Q are integers, and M + P + Q ═ N.

12. The apparatus of any of claims 9-11, wherein the processing module is further configured to:

13. The apparatus of claim 12, wherein the processing module is further configured to:

14. The apparatus according to any one of claims 9-13, further comprising a sending module configured to:

15. An electronic device, comprising: a memory for storing a computer program and a processor; the processor is adapted to perform the method of any of claims 1-8 when the computer program is invoked.

16. A chip system, characterized in that the chip system comprises a processor coupled with a memory, the processor executing a computer program stored in the memory to implement the method according to any of claims 1-9.