CN116320248B - Memory chip sharing system, method, related device and storage medium - Google Patents
Memory chip sharing system, method, related device and storage medium Download PDFInfo
- Publication number
- CN116320248B CN116320248B CN202310562410.4A CN202310562410A CN116320248B CN 116320248 B CN116320248 B CN 116320248B CN 202310562410 A CN202310562410 A CN 202310562410A CN 116320248 B CN116320248 B CN 116320248B
- Authority
- CN
- China
- Prior art keywords
- chip
- memory
- display
- built
- memory chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Computer Graphics (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the application discloses a memory chip sharing system, a memory chip sharing method, a related device and a memory medium, wherein the memory chip sharing system comprises: the chip is used for receiving the image signal in the first format and converting the image signal in the first format into the image signal in the second format supported by the display chip, the chip is also used for transmitting the image signal in the second format to the display chip, the chip comprises a built-in memory chip, the built-in memory chip is connected with the display chip, the built-in memory chip is used for storing first data required by the running program of the display chip, and the built-in memory chip is also used for storing second data required by the running program of the chip. Therefore, the storage chip can be arranged in the chip, and the storage chip can store data required by the chip and the display chip at the same time, and the chip and the display chip are not required to be hung with one storage chip, so that the utilization rate of storage space is improved, and the data caching pressure and the hardware cost are reduced.
Description
Technical Field
The present application relates to the field of storage, and in particular, to a system, a method, a related device, and a storage medium for sharing a storage chip.
Background
At present, a touch control and display drive integrated TDDI chip often adopts a plug-in flash memory chip mode, so that the plug-in flash is easy to crack and copy, the safety coefficient is low, a display processing chip Scaler chip also often adopts the plug-in flash memory chip mode, and the BOM cost of a bill of materials generated by adopting the plug-in flash memory chip is too high.
Disclosure of Invention
The embodiment of the application provides a memory chip sharing system, a memory chip sharing method, a related device and a memory medium, which can realize that the memory chip is arranged in a chip, and the memory chip can simultaneously store data required by the chip and a display chip without the need of externally hanging one memory chip on each of the chip and the display chip, thereby being beneficial to improving the utilization rate of a memory space and reducing the data caching pressure and the hardware cost.
In a first aspect, an embodiment of the present application provides a memory chip sharing system, including:
the chip is connected with the display chip and is used for receiving the image signal in the first format, converting the image signal in the first format into the image signal in the second format supported by the display chip and transmitting the image signal in the second format to the display chip;
the chip comprises a built-in memory chip, the built-in memory chip is connected with the display chip, and the built-in memory chip is used for storing first data required by the running program of the display chip and storing second data required by the running program of the chip;
the display chip is used for acquiring the first data from the built-in memory chip.
In a second aspect, a memory chip sharing apparatus includes:
a substrate connected with the chips in the memory chip sharing system and used for transmitting the image signals in the first format to the chips;
the memory chip shares a system; the memory chip sharing system includes: the chip is connected with the display chip and is used for converting the image signal in the first format into the image signal in the second format supported by the display chip and transmitting the image signal in the second format to the display chip; the chip comprises a built-in memory chip, the built-in memory chip is connected with the display chip, and the built-in memory chip is used for storing first data required by the running program of the display chip and storing second data required by the running program of the chip; the display chip is connected with the display screen and is used for acquiring the first data from the built-in memory chip and transmitting the image signal in the second format to the display screen;
and the display screen is used for generating an image for display, which corresponds to the image signal in the second format.
In a third aspect, a memory chip sharing method is applied to a memory chip sharing system, where the memory chip sharing system includes: the chip comprises a built-in memory chip; the chip is connected with the display chip, and the built-in memory chip is connected with the display chip;
the memory chip sharing method comprises the following steps:
receiving an image signal in a first format through the chip, converting the image signal in the first format into an image signal in a second format supported by the display chip through the chip, and transmitting the image signal in the second format to the display chip through the chip;
storing first data required by the running program of the display chip through the built-in memory chip, and storing second data required by the running program of the chip through the built-in memory chip;
and acquiring the first data from the built-in memory chip through the display chip.
In a fourth aspect, an embodiment of the present application provides an electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing part or all of the steps as described in the third aspect of the embodiment of the present application.
In a fifth aspect, embodiments of the present application provide a computer-readable storage medium storing a computer program for electronic data exchange, where the computer program causes a computer to perform some or all of the steps described in the method of the third aspect of the embodiments of the present application.
It can be seen that, in the embodiment of the present application, the chip is configured to convert the received image signal in the first format into the image signal in the second format that can be supported by the display chip, and transmit the image signal in the second format to the display chip, where the chip includes a built-in memory chip, and the built-in memory chip is configured to store first data required by the running program of the display chip, and store second data required by the running program of the chip. Therefore, the memory chip can be arranged in the chip, the data required by running programs of the chip and the display chip can be stored simultaneously by the built-in memory chip, and the chip and the display chip are not required to be hung with one memory chip, so that the memory space utilization rate is improved, and the data caching pressure and the hardware cost are reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1a is a schematic diagram of a memory chip sharing system 100c according to an embodiment of the present application;
FIG. 1b is a schematic diagram illustrating another memory chip sharing system 100c according to an embodiment of the present application;
FIG. 1c is a schematic diagram illustrating another memory chip sharing system 100c according to an embodiment of the present application;
FIG. 1d is a schematic diagram illustrating another memory chip sharing system 100c according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a memory chip sharing device 100b according to an embodiment of the present application;
fig. 3 is a flow chart of a memory chip sharing method according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
1) The electronic device according to the embodiment of the present application may include various handheld devices, vehicle-mounted devices, wearable devices, computing devices or other processing devices connected to a wireless modem, and various forms of User Equipment (UE), mobile Station (MS), terminal devices (terminal devices), and so on. For convenience of description, the above-mentioned devices are collectively referred to as electronic devices.
2) The TDDI (touch and display driver integration, touch and Display Driver) controls both the touch and display functions of the smart phone by two independent chips, and the TDDI integrates the touch chip and the display chip into a single chip.
3) The flash chip is one of memory chips, and can modify data inside through a specific program, and at present, the flash chip mainly comprises two NOR flash chips and NAND flash chips, belongs to a nonvolatile flash memory technology, and has the characteristics of large capacity and high reading and writing speed.
At present, the TDDI chip usually adopts a plug-in flash memory chip, and the display processing chip Scaler chip also usually adopts a plug-in flash memory chip, so that the cost of the plug-in flash chip, the Bill of materials (Bill of materials) is too high, and the stored data is easily copied and cracked due to the adoption of the plug-in flash memory chip.
In view of the foregoing, the present application provides a memory chip sharing system, a method, a related device and a storage medium, and the detailed description is given below.
Referring to fig. 1a, fig. 1a is a schematic architecture diagram of a memory chip sharing system 100c according to an embodiment of the application, where the memory chip sharing system 100c includes:
a chip 10 connected to the display chip 20 for receiving an image signal of a first format, converting the image signal of the first format into an image signal of a second format supported by the display chip 20, and transmitting the image signal of the second format to the display chip 20;
the chip 10 comprises a built-in memory chip 11, the built-in memory chip 11 is connected with the display chip 20, and the built-in memory chip 11 is used for storing first data required by the running program of the display chip 20 and second data required by the running program of the chip 10;
the display chip 20 is configured to obtain the first data from the built-in memory chip 11.
The chip 10 is a signal processing chip, which can convert the format of the received image signal, and the display chip 20 is a chip with both touch control function and display function; in the case that the screen of the electronic device newly replaced by the user is a non-original screen, the formats of the image signals supported by the original substrate of the electronic device and the display chip 20 and the substrate are different, specifically, the formats, resolutions, frame rates and the like of the supported image signals are different, which causes that the display chip 20 and the original substrate cannot be adapted, further, the replaced screen cannot normally display images, for example, when the original substrate supports high-resolution (for example, 1440×3200) and high-frame-rate (for example, 90 HZ) MIPI (Mobile Industry Processor Interface) signals, and the non-original screen only supports low-resolution (for example, 720×1560) and low-frame-rate (for example, 60 HZ) MIPI signals, and at this time, the substrate transmits high-resolution and high-frame-rate MIPI signals to the display chip 20, and the display chip 20 cannot support corresponding images, so the non-original device screen cannot display corresponding images. The chip 10 can convert the received image signal in the first format transmitted from the substrate into the image signal in the second format supported by the display chip 20, so as to establish a connection between the substrate and the display chip 20, so that the substrate and the display chip 20 can be adapted, and the electronic device can normally display images. In some specific embodiments, the chip 10 may be a Scaler chip, the display chip 20 may be a touch and display driver integrated TDDI chip, the image signal may be a MIPI signal, and the Scaler chip is a chip for performing image processing such as image decompression, video format, resolution and refresh rate conversion, and image quality enhancement.
For example, when the electronic device is a mobile phone, it may be considered that in the market where the mobile phone is mature, the brands and models of the mobile phones are many, and although most of the mobile phone substrates of different types of mobile phones transmit signals according to the MIPI protocol, there are differences (resolution, frame rate, format, etc.) in signal content, the chip 10 can analyze the image signals transmitted by the mobile phone substrates of different mobile phone models, and can establish a connection with the display chip 20, and convert the image signals of the first format into the image signals of the second format supported by the display chip 20, thereby establishing a connection between the display chip 20 in the original mobile phone substrate and the non-original screen, and realizing normal display of pictures and videos of the mobile phone after the screen is replaced.
The built-in memory chip 11 is disposed inside the chip 10, and may be used to store both codes required by the chip 10 to run a program, i.e., the second data, and codes required by the display chip 20 to run the program, i.e., the first data, where the first data may include codes required by the display chip 20 to run the program for adapting to different signals of the substrate, and in some specific embodiments, the built-in memory chip 11 may be a flash chip.
It can be seen that, in the embodiment of the present application, the chip 10 is configured to convert the received image signal in the first format into the image signal in the second format that can be supported by the display chip 20, and transmit the image signal in the second format to the display chip 20, and the chip 10 includes the built-in memory chip 11, and the built-in memory chip 11 is configured to store the first data required for the display chip 20 to run the program, and store the second data required for the chip 10 to run the program. In this way, the memory chip can be arranged inside the chip 10, and the memory chip can simultaneously store data required by running programs of the chip 10 and the display chip 20, and one memory chip is not required to be hung outside each of the chip 10 and the display chip 20, so that the memory space utilization rate is improved, and the data caching pressure and the hardware cost are reduced.
In one possible example, the built-in memory chip 11 includes a first memory area 111 and a second memory area 112, the first memory area 111 is connected to the display chip 20, and the first memory area 111 is used for storing the first data;
the second storage area 112 is used for storing the second data.
Referring to fig. 1b, fig. 1b is a schematic diagram of an architecture of another memory chip sharing system 100c according to an embodiment of the present application, where a chip 10 includes a built-in memory chip 11, the built-in memory chip 11 includes a first memory area 111 and a second memory area 112, the chip 10 is connected to a display chip 20, the first memory area 111 is connected to the display chip 20, specifically, the first memory area 111 may store first data, the display chip 20 accesses the built-in memory chip 11 by accessing the built-in memory chip 11, and the chip 10 accesses the built-in memory chip 11 and obtains second data from the second memory area 112 when running a program.
Alternatively, the first storage area 111 may be connected to the display chip 20 through a serial peripheral interface SPI interface, and the display chip 20 may access the built-in storage chip 11 through the serial peripheral interface SPI interface when running a program, and obtain the first data from the first storage area 111.
In this example, the chip 10 includes the built-in memory chip 11, and the built-in memory chip 11 can distinguish different memory areas to store the data needed by the chip 10 and the display chip 20 respectively, so that compared with the chip 10 and the display chip 20, one memory chip is hung externally, which is beneficial to improving the utilization rate of the memory space and reducing the data caching pressure and the hardware cost.
In one possible example, the built-in memory chip 11 corresponds to a default usage mode and an external usage mode;
the display chip 20 is configured to acquire the first data in the first storage area 111 in the external use mode of the built-in memory chip 11; the chip 10 is configured to acquire the second data in the second storage area 112 in the default usage mode of the built-in memory chip 11.
In general, the built-in memory chip 11 allows only one of the chip 10 and the display chip 20 to access at the same time, and in order to avoid the access conflict between the chip 10 and the display chip 20 accessing the built-in memory chip 11, the frequency of use of the built-in memory chip 11 can be controlled by a time division multiplexing mode.
Specifically, in one possible embodiment, the chip 10 may set a default usage mode and an external usage mode of the internal memory chip 11, and the internal memory chip 11 is set to the default usage mode when the internal memory chip 11 is started, only the chip 10 may access the internal memory chip 11, after the chip 10 accesses the internal memory chip 11 and obtains the second data from the second memory area 112, the chip 10 controls the internal memory chip 11 to switch the default usage mode to the external usage mode, the chip 10 may simultaneously send the storage usage information to the display chip 20, and after the display chip 20 receives the storage usage information that may access the internal memory chip 11, the display chip 20 accesses the internal memory chip 11 and obtains the first data from the first memory area 111.
In this example, the display chip 20 and the chip 10 can access the built-in memory chip 11 in a time-sharing manner, so that the defect that the display chip 20 and the chip 10 cannot operate the program due to access conflict in time is avoided, and the scheme can effectively maintain the stability of the program operation of the display chip 20 and the chip 10.
In one possible example, the chip 10 is connected to the display chip 20 through a pin, the chip 10 is used to switch the default usage mode of the built-in memory chip 11 to the external usage mode, and to transmit memory usage information to the display chip 20 through the pin; the display chip 20 is configured to acquire the first data from the first storage area 111 after receiving the storage usage information.
Referring to fig. 1c, fig. 1c is a schematic diagram of an architecture of another memory chip sharing system 100c according to an embodiment of the present application, where chips 10 and display chips 20 may be connected by pins, in some specific embodiments, pins may be Reset pins, and chips 10 may send a Reset signal, that is, memory usage information, to display chips 20 by pulling down pulses of the Reset pins and then pulling up pulses of the Reset pins according to timing requirements of display chips 20, and after receiving the memory usage information that may access built-in memory chips 11, display chips 20 may access built-in memory chips 11 to obtain first data from first memory area 111.
Note that switching between the default use mode and the external use mode of the built-in memory chip 11 may be controlled by the chip 10, while the chip 10 may control transmission of the memory usage information that the display chip 20 may access the built-in memory chip 11 to the display chip 20.
In this example, the chip 10 controls to realize the time-sharing access of the display chip 20 and the chip 10 to the built-in memory chip, so that the defect that the display chip 20 and the chip 10 cannot operate the program due to the time access conflict is avoided, and the scheme can effectively maintain the stability of the program operation of the display chip 20 and the chip 10.
In one possible example, the display chip 20 corresponds to a chip identifier, and the chip 10 is configured to obtain the chip identifier, and further configured to determine, according to the chip identifier, a second format supported by the display chip 20.
When the display screen of the actual electronic device is damaged and replaced, there are often a plurality of display screens with different prices for selection, and the image formats supported by the display chips 20 in the display screens with different prices are different, so that the chip 10 is required to determine the format of the image signals supported by the display chips.
Specifically, the chip 10 stores a reference format set of a correspondence between the chip identifier and the second format, after the connection between the chip 10 and the display chip 20 is established, the chip 10 may obtain the chip identifier of the display chip 20, and then the chip 10 may query the reference format set according to the chip identifier, and further query the second format corresponding to the chip identifier of the display chip 20.
In this example, the chip 10 can determine the second format supported by the display chip 20, and further establish a connection between the substrate of the electronic device and the display chip 20 by converting the image signal format, so as to realize a normal image display function of the electronic device, which is beneficial to improving usability of the display chip 20.
In a possible example, the built-in memory chip 11 further includes a key storage area 113, where the key storage area 113 is connected to the display chip 20, the key storage area 113 is used to store a target key, and the display chip 20 is used to obtain the target key from the key storage area 113.
Referring to fig. 1d, fig. 1d is a schematic diagram of an architecture of another memory chip sharing system 100c according to an embodiment of the present application, where the built-in memory chip 11 includes a first memory area 111, a second memory area 112, and a key memory area 113, and the key memory area 113 is used for storing a target key required for normal start of the display chip 20.
Specifically, in one example, when the display chip 20 is started, the built-in memory chip 11 may be accessed through the SPI interface to obtain the target key in the key storage area 113, and when the target key is the same as the first key calculated by the display chip 20, the display chip 20 is started to operate normally, otherwise, the program is locked, and the display chip 20 cannot be started normally.
It can be seen that, in this example, the built-in memory chip 11 divides the key storage area 113 to store the target key required for the start-up of the display chip 20, which is beneficial to improving the safety of the start-up of the display chip 20.
In a possible example, the first storage area 111 corresponds to a first storage identifier, the second storage area 112 corresponds to a second storage identifier, the key storage area 113 corresponds to a third storage identifier, and the chip 10 is configured to send the first storage identifier and the third storage identifier to the display chip 20;
the display chip 20 is configured to identify the first storage area 111 according to the first storage identifier, and identify the key storage area 113 according to the third storage identifier.
The chip 10 sends the first storage identifier and the third storage identifier to the display chip 20, the display chip 20 identifies the first storage area 111 according to the first storage identifier, obtains the first data from the first storage area 111, identifies the key storage area 113 according to the third storage identifier, obtains the target key from the key storage area 113, and the chip 10 obtains the second data from the second storage area 112 according to the second storage identifier.
It can be seen that, in this example, the first storage area 111, the second storage area 112, and the key storage area 113 each correspond to a storage area identifier, which is beneficial to improving accuracy of accessing the built-in storage chip 11 by the chip 10 and the display chip 20 and acquiring corresponding data.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory chip sharing device 100b according to an embodiment of the application, where the memory chip sharing device 100b includes:
a memory chip sharing system 100c as described above;
a substrate 30 connected to the chips 10 in the memory chip sharing system for transmitting an image signal of a first format to the chips 10;
and a display screen 40 connected with the display chip 20 in the memory chip sharing system, and used for generating a corresponding image for display by the image signal in the second format transmitted by the display chip 20.
In a specific embodiment, the substrate 30 is connected to the chips 10 in the memory chip sharing system 100c, and is configured to transmit the image signal in the first format to the chips 10;
the memory chip sharing system 100c; the memory chip sharing system 100c includes: the chip 10 is connected to the display chip 20, and is configured to convert the image signal in the first format into an image signal in a second format supported by the display chip 20, and transmit the image signal in the second format to the display chip 20; the chip 10 comprises a built-in memory chip 11, the built-in memory chip 11 is connected with the display chip 20, and the built-in memory chip 11 is used for storing first data required by the running program of the display chip 20 and second data required by the running program of the chip 10; the display chip 20 is connected to the display screen 40, and is configured to obtain the first data from the built-in memory chip 11, and transmit the image signal in the second format to the display screen 40;
the display screen 40 is configured to generate an image for display corresponding to the image signal in the second format.
It can be seen that, in the embodiment of the present application, the substrate 30 in the memory chip sharing device 100b is used for transmitting the image signal in the first format to the chip 10 in the memory chip sharing system 100c, the chip 10 is used for converting the image signal in the first format into the image signal in the second format supported by the display chip 20, and transmitting the image signal in the second format to the display chip 20, the chip 10 includes the built-in memory chip 11, the built-in memory chip 11 is connected to the display chip 20, the built-in memory chip 11 is used for storing the first data required by the running program of the display chip 20, the display chip 20 is used for acquiring the first data from the built-in memory chip 11, the built-in memory chip 11 is also used for storing the second data required by the running program of the chip 10, the display chip 20 is used for transmitting the image signal in the second format to the display screen 40, and the display screen 40 is used for generating the image for display according to the image signal in the second format. In this way, the memory chip can be set inside the chip 10 in the memory chip sharing system 100c, and the memory chip can simultaneously store data required by running programs of the chip 10 and the display chip 20, without the need of externally hanging one memory chip on each of the chip 10 and the display chip 20, which is beneficial to improving the utilization rate of memory space and reducing the data caching pressure and hardware cost.
In one possible example, the built-in memory chip 11 includes a first memory area and a second memory area, the first memory area being connected to the display chip 20, the first memory area being for storing the first data;
the second storage area is used for storing the second data.
In one possible example, the built-in memory chip 11 corresponds to a default usage mode and an external usage mode;
the display chip 20 is configured to acquire the first data in the first storage area in the external use mode of the built-in memory chip;
the chip is used to acquire the second data in the second storage area in the default usage mode of the built-in memory chip 11.
In one possible example, the chip 10 is connected to the display chip 20 through a pin, the chip 10 is used to switch the default usage mode of the built-in memory chip 11 to the external usage mode, and to transmit memory usage information to the display chip 20 through the pin;
the display chip 20 is configured to acquire the first data from the first storage area after receiving the storage usage information.
In one possible example, the display chip 20 corresponds to a chip identifier, and the chip 10 is configured to obtain the chip identifier, and determine, according to the chip identifier, a second format supported by the display chip 20.
In one possible example, the built-in memory chip 11 further includes a key storage area, where the key storage area is connected to the display chip 20, the key storage area is used to store a target key, and the display chip 20 is used to obtain the target key from the key storage area.
In one possible example, the first storage area corresponds to a first storage identifier, the second storage area corresponds to a second storage identifier, the key storage area corresponds to a third storage identifier, and the chip 10 is configured to send the first storage identifier and the third storage identifier to the display chip 20;
the display chip 20 is configured to identify the first storage area according to the first storage identifier, and identify the key storage area according to the third storage identifier.
Referring to fig. 3, fig. 3 is a flow chart of a memory chip sharing method according to an embodiment of the application, where the memory chip sharing system includes: a chip 10 and a display chip 20, the chip 10 including a built-in memory chip 11; the chip 10 is connected with the display chip 20, and the built-in memory chip 11 is connected with the display chip 20;
the memory chip sharing method comprises the following steps:
step S301 of receiving an image signal in a first format through the chip 10, converting the image signal in the first format into an image signal in a second format supported by the display chip 20 through the chip 10, and transmitting the image signal in the second format to the display chip 20 through the chip 10;
step S302, storing first data required by the running program of the display chip 20 through the built-in memory chip 11, and storing second data required by the running program of the chip 10 through the built-in memory chip 11;
step S303, acquiring the first data from the built-in memory chip 11 through the display chip 20.
It can be seen that, in the embodiment of the present application, the memory chip sharing system 100c may receive the image signal in the first format through the chip 10, convert the image signal in the first format into the image signal in the second format supported by the display chip 20 through the chip 10, transmit the image signal in the second format to the display chip 20 through the chip 10, store the first data required by the display chip 20 to run the program through the built-in memory chip 11, store the second data required by the chip 10 to run the program through the built-in memory chip 11, and finally acquire the first data from the built-in memory chip 11 through the display chip 20. Thus, the chip 10 can be internally provided with the memory chip, and the memory chip can simultaneously store data required by the chip 10 and the display chip 20 without externally hanging one memory chip on each of the chip 10 and the display chip 20, thereby being beneficial to improving the utilization rate of memory space and reducing the data caching pressure and the hardware cost.
In one possible example, the built-in memory chip 11 includes a first memory area 111 and a second memory area 112, the first memory area 111 is connected to the display chip 20, and the first memory area 111 is used for storing the first data;
the second storage area 112 is used for storing the second data.
In one possible example, the built-in memory chip 11 corresponds to a default usage mode and an external usage mode;
the display chip is configured to acquire the first data in the first storage area 111 in the external use mode of the built-in memory chip 11;
the chip is used to acquire the second data in the second storage area 112 in the default usage mode of the built-in memory chip 11.
In one possible example, the chip 10 is connected to the display chip 20 through a pin, the chip 10 is used to switch the default usage mode of the built-in memory chip 11 to the external usage mode, and to transmit memory usage information to the display chip 20 through the pin;
the display chip 20 is configured to acquire the first data from the first storage area 111 after receiving the storage usage information.
In one possible example, the display chip 20 corresponds to a chip identifier, and the chip 10 is configured to obtain the chip identifier, and determine, according to the chip identifier, a second format supported by the display chip 20.
In a possible example, the built-in memory chip 11 further includes a key storage area 113, where the key storage area 113 is connected to the display chip 20, the key storage area 113 is used to store a target key, and the display chip 20 is used to obtain the target key from the key storage area 113.
In a possible example, the first storage area 111 corresponds to a first storage identifier, the second storage area 112 corresponds to a second storage identifier, the key storage area 113 corresponds to a third storage identifier, and the chip 10 is configured to send the first storage identifier and the third storage identifier to the display chip 20;
the display chip 20 is configured to identify the first storage area 111 according to the first storage identifier, and identify the key storage area 113 according to the third storage identifier.
The foregoing description of the embodiments of the present application has been presented primarily in terms of a method-side implementation. It will be appreciated that the electronic device, in order to achieve the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The embodiment of the application can divide the functional units of the electronic device according to the method example, for example, each functional unit can be divided corresponding to each function, and two or more functions can be integrated in one processing unit. The integrated units may be implemented in hardware or in software functional units. It should be noted that, in the embodiment of the present application, the division of the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice.
The embodiment of the application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program makes a computer execute part or all of the steps of any one of the above method embodiments, and the computer includes an electronic device.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, such as the above-described division of units, merely a division of logic functions, and there may be additional manners of dividing in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the above-mentioned method of the various embodiments of the present application. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and the program may be stored in a computer readable memory, which may include: flash disk, read-only memory, random access memory, magnetic or optical disk, etc.
The foregoing has outlined rather broadly the more detailed description of embodiments of the application, wherein the principles and embodiments of the application are explained in detail using specific examples, the above examples being provided solely to facilitate the understanding of the method and core concepts of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (7)
1. A memory chip sharing system, comprising:
the chip is connected with the display chip through a pin and is used for receiving the image signal in the first format, converting the image signal in the first format into the image signal in the second format supported by the display chip and transmitting the image signal in the second format to the display chip;
the chip comprises a built-in memory chip, the built-in memory chip is connected with the display chip, and the built-in memory chip is used for storing first data required by the running program of the display chip and storing second data required by the running program of the chip; the built-in memory chip comprises a first memory area and a second memory area, the first memory area is connected with the display chip, the first memory area is used for storing the first data, and the second memory area is used for storing the second data; the built-in memory chip is corresponding to a default use mode and an external use mode, and the chip is used for acquiring the second data in the second memory area under the default use mode of the built-in memory chip; the chip is used for switching the default use mode of the built-in memory chip into the external use mode and transmitting memory use information to the display chip through the pin;
the display chip is used for acquiring the first data from the first storage area in the external use mode of the built-in memory chip after receiving the memory use information.
2. The memory chip sharing system of claim 1, wherein the display chip corresponds to a chip identifier, and wherein the chip is configured to obtain the chip identifier, and determine the second format supported by the display chip according to the chip identifier.
3. The memory chip sharing system of claim 1, wherein the built-in memory chip includes a key storage area, the key storage area is connected to the display chip, the key storage area is used for storing a target key, and the display chip is used for obtaining the target key from the key storage area.
4. The memory chip sharing system according to claim 3, wherein the first memory area corresponds to a first memory identifier, the second memory area corresponds to a second memory identifier, the key memory area corresponds to a third memory identifier, and the chip is configured to send the first memory identifier and the third memory identifier to the display chip;
the display chip is used for identifying the first storage area according to the first storage identification, and identifying the key storage area according to the third storage identification.
5. A memory chip sharing apparatus, comprising:
a memory chip sharing system as claimed in any one of claims 1 to 4;
a substrate connected with the chips in the memory chip sharing system and used for transmitting the image signals in the first format to the chips;
and the display screen is connected with the display chip in the memory chip sharing system and is used for generating a corresponding image for display from the image signal in the second format transmitted by the display chip.
6. A memory chip sharing method, characterized in that it is applied to a memory chip sharing system, the memory chip sharing system comprising: the chip comprises a built-in memory chip; the chip is connected with the display chip through a pin, and the built-in memory chip is connected with the display chip;
the memory chip sharing method comprises the following steps:
receiving an image signal in a first format through the chip, converting the image signal in the first format into an image signal in a second format supported by the display chip through the chip, and transmitting the image signal in the second format to the display chip through the chip;
storing first data required by the running program of the display chip through the built-in memory chip, and storing second data required by the running program of the chip through the built-in memory chip, wherein the built-in memory chip comprises a first memory area and a second memory area, the first memory area is connected with the display chip, the first memory area is used for storing the first data, the second memory area is used for storing the second data, and the built-in memory chip corresponds to a default use mode and an external use mode;
acquiring the second data in the second storage area in the default use mode of the built-in memory chip through the chip; switching the default use mode of the built-in memory chip to the external use mode through the chip, and transmitting memory use information to the display chip through the pin;
after the display chip receives the storage use information, the first data is acquired from the first storage area through the display chip in the external use mode of the built-in storage chip.
7. A computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to execute a memory chip sharing method according to claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310562410.4A CN116320248B (en) | 2023-05-18 | 2023-05-18 | Memory chip sharing system, method, related device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310562410.4A CN116320248B (en) | 2023-05-18 | 2023-05-18 | Memory chip sharing system, method, related device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116320248A CN116320248A (en) | 2023-06-23 |
| CN116320248B true CN116320248B (en) | 2023-08-29 |
Family
ID=86796308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310562410.4A Active CN116320248B (en) | 2023-05-18 | 2023-05-18 | Memory chip sharing system, method, related device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116320248B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101443675A (en) * | 2006-03-09 | 2009-05-27 | 欧洲太空署 | Receiver and emitter for satellite navigation system |
| CN208174848U (en) * | 2017-11-28 | 2018-11-30 | 中科亿海微电子科技（苏州）有限公司 | Big space of a whole page video monitoring apparatus based on FPGA |
| CN111193877A (en) * | 2019-08-29 | 2020-05-22 | 桂林电子科技大学 | ARM-FPGA (advanced RISC machine-field programmable gate array) cooperative wide area video real-time fusion method and embedded equipment |
| CN112419945A (en) * | 2019-08-23 | 2021-02-26 | 陕西坤同半导体科技有限公司 | Display test system and test method |
| CN216119515U (en) * | 2021-08-26 | 2022-03-22 | 南京初芯集成电路有限公司 | All-pass TFT screen control circuit |
| CN115002304A (en) * | 2022-04-12 | 2022-09-02 | 华东师范大学 | Video image resolution self-adaptive conversion device |
| CN116055779A (en) * | 2023-03-29 | 2023-05-02 | 深圳曦华科技有限公司 | Video mode chip data stream transmission time sequence control method and device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102519727B1 (en) * | 2016-08-02 | 2023-04-10 | 삼성전자주식회사 | A display driving method and a display driving circuit and an electronic device supporting the same |
| TWI683253B (en) * | 2018-04-02 | 2020-01-21 | 宏碁股份有限公司 | Display system and display method |
| CN114757872A (en) * | 2021-01-08 | 2022-07-15 | 长鑫存储技术有限公司 | Chip acquisition method and chip positioning method |
-
2023
- 2023-05-18 CN CN202310562410.4A patent/CN116320248B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101443675A (en) * | 2006-03-09 | 2009-05-27 | 欧洲太空署 | Receiver and emitter for satellite navigation system |
| CN208174848U (en) * | 2017-11-28 | 2018-11-30 | 中科亿海微电子科技（苏州）有限公司 | Big space of a whole page video monitoring apparatus based on FPGA |
| CN112419945A (en) * | 2019-08-23 | 2021-02-26 | 陕西坤同半导体科技有限公司 | Display test system and test method |
| CN111193877A (en) * | 2019-08-29 | 2020-05-22 | 桂林电子科技大学 | ARM-FPGA (advanced RISC machine-field programmable gate array) cooperative wide area video real-time fusion method and embedded equipment |
| CN216119515U (en) * | 2021-08-26 | 2022-03-22 | 南京初芯集成电路有限公司 | All-pass TFT screen control circuit |
| CN115002304A (en) * | 2022-04-12 | 2022-09-02 | 华东师范大学 | Video image resolution self-adaptive conversion device |
| CN116055779A (en) * | 2023-03-29 | 2023-05-02 | 深圳曦华科技有限公司 | Video mode chip data stream transmission time sequence control method and device |
Non-Patent Citations (1)
| Title |
|---|
| 盛磊,徐科军,赵明,陈智渊.液晶显示驱动板的设计与实现.电视技术.2005,(第02期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116320248A (en) | 2023-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102170781B1 (en) | Electronic device and method for processing image | |
| CN108702480B (en) | Electronic device and method for driving display thereof | |
| US9696958B2 (en) | Method and system for presenting content | |
| US9635268B2 (en) | Electronic device and method for generating thumbnail data | |
| US10237318B2 (en) | Electronic device and method for encoding image data thereof | |
| CN114205485B (en) | Method and device for sending image data | |
| CN107948724B (en) | Video transmission control method, device, storage medium and mobile terminal | |
| US10747489B2 (en) | Method for displaying content and electronic device therefor | |
| CN112764817A (en) | Equipment function awakening method and device | |
| CN114489529A (en) | Screen projection method of electronic device, medium thereof and electronic device | |
| US9456110B2 (en) | Method for improving video output definition and terminal device | |
| KR100663380B1 (en) | Imaging device and method for transferring image signal | |
| CN116320248B (en) | Memory chip sharing system, method, related device and storage medium | |
| CN109445876B (en) | Method and monitor for loading LUT data | |
| CN113934396A (en) | On-screen display method, device and system | |
| EP4206898A1 (en) | Mirroring method, apparatus and system | |
| CN114339966A (en) | Interface control method, device, medium and electronic equipment for data transmission | |
| CN115878058A (en) | Information processing method and device, cloud terminal, cloud server and storage medium | |
| CN113126869B (en) | Method and system for realizing KVM image high-speed redirection based on domestic BMC chip | |
| JP2000115732A (en) | Portable video telephone set | |
| CN110996013A (en) | Electronic device and method for processing image | |
| US9407938B2 (en) | Method for processing image and electronic device for the method | |
| CN117251125A (en) | Display control method, device, equipment and storage medium | |
| US20030210238A1 (en) | Digital image display stand, digital image display system, and use method of digital image display stand | |
| CN113099552A (en) | Pluggable equipment and screen transmission method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |