CN116798376A

CN116798376A - Display panel and driving method thereof

Info

Publication number: CN116798376A
Application number: CN202310962757.8A
Authority: CN
Inventors: 刘腾; 鲁文武
Original assignee: Suzhou China Star Optoelectronics Technology Co Ltd
Current assignee: Suzhou China Star Optoelectronics Technology Co Ltd
Priority date: 2023-08-02
Filing date: 2023-08-02
Publication date: 2023-09-22
Anticipated expiration: 2043-08-02
Also published as: CN116798376B

Abstract

The invention provides a display panel and a driving method thereof, wherein the method comprises the following steps: in a first stage, controlling a plurality of sub-pixels to display a first picture at a first refresh rate; in a second stage, controlling the plurality of sub-pixels to display a black picture; in a third stage thereafter, switching the first refresh rate to the second refresh rate; in a fourth stage thereafter, controlling the plurality of sub-pixels to be turned off; in a fifth stage thereafter, controlling the plurality of sub-pixels to display a second picture at a second refresh rate; the third stage and the fourth stage are arranged between the first stage and the fifth stage, so that the risk of the phenomenon of screen flashing or screen pattern is reduced.

Description

Display panel and driving method thereof

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a driving method thereof.

Background

The technical principle of the double-line grid (DualLineGate, DLG) is that the panel scans two lines of pixels at one time in each frame picture, the scanning times can be halved compared with progressive scanning, and the double-refresh rate effect can be achieved on the premise of not changing the original hardware and chip calculation force, so that the double-line grid is widely applied to large-size and high-refresh rate display panels.

However, when DLG technology is introduced, there is necessarily a refresh rate switching, and the timing controller is required to reinitialize the refresh rate switching, and because there is an uncontrollable state in the transient process of switching, particularly, a data signal for controlling the emission of the sub-pixels is interfered, so that the display picture is affected, a phenomenon of screen flashing or screen pattern appears at the moment of refresh rate switching, and the quality of the display picture is reduced.

Accordingly, the conventional display panel using DLG technology has the above-described problems, and improvements are urgently needed.

Disclosure of Invention

The embodiment of the invention provides a display panel and a driving method thereof, which are used for solving the technical problem that the existing display panel has a splash screen or a flower screen when the refresh rate is switched.

An embodiment of the present invention provides a driving method of a display panel, for driving the display panel, the display panel including a plurality of sub-pixels, the method including:

in a first stage, controlling a plurality of the sub-pixels to display a first picture at a first refresh rate;

in a second stage, controlling a plurality of sub-pixels to display a black picture, wherein the second stage is positioned after the first stage;

switching the first refresh rate to a second refresh rate in a third phase, the third phase being located after the second phase;

controlling a plurality of the subpixels to be turned off in a fourth stage, the fourth stage being located after the third stage;

and in a fifth stage, controlling a plurality of the sub-pixels to display a second picture at the second refresh rate, wherein the fifth stage is positioned after the fourth stage.

In an embodiment, in the second stage, the step of controlling the plurality of sub-pixels to display a black frame includes:

the control grid driving module outputs effective grid voltage to control a plurality of sub-pixels to be started;

and controlling the source electrode driving module to output a first black data voltage, wherein the first black data voltage is used for controlling a plurality of sub-pixels to display the black picture.

In an embodiment, the end time of the source driving module outputting the first black data voltage is later than the end time of the gate driving module outputting the effective gate voltage.

In an embodiment, the step of controlling the source driving module to output the first black data voltage includes:

and controlling the source driving module to alternately output a first sub-black data voltage and a second sub-black data voltage in the first black data voltage, wherein a reference data voltage is arranged between the first sub-black data voltage and the second sub-black data voltage, and the absolute value of the difference value of the first sub-black data voltage and the reference data voltage is equal to the absolute value of the difference value of the second sub-black data voltage and the reference data voltage.

In an embodiment, in the fifth stage, the step of controlling the plurality of sub-pixels to display the second picture at the second refresh rate includes:

controlling a source electrode driving module to output non-black data voltage, wherein the non-black data voltage is used for controlling a plurality of sub-pixels to display a non-black picture;

wherein in the fourth stage, the step of controlling the plurality of sub-pixels to be turned off includes:

controlling the grid driving module to output invalid grid voltage so as to control a plurality of sub-pixels to be closed;

and controlling the source electrode driving module to output a third black data voltage, wherein the third black data voltage is used for controlling a plurality of sub-pixels to display the black picture.

In an embodiment, the method further comprises:

in a sixth stage, the gate driving module is controlled to output the invalid gate voltage to control a plurality of the sub-pixels to be turned off, and the source driving module is controlled to output a second black data voltage, wherein the second black data voltage is used for controlling a plurality of the sub-pixels to display the black picture, an absolute value of a difference value between the second black data voltage and a reference voltage is smaller than an absolute value of a difference value between the first black data voltage and the reference voltage, and the sixth stage is located between the third stage and the fourth stage.

In an embodiment, before the step of controlling the source driving module to output the non-black data voltage, the method includes:

and controlling the source driving module to output a fourth black data voltage so as to control a plurality of the sub-pixels to display the black picture.

The embodiment of the invention also provides a display panel, which comprises:

a panel body including a plurality of sub-pixels;

a memory for storing program instructions;

the driving chip is electrically connected with the panel main body and the memory, and is used for executing the program instructions to realize the following steps:

In an embodiment, the driving chip includes a timing controller, and the panel body or the driving chip further includes at least one of a gate driving module and a source driving module electrically connected between the sub-pixel and the timing controller;

wherein, the time schedule controller is used for executing the following steps in the second stage:

controlling the grid driving module to output effective grid voltage so as to control a plurality of sub-pixels to be started;

The embodiment of the invention also provides another display panel which comprises a plurality of sub-pixels;

in a first stage, the plurality of sub-pixels display a first picture at a first refresh rate;

in a second stage, displaying black pictures by a plurality of the sub-pixels, wherein the second stage is positioned after the first stage;

switching from the first refresh rate to a second refresh rate in a third phase, the third phase being located after the second phase;

in a fourth stage, a plurality of the subpixels are turned off, the fourth stage being located after the third stage;

in a fifth stage, the plurality of sub-pixels display a second picture at the second refresh rate, the fifth stage being located after the fourth stage.

The invention provides a display panel and a driving method thereof, wherein the third stage and the fourth stage are arranged between the first stage and the fifth stage, the second stage is used for ensuring that the display panel displays a black picture in the second stage regardless of a first picture in the first stage, and the fourth stage is used for ensuring that a plurality of sub-pixels can be closed so as to prevent abnormal data signals from acting on the plurality of sub-pixels, and simultaneously ensuring that the plurality of sub-pixels still maintain the state of the second stage, namely are presented as the black picture, thereby reducing the risk of occurrence of a phenomenon of screen flashing or screen display.

Drawings

The invention is further illustrated by the following figures. It should be noted that the drawings in the following description are only for illustrating some embodiments of the invention, and that other drawings may be obtained from these drawings by those skilled in the art without the inventive effort.

Fig. 1, fig. 5, and fig. 6 are flowcharts of a driving method of a display panel according to an embodiment of the invention.

Fig. 2 is a block diagram of a display panel according to an embodiment of the present invention.

Fig. 3 and fig. 4 are waveform diagrams of clock signals and data signals in a display panel according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or modules but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Embodiments of the present invention provide a driving method of a display panel for driving the display panel, including but not limited to the following embodiments and combinations between the following embodiments.

In one embodiment, as shown in FIG. 1, the method includes steps that may include, but are not limited to, the following.

S1, in a first stage, controlling a plurality of sub-pixels to display a first picture at a first refresh rate.

In this embodiment, the type of the display panel is not limited, and the display panel may be, but is not limited to, a liquid crystal display panel. As shown in fig. 2, the display panel 100 may include a panel body 10, the panel body 10 may include a plurality of sub-pixels, a plurality of gate lines, and a plurality of data lines, each of the gate lines may be connected to a corresponding plurality of sub-pixels to simultaneously turn on the plurality of sub-pixels, and each of the data lines may be connected to a corresponding plurality of sub-pixels; in a frame, when a plurality of sub-pixels corresponding to the same gate line are turned on, each data line can respectively transmit corresponding data voltages to the corresponding sub-pixels, so that the corresponding plurality of sub-pixels are respectively loaded with the corresponding plurality of data voltages to respectively emit light rays with corresponding brightness at the same time, and each sub-pixel can keep emitting light in a frame through a storage capacitor in the corresponding pixel driving circuit so as to present the frame picture; and loading the data voltage corresponding to the next frame through the process in the next frame again so as to present the picture of the next frame.

Further, the display panel 100 may further include a timing controller 20, and a source driving module 30 electrically connected between the timing controller 20 and the plurality of data lines. The timing controller 20 may acquire an image signal and process the image signal to generate an initial data signal including a plurality of initial data voltages corresponding to a plurality of sub-pixels in each frame and transmit the initial data signal to the source driving module 30, and the source driving module 30 may process the initial data signal in combination with a gamma voltage to obtain a data signal and transmit a corresponding data signal, which may include a plurality of data voltages corresponding to a plurality of sub-pixels, to each data line. As shown in fig. 2, the timing controller 20 may load a refresh rate command to inform the display panel 100 of how much refresh rate should be used for displaying the images, and further the timing controller 20 needs to establish communication with the source driving module 30 to ensure that the signals can be sent and received normally, and then perform the above-mentioned operation of transmitting the initial data signal to the source driving module 30.

It will be appreciated that the refresh rate represents the number of frames of pictures that the display panel 100 is capable of displaying per second, typically in hertz (Hz), for example, a refresh rate of 60Hz means that the display panel 100 can display 60 frames of pictures per second. It should be noted that, for the refresh rate to be switched repeatedly, as discussed above, the timing controller 20 needs to load a new refresh rate repeatedly, which results in that the process of "the timing controller 20 needs to establish communication with the source driving module 30" needs to be repeated, but in this process, the timing controller 20 will affect the amplitude of the initial data signal when processing information, even affect the timing of the initial data signal, which results in that the initial data signal received by the source driving module 30 is abnormal, and at least one of the amplitude and the timing of the data voltage acting on the plurality of sub-pixels obtained by the final processing is also abnormal, which causes a splash or a splash phenomenon.

Further, as shown in fig. 2, the display panel 100 may further include a gate driving module 40 electrically connected between the timing controller 20 and the plurality of gate lines. The timing controller 20 may generate at least one clock signal CK and a vertical synchronization signal STV for transmission to the gate driving module 40, and the gate driving module 40 may include a plurality of gate driving units in cascade, each of which may be electrically connected to a corresponding gate line. Each clock signal CK may be loaded to a corresponding multi-stage gate driving unit, the first-stage gate driving unit may load a vertical synchronization signal STV, generate a first-stage gate signal under the action of the corresponding clock signal CK, and transmit the first-stage gate signal to a corresponding gate line and a next-stage gate driving unit, and so on, the subsequent gate driving unit may generate a corresponding gate signal under the action of the corresponding clock signal CK and the gate signal generated by the previous-stage gate driving unit, and transmit the corresponding gate signal to the corresponding gate line and the next-stage gate driving unit.

Still further, each gate signal may include a gate effective voltage located at a corresponding period, and the gate effective voltage in the previous gate signal may trigger the gate driving unit of the present stage to generate a corresponding gate effective voltage of the present stage (including the gate signal of the present stage), so that the multi-stage gate signals generated by the multi-stage gate driving unit may be considered as the multi-stage gate signals respectively, and the corresponding plurality of gate effective voltages may be sequentially output along the positive direction of the time axis, so as to sequentially turn on the plurality of sub-pixels respectively connected to the plurality of gate lines.

Particularly, in this embodiment, whether the waveform corresponding to the effective gate voltage is the same as the corresponding pulse in the corresponding clock signal CK is not limited, and it may be considered that the duration of the waveform corresponding to the effective gate voltage is at least equal to the pulse width of the corresponding pulse in the corresponding clock signal CK, and the amplitude of the waveform corresponding to the effective gate voltage may be equal to the amplitude of the corresponding pulse in the corresponding clock signal CK; however, it is considered that if there is no pulse in the clock signal CK corresponding to the gate driving unit, the gate driving unit stops working, that is, the output gate signal does not include the effective gate voltage, or the corresponding gate signal is not output, so that the corresponding plurality of sub-pixels are turned off.

Specifically, the first frame in step S1 of the present embodiment may include a plurality of first sub-frames, and the plurality of first sub-frames may be sequentially displayed at the first refresh rate, where it is not limited whether the plurality of first sub-frames are the same, for example, when the plurality of first sub-frames are different, the display panel 100 may be presented as a dynamic frame in the first stage, for example, when the plurality of first sub-frames are the same, the display panel 100 may be presented as a static frame in the first stage. Also, it is not limited here whether the first frame (i.e., the plurality of sub-frames therein) is a black frame, i.e., the display panel 100 may always present a black frame in the first stage.

As shown in fig. 3, in the first stage t1, each clock signal CK (only one is illustrated here) may include a pulse pl in each frame to control the operation of the multi-stage gate driving unit to control all the sub-pixels to be turned on, so as to be respectively loaded with a corresponding data voltage (referred to herein as a first data voltage data 1), and sequentially display a plurality of first sub-pictures at a first refresh rate, so as to be a complete first picture. The Data signal Data may be a generic term of signals transmitted by a plurality of Data lines, that is, the first Data voltage Data1 is included therein.

S2, in a second stage, controlling the plurality of sub-pixels to display a black picture, wherein the second stage is located after the first stage.

When the first frame displayed in the first stage is not a black frame, the plurality of sub-pixels are considered to be not illuminated by the corresponding data voltages in the second stage, so that the display panel 100 always presents a black frame in the second stage. Specifically, as shown in fig. 5, step S2 may include, but is not limited to, the following steps.

S21, the control grid driving module outputs effective grid voltage so as to control a plurality of sub-pixels to be started.

Based on the above discussion, it can be understood that, as shown in fig. 3, each clock signal CK (only one is illustrated here) may include a pulse pl in the second stage t2 by controlling the multi-stage gate driving units in the gate driving module to operate so as to sequentially output a plurality of effective gate voltages to sequentially turn on a plurality of sub-pixels respectively connected to a plurality of gate lines.

S22, controlling the source electrode driving module to output a first black data voltage, wherein the first black data voltage is used for controlling the plurality of sub-pixels to display the black picture.

In connection with the above discussion, based on the sequential turn-on of the plurality of sub-pixels respectively connected to the plurality of gate lines, as shown in fig. 3, it is further required to further control the source driving module to transmit the plurality of data voltages corresponding to the plurality of sub-pixels of each gate line, specifically, the first black data voltage data2, to the plurality of data lines during the turn-on period of the plurality of sub-pixels corresponding to each gate line, where the first black data voltage data2 is understood to be used to control the sub-pixels not to emit light so that the picture is a black picture.

Therefore, at this time, it can be considered that in the second stage t2, it is equivalent to turning on the plurality of sub-pixels again to load the plurality of sub-pixels with the first black data voltage data2 different from the first data voltage data1 in the first stage, so that the display panel 100 can present a black screen in the second stage t 2.

Further, as shown in fig. 3, the end time of the source driving module 30 outputting the first black data voltage data2 is later than the end time of the gate driving module 40 outputting the effective gate voltage (i.e. the end time of the pulse pl in the corresponding clock signal CK). It can be understood that in this case, in the process of turning on the plurality of sub-pixels, the corresponding plurality of first black data voltages data2 can be fully loaded to the corresponding plurality of sub-pixels, so as to reduce the risk of insufficient charging caused by early termination of the first black data voltages data 2.

When the first frame displayed in the first stage is a black frame, the plurality of sub-pixels are considered to be turned on in the second stage, and are not illuminated by the corresponding first black data voltage data2, so that the display panel 100 always presents the black frame in the second stage (refer to steps S21 to S22 in detail), and of course, in conjunction with the discussion about the gate driving module, the gate driving module (different from that described in fig. 3) may also be considered to be turned off in the second stage to maintain the first frame (black frame) displayed in the first stage.

In an embodiment, as shown in fig. 3, the step of controlling the source driving module to output the first black data voltage in step S22 may include, but is not limited to, the following steps: the source driving module is controlled to alternately output a first sub-black data voltage and a second sub-black data voltage in the first black data voltage, the reference data voltage data0 is between the first sub-black data voltage and the second sub-black data voltage, and the absolute value of the difference value between the first sub-black data voltage and the reference data voltage data0 and the absolute value of the difference value between the second sub-black data voltage and the reference data voltage data0 are equal.

Specifically, the display panel 100 in this embodiment may perform the image display in a column inversion, a row inversion or a frame inversion manner, and if the column inversion is performed, the first sub-black data voltage data21 and the second sub-black data voltage data22 in fig. 3 may be collectively referred to as the data voltages loaded by one sub-pixel in the corresponding one frame, and if the frame inversion is performed, the first sub-black data voltage data21 in fig. 3 may be understood as the data voltages loaded by a plurality of sub-pixels in the corresponding one frame. The reference data voltage data0 may be understood as a data voltage that may be used to control the sub-pixels to emit no light at all, and if there is a difference between the data voltage and the reference data voltage data0, the luminance of the corresponding sub-pixels emitting light may be positively correlated with the absolute value of the difference. Therefore, it can be considered that both the first sub-black data voltage data21 and the second sub-black data voltage data22 can be used to control the sub-pixels to display the same brightness.

It should be noted that the deviations of the first sub-black data voltage data21 and the second sub-black data voltage data22 from the reference data voltage data0 discussed above may be set smaller, so that the sub-pixels may still not emit light, and if the display panel 100 is a liquid crystal display panel, the liquid crystal molecules may be prevented from deflecting in the same direction for a long period of time, so as to reduce the risk of the physical property damage caused by the polarization of the liquid crystal. Also, as shown in fig. 3, in the first stage t1, the first data voltage data1 may be set to include the first sub data voltage data11 and the second sub data voltage data12 symmetrical with respect to the reference data voltage data0, thereby implementing the above-described row inversion or frame inversion.

S3, switching the first refresh rate to a second refresh rate in a third stage, wherein the third stage is positioned after the second stage.

Specifically, as shown in fig. 3, in conjunction with the above discussion, at the third stage t3, it may be considered that the timing controller 20 is receiving the refresh rate command corresponding to the first refresh rate, and changes to receiving the new refresh rate command corresponding to the second refresh rate again, so as to be informed that the display panel 100 should switch from displaying the screen at the first refresh rate to displaying the screen at the second refresh rate. In this process, the source driving module 30 does not output any data voltage, so the display panel 100 can be considered to remain as a black screen. It can also be seen that in the second phase t2, the refresh rate of the display panel 100 is still equal to the first refresh rate.

In particular, since the source driving module 30 does not output any data voltage in the third stage t3, it is not limited whether the clock signal CK includes the pulse pl in this stage to turn on or off the plurality of sub-pixels in the present embodiment, and only the clock signal CK is shown in fig. 3 to include no pulse pl in this stage.

And S4, in a fourth stage, controlling a plurality of sub-pixels to be closed, wherein the fourth stage is positioned after the third stage.

As can be seen from the above discussion, as shown in fig. 3, after the third stage t3, the timing controller 20 needs to establish communication with the source driving module 30 to ensure that the signal can be normally sent and received, and then the above operation of "transmitting the initial Data signal to the source driving module 30" is further performed, so it can be considered that at least one of the amplitude and the timing of the Data signal Data will be disturbed by the timing controller 20 and abnormal in the fourth stage t4 after the third stage t 3.

It can be understood that, in the present embodiment, since the second stage t2 displays the black frame, and the third stage t3 maintains the black frame, further, in the fourth stage t4, the plurality of sub-pixels are controlled to be turned off, i.e. the clock signal CK does not include the pulse pl in the fourth stage t4, so that the plurality of sub-pixels can still maintain the black frame no matter how much the Data signal Data is disturbed.

And S5, controlling the plurality of sub-pixels to display a second picture at the second refresh rate in a fifth stage, wherein the fifth stage is positioned after the fourth stage.

As can be seen from the above discussion, the refresh rate of the display panel 100 in the fourth stage t4 and the fifth stage t5 after the third stage t3 is equal to the second refresh rate, and the plurality of sub-pixels can be controlled to normally emit light in the fifth stage t5 to display the second picture.

It can be understood that, in this embodiment, the second stage t2 and the fourth stage t4 are sequentially arranged before the fifth stage t5 in which the plurality of sub-pixels normally emit light to display the second frame, where the second stage t2 is used to ensure that the display panel 100 displays a black frame in the second stage t2 regardless of the first frame in the first stage t1, and the fourth stage t4 is used to ensure that the plurality of sub-pixels can be turned off to avoid abnormal data signals from acting on the plurality of sub-pixels, and simultaneously ensure that the plurality of sub-pixels still remain in the state of the second stage t2, that is, are presented as black frames, so that the risk of occurrence of a splash screen or a splash screen phenomenon is reduced.

Specifically, as shown in fig. 6, step S5 may include, but is not limited to, the following steps.

S51, the control grid driving module outputs effective grid voltage so as to control a plurality of sub-pixels to be started.

In particular, reference may be made to the relevant discussion above regarding step S21.

S52, controlling the source electrode driving module to output non-black data voltage, wherein the non-black data voltage is used for controlling a plurality of sub-pixels to display a non-black picture.

In particular, reference may be made to the relevant discussion above regarding step S22. The difference from step S22 is that the source driving module transmits a plurality of data voltages corresponding to a plurality of sub-pixels of the gate line to the plurality of data lines, specifically, all of the data voltages are non-black data voltages data3, and the non-black data voltages data3 are understood to be used for controlling the sub-pixels to emit light so that the picture is a non-black picture. Also, there is no limitation in whether the non-black picture is a still picture or a moving picture. Also, as shown in fig. 3, in the fifth stage t5, the non-black data voltage data3 may be set to include the first sub non-black data voltage data31 and the second sub-non-black data voltage data32 symmetrical with respect to the reference data voltage data0, thereby implementing the above-mentioned line inversion or frame inversion.

Based on steps S51 to S52, the step of "controlling a plurality of the sub-pixels to be turned off" in step S4 may include, but is not limited to, the following steps.

S41, controlling the grid driving module to output invalid grid voltage so as to control a plurality of sub-pixels to be closed.

In connection with the above discussion, as shown in fig. 3, each of the multi-stage gate signals output by the multi-stage gate driving unit in this stage may not include an effective gate voltage, that is, the amplitude of the waveform of the corresponding period is equal to an ineffective gate voltage, that is, each of the clock signals CK (only one is illustrated here) is controlled to include no pulse pl in the fourth stage t4, so as to control the multi-stage gate driving unit in the gate driving module to be inoperative, so as to sequentially output a plurality of ineffective gate voltages, thereby turning off a plurality of sub-pixels.

S42, controlling the source electrode driving module to output a third black data voltage, wherein the third black data voltage is used for controlling the plurality of sub-pixels to display the black picture.

Based on the above step S52, in the fourth stage t4, it is not limited whether the third black data voltage is the same as the first black data voltage data2, i.e. the brightness of the black frame displayed in the fourth stage t4 and the brightness of the black frame displayed in the second stage t2 of the display panel may have a smaller difference, but the gray scale values corresponding to the two may be close to 0.

For convenience of description, only the third black data voltage is shown as the same as the first black data voltage data2 in fig. 3, and the absolute value of the difference between the third black data voltage (the same as the first black data voltage data 2) and the reference voltage is smaller than the absolute value of the difference between the non-black data voltage and the reference voltage, that is, the difference between the third black data voltage and the reference voltage data0 is smaller than the non-black data voltage data3, so that the source driving module has a transition fourth stage t4 to output the third black data voltage closer to the reference data voltage data0 in the process of outputting the non-black data voltage data3 from the third stage t3 to the fifth stage t5, so that the data voltage transmitted on the data line can be switched to the non-black data voltage data3 more quickly in the fifth stage t5, and the charging efficiency of the sub-pixel is improved.

In one embodiment, the method further includes, but is not limited to, the steps of:

and S6, controlling the grid driving module to output the invalid grid voltage to control a plurality of sub-pixels to be closed, and controlling the source driving module to output a second black data voltage, wherein the second black data voltage is used for controlling a plurality of sub-pixels to display the black picture, the absolute value of the difference value of the second black data voltage and a reference voltage is smaller than that of the first black data voltage and the reference voltage, and the sixth stage is positioned between the third stage and the fourth stage.

It can be understood that, in this embodiment, a sixth stage t6 is further disposed between the third stage t3 and the fourth stage t4, on the one hand, in this stage, each clock signal CK (only one is shown here) does not include a pulse pl either, so that a plurality of sub-pixels can be controlled to be turned off, and the display panel can still be maintained as a black frame, on the other hand, in the same manner as step S42, in this stage, the source driving module is controlled to output the second black data voltage data4, and the difference between the second black data voltage data4 and the reference data voltage data0 is smaller compared with the first black data voltage data2 (in fig. 3, taking the second black data voltage data4 as the reference data voltage data0 as an example), so that in the process of outputting the first black data voltage data2 from the third stage t3 to the fourth stage t4, there is a transitional sixth stage t6 to output the second black data voltage data4 which is closer to the reference data voltage data0, so that the fourth stage data voltage transmitted on the data line can be switched to the first black data voltage 2 faster than the first black data voltage 2.

In an embodiment, as shown in fig. 4, before the step of controlling the source driving module to output the non-black data voltage in the step S5, the following steps may be further included, but are not limited to: and controlling the source driving module to output a fourth black data voltage so as to control a plurality of the sub-pixels to display the black picture. Similarly, it is not limited whether the fourth black data voltage is the same as the first black data voltage data2, that is, the brightness of the black frame displayed in the fifth stage t5 and the brightness of the black frame displayed in the second stage t2 of the display panel may have a smaller difference, but the gray scale values corresponding to the fourth and the first black data voltages may be close to 0. Fig. 4 illustrates that the fourth black data voltage is identical to the first black data voltage data 2.

It will be appreciated that before the first black data voltage data2 is not transmitted to the plurality of data lines in the fifth stage t5, the plurality of sub-pixels may be considered to be turned on at this time, and in this embodiment, the fourth black data voltage (for example, the same as the first black data voltage data 2) is still transmitted to the plurality of sub-pixels at this stage, the data voltages may be buffered in advance, so that the later non-black data voltage may be more quickly loaded to the plurality of sub-pixels, and the loaded first black data voltage is used to control the plurality of sub-pixels to present a black picture, and also avoid the display picture from being displayed as an abnormal non-black picture.

In the present invention, as shown in fig. 3, the first refresh rate and the second refresh rate are only equal to 120 hz and 240 hz, respectively, but the size relationship and specific numerical values of the two are not limited in practice. In the present invention, the sum of the second stage t2, the third stage t3, the sixth stage t6 and the fourth stage t4 is 680ms, and the fourth stage t4 includes 15 frames, but the above two data are not limited in practice.

Embodiments of the present invention provide a display panel, including, in conjunction with the discussion above regarding fig. 2: the panel main body comprises a plurality of sub-pixels; a memory for storing program instructions; the driving chip 50 is electrically connected to the panel body and the memory, and is configured to execute the program instructions to implement the following steps:

The driving chip 50 may include, but is not limited to, the timing controller 20 described above, and the above steps may be performed by, but are not limited to, the timing controller 20. Further, the driving chip 50 may further include at least one of the source driving module 30 and the gate driving module 40, and fig. 2 only illustrates that the driving chip 50 includes the source driving module 30. The memory may exist independently of the driver chip 50, and the program instructions stored in the memory may also be used by the driver chip 50 to perform steps other than those described above. In particular, the first to fifth stages may be referred to the above description.

In an embodiment, as shown in fig. 2, the panel body 10 or the driving chip 50 further includes at least one of a gate driving module 40 and a source driving module 30 electrically connected between the sub-pixels and the timing controller 20; wherein, the timing controller 20 is configured to perform the following steps in the second stage:

Specifically, in fig. 2, only the case where the panel body 10 includes the gate driving module 40 and the driving chip 50 includes the source driving module 30 is taken as an example, and the steps of the timing controller 20 for performing in the second stage may be described with reference to the above related descriptions about steps S21 to S22.

The embodiment of the invention also provides a display panel which comprises a plurality of the sub-pixels;

It should be understood that, in the present embodiment, as long as the display panel includes the above-mentioned plurality of sub-pixels, and the plurality of sub-pixels may have the working states of the first stage to the fifth stage, the execution subject of the above-mentioned steps is not limited.

The display panel and the driving method thereof provided by the embodiment of the invention are described in detail, and specific examples are applied to illustrate the principle and the implementation of the invention, and the description of the above embodiments is only used for helping to understand the technical scheme and the core idea of the invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A driving method of a display panel, for driving the display panel, the display panel including a plurality of sub-pixels, the method comprising:

2. The method of driving a display panel according to claim 1, wherein the step of controlling the plurality of sub-pixels to display a black picture in the second stage comprises:

3. The driving method of the display panel according to claim 2, wherein an end time of the source driving module outputting the first black data voltage is later than an end time of the gate driving module outputting the effective gate voltage.

4. A driving method of a display panel according to claim 2 or 3, wherein the step of controlling the source driving module to output the first black data voltage comprises:

5. The method of driving a display panel according to claim 2, wherein in the fifth stage, the step of controlling the plurality of sub-pixels to display the second picture at the second refresh rate comprises:

6. The driving method of a display panel according to claim 5, further comprising:

7. The driving method of a display panel according to claim 5 or 6, wherein before the step of controlling the source driving module to output the non-black data voltage, the method comprises:

8. A display panel, comprising:

a panel body including a plurality of sub-pixels;

a memory for storing program instructions;

9. The display panel of claim 8, wherein the driving chip includes a timing controller, the panel body or the driving chip further includes at least one of a gate driving module and a source driving module electrically connected between the sub-pixels and the timing controller;

10. A display panel, comprising a plurality of sub-pixels;