WO2022057222A1 - 一种基于电流积分的存内脉冲神经网络 - Google Patents

一种基于电流积分的存内脉冲神经网络 Download PDF

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WO2022057222A1
WO2022057222A1 PCT/CN2021/081340 CN2021081340W WO2022057222A1 WO 2022057222 A1 WO2022057222 A1 WO 2022057222A1 CN 2021081340 W CN2021081340 W CN 2021081340W WO 2022057222 A1 WO2022057222 A1 WO 2022057222A1
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synaptic
neural network
neuron
voltage
integrating capacitor
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PCT/CN2021/081340
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English (en)
French (fr)
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杨闵昊
刘洪杰
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深圳市九天睿芯科技有限公司
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Priority to US17/768,657 priority Critical patent/US20240111987A1/en
Priority to EP21868061.9A priority patent/EP4024289A4/en
Publication of WO2022057222A1 publication Critical patent/WO2022057222A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means

Definitions

  • the present application belongs to the field of neural networks, and more particularly, relates to an in-memory impulse neural network based on current integration.
  • SNNs Spiking Neural Networks
  • CMOS complementary metal oxide semiconductor
  • the core of the key module is The neurosynaptic nucleus is the synaptic nucleus of neurons; in addition, there are Loihi of Intel and Tanjic ("Tianjing") of Tsinghua University.
  • computing elements ie neurons
  • SRAM Static Random Access Memory
  • each Processing Element can be regarded as a local Von-Neumann architecture.
  • the Neumann processor has a local processing unit (Local Processing Units, LPU), a local memory, a route for communication between PEs or global data, and the like. But the energy that such an architecture spends repeatedly moving data (mainly synaptic weights) back and forth between processing units and local memory is still a waste compared to the static data flow of weights in biological neural networks.
  • Silicon-based traditional memories such as SRAM, Dynamic Random Access Memory (DRAM), and Flash
  • NVM Non-Volatile-Memory
  • SRAM Spin-Transfer Torque Magnetic RAM
  • ReRAM Resistive Random Access Memory
  • PCM Phase-change Memory
  • DNN Deep Neural Network
  • NVMs such as PCM can store multiple bits of information in one storage element/unit, with Compared to storing a single bit in a single SRAM cell, the area and potential energy efficiency are greatly improved, but NVM materials are prone to many non-idealities such as limited precision, randomness, nonlinearity, conduction drift over time, etc. In contrast, the characteristics of silicon-based transistors are more stable.
  • units such as SRAM have been applied to crossed synaptic arrays.
  • Chinese patent CN111010162A mentioned that the units in the crossed array can be SRAM cells.
  • the memory unit can be SRAM, but there is no further design for the SNN architecture of the in-SRAM and the signal transmission design of the synaptic array and the neuron circuit after using the SRAM unit.
  • the present application proposes a current-integration-based internal pulse neural network, in order to achieve the above purpose, the present invention adopts the following technical solutions:
  • an in-memory spiking neural network based on current integration including a pre-neuron, a synaptic array, and a post-neuron circuit;
  • the synapse array is configured to receive the pulse signal input by the preneuron, the synapse array is composed of i*j synaptic circuits, i is the number of rows, j is the number of columns; i, j are both positive and greater than or equal to 1. integer;
  • each of the synaptic circuits includes a memory cell
  • the memory cell consists of a conventional 6T SRAM that stores one bit of synaptic weight, and 2 transistors connected in series for reading the synaptic weight, where the gate of one transistor is connected to the output of an inverter in the conventional 6T SRAM , the source is connected to the high level, the drain is connected to the source of another transistor, the gate of the other transistor is connected to the read word line, the drain is connected to the read bit line, and the conduction current on the read bit line is the output current of the synaptic circuit;
  • the post-neuron circuit includes an integrating capacitor and a comparator, and each post-neuron circuit is configured to integrate the output current of a column of synaptic circuits connected to the post-neuron circuit in the integrating capacitor, based on the accumulated voltage across the integrating capacitor and the threshold voltage. The results of the comparison fire to the next level of neuron spikes.
  • the memory unit is integrated with storage and computing, which can also be said to be in-memory computing.
  • NVM cell in the prior art synapse array with a cell consisting of a conventional 6T SRAM that stores one-bit synaptic weights, and 2 transistors in series for reading the synaptic weights, the resistive Non-ideality due to NVM material.
  • the on-current of the transistor is accumulated on the integrating capacitor in the circuit of the post-neuron, and the voltage across the obtained integrating capacitor is compared with the threshold voltage. In this process, the synaptic weight does not need to be explicitly read from the traditional 6T SRAM.
  • the SNN architecture adopts the calculation method in the charge domain, which is naturally compatible with the working methods of neurons, such as the IF neuron model, the presynaptic membrane
  • the transmitted stimulation signal discontinuously acts on the postsynaptic membrane of the post-neuron and accumulates on the post-synaptic membrane.
  • the post-neuron is stimulated to generate a pulse signal, thereby avoiding The problem of current domain readout is solved.
  • the synaptic array receiving the input of the previous neuron circuit is realized by connecting the read word lines in a row of synaptic circuits through the pulse signal input by each pre-neuron.
  • the accumulated voltage across the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, the accumulated voltage across the integrating capacitor is the voltage on the upper plate of the integrating capacitor.
  • the SNN architecture of the first aspect can also be used for multi-bit synapse weight calculation, combining the number of columns according to the number of synapse weight bits , each column corresponds to the position of each bit of the synaptic weight, and the parallel comparators send out pulse signals respectively, and the pulse signals are collected by the ripple counters connected to the comparators, and the value in the ripple counters is based on the bit weight of the position. Shift and add, based on the comparison result of the sum value of all ripple counters' shift and addition and the digital threshold, the next-level neuron pulse signal is excited.
  • the number of combined columns is programmable, which is the same bit width as the synaptic weights.
  • the accumulated voltages at both ends of the integrating capacitors share a comparator's voltage by time multiplexing.
  • the input terminal selects the accumulated voltage corresponding to the position compared with the threshold voltage according to the switch selection signal.
  • the output of the comparator is connected to a register, and when the output of the comparator is high, the output of the register is used as an operand of the adder connected to it.
  • another operand of the adder is the bit weight of the bit, and the output of the adder is higher than the digital threshold, and the neuron circuit sends out a pulse signal.
  • the threshold voltages of different columns are different.
  • the neural network further includes an automatic calibration circuit.
  • the output current change of the synaptic circuit caused by PVT can be offset, and the obtained adjusted pulse width can be used as the input of the synaptic array again.
  • the calibration principle is: :
  • V ref is the threshold voltage
  • I 0 is the output current
  • C 0 is the capacitance value
  • an in-memory spiking neural network based on current integration including a pre-neuron, a synaptic array, and a post-neuron circuit;
  • the synapse array is configured to receive the pulse signal input by the preneuron, the synapse array is composed of i*j synaptic circuits, i is the number of rows, j is the number of columns; i, j are both positive and greater than or equal to 1. integer;
  • each of the synaptic circuits includes a memory cell
  • the memory unit is composed of one NVM resistor and one field effect transistor, one end of the NVM resistor is connected to the drain of the field effect transistor, and one end is connected to the bit line, and the conduction current on the bit line is the output current of the synaptic circuit; the The source of the field effect transistor is connected to the source line, and the gate is connected to the word line.
  • the post-neuron circuit includes an integrating capacitor and a comparator, and each post-neuron circuit is configured to integrate the output current of a column of synaptic circuits connected to the post-neuron circuit in the integrating capacitor, based on the accumulated voltage across the integrating capacitor and the threshold voltage. The results of the comparison fire to the next level of neuron spikes.
  • the output current of a column of bit lines passes through a field effect transistor before being injected into the integrating capacitor.
  • the source of the FET is connected to the bit line, the drain is connected to the top plate of the integrating capacitor, and the gate is connected to the output of an error amplifier.
  • the positive input of the amplifier is connected to a reference voltage, and the negative input is connected to the bit line.
  • the synaptic array receives the input of the previous neuron circuit by connecting the read word lines of a row of synaptic circuits through the pulse signal input by each pre-neuron.
  • the accumulated voltage at both ends of the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, the accumulated voltage at both ends of the integrating capacitor is equal to plate voltage.
  • the neural network further includes an automatic calibration circuit.
  • the pulse width By adjusting the pulse width, the output current change of the synaptic circuit caused by PVT can be offset, and the obtained adjusted pulse width can be used as the input of the synaptic array again.
  • In-memory spiking neural networks using silicon-based SRAMs do not suffer from similar problems with NVM materials.
  • the synaptic array uses SRAM cells as memory cells, the design of the post-neuron circuit corresponds to it, so that the in-memory SNN architecture can be used for the calculation of multi-bit synaptic weights, and the number of combined columns is programmable .
  • the circuit is designed as a time multiplexing of resource sharing. Reusable form.
  • an automatic pulse width calibration circuit is proposed to offset the variation of on-current caused by factors such as manufacturing process, voltage, temperature (PVT), etc., so that the calculation result is more accurate.
  • the NVM unit used in the second aspect is compatible with the SNN architecture, that is, the in-memory spiking neural network based on the NVM unit can also be designed from this application. Benefit from the interface circuit to the posterior neuron and the pulse width self-calibration circuit.
  • Figure 1 is a schematic diagram of information transmission between pre-neuron, synapse and post-neuron in a biological spiking neural network
  • Fig. 2 is the schematic diagram of the cross matrix circuit constructed according to the biological impulse neural network
  • FIG. 3a is a schematic diagram of the preneuron input and synapse array in an embodiment of the present invention.
  • 3b is a schematic diagram of a memory unit in an embodiment of the present invention.
  • 3c is a schematic diagram of a posterior neuron circuit in an embodiment of the present invention.
  • 4a is a schematic diagram for multi-bit calculation in an embodiment of the present invention.
  • 4b is a schematic diagram of time multiplexing for multi-bit weight calculation in an embodiment of the present invention.
  • 5a is a schematic diagram of a memory unit based on an NVM unit in another embodiment of the present invention.
  • 5b is a schematic diagram of a memory cell based on an NVM cell and a bit line interface circuit thereof in another embodiment of the present invention
  • 6a is a schematic diagram of a calibration circuit according to an embodiment of the present invention.
  • FIG. 6b is a schematic diagram of a calibration circuit in another embodiment of the present invention.
  • IF integrated-and-fire, integral excitation
  • LIF model leaky integrate-and-fire, leaky integral excitation
  • impulse response model Spike response model, SRM
  • Hodgkin-Huxley models at least one of the Hodgkin-Huxley models.
  • the post-synaptic neuron receives all the impulses from the axon terminals of the pre-synaptic neuron connected to the neuron; when the post-synaptic neuron When the membrane potential exceeds the threshold potential, the postsynaptic neuron sends a pulse along the neuron's axon to the axon terminal. After the post-synaptic neuron sends a pulse, it will enter a hyperpolarized state, followed by a refractory period. During the refractory period, the post-synaptic neuron will not respond even if it is stimulated, that is, the neuron will no longer receive stimulation. , maintain the resting potential.
  • paper 1 proposes an in-memory SNN neural network architecture based on NVM.
  • the latter neuron receives all the signals from all neurons in the previous layer, constructing The cross-matrix structure circuit shown in Figure 2 is shown.
  • the word line carries the input vector
  • the admittance value of each resistive NVM cell represents a matrix element
  • the current on the bit line represents the inner product value of the input vector and a column vector of a matrix.
  • the output of the matrix can be expressed as:
  • X [x 1 , x 2 ,..., x n ] is the voltage input vector
  • Y [y 1 , y 2 ,..., y m ] is the current output vector
  • This application proposes a current integration-based spiking neural network, including pre-neuron input, synaptic array and post-neuron circuit.
  • the architecture of the synaptic array is shown in Figure 3a. Resistive NVM cells in synaptic arrays are replaced with memory cells.
  • the synapse array is configured to receive the pulse signal input by the preneuron, the synapse array is composed of i*j synaptic circuits, i is the number of rows, j is the number of columns; i, j are both positive and greater than or equal to 1. Integer; n and m in the figure are the number of pre-neurons and post-neurons, respectively.
  • each of the synaptic circuits includes a memory cell
  • the memory cell consists of a conventional 6T SRAM that stores one bit of synaptic weight, and 2 transistors connected in series for reading the synaptic weight; the gate of one transistor is connected to the output of an inverter in the conventional 6T SRAM , the source is connected to the high level, the drain is connected to the source of another transistor, the gate of the other transistor is connected to the read word line, the drain is connected to the read bit line, and the conduction current on the read bit line is the output current of the synaptic circuit;
  • the conventional 6T SRAM is composed of six transistors, of which four field effect transistors form two cross-coupled inverters to store each bit, and the other two field effect transistors are the basic unit for storage to be used for reading Control switch for the write bit line.
  • FIG. 3b is an embodiment of the memory cell, the transistors use P-channel field effect transistors, it should be understood that the transistors may also work with N-channel field effect transistors.
  • the memory cell can also be an 8-T SRAM cell based on traditional 6T SRAM proposed by IBM in the paper "JSSC-2008-An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches" , in this embodiment, the N-channel field effect transistor is used to read the stored synaptic weights in the conventional 6T SRAM cell.
  • the post-neuron circuit includes an integrating capacitor and a comparator, and each post-neuron circuit is configured to integrate the output current of a column of synaptic circuits connected to the post-neuron circuit in the integrating capacitor, based on the accumulated voltage across the integrating capacitor and the threshold voltage. The results of the comparison fire to the next level of neuron spikes.
  • the voltage level “1" indicates that the voltage is equal to the power supply voltage VDD
  • the voltage level "0" indicates that the voltage is equal to the ground voltage VSS.
  • the read word line ( n RWL) is enabled at a low level, and the synaptic weight stored in the conventional 6T SRAM is read from the read bit line (read bit line, RBL).
  • the read word line n RWL carries the input vector, and it can also be said that the read word line n RWL is used as the pulse input of the SNN.
  • the same column RBL is connected to an integrating capacitor that is part of a post-neuron circuit, one embodiment of which is shown in Figure 3c.
  • the described row and column are different according to the input direction and the setting manner of the memory cells.
  • the pulse signal is input from the column direction, and the memory cells are set with a reverse rotation of 90 degrees, this
  • the RBLs of the same row are connected to an integrating capacitor.
  • the duration of each pulse is ⁇ t and the on-current of the transistors in each memory cell is I 0
  • the incremental voltage on the integrating capacitor C 0 due to the existence of one pulse is as follows:
  • the total cumulative voltage change on the integrating capacitor V mem is the product of ⁇ V and the number of pulses.
  • the voltage change caused by each pulse multiplied by the total number of pulses contained in a column of input refers to The posterior neuron receives spikes from all neurons in the previous layer.
  • V ref the specified threshold voltage
  • the post-synaptic neuron membrane potential in the biological neuron corresponding to this process exceeds the threshold potential, the post-synaptic neuron emits a pulse, and then the post-synaptic neuron falls back to the resting potential.
  • the output current of the synaptic array is accumulated on the integrating capacitor in the post-neuron circuit, and the obtained voltage across the integrating capacitor is compared with the threshold voltage.
  • the synaptic weights do not need to be explicitly read from the traditional 6T SRAM, and based on the comparison results, it is decided whether to excite the pulses to the next level neurons.
  • the SNN architecture adopts a natural way of computing in the charge domain. It is compatible with the way neurons work and avoids the problem of reading out from the current domain.
  • each SRAM cell can only store one bit of information
  • the spiking neural network based on the SRAM memory cell in the above embodiment can be used for multi-bit weight calculation.
  • the pulse signals from multiple IF neuron circuits can be digitally combined from the parallel bit lines RBL j to be regarded as a whole neuron pulse output, that is, Multiple post-neuron circuits combine the number of columns from the parallel bit line RBL j according to the number of synaptic weights. If the synaptic weight has 3 bits, then the combined column is 3 columns, and each column corresponds to the position of each bit of the synaptic weight.
  • the pulse signal sent by the parallel comparator is collected by the parallel ripple counter connected to the comparator, the value in the ripple counter is shifted and added according to the bit weight of the bit, and the sum value based on the shift and the digital
  • the result of the comparison of the thresholds fires the impulse signal to the next level neuron.
  • the combined pulses from k comparators in parallel are collected by a parallel ripple counter (cnt).
  • cnt parallel ripple counter
  • the bit weight of the k-th bit may be 2k-1 , and the value in each ripple counter is shifted and added to the shifted values in the other ripple counters.
  • the 1st column is the least significant bit (LSB), which is not shifted; the kth column is the most significant bit (MSB), and the value of the ripple counter is shifted left by k-1 bits , compare the summed value obtained by shifting and adding all the ripple counters calculated with the k-bit synaptic weight with the digital threshold (threshold), once the digital threshold is exceeded, a spike or more pulse and reset all ripple counters in the combined neuron circuit after emitting the pulse signal.
  • the number of combined columns k is programmable, which is the same as the bit width of the synaptic weights.
  • the transistor operates in the saturation region when it is turned on, which is important to maintain a relatively consistent on-current I 0 and minimize its effect on the transistor drain voltage. Long channel lengths can be employed to further increase the output impedance of the compound transistor.
  • the comparator in Figure 3c and the circuit in Figure 4a need to be modified and shared for a multi-column post-neuron circuit for k-bit weight calculation. share a comparator.
  • the accumulated voltage across the integrating capacitor is connected to the input terminal of the shared comparator in a time-multiplexed manner, and the other input terminal of the comparator is threshold voltage.
  • time multiplexing is controlled by a clock.
  • the two operands of the adder in the accumulator are the output of the D-type register and the weight selected by the switch selection signal S sk according to the position of the current bit, that is, the selected bit. right.
  • the bit weight is 2 k-1 , but in other embodiments, the bit weight corresponding to each column is not necessarily allocated according to the proportional sequence of 2, for example, it can also be 8 In particular, in other embodiments, when the integrated voltage on the integrating capacitor of each column is compared with its corresponding threshold voltage, the threshold voltages of these columns do not need to be the same, that is, each column does not need to be the same. Threshold voltages can be different between postneural circuits.
  • the cumulative voltage on the integral capacitor connected to each bit is compared with the threshold voltage separately, the result of each bit needs to correspond to the bit weight, and then the result of adding the bit weight to each bit is added until the sum of the sum is added.
  • the value is greater than the digital threshold to pulse, or all bits are added but not pulsed.
  • the selection of the weight can be further gated according to the output of the comparator. pick 0.
  • the two resets included here the former is that the accumulated voltage corresponding to each bit is higher than the threshold voltage V ref , and the latter is that the accumulated voltage of the corresponding multi-bit weight is higher than the digital neuron threshold D TH . That is, the integrating capacitor is reset either because its accumulated voltage V memj is greater than the threshold voltage, or because the synaptic weights combined by multiple columns emit pulses.
  • the output of the comparator and the output of the AND operation of S sk are used as one input of the OR gate, and the other input of the OR gate is the generated pulse, and the output of this OR gate is Srk .
  • an in-memory spiking neural network based on current integration including a pre-neuron, a synaptic array, and a post-neuron circuit: the synaptic array is configured to receive a spiking signal input from the pre-neuron, and the synaptic
  • the touch array is composed of i*j synaptic circuits, i is the number of rows, j is the number of columns; i, j are both positive integers greater than or equal to 1; each of the synaptic circuits includes a memory unit;
  • a one-memristor one-transistor (1R1T) NVM cell can also be derived from the above SNNs benefit from the architecture.
  • the NVM cell in Figure 3a can be constructed as shown in Figure 5a.
  • the memory unit is composed of an NVM resistor and a field effect transistor.
  • One end of the NVM resistor is connected to the drain of the field effect transistor, and the other end is connected to the bit line BL.
  • the conduction current on the bit line is the output of the synaptic circuit. Current; the source of the field effect transistor is connected to the source line SL, and the gate is connected to the word line WL.
  • Equation 1 no longer holds, and a specific SNN training algorithm is required to take this into account. If a training algorithm that satisfies Equation 1 is to be used, in one embodiment, additional circuitry as shown in Figure 5b needs to be added to the bit lines.
  • the source of a p-type field effect transistor is connected to the bit line, the drain is connected to the integrating capacitor, and the gate is connected to the output of the error amplifier.
  • the positive input of the error amplifier is connected to a reference voltage, and the negative input is connected to the bit line.
  • the post-neuron circuit includes an integrating capacitor and a comparator, and each post-neuron circuit is configured to integrate the output current of a column of synaptic circuits connected to the post-neuron circuit in the integrating capacitor, based on the accumulated voltage across the integrating capacitor and the threshold voltage. The results of the comparison fire to the next level of neuron spikes.
  • the synaptic array receives the input of the previous neuron circuit by connecting the word lines of a row of synaptic circuits through the pulse signal input by each pre-neuron, that is, the voltage pulse is applied through the word line. After the post-neuron circuit sends out a pulse signal, the accumulated voltage across the integrating capacitor is reset to zero. If one end of the integrating capacitor is grounded, the accumulated voltage across the integrating capacitor is the voltage on the upper plate of the integrating capacitor.
  • any variation in I 0 caused by changes in manufacturing process, voltage and temperature (PVT) can be compensated by adjusting the pulse width ⁇ t of the pulse train, and the adjustment procedure can be automatic.
  • the uncalibrated spike leading edge sets the gates of transistors M a and M b low.
  • M a and M b are replica transistors of the 2 P-channel FETs used for reading in Figure 3b, and the on-current starts to charge the capacitor Cx . Once the potential on Cx exceeds the threshold voltage Vref , the comparator output goes high and sets the gates of Ma and Mb high again.
  • the pulse width of xi is automatically adjusted according to the on-current of the compound transistors Ma and Mb , and is fed into the SNN array as a pulse train of pulse width ⁇ t like the input in Figure 3a.
  • the condition for using the SR latch is that the pulse width of the input pulse is smaller than that of the output pulse.
  • the verification principle can be expressed by the following formula:
  • V ref is the threshold voltage
  • I 0 is the output current
  • C 0 is the capacitance value
  • the calibrated pulse width of the pulse can be stored digitally by a calibration circuit as shown in FIG. 6b. Its working mechanism is still restricted by Equation 3.
  • the counter starts counting clock cycles and stops when the integrated voltage on Cx exceeds Vref .
  • the switch for resetting the integrated voltage on Cx is implemented with an n-type field effect transistor. Stop counting when the comparator output is high, making the NOR gate output low. The value stored in the counter can then be applied to all incoming pulses into the array as shown in Figure 3a, without the need to frequently enable this calibration circuit.
  • Fig. 6a and Fig. 6b can also be based on the SNN architecture of the NVM unit.
  • the source of the P-channel field effect transistor in the NVM cell is connected to VDD, and the drain of R is connected to Cx through the P-type field effect transistor on the bit line.
  • the SNN architecture and calibration principle proposed in this application are not only compatible with 8T SRAM, but the NVM unit can also benefit from the SNN architecture.
  • the selected form of the memory unit is 8T SRAM or NVM, and the spiking neural network based on the memory unit can all have the aforementioned beneficial effects.
  • the memory cells used in the impulse neural network based on current integration proposed in this application are not limited to 8T SRAM or NVM cells.
  • the memory unit can also be in other forms that can satisfy the principle of current addition while the current is not affected by the integrated voltage on the capacitor in the posterior neuron.

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Abstract

一种基于电流积分的存内脉冲神经网络，基于电荷域的计算与神经元的工作机制天然兼容。一方面，为了避免采用NVM材料的非理想性，架构中突触阵列的存储器单元采用硅基的SRAM单元。另外提供了修改后的NVM单元也能从所述存内脉冲神经网络的架构中受益。在突触阵列采用SRAM单元作为存储单元时，后神经元电路的设计与之相对应，使得在该存内SNN架构可以用于多位突触权重的计算，并且组合的列数是可编程的。进一步地，为了提高面积的使用效率以及节省能效，在多位突触权重的计算中，将电路设计为资源共享的时间多路复用形式。最后，提出一种自动校准电路，抵消工艺、电压、温度（PVT）等因素带来的导通电流的变化，使得计算结果更准确。

Description

一种基于电流积分的存内脉冲神经网络
本申请要求于2020年09月15日提交中国专利局、申请号为202010965425.1、发明名称为“一种基于电流积分的存内脉冲神经网络”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于神经网络领域，更具体的，涉及一种基于电流积分的存内脉冲神经网络。
背景技术
受生物神经网络的启发，神经形态计算，或者更具体地说，脉冲神经网络(Spiking Neural Network，SNN)被认为是当前流行的人工神经网络的一种有前途的未来进化。SNN利用脉冲在任意连接的一对神经元之间进行通信(大多是单向的)，且SNN中的神经元只有在接收或发出脉冲信号时才处于活跃状态，如果能保证脉冲活动的稀疏性，该独特的事件驱动特性就有可能带来显著的节能效果。工业界和学术界一直在热衷于研究SNN的电路和架构。近期的一些代表性例子如IBM的TrueNorth，是用互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)电路器件组成生物学中的神经元的轴突、树突、突触，其关键模块核心是neurosynaptic核，即神经元突触内核；此外还有英特尔的Loihi和清华大学的Tanjic(“天机芯”)等。在这些现有技术中，计算元素(即神经元)，需要明确地从静态随机存取存储器(Static Random Access Memory，SRAM)中读出突触权值，进行状态更新计算，即膜电位计算。
与传统的集中式存储器和处理单元的冯-诺依曼架构相比，分布式存储器有助于缓解数据通信瓶颈，但每个处理元素(Processing Element，PE)可以看作是一个局部的冯-诺依曼处理器，具有局部处理单元(Local Processing Units，LPU)、局部存储器、用于PE之间或者是全局数据通信的路由等。但是与生物神经网络中的权重静态数据流相比，此种架构在处理单元和本地存储器之间来回重复移动数据(主要是突触权重)所花费的能量仍然是一种浪费。
因此，存内计算的概念引起了很多人的关注。基于硅的传统存储器如SRAM、动态随机存取存储器(Dynamic Random Access Memory，DRAM)和Flash；以及新兴的非易失性存储器(Non-Volatile-Memory，NVM)，包括自旋矩随机存取存储器(Spin-Transfer Torque Magnetic RAM，STT-MRAM)、阻变随机存取存储器(Resisitive Random Access Memory，ReRAM)和相变存储器(Phased-charge memory，PCM)等，都可以具备处理能力，并已经用于深度神经网络(Deep Neural Network，DNN)加速等应用。研究人员也开始将存内计算的概念应用到SNN上，但几乎都是基于NVM单元。正如论文arXiv-2019-Supervised learning in spiking neural networks with phase-change memory synapses(以下简称“论文1”)所指出的，尽管NVM，例如PCM可以将多位信息存储在一个存储元件/单元中，与单比特存储在一个SRAM单元中相比，很大程度上提高了面积和潜在的能效，但NVM材料容易出现许多非理想性，如精度有限、随机性、非线性、随时间的传导漂移等。相比之下，硅基晶体管的特性更加稳定。
现有技术中开始将SRAM等单元应用于交叉的突触阵列，如中国专利CN111010162A提及交叉阵列中的单元可以是SRAM单元、CN109165730A提及可以采用6T SRAM、CN103189880B提及的突触装置包含的存储器单元可以是SRAM，但是没有进一步对in-SRAM的SNN架构以及采用SRAM单元后，突触阵列与神经元电路的信号传递设计。
因此，本领域亟需一种基于电流积分的存内脉冲神经网络，不需要在处理单元与存储单元之间移动数据，采用存算一体的存储单元是硅基的SRAM单元或者是NVM单元。
发明内容
基于此，本申请提出了的一种基于电流积分存内脉神经网络，为实现上述目的，本发明采用如下的技术方案：
第一方面，提供了一种基于电流积分的存内脉冲神经网络，包括前神经元、突触阵列、后神经元电路；
所述突触阵列被配置为接收前神经元输入的脉冲信号，突触阵列由i*j个突触电路组成，i为行数，j为列数；i，j均为大于等于1的正整数；
每一所述突触电路包含一个存储器单元；
所述存储器单元由存储一位突触权重的传统6T SRAM，以及用于读取突触权重的串联着的2个晶体管组成，其中一个晶体管的栅极连接传统6T SRAM中一个反相器的输出，源极接高电平，漏极接另一晶体管源极，另一晶体管的栅极连接读字线，漏极连接读位线，读位线上导通电流为突触电路的输出电流；
所述后神经元电路包含积分电容、比较器，每一个后神经元电路被配置为根据其连接的一列突触电路的输出电流在积分电容内的积分，基于积分电容两端累积电压与阈值电压的比较结果激发给下一级神经元脉冲信号。
本申请实施例中，存储器单元是存算一体的，也可以说是存内计算。通过将现有技术中突触阵列中的NVM单元替换为由存储一位突触权重的传统6T SRAM，以及用于读取突触权重的串联着的2个晶体管组成的单元，避免由电阻性NVM材料引起的非理想性。晶体管的导通电流在后神经元的电路内的积分电容上累积，得到的积分电容两端的电压与阈值电压进行比较，这一过程中，突触权重并不需要明确地从传统6T SRAM中读出，并基于比较结果决定是否激发给到下一层级神经元的脉冲，所述SNN架构采用在电荷域内计算的方式天然地兼容了神经元的工作方式，如IF神经元模型，突触前膜传递的刺激信号不连续地作用在后神经元的突触后膜上，并在突触后膜上累积，当突触后膜累积的电压超过阈值电压，激发后神经元产生脉冲信号，从而规避了电流域读出的问题。
在一种可能的实施方式中，突触阵列接收前一神经元电路的输入是通过每一前神经元输入的脉冲信号连接一行突触电路中的读字线实现。
在一种可能的实施方式中，后神经元电路发出脉冲信号后，积分电容两端累积电压复位到零，若积分电容一端接地，那么积分电容两端的累积电压为积分电容上极板的电压。
在一种可能的实施方式中，即使每个存储单元只能存储一位的突触权重，但是第一方面的SNN架构也可用于多位突触权重计算，根据突触权重位数组合列数，每列对应突触权重每位的位置，得到并行的比较器分别发出脉冲信号，所述脉冲信号分别由与比较器连接的纹波计数器收集，纹 波计数器中的值根据所在位的位权移位相加，基于所有纹波计数器移位相加的和值与数字阈值的比较结果激发给下一级神经元脉冲信号。组合列数是可编程的，其与突触权值的位宽相同。
进一步地，在一种可能的实施方式中，为了提高采用SRAM单元时的面积效率和节省能效，组合的列数内，积分电容两端的累积电压通过时间多路复用的方式共用一个比较器的输入端，根据开关选择信号选择与阈值电压比较的与所在位对应的累积电压。
在一种可能的实施方式中，比较器输出端连接一个寄存器，当比较器输出为高时，则寄存器的输出作为与其连接的加法器的一个操作数。
在一种可能的实施方式中，加法器的另一个操作数为所在位的位权，加法器的输出高于数字阈值，后神经元电路发出脉冲信号。
在一种可能的实施方式中，每一列的积分电容上的积分电压与其相应的阈值电压进行比较时，不同列的阈值电压不相同。
在一种可能的实施方式中，神经网络还包括自动校准电路，通过调整脉宽可以抵消PVT引起的突触电路输出电流变化，得到的调整脉宽重新作为突触阵列的输入，校验原理为：
Figure PCTCN2021081340-appb-000001
其中Δt表示需调整的脉宽，V ref为阈值电压，I 0为输出电流，C 0为电容容值。
第二方面，提供了一种基于电流积分的存内脉冲神经网络，包括前神经元、突触阵列、后神经元电路；
所述突触阵列被配置为接收前神经元输入的脉冲信号，突触阵列由i*j个突触电路组成，i为行数，j为列数；i，j均为大于等于1的正整数；
每一所述突触电路包含一个存储器单元；
所述存储器单元由1个NVM电阻与1个场效应管组成，NVM电阻的一端连接场效应管的漏极，一端连接位线，位线上导通电流为突触电路的输出电流；所述场效应管的源极连接源线，栅极连接字线。
所述后神经元电路包含积分电容、比较器，每一个后神经元电路被配置为根据其连接的一列突触电路的输出电流在积分电容内的积分，基于积 分电容两端累积电压与阈值电压的比较结果激发给下一级神经元脉冲信号。
结合第二方面，在一种可能的实施方式中，在一列位线输出电流注入到积分电容前经过一个场效应晶体管。场效应晶体管的源极连接到位线，漏极连接到积分电容的上极板，栅极连接到一个误差放大器的输出端。该放大器的正输入端接一个参考电压，负输入端连接位线。这样可以让该存储单元中的导通电流对积分电容上的电压不敏感，利用了晶体管大的漏极阻抗，并且该阻抗随着沟道长度的增加而增大。
结合第二方面，在一种可能的实施方式中，突触阵列接收前一神经元电路的输入是通过每一前神经元输入的脉冲信号连接一行突触电路的读字线实现。
结合第二方面，在一种可能的实施方式中，后神经元电路发出脉冲信号后，积分电容两端累积电压复位到零，若积分电容一端接地，那么积分电容两端的累积电压为积分电容上极板的电压。
结合第二方面，在一种可能的实施方式中，神经网络还包括自动校准电路，通过调整脉宽可以抵消PVT引起的突触电路输出电流变化，得到的调整脉宽重新作为突触阵列的输入。
基于上述的技术方案，本申请第一方面为了避免采用NVM材料的存内脉冲神经网络因NVM本身的非理想性包括有限的精度、随机性、非线性，以及编程电导状态随时间的漂移等，采用了基于硅基的SRAM的存内脉冲神经网络，不会出现NVM材料类似的问题。在突触阵列采用SRAM单元作为存储单元时，后神经元电路的设计与之相对应，使得在该存内SNN架构可以用于多位突触权重的计算，并且组合的列数是可编程的。进一步地，由于硅基SRAM只能存储单位突触权重，为了提高面积的使用效率以及节省能效，在多位突触权重的计算中，依据前述的架构，对电路设计为资源共享的时间多路复用形式。最后，根据所提出SNN的可能实施方式，提出一种脉冲脉宽自动校准电路，抵消制造工艺、电压、温度(PVT)等因素带来的导通电流的变化，使得计算的结果更准确。
另外，虽然现有的NVM材料本身特性容易出现非理想型，但第二方面采用的NVM单元是与SNN架构相适应的，即基于NVM单元的存内 脉冲神经网络也能从本申请所设计的与后神经元连接的接口电路以及脉宽自校准电路中受益。
本申请采用的技术方案可以解决至少以上背景技术中提及的问题和/或缺点以及以上未描述的其他缺点。
说明书附图
图1为生物脉冲神经网络中，前神经元、突触、后神经元信息传递示意图；
图2为根据的生物脉冲神经网络构建的交叉矩阵电路示意图；
图3a为本发明一实施例中前神经元输入与突触阵列示意图；
图3b为本发明一实施例中存储器单元示意图；
图3c为本发明一实施例中后神经元电路示意图；
图4a为本发明一实施例中用于多位计算的示意图；
图4b为本发明一实施例中用于多位权重计算的时间多路复用示意图；
图5a为本发明另一实施例中基于NVM单元的存储器单元示意图；
图5b为本发明另一实施例中基于NVM单元的存储器单元及其位线接口电路的示意图；
图6a为本发明一实施例中校准电路示意图；
图6b为本发明另一实施例中校准电路示意图。
具体实施方式
为了使发明的目的、原理、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，正如本发明内容部分所述，此处所描述的具体实施例用以解释本发明，并不用于限定本发明。
本申请提出的方案可以适用但不限于IF(integrate-and-fire，积分激发)神经元模型、LIF模型(leaky integrate-and-fire，泄露积分激发)、脉冲响应模型(Spike response model，SRM)以及Hodgkin-Huxley模型中的至少一种。
以常用的IF神经元模型为例，突触后神经元(presynaptic neuron)会接收所有与该神经元相连的来自突触前神经元(postsynaptic neuron)轴突末端发出的脉冲；当突触后神经元膜电位超过阈值电位时，突触后神 经元会发送脉冲沿该神经元轴突传递至轴突末端。突触后神经元发送脉冲后会进入超极化状态，然后是不应期(Refractory Period)，在不应期内即使给予刺激突触后神经元也不会反应，即神经元不再接收刺激，保持静息电位。
为了将存内计算应用在SNN上，论文1提出了一种基于NVM的存内SNN神经网络架构，根据图1的SNN模型，后一神经元接收所有来自前一层所有神经元的信号，构建出了如图2的交叉矩阵结构电路。原理上，字线携带输入向量，每个电阻式NVM单元的导纳值代表一个矩阵元素，位线上的电流代表输入向量和一个矩阵的列向量的内积值。从图形上看，如图2所示，从数学上看，矩阵的输出可以表示为：
Y＝GX   (等式1)G＝1/R
其中X＝[x 1，x 2，...，x n]是电压输入矢量，Y＝[y 1，y 2，...，y m]是电流输出矢量，G＝[g ij](i＝1，2，...，n；j＝1，2，...，m)是电导矩阵。
但如何利用位线电流来更新神经元状态，即用神经科学的术语来更新膜电位，往往没有得到充分的解决。例如，在论文1中，LIF神经元动态只在软件中实现。在论文“TETCI-2018-An all-memristor deep spiking neural computing system:a step toward realizing the low-power stochastic brain”提出的方案中，为了保持等式1的有效性，采用比NVM元件值小得多的电阻来感应输出电流，结果输出电压非常小，需要使用耗电的电压放大器进行放大。值得一提的是，在论文“ISSCC-2020-A 74 TMACS/W CMOS-RRAM neurosynaptic core with dynamically reconfigurable dataflow and in-situ transposable weights for probabilistic graphical models”提出的方案中，虽然采用了基于单晶体管单忆阻器(one-transistor–one-memristor，1T1R)存储单元的所谓IF神经元进行NVM单元存内计算，但其依靠的是电压采样而不是电流积分，而且该架构用于概率图形模型，不便于实现脉冲神经网络。
综上，现有技术中所提到的NVM所具有的非理想性，往往导致人工神经网络或脉冲神经网络硬件与软件模型相比推理精度不高。另外，文献中的大部分作品只是展示了在模型仿真中使用NVM进行存内ANN或SNN的原理，而不是构建实际的基于NVM单元的工作芯片。
如论文1中的图表所示，由于NVM，例如PCM的电导值随时间变化的不稳定性，即使在相对简单的任务中也会导致推理精度的显著下降。硅基SRAM可以规避这些与NVM材料本身特性相关的问题。
本申请提出了一种基于电流积分的脉冲神经网络，包括前神经元输入，突触阵列以及后神经元电路，突触阵列的架构如图3a所示，可以理解是将图2中所示的突触阵列中电阻式NVM单元替换为存储器单元(cell)。所述突触阵列被配置为接收前神经元输入的脉冲信号，突触阵列由i*j个突触电路组成，i为行数，j为列数；i，j均为大于等于1的正整数；图中的n，m分别是前神经元的个数和后神经元个数。
每一所述突触电路包含一个存储器单元；
所述存储器单元由存储一位突触权重的传统6T SRAM，以及用于读取突触权重的串联着的2个晶体管组成；其中一个晶体管的栅极连接传统6T SRAM中一个反相器的输出，源极接高电平，漏极接另一晶体管源极，另一晶体管的栅极连接读字线，漏极连接读位线，读位线上导通电流为突触电路的输出电流；应当理解，所述传统6T SRAM由六个晶体管组成，其中四个场效应管构成两个交叉耦合的反相器中存储每一比特，另外的两个场效应管是存储基本单元到用于读写的位线的控制开关。如图3b为存储器单元的一个实施例，所述晶体管采用P沟道场效应管，应当理解，晶体管采用N沟道场效应管也可以工作。在另一实施例中，存储器单元还可以是论文“JSSC-2008-An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches”中IBM提出的基于传统6T SRAM的8-T SRAM单元，在该实施例中，采用N沟道场效应管读取传统6T SRAM单元内的存储的突触权重。
所述后神经元电路包含积分电容、比较器，每一个后神经元电路被配置为根据其连接的一列突触电路的输出电流在积分电容内的积分，基于积分电容两端累积电压与阈值电压的比较结果激发给下一级神经元脉冲信号。
具体地，该实施例在写入1位突触权重的过程中，写字线(write word line，WWL)被使能高电平，写位线(write bit line，WBL/ nWBL)被驱动到需要写的内容的互补电压，如写入w＝1,则WBL驱动至高电平， nWBL被 驱动至低电平。可以理解，电压电平“1”表示该电压等于电源电压VDD，电压电平“0”表示该电压等于接地电压VSS。
在读取过程中，使能读字线(read word line， nRWL)低电平，从读位线(read bit line，RBL)读取传统6T SRAM中存储的突触权重。
在计算过程中，并行来自前神经元的脉冲信号被发送到突触阵列的输入x i(i＝1，2，...，n)，每个输入x i与一行的 nRWL相连，即可以理解，读字线 nRWL携带输入向量，也可以说读字线 nRWL上作为SNN的脉冲输入。
同一列RBL连接到一个积分电容，该积分电容是后神经元电路的一部分，图3c为后神经元电路的一个实施例。应当理解，所述的行、列根据的输入的方向以及存储器单元的设置方式不同而不同，比如在另外的实施例中，当脉冲信号由列方向输入，存储器单元逆向旋转90度设置时，此时为每个输入x i与一列的 nRWL相连，同一行的RBL连接到一个积分电容。假设每个脉冲的持续时间为Δt，每个存储器单元中晶体管的导通电流为I 0，则由于一个脉冲的存在，积分电容C 0上的增量电压如下：
Figure PCTCN2021081340-appb-000002
在输入x i线上存在多个脉冲时，积分电容V mem上的累积电压变化总量为ΔV与脉冲数的乘积，每一个脉冲引起的电压变化乘以一列输入包含的总脉冲数指的是后神经元接收前一层所有神经元的脉冲信号。当积分电容上的电压V mem超过规定的阈值电压V ref，图3c中比较器S j(j＝1，2，...，m)的输出端就会产生一个脉冲，随后积分电容上的电压被复位到地。可以理解，此过程对应的生物神经元中的突触后神经元膜电位超过阈值电位，突触后神经元发出脉冲，随后该后神经元回落到静息电位。
可以理解，突触阵列的输出电流在后神经元电路内的积分电容上累积，得到的积分电容两端的电压与阈值电压进行比较。这一过程中，突触权重并不需要明确地从传统6T SRAM中读出，并基于比较结果决定是否激发给到下一层级神经元的脉冲，所述SNN架构采用在电荷域内计算的方式天然地兼容了神经元的工作方式，规避了从电流域中读出的问题。
特别地，虽然每个SRAM单元只能存储一位的信息，但上述实施例 基于SRAM存储器单元的脉冲神经网络可用于多位权重的计算。可选的，在多位突触权重的情况下，可以将来自多个IF神经元电路的脉冲信号从平行的位线RBL j上数字组合起来，视为一个整体的神经元脉冲输出，也即将多个后神经元电路从平行位线RBL j上根据突触权重位数组合列数，如突触权重有3位，那么被组合的列为3列，每列对应突触权重每位的位置，得到并行的比较器发出的脉冲信号由与比较器连接的并行的纹波计数器收集，纹波计数器中的值根据所在位的位权移位相加，基于移位相加的和值与数字阈值的比较结果激发给下一级神经元脉冲信号。
在一个实施例中，如图4a所示，为用于k位突触权重计算的架构，经组合的来自并行的k个比较器的脉冲由并行纹波计数器(cnt)收集。值得注意，根据每列所对应的突触权重的位的位置。例如，在一个实施例中，第k位的位权可以是2 k-1，每一个纹波计数器中的值被移位并与其他的纹波计数器中经移位的值相加。具体地，在该实施例中，第1列是最不重要的位(LSB)，不发生位移；第k列是最重要的位(MSB)，纹波计数器的值被左移k-1位，将用该k位突触权重的计算的所有纹波计数器移位相加得到的求和值与数字阈值(threshold)进行比较，一旦超过数字阈值，就会产生一个脉冲(spike)或多个脉冲，并在发出脉冲信号之后使该组合的神经元电路中的所有纹波计数器复位(reset)。可以理解，组合列数k是可编程的，其与突触权重的位宽相同。
应当特别注意，只要图3c中的阈值电压V ref足够小，使V mem被调节到一个低电压，图3b中的两个P沟道场效应管，被视为是一个单一的复合晶体管，当 nRWL上出现脉冲且W＝1时，可以保持饱和状态。晶体管在导通时工作在饱和区域，对保持相对一致的导通电流I 0、最小化其受晶体管漏端电压的影响很重要。可以采用长沟道长度来进一步提高复合晶体管的输出阻抗。
进一步地，为了提高用于多位突触权重计算时的面积效率，图3c中的比较器以及图4a中的电路需要进行修改和共享，用于一个k位权重计算的多列后神经元电路内共享一个比较器。具体地，如图4b所示的一个实施例，组合的列数内，积分电容器两端的累积电压以时间多路复用的方式连接到共享比较器的输入端，比较器的另一个输入端为阈值电压。本实 施例中，时间多路复用是由时钟控制的。应当注意，尽管时钟的概念似乎与异步系统不相容，但积分电容上累积电压的更新和脉冲通信并不是由时钟协调的，如果时钟频率相比于积分电压的变化速度足够高，系统可以近似看作是异步系统。
举例说明，当第j位(j∈[1,k])所对应的积分电容连接比较器时，与阈值V ref相比，如果累积电压V memj(j＝1，...,k)较大，比较器输出高时，使累加器通过D型寄存器更新其输出，比较器输出低时，累加器的输出不更新。可以理解，在多位突触权重的计算中，累加器中加法器的两个操作数分别是D型寄存器的输出和开关选择信号S sk根据当前位的位置选择的权重，也即选择的位权。应当注意，在图4b的实施例中，位权为2 k-1，但在其他的实施例中，每一列对应的位权不一定是按照2的等比数列分配，例如也可以是的8进制或者16进制等；特别地，在另一些实施例中，每一列的积分电容上的积分电压与其相应的阈值电压进行比较时，这些每列的阈值电压并不需要相同，也即每个后神经电路之间，阈值电压可以是不同。也可以说是，将每位所连接积分电容上累积电压单独与阈值电压比较，每位的结果需要与位权相对应，再将每位添加了位权的结果相加，直至相加的和值大于的数字阈值从而发出脉冲或者是所有位都进行相加完毕但没有的发出脉冲。
可选的，为了节省加法器的功率，在一些实施例中，权重的选择可根据比较器的输出进一步门控，比如只有比较器输出高时才将权重与加法器的输入端相连，否则改接0。
当S sk使能，与S sk对应的累积电压V memk连接比较器输入端，且当比较器输出为高电平时，S rk使能，使相应积分电容的累积电压复位到地；当比较器的输出为低时，S rk不使能，相应的积分电容的累积电压不被复位。进一步的，所有的位对应的积分电容上的累积电压都经过比较之后，在累加器的输出超过数字神经元阈值D TH时，产生脉冲，寄存器被复位，所有积分电容电位被复位到地。
可以理解，此处包含的两处复位，前者是每一位对应的累积电压高于阈值电压V ref，后者是对应多位权重的累积电压高于数字的神经元阈值D TH。也即积分电容被复位既可以因为其累积电压V memj大于阈值电压， 也可以是在由多列组合的突触权重发出脉冲。那么在一种可能的实施方式中，如图所示，比较器的输出和S sk与运算的输出作为或门的一个输入，或门的另一个输入是产生的脉冲，此或门的输出为S rk。
第二方面，提供了一种基于电流积分的存内脉冲神经网络，包括前神经元、突触阵列、后神经元电路：所述突触阵列被配置为接收前神经元输入的脉冲信号，突触阵列由i*j个突触电路组成，i为行数，j为列数；i，j均为大于等于1的正整数；每一所述突触电路包含一个存储器单元；
虽然现有基于电阻式NVM单元的存内SNN存在非理想性的问题，但在一个实施例中，单晶体管单忆阻器(one-memristor one-transistor，1R1T)的NVM单元也可以从上述SNN架构中获益。图3a中使用NVM单元可以如图5a所示构建。具体地，所述存储器单元由1个NVM电阻与1个场效应管组成，NVM电阻的一端连接场效应管的漏极，一端连接位线BL，位线上导通电流为突触电路的输出电流；所述场效应管的源极连接源线SL，栅极连接字线WL。在这种拓扑结构下，NVM元件两端电压会随积分电容上极板的电压的变化而改变，从而使得流过NVM元件的电流随之改变。这样的积分电流的特质虽然也可以用来构建SNN，但是等式1已不再成立，需要特定的SNN训练算法来考虑这一点。如果要用满足等式1的训练算法，则在一种实施例中，需要在位线上加入如图5b所示的额外的电路。一个p型场效应晶体管的源极接位线，漏极接积分电容，栅极接误差放大器的输出。误差放大器的正输入端接一个参考电压，负输入端接位线。
所述后神经元电路包含积分电容、比较器，每一个后神经元电路被配置为根据其连接的一列突触电路的输出电流在积分电容内的积分，基于积分电容两端累积电压与阈值电压的比较结果激发给下一级神经元脉冲信号。
同样的，该存内脉冲神经网络的工作方式与第一方面类似。具体地，突触阵列接收前一神经元电路的输入是通过每一前神经元输入的脉冲信号连接一行突触电路的字线实现，即电压脉冲通过字线施加。后神经元电路发出脉冲信号后，积分电容两端累积电压复位到零，若积分电容一端接地，那么积分电容两端的累积电压为积分电容上极板的电压。
为了解决现有技术中没有充分解决的因制造工艺、电压和温度(PVT)引起的导通电流的变化，申请人提出了一种脉冲脉宽自动校准电路，可以抵消上述因素带来的导通电流的变化。
具体地，任何制造工艺、电压和温度(PVT)变化引起的I 0的变化都可以通过调整脉冲序列的脉宽Δt来补偿，调整程序可以是自动的。可选的，在一个实施例中，如图6a所示，未经校准的尖峰前缘(在不失通用性的前提下假设为正)将晶体管M a和M b的栅极设置为低电平，M a和M b为图3b中用于读取的2个P沟道场效应管的复制晶体管，导通电流开始对电容器C x充电。一旦C x上的电位超过阈值电压V ref，比较器输出就变成高电平，并将M a和M b的栅极再次置高。这样，x i的脉宽就会根据复合晶体管M a和M b的导通电流自动调整，并作为像图3a中的输入那样将脉冲宽度为Δt的脉冲序列送入到SNN阵列中。在图6a中，使用SR锁存器的条件是输入脉冲的脉宽小于输出脉冲。校验原理可以用下式表示：
Figure PCTCN2021081340-appb-000003
其中Δt表示需调整的脉宽，V ref为阈值电压，I 0为输出电流，C 0为电容容值。
可选的，如果有合理分辨率的时钟，可以如图6b所示的校准电路将脉冲的校准脉宽数字化存储。其工作机理仍受等式3制约。当校准启用，计数器开始对时钟周期进行计数，当C x上的积分电压超过V ref时停止计数。在本实施例中，用来重置C x上积分电压的开关用n型场效应晶体管实现。当比较器输出为高，使得或非门输出为低时停止计数。然后，计数器中存储的值就可以像图3a一样，应用于所有输入的脉冲到阵列中，而不需要频繁地启用这个校准电路。
应当注意，图6a，图6b的实施例同样可基于NVM单元的SNN架构。可选的，用图5b的实施例中1R1T结构代替M a和M b。具体地，NVM单元内的P沟道场效应管的源极连接到VDD，R经由位线上的P型场效应晶体管后由其漏极连接到C x。
因此，也可以理解，本申请所提出SNN架构以及校准原理不仅与8T SRAM是适应的，NVM单元也可以从所述SNN架构中获益。也可以理 解，存储器单元选择的形式为8T SRAM或者是NVM，基于该存储器单元的脉冲神经网络都可以具备所述有益效果。进一步，应当理解，本申请所提出的基于电流积分的脉冲神经网络，采用的存储器单元不局限于8T SRAM或者NVM单元。理论上，所述存储器单元还可以是能满足电流相加原理同时电流能不受后神经元中电容上的积分电压的影响的其他形式。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
本领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的装置和设备的具体工作过程以及产生的技术效果，可以参考前述方法实施例中对应的过程和技术效果，可以清楚的通过附图以及文字描述确定，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种基于电流积分的存内脉冲神经网络，包括前神经元、突触阵列、后神经元电路，其特征在于：
    所述突触阵列被配置为接收前神经元输入的脉冲信号，突触阵列由i*j个突触电路组成，i为行数，j为列数；i，j均为大于等于1的正整数；
    每一所述突触电路包含一个存储器单元；
    所述存储器单元由存储一位突触权重的传统6T SRAM，以及用于读取突触权重的串联着的2个晶体管组成，其中一个晶体管的栅极连接传统6T SRAM中一个反相器的输出，源极接高电平，漏极接另一晶体管源极，另一晶体管的栅极连接读字线，漏极连接读位线，读位线上导通电流为突触电路的输出电流；
    所述后神经元电路包含积分电容、比较器，每一个后神经元电路被配置为根据其连接的一列突触电路的输出电流在积分电容内的积分，基于积分电容两端累积电压与阈值电压的比较结果激发给下一级神经元脉冲信号。
  2. 如权利要求1所述的脉冲神经网络，其特征在于，每一前神经元输入的脉冲信号连接一行突触电路中的读字线。
  3. 如权利要求2所述的脉冲神经网络，其特征在于，后神经元电路发出脉冲信号后，积分电容两端累积电压复位到零。
  4. 如权利要求1至3中任一项所述的脉冲神经网络，其特征在于，用于多位突触权重计算时，根据突触权重位数组合列数，每列突触电路对应突触权重每位的位置，得到并行的比较器分别发出脉冲信号，所述脉冲信号分别由与比较器连接的纹波计数器收集，纹波计数器中的值根据所在位的位权移位相加，基于所有纹波计数器移位相加的和值与数字阈值的比较结果激发给下一级神经元脉冲信号。
  5. 如权利要求4所述的脉冲神经网络，其特征在于，组合的列数内，积分电容两端累积电压通过时间多路复用的方式共用一个比较器的输入端，根据开关选择信号选择与阈值电压比较的与所在位对应的累积电压。
  6. 如权利要求5所述的脉冲神经网络，其特征在于，比较器输出端连接一个寄存器，比较器输出为高时，则寄存器的输出作为与其连接的加法器的一个操作数。
  7. 如权利要求6所述的脉冲神经网络，其特征在于，加法器的另一个操作数为所在位位权，加法器的输出高于数字阈值，后神经元电路发出脉冲信号。
  8. 如权利要求7所述的脉冲神经网络，其特征在于，每一列的积分电容上的积分电压与其相应的阈值电压进行比较时，不同列的阈值电压不相同。
  9. 如权利要求1所述的脉冲神经网络，其特征在于，神经网络还包括自动校准电路，PVT引起的突触电路输出电流变化通过调整脉宽补偿，得到的调整脉宽重新作为突触阵列的输入，校验原理为：
    Figure PCTCN2021081340-appb-100001
    其中，Δt表示需调整的脉宽，V ref为阈值电压，I 0为输出电流，C 0为电容值。
  10. 一种基于电流积分的存内脉冲神经网络，包括前神经元、突触阵列、后神经元电路，其特征在于：
    所述突触阵列被配置为接收前神经元输入的脉冲信号，突触阵列由i*j个突触电路组成，i为行数，j为列数；i，j均为大于等于1的正整数；
    每一所述突触电路包含一个存储器单元；
    所述存储器单元由1个NVM电阻与1个场效应管组成，NVM电阻的一端连接场效应管的漏极，一端连接位线，位线上导通电流为突触电路的输出电流；所述场效应管的源极连接源线，栅极连接字线。
    所述后神经元电路包含积分电容、比较器，每一个后神经元电路被配置为根据其连接的一列突触电路的输出电流在积分电容内的积分，基于积分电容两端累积电压与阈值电压的比较结果激发给下一级神经元脉冲信号。
  11. 如权利要求10所述的脉冲神经网络，其特征在于，位线上导通电流注入到积分电容上进行积分之前，经过另一个场效应晶体管；所述场效应晶体管源极接位线，漏极接积分电容的上极板，栅极接一个误差放大器的输出端，所述误差放大器的正输入端接一个参考电压，负输入端接位线。
  12. 如权利要求10或11任一项所述的脉冲神经网络，其特征在于， 后神经元电路发出脉冲信号后，积分电容两端累积电压复位到零，若积分电容一端接地，那么积分电容两端的累积电压为积分电容上极板的电压。
  13. 如权利要求12所述的脉冲神经网络，其特征在于，神经网络还包括自动校准电路，通过调整脉宽抵消PVT引起的突触电路输出电流变化，得到的调整脉宽重新作为突触阵列的输入。
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