WO2022053030A1 - 一种芯片调试方法、芯片及芯片调试系统 - Google Patents

一种芯片调试方法、芯片及芯片调试系统 Download PDF

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Publication number
WO2022053030A1
WO2022053030A1 PCT/CN2021/117813 CN2021117813W WO2022053030A1 WO 2022053030 A1 WO2022053030 A1 WO 2022053030A1 CN 2021117813 W CN2021117813 W CN 2021117813W WO 2022053030 A1 WO2022053030 A1 WO 2022053030A1
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processing core
debugging
chip
debug
processing
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PCT/CN2021/117813
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English (en)
French (fr)
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季伟才
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北京希姆计算科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G06F11/3656—Software debugging using additional hardware using a specific debug interface
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

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  • the present application relates to the field of chips, in particular to a chip debugging method, a chip and a chip debugging system.
  • SoCs When the chip executes a software program, a debugging method is required for the software personnel to debug the program.
  • SoCs With the increasing scale of chip design, SoCs also integrate more and more core systems, especially artificial intelligence chips, with dozens or even hundreds of computing cores.
  • each processing core usually performs different tasks, and the correlation between the tasks is not strong. Therefore, usually, when debugging a multi-core chip, one processing core is debugged at a time.
  • the purpose of this application is to provide a chip debugging method, a chip and a chip debugging system.
  • the method is activated by a target processing core to form a debugging processing core chain, which can debug each processing core on the debugging processing core chain at the same time, and the method is simple and easy to use. , and can flexibly form a debug processing core chain according to the needs to meet the debugging needs of artificial intelligence chips.
  • a first aspect of the present application provides a chip debugging method, the chip includes a plurality of processing cores connected on a link, wherein the debugging method includes: activating a target processing core in the plurality of processing cores , so that the target processing core is connected to the debug processing core chain; debug data is transmitted to the target processing core through the debug processing core chain; each of the target processing cores is controlled to run the respective debug data simultaneously.
  • the chip debugging method provided by the embodiments of the present application forms a chain of debugging and processing cores by activating the target processing core, and can simultaneously debug each processing core on the chain of debugging and processing cores.
  • the method is simple and easy to use, and the debugging processing can be flexibly formed according to requirements
  • the core chain meets the debugging needs of artificial intelligence chips.
  • each of the processing cores is provided with a selector
  • the activating a target processing core in the plurality of processing cores includes: sending an activation signal to enable the selector in the target processing cores state becomes active.
  • the hold signal is sent to keep the selector state in the non-target processing core in an inactive state.
  • transmitting the debug data to the target processing core through the debug processing core chain includes: sequentially sending the debug data to the target processing core with a higher order in the debug processing core chain , the original debugging data of each target processing core is transferred to the next target processing core.
  • the method before activating a target processing core in the plurality of processing cores so that the target processing core is connected to the chain of debug processing cores, the method further includes: receiving a debug instruction, the debug instruction being used to instruct The target processing core in the multiple processing cores is activated; the transmission format of the debug instruction is converted into the IJTAG protocol format; each target processing core on the debug processing core chain transmits the debug instruction and debug data through the IJTAG protocol.
  • a chip including a plurality of processing cores; the processing cores are configured to be connected to a chain of debugging processing cores according to an activation signal; the processing cores on the chain of debugging processing cores receive debug data; the processing cores on the debug processing core chain run their respective debug data simultaneously.
  • each of the processing cores is provided with a selector; the processing core is configured to change its own selector state to an active state according to the received activation signal to connect to the debug processing core chain.
  • the processing core is configured to maintain its own selector state as an inactive state according to the received hold signal.
  • the first processing core in the chain of debugging processing cores receives the debugging data, and transmits the original debugging data to the next processing core.
  • a JTAG interface is further included, the output end of the JTAG interface is connected with the input end of the first processing core in the link, and the input end of the JTAG interface is connected with the tail processing core in the link output connection.
  • each processing core is provided with an IJTAG interface, and the processing cores on the debug processing core chain transmit data through the IJTAG interface.
  • a card board including one or more chips provided in the second aspect.
  • an electronic device including one or more card boards provided in the third aspect.
  • a chip debugging system comprising: a chip debugger for sending debugging instructions and debugging data; a chip including a plurality of processing cores, the chip for The target processing cores are activated, so that the target processing cores are connected to form a chain of debug processing cores, and the received debug data is transmitted to the target processing cores through the debug processing chain, so that each of the target processing cores Run the respective debug data at the same time.
  • the chip debugger is provided with a JTAG interface, and the chip debugger sends debugging instructions and debug data through the JTAG interface;
  • the chip is provided with a JTAG interface and a protocol conversion module, and each processing core is provided with IJTAG interface;
  • the chip is used to receive data sent by the chip debugger through its own JTAG interface;
  • the protocol conversion module is used to convert the data received by the chip into the IJTAG protocol format; the debugging processing core chain
  • Each of the processing cores transmits the data through the IJTAG interface.
  • a computer storage medium stores a program, and when the program is executed, the chip debugging method provided in the first aspect is implemented,
  • an electronic device including a memory, a processor, and a computer program stored in the memory and running on the processor, and the chip debugging method provided in the first aspect is implemented when the processor executes the program .
  • a computer program product which includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute the chip debugging method provided in the first aspect.
  • the chip debugging method provided by the embodiments of the present application forms a chain of debugging processing cores by activating the target processing core, and can simultaneously debug each processing core on the processing core chain.
  • the method is simple and easy to use, and the debugging processing can be flexibly formed according to requirements.
  • the core chain meets the debugging needs of artificial intelligence chips.
  • FIG. 1 is a schematic flowchart of a chip debugging method provided according to a first embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a chip according to a second embodiment of the present application.
  • FIG. 3 is a schematic diagram of a debug processing core chain provided according to a second embodiment of the present application.
  • FIG. 1 is a schematic flowchart of a chip debugging method provided according to a first embodiment of the present application.
  • the chip includes a plurality of processing cores sequentially connected to a link.
  • each processing core is numbered sequentially.
  • the chip debugging method includes:
  • Step S101 activating a target processing core among the plurality of processing cores, so that the target processing core is connected to the debug processing core chain, and the target processing core is at least one of the plurality of processing cores to be debugged.
  • step S102 debug data is transmitted to the target processing core through the debug processing core chain.
  • Step S103 controlling each of the target processing cores to run their respective debug data simultaneously.
  • each processing core on the debugging processing core chain can be debugged simultaneously.
  • the method is simple and easy to use, and can be used according to the It is required to flexibly form a debugging and processing core chain to meet the debugging needs of artificial intelligence chips.
  • each processing core in the chip is provided with a selector sel, wherein activating a target processing core in the plurality of processing cores, so that the target processing core is connected to the debug processing core chain, includes:
  • An activation signal is sent to cause the selector state in the target processing core to become an active state.
  • an external chip debugger may send an activation signal to the target processing core of the chip, and the sel of the target processing core changes the state of the sel to the activated state according to the received activation signal.
  • the state of the sel of the target processing core becomes the active state, which means that the target processing core is activated.
  • the activated multiple The core forms a debug processing core chain.
  • a hold signal is sent to the non-target processing core to keep the sel in the non-target processing core in an inactive state.
  • an external chip debugger can send a debug command, the debug command includes a hold signal and an activation signal, and each processing core will receive its own debug command.
  • the sel of the processing core that receives the hold signal remains in the inactive state, and the state of the sel of the processing core that receives the activation signal becomes the active state, so that all activated processing cores form a debug processing core chain.
  • transmitting debug data to the target processing core through the debug processing core chain includes:
  • the debug data is sequentially sent to the target processing cores in the debug processing core chain, and each target processing core transmits its own original debug data to the next target processing core.
  • the first target processing core first receives the first debugging data sent by the external debugger, and sends the debugging data originally stored by itself to the second target processing core, and the second target processing core sends the originally stored debugging data to the second target processing core.
  • the debugging data is sent to the next target processing core, and so on.
  • the second-to-last target processing core receives the debugging data sent by the third-to-last target processing core, and sends the original debugging data stored by itself to the last target processing core.
  • the last target processing core will send the debug data originally stored by itself to the external chip debugger until the last target processing core receives the first debug data.
  • the first target processing core receives the debugging data B4 sent by the chip debugger, and sends the debugging data A1 stored by itself to the second target processing core
  • the second target processing core stores A1 and sends the debug data A2 stored by itself to the third target processing core
  • the third target processing core stores A2 and sends the debug data A3 stored by itself to the fourth target processing core.
  • the fourth target processing core will store A3 and send its own stored debug data A4 to the debugger.
  • the chip debugger sends the debugging data B3 to the first target processing core, and the first target processing core sends the last stored B4 to the second target processing core, and so on, until the chip debugger has sent all the data to be debugged.
  • the data In other words, when the chip debugger finishes sending B1, it means that all the data to be debugged this time have been sent.
  • controlling each of the target processing cores to run their respective debug data at the same time includes: after each of the processing cores has received the respective data to be debugged this time, and the state machine of the JTAG interface of the chip changes to an update state ( update state), each target processing core on the debug processing core chain runs the respective debug data simultaneously.
  • the chip is further provided with a JTAG interface, all processing cores in the chip are sequentially connected to form a processing core chain, and the output end of the JTAG interface is connected to the input end of the first processing core among all the processing cores of the chip, that is, The output terminal of the JTAG interface is connected to the input terminal of the first processing core of the processing core chain, and the input terminal of the JTAG interface is connected to the output terminal of the tail processing core in all processing cores of the chip, that is, the input terminal of the JTAG interface is connected to the processing core of the processing core.
  • the output terminal of the tail processing core of the core chain, the external chip debugger sends the debugging data to the debugging processing core chain of the chip through the JTAG interface.
  • all the processing cores of the chip are connected to each other to form a processing core chain; and the debugging processing core chain is formed by the target processing core that needs to be debugged at the same time according to Sel, so the processing cores on the processing core chain are The number is greater than or equal to the number of processing cores on the debug processing core chain.
  • a target processing core of the plurality of processing cores before activating a target processing core of the plurality of processing cores to connect the target processing core to the debug processing core chain, further comprising:
  • the debug instruction is used to instruct a target processing core in the plurality of processing cores to activate and instruct a non-target processing core in the plurality of processing cores to remain in an inactive state;
  • the transmission format of the debug instruction is converted into the IJTAG protocol format; each processing core of the chip transmits the debug instruction through the IJTAG protocol; the target processing core on the debug processing core chain transmits the debug data through the IJTAG protocol.
  • the debug command is transmitted by the external chip debugger through the JTAG interface, that is, the format of the debug command received by the chip is the format under the JTAG protocol. Therefore, after the chip receives the debug command, it first converts the debug command format into the IJTAG protocol format, which is convenient for the target processing core on the debug processing core chain to transmit the debug command in the IJTAG protocol format.
  • both the chip debugger and the chip are provided with a JTAG interface, and each processing core of the chip is provided with an IJTAG interface.
  • the chip debugger sends the debugging instructions in the JTAG protocol format to the JTAG interface of the chip through its own JTAG interface, and then the chip receives the debugging instructions in the JTAG protocol format through its own JTAG interface, and converts the JTAG protocol through its own protocol conversion module.
  • the debugging instructions in the protocol format are converted into the IJTAG protocol format, and then the debugging instructions in the IJTAG protocol format are transmitted to the first processing core through the IJTAG interface of the first processing core of the processing core chain of the chip, and each processing core of the chip transmits the debugging instructions through the IJTAG protocol.
  • each processing core needs to be connected to a JTAG interface, and each processing core needs to be debugged respectively.
  • multiple processing cores are connected in sequence, and the first processing core and the tail processing core are connected to the JTAG interface, which can save the pins of the chip.
  • FIG. 2 is a schematic structural diagram of a chip according to a second embodiment of the present application.
  • the chip includes a plurality of processing cores.
  • the chip has 32 processing cores, Core0-Core31.
  • each processing core is used to connect to the debug processing core chain according to the activation signal.
  • Each of the processing cores on the chain of debug processing cores receives debug data.
  • Each of the processing cores on the chain of debug processing cores runs their respective debug data simultaneously.
  • each processing core is connected to the debug processing core chain according to the activation signal, so that each processing core on the debug processing core chain can be debugged at the same time.
  • the method is simple and easy to use, and can be configured and debugged flexibly according to requirements. Process the core chain to meet the debugging needs of artificial intelligence chips.
  • each processing core is provided with a selector sel. Wherein, the processing core is used to change its selector state into an active state according to the received activation signal, so as to connect to the debug processing core chain.
  • the processing core is configured to maintain its own selector state as an inactive state according to the received hold signal.
  • the first processing core on the chain of debugging processing cores is used to receive debugging data; the other processing cores on the chain of debugging processing cores are used to receive the debugging data transmitted from the respective previous processing cores.
  • the first processing core on the debugging processing core chain receives the debugging data sent by the external chip debugger, and the other processing cores on the debugging processing core chain all receive the debugging data transmitted from their respective previous processing cores.
  • the tail processing core is used to transfer the original debug data back to the external chip debugger.
  • the chip further includes a JTAG interface, an output end of the JTAG interface is connected to the input end of the first processing core among all the processing cores in the chip, and the input end of the JTAG interface is connected to the tail processing end of all the processing cores in the chip The output of the core is connected.
  • the chip further includes a protocol conversion module, the protocol conversion module is connected to the JTAG interface, the chip is used to receive the debugging instructions sent by the chip debugger through its own JTAG interface, and convert the debugging instructions into IJTAG through its own protocol conversion module Format; debug commands are transmitted between each processing core of the chip through their respective IJTAG interfaces.
  • the protocol conversion module is connected to the JTAG interface, the chip is used to receive the debugging instructions sent by the chip debugger through its own JTAG interface, and convert the debugging instructions into IJTAG through its own protocol conversion module Format; debug commands are transmitted between each processing core of the chip through their respective IJTAG interfaces.
  • the chip is configured to receive debug data sent by the chip debugger through its own JTAG interface, and convert the debug data into IJTAG format through its own protocol conversion module.
  • the IJTAG interface transfers debug data.
  • a card board including one or more chips provided in the second embodiment.
  • an electronic device including one or more card boards provided in the third embodiment.
  • FIG. 3 is a schematic diagram of a debug processing core chain provided according to a second embodiment of the present application.
  • the jtag2ijtag represents a protocol conversion module, which is used to convert the jtag protocol to ijtag.
  • the chip includes a JTAG interface and 32 processing cores, each of which is core0-core31, and the 32 processing cores are numbered 0-31 in sequence.
  • the length of the debug data register (DR) of each processing core is 30 bits
  • a sel is set inside each processing core, and sel is used to determine whether the current core is on the IJTAG chain of the debugging processing core, that is When sel is activated, it means that the core is on the IJTAG chain, and when sel is not activated, it means that the core is not on the IJTAG chain.
  • a processing core with sel in gray indicates that the processing core is on the IJTAG chain.
  • each processing core is provided with an IJTAG interface, and debugging instructions or debugging data are transmitted between the processing cores through the IJTAG interface.
  • sel can be a JTAG data register (JTAG Data Register, JTAG DR).
  • JTAG DR JTAG Data Register
  • each JTAG DR occupies 1 byte.
  • the specific debugging methods of the chip include:
  • the debug commands in the JTAG format transmitted under the JTAG protocol are converted into the debug commands in the IJTAG format under the IJTAG protocol through the protocol conversion module.
  • each processing core receives debug commands in IJTAG format through respective IJTAG interfaces.
  • the sel of the target processing core changes the state to the active state according to the debug command, and the sel of the non-target processing core keeps the state inactive according to the debug command, so that the target processing cores that need to be debugged at the same time are all in the active state.
  • the debugging during this configuration is for the target processing core on the IJTAG chain.
  • the debug command is 32'h0A0A_0055.
  • 32 represents 32 bits, that is, the debugging instruction includes 32 debugging signals.
  • Debug signals include activate signals and hold signals.
  • 'h represents hexadecimal
  • 0A0A_0055 represents hexadecimal number.
  • the debugging instruction is 00001010000010100000000001010101, that is, the 32-bit binary numbers correspond to the 0th processing core from left to right.
  • each number in the 32 binary numbers represents a debug signal, where 1 means is the activation signal, and 0 is the hold signal.
  • setting the sel corresponding to the target core to be debugged and shifting 32 debug signals in sequence with JTAG means: these 32-bit debug signals, the first debug signal on the right is 1 (the signal The actual corresponding is to control the 31st processing core), the first debug signal on the right will be sent to the sel of the 0th processing core for storage, and then the sel of the 0th processing core will send the original debug signal stored by itself to the first.
  • the 31st processing core stores the 30th processing core's sel original debugging signal, and sends its own original debugging signal back to the chip debugger, and then the chip debugger sends the second debugging signal on the right
  • the sel of the 0th processing core will send the sel debug signal 1 stored last time to the 1st processing core, and so on, until the 0th processing core stores the first debugging signal on the left Signal 0, the 1st processing core stores the second debug signal 0 on the left, ..., and the 31st processing core stores the first debug signal 1 on the right. It means that each processing core has received its own debugging instructions.
  • the above-mentioned debugging instruction 32'h0A0A_0055 instructs the fourth processing core, the sixth processing core, the twelfth processing core, the fourteenth processing core, the twenty-fifth processing core, the twenty-seventh processing core, the twenty-ninth processing core
  • the core and the sel of the thirty-first processing core become active.
  • the sel of the remaining processing cores remains inactive.
  • the above debug command 32'h0A0A_0055 indicates that after the state machine of the JTAG interface of the chip becomes the update state (update), a total of 8 cores of core4, core6, core12, core14, core25, core27, core29, and core31 are connected to the IJTAG chain the target processing core.
  • the length of the IJTAG chain will change, and the new data length bits of the IJTAG chain are 8*30+32 (number of cores in the chain * DR length in each core + 32SEL module). Subsequent transmission of debug data will perform a DR shift operation according to the new IJTAG DR chain length.
  • the debug data is transmitted to each target processing core through the IJTAG chain, that is, the debug data is sent to the target processing cores in the IJTAG chain in turn, and each target processing core transmits its own original debug data to the next target processing core, until Each target processing core receives its own debug data.
  • a fifth embodiment of the present application provides a chip debugging system, including a chip debugger and a chip.
  • the chip debugger is used to send debugging instructions and debugging data.
  • the chip includes a plurality of processing cores, the chip is used for activating a target processing core in the plurality of processing cores according to the debug instruction, so that the target processing cores are connected to form a chain of debug processing cores, and through all the processing cores
  • the debug processing core chain transmits the received debug data to each of the target processing cores, so that each of the target processing cores runs the respective debug data simultaneously.
  • the chip debugger is provided with a JTAG interface, and the chip debugger sends debugging instructions and debugging data through the JTAG interface.
  • the chip is provided with a JTAG interface and a protocol conversion module, and each of the processing cores is provided with an IJTAG interface.
  • the chip is used to receive debugging instructions or debugging data sent by the chip debugger through its own JTAG interface; the protocol conversion module is used to convert the debugging instructions or debugging data received by the chip into the IJTAG protocol format; the debugging processing core chain
  • Each processing core on the device transmits debugging instructions or debugging data through the IJTAG interface.
  • a computer storage medium stores a program, and when the program is executed, the chip debugging method provided by the first aspect is implemented,
  • an electronic device including a memory, a processor, and a computer program stored in the memory and running on the processor, and the chip debugging provided in the first aspect is implemented when the processor executes the program method.
  • a computer program product which includes computer instructions, and when the computer instructions are executed by a computing device, the computing device can execute the chip debugging method provided by the first aspect.

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Abstract

本申请公开了一种芯片调试方法、芯片及芯片调试系统，其中，芯片包括顺次连接在一条链路上的多个处理核，其中，调试方法包括：将所述链路上的目标处理核激活，以形成调试处理核链；将调试数据通过所述调试处理核链传输至所述目标处理核；控制各个所述目标处理核同时运行各自的调试数据。本申请实施方式提供的芯片调试方法通过目标处理核激活，形成调试处理核链，可以对调试处理核链上的各个处理核同时调试，方法简单易用，而且可以根据需求灵活的形成调试处理核链，满足人工智能芯片的调试需求。

Description

一种芯片调试方法、芯片及芯片调试系统
交叉引用
本申请基于申请号为202010963128.3、申请日为2020年09月14日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及芯片领域、尤其是一种芯片调试方法、芯片及芯片调试系统。
背景技术
芯片执行软件程序时，需要有调试手段提供给软件人员调试程序。随着芯片设计规模越来越大，片上系统也集成了越来越多的内核系统，尤其人工智能芯片，计算内核几十个甚至上百个。
然而现有的对多核芯片通常是每个处理核分别执行不同的任务，各个任务之间的关联性不强，所以通常调试多核芯片是每次对一个处理核进行调试。
随着技术的发展，人工智能计算芯片中，通常是多个处理核共同执行一个任务，多个处理核之间的关联性比较强，因此，现有的芯片调试方法不能满足人工智能计算芯片的调试的需求。
发明内容
本申请的目的是提供一种芯片调试方法、芯片及芯片调试系统， 该方法通过目标处理核激活，形成调试处理核链，可以对调试处理核链上的各个处理核同时调试，方法简单易用，而且可以根据需求灵活的形成调试处理核链，满足人工智能芯片的调试需求。
为解决上述问题，本申请的第一方面提供了一种芯片调试方法，芯片包括连接在一条链路上的多个处理核，其中，调试方法包括：将多个处理核中的目标处理核激活，以使所述目标处理核连接至调试处理核链；将调试数据通过所述调试处理核链传输至所述目标处理核；控制各个所述目标处理核同时运行各自的调试数据。
本申请实施方式提供的芯片调试方法，通过目标处理核激活，形成调试处理核链，可以对调试处理核链上的各个处理核同时调试，方法简单易用，而且可以根据需求灵活的形成调试处理核链，满足人工智能芯片的调试需求。
在一些实施例中，每个所述处理核均设置有选择器，所述将多个处理核中的目标处理核激活，包括：发送激活信号，使所述目标处理核内的所述选择器状态变为激活状态。
在一些实施例中，发送保持信号，使非目标处理核内的选择器状态保持未激活状态。
在一些实施例中，将调试数据通过所述调试处理核链传输至所述目标处理核，包括：将所述调试数据依次送入所述调试处理核链中位次靠前的目标处理核中，每一个所述目标处理核的原调试数据向下一目标处理核中传递。
在一些实施例中，在将所述多个处理核中的目标处理核激活，以 使所述目标处理核连接至调试处理核链之前，还包括:接收调试指令，所述调试指令用于指示多个处理核中的目标处理核激活；将所述调试指令的传输格式转换成IJTAG协议格式；调试处理核链上的各个目标处理核通过IJTAG协议传输所述调试指令和调试数据。
根据本申请的第二方面，提供了一种芯片，包括多个处理核；所述处理核，用于根据激活信号连接至调试处理核链；所述调试处理核链上的所述处理核接收调试数据；所述调试处理核链上的所述处理核同时运行各自的调试数据。
在一些实施例中，每个所述处理核均设置有选择器；所述处理核用于根据接收的所述激活信号将自身的选择器状态变为激活状态以连接至调试处理核链。
在一些实施例中，所述处理核用于根据接收的保持信号，保持自身的选择器状态为未激活状态。
在一些实施例中，所述调试处理核链中位次靠前的处理核接收调试数据，并将原调试数据向下一处理核中传递。
在一些实施例中，还包括JTAG接口，所述JTAG接口的输出端与所述链路中的首处理核的输入端连接，所述JTAG接口的输入端与所述链路中的尾处理核的输出端连接。
在一些实施例中，每个处理核均设置有IJTAG接口，所述调试处理核链上的处理核通过所述IJTAG接口传输数据。
根据本申请的第三方面，提供了一种卡板，包括一个或多个第二方面提供的芯片。
根据本申请的第四方面，提供了一种电子设备，包括一个或多个第三方面提供的卡板。
根据本申请的第五方面，提供了一种芯片调试系统，包括：芯片调试器，用于发送调试指令和调试数据；芯片，包括多个处理核，所述芯片用于根据所述调试指令将目标处理核激活，以使所述目标处理核相连接以形成调试处理核链，并通过所述调试处理链将接收的所述调试数据传输至所述目标处理核，使各个所述目标处理核同时运行各自的调试数据。
在一些实施例中，芯片调试器设置有JTAG接口，所述芯片调试器通过JTAG接口发送调试指令和调试数据；所述芯片设置有JTAG接口和协议转换模块，每个所述处理核均设置有IJTAG接口；所述芯片用于通过自身的JTAG接口接收所述芯片调试器发送的数据；所述协议转换模块用于将芯片接收的所述数据转换成IJTAG协议格式；所述调试处理核链上的各个处理核通过所述IJTAG接口传输所述数据。
根据本申请的第六方面，提供了一种计算机存储介质，该存储介质存储有程序，该程序执行时实现第一方面提供的芯片调试方法，
根据本申请的第七方面，提供了一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行程序时实现第一方面提供的芯片调试方法。
根据本申请的第八方面，提供一种计算机程序产品，其中，包括计算机指令，当计算机指令被计算设备执行时，计算设备可以执行第一方面提供的芯片调试方法。
本申请实施方式提供的芯片调试方法，通过激活目标处理核，形成调试处理核链，可以对调试处理核链上的各个处理核同时调试，方法简单易用，而且可以根据需求灵活的形成调试处理核链，满足人工智能芯片的调试需求。
附图说明
图1是根据本申请第一实施方式提供的芯片调试方法的流程示意图；
图2是根据本申请第二实施方式的芯片的结构示意图；
图3是根据本申请第二实施方式提供的调试处理核链的示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚明了，下面结合具体实施方式并参照附图，对本申请进一步详细说明。应该理解，这些描述只是示例性的，而并非要限制本申请的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本申请的概念。
显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
图1是根据本申请第一实施方式提供的芯片调试方法的流程示意图。
在本实施方式中，芯片包括顺次连接在一条链路上的多个处理核。
在一些实施例中，每个处理核按照顺序编号。
如图1所示，该芯片调试方法包括：
步骤S101，将多个处理核中的目标处理核激活，使目标处理核连接至调试处理核链，所述目标处理核为待调试的至少一个所述多个处理核。
步骤S102，将调试数据通过所述调试处理核链传输至所述目标处理核。
步骤S103，控制各个所述目标处理核同时运行各自的调试数据。
本申请实施方式提供的芯片调试方法，通过将目标处理核激活，使目标处理核连接至调试处理核链，可以对调试处理核链上的各个处理核同时调试，方法简单易用，而且可以根据需求灵活的形成调试处理核链，满足人工智能芯片的调试需求。
在一些实施例中，芯片中的每个处理核均设置有选择器sel，其中，将多个处理核中的目标处理核激活，以使所述目标处理核连接至调试处理核链，包括：
发送激活信号，使所述目标处理核内的所述选择器状态变为激活状态。
在一些实施例中，例如可以是外部的芯片调试器向芯片的目标处理核发送激活信号，目标处理核的sel根据接收的激活信号，sel的状态变为激活状态。
可以理解的是，目标处理核的sel的状态变为激活状态，则表示目标处理核被激活，当待同时调试的每个处理核的sel的状态都为激活状态时，被激活的多个处理核就形成了一条调试处理核链。
在一些实施例中，向非目标处理核发送保持信号，使非目标处理核内的sel保持未激活状态。
可以理解的是，在本实施例中外部的芯片调试器可以发送调试指令，该调试指令包括保持信号和激活信号，每个处理核都会收到各自的调试指令。收到保持信号的处理核的sel保持未被激活状态，收到激活信号的处理核的sel的状态变为激活状态，使得所有被激活的处理核形成调试处理核链。
在一些实施例中，将调试数据通过所述调试处理核链传输至所述目标处理核，包括：
将调试数据依次送入调试处理核链中的目标处理核，每一个所述目标处理核将自身的原调试数据传输至向下一目标处理核。
在一些实施例中，第一个目标处理核先接收外部调试器发送的第一调试数据，将自身原来存储的调试数据发送给第二个目标处理核，第二个目标处理核将原来存储的调试数据发送给下一个目标处理核，依次类推，倒数第二个目标处理核接收倒数第三个目标处理核发送的调试数据，将自身存储的原来的调试数据发送给最后一个目标处理核。最后一个目标处理核会将自己原来存储的调试数据发送给外部芯片调试器，直到最后一个目标处理核接收到第一调试数据。
可以理解的是，由于本次待调试的多个处理核的调试数据都是芯 片调试器发送的，而且各个目标处理核会依次向下一个处理核传递调试数据，所以当芯片调试器将本次需要调试的目标处理核的调试数据发送完成，则确认所有的目标处理核均接收到了各自的调试数据。
例如，调试处理核链上有4个处理核，第一个目标处理核接收芯片调试器发送的调试数据B4，将自身存储的调试数据A1发送给第二个目标处理核，第二个目标处理核存储A1并将自身存储的调试数据A2发送给第三个目标处理核，第三个目标处理核存储A2并将自身存储的调试数据A3发送给第四个目标处理核。第四个目标处理核将存储A3并将自身存储的调试数据A4发送给调试器。接着芯片调试器将调试数据B3发给第一个目标处理核，第一个目标处理核将上次存储的B4发送给第二个目标处理核，依次类推，直至芯片调试器发送完所有待调试的数据。换言之，当芯片调试器将B1发送完成时，表示本次所有的待调试的数据已经发送完成。
在一些实施例中，控制各个所述目标处理核同时运行各自的调试数据包括：当各个处理核均接收到各自的本次要调试的数据后，且芯片的JTAG接口的状态机变为更新状态(update状态)时，调试处理核链上的各个目标处理核同时运行各自的调试数据。
在一些实施例中，芯片还设置有JTAG接口，所述芯片中的所有处理核依次连接形成处理核链，JTAG接口的输出端与芯片的所有处理核中的首处理核的输入端连接，即JTAG接口的输出端连接到处理核链的首处理核的输入端，所述JTAG接口的输入端与芯片的所有处理核中的尾处理核的输出端连接，即JTAG接口的输入端连接到处理 核链的尾处理核的输出端，外部的芯片调试器通过JTAG接口将调试数据发送给芯片的调试处理核链。
需要说明的是，芯片的所有的处理核相互连接形成了处理核链；而调试处理核链是根据Sel，由本次需要同时调试的目标处理核形成的，所以处理核链上的处理核的个数大于或等于调试处理核链上的处理核的个数。
在一些实施例中，在将所述多个处理核中的目标处理核激活，以使所述目标处理核连接至调试处理核链之前，还包括:
接收调试指令，所述调试指令用于指示多个处理核中的目标处理核激活以及，指示多个处理核中的非目标处理核保持未激活状态；
将所述调试指令的传输格式转换成IJTAG协议格式；芯片的各个处理核通过IJTAG协议传输所述调试指令；调试处理核链上的目标处理核通过IJTAG协议传输调试数据。
其中，调试指令是外部的芯片调试器通过JTAG接口传输的，即芯片接收的调试指令的格式是JTAG协议下的格式。因此，芯片收到调试指令之后，先将调试指令格式转换为IJTAG协议格式，便于调试处理核链上的目标处理核传输IJTAG协议格式下的调试指令。
换言之，芯片调试器和芯片均设置有JTAG接口，芯片的各个处理核均设置有IJTAG接口。其中，芯片调试器通过自身的JTAG接口将JTAG协议格式的调试指令发送给芯片的JTAG接口，然后芯片通过自身的JTAG接口收到JTAG协议格式的调试指令之后，通过自身的协议转换模块，将JTAG协议格式的调试指令转换为IJTAG协议格式， 然后将IJTAG协议格式的调试指令通过芯片的处理核链的首处理核的IJTAG接口传输至首处理核，芯片的各个处理核通过IJTAG协议传输调试指令。
需要说明的是，如果采用现有技术的芯片调试方法，需要每个处理核分别连接一个JTAG接口，分别对各个处理核进行调试。而本申请实施方式中，多个处理核顺次连接，首处理核和尾处理核与JTAG接口连接，可以节省芯片的管脚。
图2是根据本申请第二实施方式的芯片的结构示意图。
如图2所示，芯片包括多个处理核，在图2所示的实施例中，该芯片具有32个处理核，Core0-Core31。
其中，每个处理核，用于根据激活信号连接至调试处理核链。调试处理核链上的各个所述处理核接收调试数据。调试处理核链上的各个所述处理核同时运行各自的调试数据。
本申请实施方式提供的芯片，每个处理核根据激活信号连接至调试处理核链，进而可以对调试处理核链上的各个处理核同时调试，方法简单易用，而且可以根据需求灵活的配置调试处理核链，满足人工智能芯片的调试需求。
在一些实施例中，每个处理核都设置有选择器sel。其中，处理核用于根据接收的所述激活信号将自身的选择器状态变为激活状态以连接至调试处理核链。
在一个实施例中，所述处理核用于根据接收的保持信号，保持自身的选择器状态为未激活状态。
在一些实施例中，所述调试处理核链上的首处理核用于接收调试数据；所述调试处理核链上其他处理核，用于接收来自各自上一个处理核所传输的调试数据。
具体地，调试处理核链上的首处理核接收外部的芯片调试器发送的调试数据，调试处理核链上的其他处理核均接收来自各自上一个处理核所传输的调试数据。尾处理核用于将原调试数据传输回外部的芯片调试器。
在一些实施例中，芯片还包括JTAG接口，JTAG接口的输出端与芯片中所有处理核中的首处理核的输入端连接，所述JTAG接口的输入端与芯片中所有处理核中的尾处理核的输出端连接。
在一些实施例中，芯片还包括协议转换模块，协议转换模块与JTAG接口连接，芯片用于通过自身的JTAG接口接收芯片调试器发送的调试指令，通过自身的协议转换模块将调试指令转换为IJTAG格式；芯片的各个处理核之间通过各自IJTAG接口传输调试指令。
在一些实施例中，芯片用于通过自身的JTAG接口接收芯片调试器发送的调试数据，通过自身的协议转换模块将调试数据转换为IJTAG格式，调试处理核链路上的各个处理核通过各自的IJTAG接口传输调试数据。
根据本申请的第三实施方式，提供了一种卡板，包括一个或多个第二实施方式提供的芯片。
根据本申请的第四实施方式，提供了一种电子设备，包括一个或多个第三实施方式提供的卡板。
下面将结合附图详细说明本申请第二实施方式提供的芯片和芯片调试方法。
图3是根据本申请第二实施方式提供的调试处理核链的示意图。
如图3所示，该jtag2ijtag表示协议转换模块，用于将jtag协议转换为ijtag。
该芯片包括JTAG接口和32个处理核，每个处理核分别为core0-core31,这32个处理核的编号依次为0-31。其中，每个处理核的调试数据寄存器(Data Register，DR)的长度为30bit，每个处理核的内部都设置有一个sel，sel用于确定当前的core是否在调试处理核IJTAG链上，即当sel被激活，说明该core在IJTAG链上，当sel未被激活，说明该core不在IJTAG链上。
在图3所示的实施方式中，sel为灰色的处理核表示该处理核在IJTAG链上。另外，每个处理核均设置有IJTAG接口，处理核之间通过IJTAG接口传输调试指令或调试数据。
其中sel可以是一个JTAG数据寄存器(JTAG Data Register，JTAG DR)。可选的，每个JTAG DR占用1个字节。
芯片的具体的调试方法包括：
首先，通过JTAG接口接收JTAG格式的调试指令。
然后，通过协议转换模块将JTAG协议下的传输的JTAG格式的调试指令转换为IJTAG协议下的IJTAG格式的调试指令。
然后，各个处理核通过各自的IJTAG接口接收IJTAG格式的调试指令。
目标处理核的sel根据调试指令将状态变为激活状态，非目标处理核的sel根据调试指令将状态保持未激活状态，这样本次需要同时调试的目标处理核都处于激活状态。
具体地，由于初始状态下，所有的core都不在IJTAG链上，所以要想调试多个core，需要先配置待调试的处理核的Sel，即令目标处理核对应的sel有效，从而将目标处理核配置在IJTAG链上，本次配置期间的调试都是针对IJTAG链上的目标处理核。
具体地，将想要调试的目标core对应的sel的置位，用JTAG依次将32个调试信号移入。
比如：调试指令为32'h0A0A_0055。其中，32表示的是32位，即调试指令包括32个调试信号。调试信号包括激活信号和保持信号。其中的'h表示的是16进制，0A0A_0055表示的是16进制数，将0A0A_0055转换为二进制后，则调试指令为00001010000010100000000001010101，即这32位的二进制数从左至右分别对应第0处理核至第31处理核，即从左至右的第一位“0”用于控制32个处理核中的首处理核，即这32个二进制数中每个数字均代表一个调试信号，其中1表示的是激活信号，0表示的是保持信号。
可以理解的是，将想要调试的目标core对应的sel的置位，用JTAG依次将32个调试信号移入，是指：这32位的调试信号，右侧第一个调试信号1(该信号实际对应的是控制第31处理核)，右侧的第一个调试信号会先发送至第0处理核的sel中存储，然后第0处理核的sel会将自身存储的原调试信号发送给第1处理核的sel，依次 类推，第31处理核存储第30处理核的sel原调试信号，并将自身的原调试信号发送回芯片调试器，然后芯片调试器将右侧的第二个调试信号在发送给第0处理核的sel，第0处理核的sel会将自身上一次存储的sel调试信号1发送给第1处理核，依次类推，直到第0处理核存储了左侧第一个调试信号0、第1处理核存储了左侧第二个调试信号0,…,第31处理核存储了右侧的第一个调试信号1。说明各个处理核都收到了各自的调试指令。
其中，上述调试指令32'h0A0A_0055指示第四处理核、第六处理核、第十二处理核、第十四处理核、第二十五处理核、第二十七处理核、第二十九处理核、第三十一处理核的sel变为激活状态。其余处理核的sel保持未激活状态。
换言之，上述调试指令32'h0A0A_0055表示在芯片的JTAG接口的状态机变为更新状态(update)之后，core4，core6，core12，core14，core25，core27，core29，core31一共8个core为连接在IJTAG链上的目标处理核。
此时IJTAG链长度会变化，IJTAG链新的数据长度位为8*30+32(在链的core数*每个core内DR长度+32SEL模块)。后续调试数据的发送会按照新的IJTAG DR链长度进行DR移位操作。
接着，将调试数据通过IJTAG链传输至各个目标处理核，即将调试数据依次送入IJTAG链中的目标处理核中，每一个目标处理核将自身的原调试数据传输至下一目标处理核，直到各个目标处理核都收到各自的调试数据。
再然后，当JTAG接口的状态机变为更新状态时，IJTAG链上所有的目标处理核同时执行各自的调试数据，从而实现多个目标处理核的同时调试。
需要说明的是，当需要同时调试的处理核改变时，只需要更改IJTAG链上的目标处理核，即重新再配置一次sel，即可形成新的IJTAG链，进而可以同时对改变后的多个处理核进行调试。
本申请的第五实施方式提供了一种芯片调试系统，包括：芯片调试器和芯片。
其中，芯片调试器，用于发送调试指令和调试数据。
芯片，包括多个处理核，所述芯片用于根据所述调试指令将所述多个处理核中目标处理核激活，以使所述目标处理核相连接以形成调试处理核链，并通过所述调试处理核链将接收的所述调试数据传输至各个所述目标处理核，使各个所述目标处理核同时运行各自的调试数据。
在一些实施例中，芯片调试器设置有JTAG接口，所述芯片调试器通过JTAG接口发送调试指令和调试数据。
芯片设置有JTAG接口和协议转换模块，每个所述处理核均设置有IJTAG接口。芯片用于通过自身的JTAG接口接收所述芯片调试器发送的调试指令或调试数据；所述协议转换模块用于将芯片接收的调试指令或者调试数据转换成IJTAG协议格式；所述调试处理核链上的各个处理核通过所述IJTAG接口传输调试指令或调试数据。
根据本申请的第六实施方式，提供了一种计算机存储介质，该存 储介质存储有程序，该程序执行时实现第一方面提供的芯片调试方法，
根据本申请的第七实施方式，提供了一种电子设备，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，处理器执行程序时实现第一方面提供的芯片调试方法。
根据本申请的第八实施方式，提供一种计算机程序产品，其中，包括计算机指令，当计算机指令被计算设备执行时，计算设备可以执行第一方面提供的芯片调试方法。
应当理解的是，本申请的上述具体实施方式仅仅用于示例性说明或解释本申请的原理，而不构成对本申请的限制。因此，在不偏离本申请的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。此外，本申请所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (13)

  1. 一种芯片调试方法，芯片包括多个处理核，其中，调试方法包括：
    将所述多个处理核中的目标处理核激活，以使所述目标处理核连接至调试处理核链；
    将调试数据通过所述调试处理核链传输至所述目标处理核；
    控制各个所述目标处理核同时运行各自的调试数据。
  2. 根据权利要求1所述的调试方法，其中，每个所述处理核均设置有选择器，所述将所述多个处理核中的目标处理核激活，包括：
    发送激活信号，使所述目标处理核内的所述选择器状态变为激活状态。
  3. 根据权利要求2所述的调试方法，其中，
    发送保持信号，使非目标处理核内的所述选择器保持未激活状态。
  4. 根据权利要求1-3任一项所述的调试方法，其中，所述将调试数据通过所述调试处理核链传输至所述目标处理核，包括：
    将所述调试数据依次送入所述调试处理核链中的目标处理核中，每一个所述目标处理核将自身的原调试数据传输至下一目标处理核。
  5. 一种芯片，包括多个处理核；
    所述处理核，用于根据激活信号连接至调试处理核链；
    所述调试处理核链上的所述处理核接收调试数据；
    所述调试处理核链上的所述处理核同时运行各自的调试数据。
  6. 根据权利要求5所述的芯片，其中，每个所述处理核均设置有选择器；
    所述处理核用于根据接收的所述激活信号将自身的选择器状态变为激活状态以连接至调试处理核链。
  7. 根据权利要求6所述的芯片，其中，
    所述处理核用于根据接收的保持信号，保持自身的选择器状态为未激活状态。
  8. 根据权利要求5-7任一项所述的芯片，其中，
    所述调试处理核链上的首处理核用于接收调试数据；
    所述调试处理核链上其他处理核，用于接收来自各自上一个处理核传输的调试数据。
  9. 根据权利要求5-8任一项所述的芯片，其中，还包括JTAG接口，所述JTAG接口的输出端与所述芯片中所有处理核中的首处理核的输入端连接，所述JTAG接口的输入端与所述芯片中所有处理核中的尾处理核的输出端连接。
  10. 一种芯片调试系统，包括：
    芯片调试器，用于发送调试指令和调试数据；
    芯片，包括多个处理核，所述芯片用于根据所述调试指令将目标处理核激活，以使所述目标处理核相连接以形成调试处理核链，并通过所述调试处理链将接收的所述调试数据传输至所述目标处理核，使各个所述目标处理核同时运行各自的调试数据。
  11. 一种计算机存储介质，所述存储介质上存储有计算机程序， 所述程序被处理器执行时实现权利要求1-4中任意一项所述调试方法的步骤。
  12. 一种电子设备，包括存储器、显示器、处理器及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述程序时实现权利要求1-4中任意一项所述调试方法的步骤。
  13. 一种计算机程序产品，包括计算机指令，当计算机指令被计算设备执行时，计算设备执行权利要求1-4中任意一项所述的调试方法。
PCT/CN2021/117813 2020-09-14 2021-09-10 一种芯片调试方法、芯片及芯片调试系统 WO2022053030A1 (zh)

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CN101840368A (zh) * 2010-03-26 2010-09-22 中国科学院计算技术研究所 多核处理器的jtag实时片上调试方法及其系统
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CN103365749A (zh) * 2013-06-06 2013-10-23 北京时代民芯科技有限公司 一种多核处理器调试系统
CN209765501U (zh) * 2019-05-31 2019-12-10 河南思维轨道交通技术研究院有限公司 一种基于jtag的多处理器仿真调试装置

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CN101840368A (zh) * 2010-03-26 2010-09-22 中国科学院计算技术研究所 多核处理器的jtag实时片上调试方法及其系统
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