WO2022052592A1 - 晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质 - Google Patents

晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质 Download PDF

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WO2022052592A1
WO2022052592A1 PCT/CN2021/103716 CN2021103716W WO2022052592A1 WO 2022052592 A1 WO2022052592 A1 WO 2022052592A1 CN 2021103716 W CN2021103716 W CN 2021103716W WO 2022052592 A1 WO2022052592 A1 WO 2022052592A1
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wafer
defect
data
failed
memory block
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PCT/CN2021/103716
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English (en)
French (fr)
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陈予郎
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长鑫存储技术有限公司
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Priority to US17/475,628 priority Critical patent/US11927544B2/en
Publication of WO2022052592A1 publication Critical patent/WO2022052592A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method, device, electronic device, and computer-readable medium for tracing wafer defects.
  • defects In the manufacture of wafers, defects often appear on the wafers, and the reasons for the defects may be that there are too many micro-suspended particles in the air, or some steps may not be cleaned effectively. Wafer problem. The occurrence of defects can easily lead to the generation of defective bits, and when there are too many defective bits, the limited spare circuit cannot repair all the defective bits, so that the chip (Chip) is judged as a defective product.
  • embodiments of the present disclosure provide a method, device, electronic device, and computer-readable medium for tracing wafer defects, which can trace the source of abnormal states of defects and provide an effective method for quickly solving abnormal problems.
  • a method for traceability of wafer defects includes: obtaining defect data of a wafer; obtaining position data of a failed bit of the wafer; and determining the wafer according to the defect data.
  • the number is processed to obtain a correlation coefficient; the abnormal cause of the failed bit of the wafer is determined according to the correlation coefficient.
  • processing the defect area and the number of failed bits of memory blocks in the wafer, and obtaining a correlation coefficient includes: obtaining the wafer according to the defect data Determine the defect area index of the storage block in the wafer according to the ratio of the defect area of the storage block in the wafer and the area of the defect affected area; The ratio of the number of failed bits to the area of the defect affected area determines the failed bit index of the memory block in the wafer; the defect area index of the memory block in the wafer and the corresponding failed bit The indicators are subjected to correlation analysis to obtain the correlation coefficient.
  • performing correlation analysis on the defect area index of the memory block in the wafer and the corresponding failed bit index, and obtaining the correlation coefficient includes: The storage blocks containing abnormal data in the circle are eliminated, and a target storage block set is obtained; an association analysis is performed on the defect area index of the storage block in the target storage block set and the corresponding failed bit index, and the association is obtained. coefficient.
  • removing the memory blocks containing abnormal data in the wafer, and obtaining the target memory block set includes one or more of the following conditions: removing the invalid data in the wafer The storage blocks whose bit index is greater than the threshold of the failed bit index are eliminated to obtain the target storage block set; the storage blocks whose number of failed bits in the wafer is greater than the threshold of the number of failed bits are eliminated to obtain the A collection of target chunklets.
  • determining the abnormal cause of the failed bit of the wafer according to the correlation coefficient includes: acquiring process data of the wafer, where the process data includes structural layer information and all process information corresponding to the structural layer information; if the correlation coefficient is greater than the correlation coefficient threshold, determine the structural layer information where the defect data is located; determine the process information corresponding to the structural layer information where the defect data is located Abnormal.
  • determining the abnormal cause according to the process information corresponding to the structural layer information where the defect data is located includes: obtaining according to the process information corresponding to the structural layer information where the defect data is located the environmental data of the process information; analyze the environmental data of the process information to obtain the abnormal cause.
  • determining the abnormal cause according to the process information corresponding to the structural layer information where the defect data is located includes: determining the abnormal cause according to the defect data and the position data of the failed bit.
  • the number of defects that do not cause failure bits in the wafer; the ratio of the number of defects that do not cause failure bits in the wafer to the total number of defects in the defect data is determined as the defect removal rate of the wafer; according to A rule of thumb is used to evaluate the defect removal rate of the wafer; if the evaluation result is abnormal, it is determined that the step of including the abnormal cleaning function in the process information is the cause of the abnormality.
  • a device for tracing wafer defects includes: a defect data module configured to obtain defect data of a wafer; a failure bit data module configured to obtain failure bits of the wafer A defect area statistics module, configured to determine the defect area of a memory block in the wafer according to the defect data; a failed bit quantity module, configured to determine the wafer according to the position data of the failed bit The number of failed bits of the memory block in the circle; the correlation coefficient module is configured to process the defect area and the number of failed bits of the memory block in the wafer to obtain the correlation coefficient; the defect traceability module is configured according to The correlation coefficient determines the abnormal cause of the failed bits of the wafer.
  • an electronic device includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are processed by the one or more processors Execution causes one or more processors to implement a method as described above.
  • a computer-readable medium on which a computer program is stored, the program, when executed by a processor, implements the method as described above.
  • the defect data of the wafer and the position data of the failed bit are used to establish a relationship, and the relationship between the defect data and the failed bit is obtained.
  • the correlation coefficient of the relationship between the two can be used to determine whether the defect data is the cause of the failure bit based on the correlation coefficient, which is helpful to determine the abnormal cause of the wafer failure bit based on the wafer process data, which is helpful to solve the problem as soon as possible. Abnormal problems, improve wafer yield.
  • FIG. 1 is a flowchart of a method for tracing wafer defects according to an exemplary embodiment.
  • FIG. 2 is a schematic diagram of a wafer shown according to an exemplary embodiment.
  • FIG. 3 is a schematic diagram of a chip according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram illustrating an association analysis process according to an exemplary embodiment.
  • FIG. 5 is a flowchart of a method for tracing wafer defects according to an exemplary embodiment.
  • FIG. 6 is a block diagram of an apparatus for tracing wafer defects according to an exemplary embodiment.
  • FIG. 7 schematically shows a structural diagram of a computer system suitable for implementing an electronic device according to an embodiment of the present invention.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar parts, and thus their repeated descriptions will be omitted.
  • first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Accordingly, a first component discussed below could be referred to as a second component without departing from the teachings of the concepts of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • FIG. 1 is a flowchart of a method for tracing wafer defects according to an exemplary embodiment.
  • the method for tracing wafer defects provided by the embodiments of the present disclosure may be executed by any electronic device with computing processing capabilities, such as a user terminal and/or a server.
  • the server executes the method as an example for illustration. , but the present disclosure is not limited to this.
  • the method for tracing wafer defects provided by the embodiments of the present disclosure may include steps S102 to S112.
  • step S102 defect data of the wafer is acquired.
  • the defect data provides detailed data of defects, which may include the number of defects, defect area data of the area occupied by the defect in the wafer, location information of the defect in the wafer, and the wafer where the defect data is located.
  • the defect data may include: absolute position, relative position, area, type, structural layer, and the like.
  • the absolute position is a coordinate position based on the range of one wafer.
  • the relative position is the coordinate position based on the range of one chip.
  • the category is the category analyzed by the pattern recognition system.
  • Structural layer refers to a certain layer in the wafer. Each layer may be processed by one or more processes. ADDR is used to record whether this defect is a new defect. In other words, it does not exist on the previous older layer.
  • step S104 position data of the failed bits of the wafer are obtained.
  • the position data of the failed bits can be obtained through a wafer test (Circuit Probing, also called CP test).
  • the wafer test is to perform a needle test on each die on the wafer.
  • the detection head is equipped with a probe as thin as a hair made of gold wire, which is in contact with the node (pad) on the die to test its electrical properties. characteristic process. Fail Bits are unqualified units obtained during wafer testing.
  • step S106 the defect area of the memory block in the wafer is determined according to the defect data.
  • a wafer may include several chips (chips), and a chip (chip) organization structure includes several banks (Banks), and each bank may be divided into two left and right banks of the same size Block (Half-Bank) (different products have different division methods, and some are also divided into four blocks).
  • Each memory block has a memory array (array), and the memory array includes a plurality of memory memory cells defined by the intersection of bit lines and word lines, and one memory cell represents one bit element (bit).
  • the memory block in the wafer is used as the research granularity, and in other embodiments, a quarter of the memory bank may be used as the research granularity, which is not specifically limited in the present disclosure.
  • FIG. 2 is a schematic diagram of a wafer shown according to an exemplary embodiment. As shown in FIG. 2 , one cell in the wafer 20 is one chip 21 .
  • FIG. 3 is a schematic diagram of a chip according to an exemplary embodiment. As shown in FIG. 3 , the chip 21 may include several memory banks 30 , and each memory bank may be divided into two left and right memory blocks 31 of the same size.
  • defect data corresponding to the location of the memory block may be determined according to the defect data, and the total area of all defects in the memory block may be calculated as the defect area of the memory block in the wafer.
  • step S108 the number of failed bits of the memory block in the wafer is determined according to the position data of the failed bits.
  • the failed bit data corresponding to the position of the memory block can be determined according to the position data of the failed bit, and the number of all failed bits in the memory block can be calculated as the number of failed bits of the memory block in the wafer .
  • step S110 the defect area and the number of failed bits of the memory block in the wafer are processed to obtain a correlation coefficient.
  • a defect may or may not result in a failed bit. Therefore, by processing the defect area and the number of failed bits of each memory block in the wafer, the obtained correlation coefficient can characterize whether the defect has a causal relationship with the formation of the failed bits.
  • the defect area and the number of failed bits of each memory block in the wafer can be obtained by statistics, taking the memory block as the granularity, and the defect area and the number of failed bits of each memory block as the horizontal and vertical coordinates respectively. Correlation analysis to obtain the correlation coefficient.
  • step S112 the abnormal cause of the failed bit of the wafer is determined according to the correlation coefficient.
  • the cause of formation of a causal defect can be determined by the correlation coefficient.
  • the cause of the formation may be in the process in which the defect is formed.
  • the relationship between the defect data of the wafer and the position data of the failed bit is used to establish a relationship, and the correlation coefficient representing the relationship between the defect data and the failed bit is obtained, which can be based on the correlation coefficient. It is helpful to determine whether the defect data is the cause of the formation of the failed bits, and then it is helpful to determine the abnormal cause of the failed bits of the wafer based on the wafer process data, which is helpful to solve the abnormal problem as soon as possible and improve the yield of the wafer.
  • a Defect Affected Region (DAR) of the wafer may be obtained according to defect data; according to the defect area of the memory block in the wafer and the area of the defect affected area Determine the defect area index of the memory block in the wafer according to the ratio of the defective bits of the memory block in the wafer and the ratio of the defect affected area to determine the defective bit of the memory block in the wafer. index; perform correlation analysis on the defect area index of the memory block in the wafer and the corresponding failed bit index to obtain the correlation coefficient.
  • DAR Defect Affected Region
  • the defect-affected area is the range that may cause the failed bit.
  • the defect area index and the failed bit index of each memory block in the wafer can be obtained statistically, with the memory block as the granularity, and the defect area index and the failed bit index of each memory block as the horizontal and vertical respectively Correlation analysis was performed on the coordinates to obtain the correlation coefficient.
  • the correlation analysis of the defect area index and the failed bit index can make different wafers have the same scaling degree compared with the embodiment shown in FIG. 1 , and improve the observability of the correlation analysis.
  • the following steps may be included when obtaining the correlation coefficient by performing correlation analysis on the defect area index of the memory block in the wafer and the corresponding failed bit index.
  • the storage blocks containing abnormal data in the wafer are eliminated, and a target storage block set is obtained; the defect area index and the corresponding failed bit index of the storage blocks in the target storage block set are correlated and analyzed to obtain the correlation coefficient.
  • one or more of the following conditions may be included: 1) The memory blocks whose failure bit index is greater than the failure bit index threshold in the wafer are processed for Eliminate to obtain the target storage block set. 2) Eliminating the memory blocks whose number of failed bits is greater than the threshold of the number of failed bits in the wafer to obtain the set of target memory blocks.
  • FIG. 4 is a schematic diagram illustrating an association analysis process according to an exemplary embodiment.
  • the threshold value ⁇ of the failed bit index is used to filter out a part of Chips that often have too many failed bits in the process (the grid with many failed bits in Figure 1), as shown in Figure 4 211 , the invalid bits in this type of Chip are not directly affected by Defect, and removing this type of Chip can help improve the accuracy of the correlation analysis.
  • the threshold value of the failed bit index can satisfy the following conditions: ⁇ FBC/2%.
  • a regression line 42 can be obtained by performing correlation analysis according to the data below the partition line 41 and FBc%>, DA%>0.
  • the correlation coefficient greater than the correlation coefficient threshold indicates that the wafer is significantly abnormal.
  • the correlation coefficient threshold is a preset parameter, usually the correlation coefficient threshold is >0.5.
  • Each chip can be divided into multiple regions: A, B, C, D, E, the outermost circle is the E region to the innermost circle is the A region in sequence.
  • the outer ring of the wafer is more easily damaged than the inner ring, and the main reason for this damage is not caused by Defect, so the data of the outer ring (such as D, E) can be ignored and not analyzed. This increases the accuracy of the correlation analysis.
  • process data of the wafer may be acquired, and the process data includes structural layer information and process information corresponding to the structural layer information; when the correlation coefficient is greater than the correlation coefficient threshold When the defect data is located, the information of the structure layer where the defect data is located is determined; the abnormal cause is determined according to the process information corresponding to the information of the structure layer where the defect data is located.
  • the correlation coefficient when the correlation coefficient is greater than the correlation coefficient threshold, the structural layer information of the defect data can be determined, and the manufacturing steps that the structural layer information has passed through can be traced, and one or several manufacturing steps can be locked in turn to be abnormal.
  • the following steps may be included: according to the process information corresponding to the structural layer information where the defect data is located Obtain the environmental data of the process information; analyze the environmental data of the process information to obtain the abnormal cause.
  • the index representing the micro-suspended particles in the air in the environmental data is higher than the preset threshold, it can be determined that the environmental abnormality is the abnormality cause.
  • the following steps may be included: determining according to the defect data and the position data of the failed bit.
  • the ratio of the number of defects that do not cause failure bits in the wafer and the total number of defects in the defect data is determined as the defect removal rate of the wafer ( Defect Cleaned Rate, DCR); according to the rule of thumb, the defect removal rate of the wafer is evaluated; if the evaluation result is abnormal, then it is determined that the step of including the abnormal cleaning function in the process information is the abnormal cause.
  • DCR Defect removal rate
  • DCR Numberer of Defects without any Fail Bit in the Defect coverage area/(Total number of Defects)
  • the DCR in normal and abnormal states will change significantly, and whether abnormality occurs can be assessed by comparing the calculated DCR with the DCR in the normal state. If there is obvious change, the evaluation result is abnormal; if there is no obvious change, the evaluation result is normal.
  • a rule of thumb states that 68% of the data will be distributed within the first standard deviation, 95% will be within the second standard deviation, and 99.7% will be within the first three standard deviations of the mean.
  • a DCR within the first standard deviation may be judged as normal, and a DCR within the second and third standard deviations may be judged as abnormal.
  • FIG. 5 is a flowchart of a method for tracing wafer defects according to an exemplary embodiment.
  • the method for traceability of wafer defects may include the following steps.
  • step S502 the defect affected area is obtained from the source data.
  • range data can be included to provide all fixed parameters, as follows:
  • Defect may cause the range of failed bits (Defect Affected Regions, defect affected area, DAR);
  • Start/end monitoring provide control parameters to start and stop monitoring
  • Threshold value and warning value provide parameters for correlation analysis, which can be set based on actual conditions.
  • Wafer set data Provides batch numbers, serial numbers, various related dates, etc. of all Wafers.
  • Defect data Provide detailed data of defect, including absolute position, relative position, area, type, Layer, ADDR, etc. in:
  • Absolute position the coordinate position based on a wafer range
  • Relative position the coordinate position based on a chip range
  • Type The category analyzed by the pattern recognition system
  • Layer refers to a layer in Wafer. Each layer may be processed by one or more processes;
  • ADDR Used to record whether this Defect is a new Defect. In other words, it does not exist on the previous older layer.
  • Fail bit position data Provide the fail bit (fail bit, FB) position data obtained during the CP test.
  • chip_region Provides the region where the chip location is located.
  • the chips in a wafer can be divided into several areas such as A, B, C, D, E, etc.
  • step S504 a piece of wafer data (hereinafter referred to as new wafer data) that has been tested and has not been read in this process is acquired.
  • step S506 rest for a short period of time, and then proceed to the next process.
  • step S508 a new memory block position is obtained in a loop from the same wafer data.
  • step S510 the defect data corresponding to the position of the memory block is obtained from the defect data, and the total area (Defect Area, DA) of all defects in the memory block is calculated.
  • step S512 the failed bit data corresponding to the position of the storage block is obtained from the position data of the failed bit, and the number of failed bits (FB Count, FBc) in the storage block is calculated.
  • step S514 the DA and FBc of the memory block are stored in the analysis data as one data point.
  • each data_point represents information of a storage block, including DA, FBc, location information, etc. of the corresponding storage block.
  • step S518 if it is the last memory block (HB), step S518 is executed. Otherwise, execute S504.
  • step S528 correlation analysis is performed.
  • correlation analysis may be performed based on the analysis data as shown in step S110 in the embodiment of FIG. 1 , and the abnormal cause of the defect is obtained retrospectively according to the obtained correlation coefficient.
  • FIG. 6 is a block diagram of an apparatus for tracing wafer defects according to an exemplary embodiment.
  • the device for tracing wafer defects provided by the embodiments of the present disclosure may include: a defect data module 602 , a failed bit data module 604 , a defect area statistics module 606 , a failed bit quantity module 608 , a correlation coefficient module 610 and a defect traceability module 612 .
  • the defect data module 602 may be configured to acquire defect data of the wafer.
  • the failed bits data module 604 may be configured to obtain location data for failed bits of the wafer.
  • the defect area statistics module 606 is configured to determine defect areas of memory blocks in the wafer according to the defect data.
  • the number of failed bits module 608 may be configured to determine the number of failed bits of memory blocks in the wafer according to the position data of the failed bits.
  • the correlation coefficient module 610 may be configured to process the defect area and the number of failed bits of the memory block in the wafer to obtain the correlation coefficient.
  • the defect tracing module 612 may be configured to determine the abnormal cause of the failed bit of the wafer according to the correlation coefficient.
  • the relationship between the defect data of the wafer and the position data of the failed bit is used to establish a relationship, and the correlation coefficient representing the correlation between the defect data and the failed bit is obtained, which can be based on the correlation coefficient. It is helpful to determine whether the defect data is the cause of the formation of the failed bits, and then it is helpful to determine the abnormal cause of the failed bits of the wafer based on the wafer process data, which is helpful to solve the abnormal problem as soon as possible and improve the yield of the wafer.
  • FIG. 7 shows a schematic structural diagram of a computer system 700 suitable for implementing an electronic device according to an embodiment of the present invention.
  • the computer system 700 of the electronic device shown in FIG. 7 is only an example, and should not impose any limitation on the function and scope of use of the embodiments of the present invention.
  • a computer system 700 includes a central processing unit (CPU) 701 which can be loaded into a random access memory (RAM) 703 according to a program stored in a read only memory (ROM) 702 or a program from a storage section 708 Instead, various appropriate actions and processes are performed.
  • RAM random access memory
  • ROM read only memory
  • various programs and data necessary for system operation are also stored.
  • the CPU 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704.
  • An input/output (I/O) interface 705 is also connected to bus 704 .
  • the following components are connected to the I/O interface 705: an input section 706 including a keyboard, a mouse, etc.; an output section 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc. ; and a communication section 709 including a network interface card such as a LAN card, a modem, and the like.
  • the communication section 709 performs communication processing via a network such as the Internet.
  • Drivers 710 are also connected to I/O interface 708 as needed.
  • a removable medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 710 as needed so that a computer program read therefrom is installed into the storage section 708 as needed.
  • embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via the communication portion 709 and/or installed from the removable medium 711 .
  • the central processing unit (CPU) 701 the above-described functions defined in the system of the present application are executed.
  • the computer-readable storage medium shown in the present invention may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples of computer readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable Programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium can also be any computer-readable storage medium other than a computer-readable storage medium that can be sent, propagated, or transmitted for use by or in connection with an instruction execution system, apparatus, or device program of.
  • Program code embodied on a computer-readable storage medium may be transmitted using any suitable medium including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more functions for implementing the specified logical function(s) executable instructions.
  • the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • the units involved in the embodiments of the present invention may be implemented in a software manner, or may be implemented in a hardware manner, and the described units may also be provided in a processor. Among them, the names of these units do not constitute a limitation on the unit itself under certain circumstances.
  • the present application also provides a computer-readable storage medium.
  • the computer-readable storage medium may be included in the electronic device described in the above-mentioned embodiments; in electronic equipment.
  • the above-mentioned computer-readable storage medium carries one or more programs, and when the above-mentioned one or more programs are executed by one of the electronic equipment, the electronic equipment is made to realize the detection method of the wafer production process as described in the above-mentioned embodiments .
  • the electronic device can implement as shown in FIG. 1 : step S102 , acquiring defect data of the wafer.
  • step S104 the position data of the failed bit of the wafer is obtained.
  • step S106 the defect area of the memory block in the wafer is determined according to the defect data.
  • step S108 Determine the number of failed bits of the memory block in the wafer according to the position data of the failed bits.
  • step S110 the defect area and the number of failed bits of the memory block in the wafer are processed to obtain a correlation coefficient.
  • step S112 the abnormal cause of the failed bit of the wafer is determined according to the correlation coefficient.
  • the electronic device can also implement the various steps shown in FIG. 5 .
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present invention, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the exemplary embodiments described herein may be implemented by software, or may be implemented by software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present invention can be embodied in the form of software products, and the software products can be stored in a non-volatile storage medium (which can be CD-ROM, U disk, mobile hard disk, etc.) or on the network , which includes several instructions to cause a computing device (which may be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiment of the present invention.
  • a computing device which may be a personal computer, a server, a touch terminal, or a network device, etc.

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Abstract

本公开涉及一种晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质。该方法包括：获取晶圆的缺陷数据；获得所述晶圆的失效位元的位置数据；根据所述缺陷数据确定所述晶圆中存储块的缺陷面积；根据所述失效位元的位置数据确定所述晶圆中存储块的失效位元数量；对所述晶圆中每一存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数；根据所述关联系数确定所述晶圆的失效位元的异常原因。本公开涉及的晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质，能够实现缺陷的异常状态的源头追溯，提供了快速解决异常问题的有效方法，进而提高晶圆的良率。 (图1)

Description

晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质
本公开要求申请日为2020年09月11日、申请号为202010953000.9、发明创造名称为《晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质》的中国发明专利申请的优先权。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质。
背景技术
在晶圆(Wafer)制造中，晶圆上时常会有缺陷(Defect)的出现，而缺陷出现的原因可能是空气中的微悬浮粒子太多的问题，也可能是某些步骤未能有效清洗晶圆问题。缺陷的出现容易造成失效位元的产生，而失效位元过多时会导致有限的备用电路无法将所有的失效位元修补，致使此芯片(Chip)被判定为不良品。
因此过多缺陷的出现会导致晶圆的良率大幅降低。
因此，需要一种新的晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质。
在所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的相关技术的信息。
发明内容
有鉴于此，本公开实施例提供一种晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质，能够实现缺陷的异常状态的源头追溯，提供了快速解决异常问题的有效方法。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本公开的实践而习得。
根据本公开的一方面，提出一种晶圆缺陷的溯源方法，该方法包括：获取晶圆的缺陷数据；获得所述晶圆的失效位元的位置数据；根据所述缺陷数据确定所述晶圆中存储块的缺陷面积；根据所述失效位元的位置数据确定所述晶圆中存储块的失效位元数量；对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数；根据所述关联系数确定所述晶圆的失效位元的异常原因。
在本公开的一种示例性实施例中，对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数包括：根据所述缺陷数据获得所述晶圆的缺陷影响区域；根据所述晶圆中存储块的缺陷面积和所述缺陷影响区域的面积的比值确定所述晶圆中存储块的缺陷面积指标；根据所述晶圆中存储块的所述失效位元数量和所述缺陷影响区域的面积的比值确定所述晶圆中存储块的失效位元指标；对所述晶圆中存储块的所述缺陷面积 指标和相应的所述失效位元指标进行关联分析，获得所述关联系数。
在本公开的一种示例性实施例中，对所述晶圆中存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数包括：将所述晶圆中包含异常数据的存储块剔除，获得目标存储块集合；对所述目标存储块集合中的存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数。
在本公开的一种示例性实施例中，将所述晶圆中包含异常数据的存储块剔除，获得目标存储块集合包括以下情况的一种或多种：将所述晶圆中所述失效位元指标大于失效位元指标阈值的存储块进行剔除，获得所述目标存储块集合；将所述晶圆中所述失效位元数量大于失效位元数量阈值的存储块进行剔除，获得所述目标存储块集合。
在本公开的一种示例性实施例中，根据所述关联系数确定所述晶圆的失效位元的异常原因包括：获取所述晶圆的制程数据，所述制程数据包括结构层信息和所述结构层信息对应的制程信息；若所述关联系数大于关联系数阈值，则确定所述缺陷数据所处的结构层信息；根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因。
在本公开的一种示例性实施例中，根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因包括：根据所述缺陷数据所处的结构层信息对应的制程信息获得所述制程信息的环境数据；对所述制程信息的环境数据进行分析，获得所述异常原因。
在本公开的一种示例性实施例中，根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因包括：根据所述缺陷数据和所述失效位元的位置数据确定所述晶圆中未造成失效位元的缺陷数量；根据所述晶圆中未造成失效位元的缺陷数量和所述缺陷数据中缺陷总数量的比值确定为所述晶圆的缺陷清除率；根据经验法则对所述晶圆的缺陷清除率进行评估；若评估结果为异常，则确定所述制程信息中包括清洗异常功能的步骤为所述异常原因。
根据本公开的一方面，提出一种晶圆缺陷的溯源装置，该装置包括：缺陷数据模块，配置为获取晶圆的缺陷数据；失效位元数据模块，配置为获得所述晶圆的失效位元的位置数据；缺陷面积统计模块，配置为根据所述缺陷数据确定所述晶圆中存储块的缺陷面积；失效位元数量模块，配置为根据所述失效位元的位置数据确定所述晶圆中存储块的失效位元数量；关联系数模块，配置为对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数；缺陷溯源模块，配置为根据所述关联系数确定所述晶圆的失效位元的异常原因。
根据本公开的一方面，提出一种电子设备，该电子设备包括：一个或多个处理器；存储装置，用于存储一个或多个程序；当一个或多个程序被一个或多个处理器执行，使得一个或多个处理器实现如上文中所述的方法。
根据本公开的一方面，提出一种计算机可读介质，其上存储有计算机程序，该程序被处理器执行时实现如上文中所述的方法。
根据本公开一些实施例提供的晶圆缺陷的溯源方法、装置、电子设备及计算机可读介 质，利用晶圆的缺陷数据和失效位元的位置数据建立联系，获得表征缺陷数据和失效位元之间关联关系的关联系数，能够基于关联系数判断缺陷数据是否为失效位元的形成原因，进而有助于基于晶圆的制程数据确定导致晶圆产生失效位元的异常原因，有助于尽快解决异常问题，提高晶圆的良率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
通过参照附图详细描述其示例实施例，本公开的上述和其它目标、特征及优点将变得更加显而易见。下面描述的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的一种晶圆缺陷的溯源方法的流程图。
图2是根据一示例性实施例示出的晶圆的示意图。
图3是根据一示例性实施例示出的芯片的示意图。
图4是根据一示例性实施例示出的关联分析过程的示意图。
图5是根据一示例性实施例示出的一种晶圆缺陷的溯源方法的流程图。
图6是根据一示例性实施例示出的一种晶圆缺陷的溯源装置的框图。
图7示意性示出了适于用来实现本发明实施例的电子设备的计算机系统的结构图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的实施例；相反，提供这些实施例使得本公开将全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知方法、装置、实现或者操作以避免模糊本公开的各方面。
附图中所示的方框图仅仅是功能实体，不一定必须与物理上独立的实体相对应。即，可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
附图中所示的流程图仅是示例性说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解，而有的操作/步骤可以合并或部分合并，因此实际执行的顺序有可能根据实际情况改变。
应理解，虽然本文中可能使用术语第一、第二、第三等来描述各种组件，但这些组件 不应受这些术语限制。这些术语乃用以区分一组件与另一组件。因此，下文论述的第一组件可称为第二组件而不偏离本公开概念的教示。如本文中所使用，术语“及/或”包括相关联的列出项目中的任一个及一或多者的所有组合。
本领域技术人员可以理解，附图只是示例实施例的示意图，附图中的模块或流程并不一定是实施本公开所必须的，因此不能用于限制本公开的保护范围。
图1是根据一示例性实施例示出的一种晶圆缺陷的溯源方法的流程图。本公开实施例提供的晶圆缺陷的溯源方法可以由任意具备计算处理能力的电子设备执行，例如用户终端和/或服务器，在下面的实施例中，以服务器执行所述方法为例进行举例说明，但本公开并不限定于此。本公开实施例提供的晶圆缺陷的溯源方法可以包括步骤S102至S112。
如图1所示，在步骤S102中，获取晶圆的缺陷数据。
本公开实施例中，缺陷数据提供了缺陷的详细数据，可包括缺陷的数量、缺陷在晶圆中所占面积的缺陷面积数据以及缺陷在晶圆中的位置信息、缺陷数据所处的晶圆的结构层(Layer)信息等。
具体地，缺陷数据可包括：绝对位置、相对位置、面积、种类、结构层等。其中，绝对位置是以一片晶圆范围为基准的座标位置。相对位置是以一颗芯片范围为基准的坐标位置。种类是经由图形辨识系统所分析出来的类别。结构层是指在晶圆中的某一层。每一层可能会经过一个或多个制程的处理。ADDR是用于记录此缺陷是否为新出现的缺陷。换句话说，它不存在于上一个比较旧的层。
在步骤S104中，获得晶圆的失效位元的位置数据。
本公开实施例中，可通过晶圆测试(Circuit Probing，也叫CP测试)获得失效位元的位置数据。晶圆测试是对晶片上的每个晶粒进行针测，在检测头装上以金线制成细如毛发的探针(probe)，与晶粒上的节点(pad)接触，测试其电气特性的过程。失效位元(Fail Bit)为晶圆测试过程中获得的不合格单元。
在步骤S106中，根据缺陷数据确定晶圆中存储块的缺陷面积。
本公开实施例中，在一个晶圆中，可包括若干个芯片(chip),一个芯片(chip)组织架构包括若干存储库(Bank)，每一个存储库可以是分成左右两个大小相同的存储块(Half-Bank)(不同的产品具有不同的划分方式，有的也划分为四块)。每个存储块中具有存储阵列(array)，存储阵列包含多个由位线字线交叉定义的存储存储单元,一个存储单元即代表一个位元(bit)。其中，在本步骤中，以晶圆中的存储块为研究粒度，在另一些实施例中，还可以四分之一个存储库为研究粒度，本公开对此并不作特殊限定。
图2是根据一示例性实施例示出的晶圆的示意图。如图2所示，晶圆20中的一个单元格为一个芯片21。图3是根据一示例性实施例示出的芯片的示意图。如图3所示，芯片21可包括若干存储库30，每个存储库可分成左右两个大小相同的存储块31。
本公开实施例中，可根据缺陷数据确定存储块位置对应的缺陷数据，并计算出在存储块中所有缺陷的总面积，作为晶圆中存储块的缺陷面积。
在步骤S108中，根据失效位元的位置数据确定晶圆中存储块的失效位元数量。
本公开实施例中，可根据失效位元的位置数据确定存储块位置对应的失效位元数据，并计算出在存储块中所有失效位元的数量，作为晶圆中存储块的失效位元数量。
在步骤S110中，对晶圆中存储块的所述缺陷面积和失效位元数量进行处理，获得关联系数。
一个缺陷可能会导致失效位元的产生，也可能不会。因此，通过对晶圆中每一存储块的所述缺陷面积和所述失效位元数量进行处理，获得的关联系数能够表征缺陷是否与失效位元的形成存在因果关系。
本公开实施例中，可统计获得晶圆中每一存储块的缺陷面积和失效位元数量，以存储块为粒度，以每一存储块的缺陷面积和失效位元数量分别作为横纵坐标进行关联分析，获得关联系数。
在步骤S112中，根据关联系数确定该晶圆的失效位元的异常原因。
在公开实施例中，能够通过关联系数确定具有因果关系的缺陷的形成原因。该形成原因可为该缺陷所形成的制程中。
根据本公开实施方式提供的晶圆缺陷的溯源方法，利用晶圆的缺陷数据和失效位元的位置数据建立联系，获得表征缺陷数据和失效位元之间关联关系的关联系数，能够基于关联系数判断缺陷数据是否为失效位元的形成原因，进而有助于基于晶圆的制程数据确定导致晶圆产生失效位元的异常原因，有助于尽快解决异常问题，提高晶圆的良率。
在示例性实施例中，在步骤S110中，可根据缺陷数据获得晶圆的缺陷影响区域(Defect Affected Region，DAR)；根据所述晶圆中存储块的缺陷面积和所述缺陷影响区域的面积的比值确定所述晶圆中存储块的缺陷面积指标；根据所述晶圆中存储块的所述失效位元数量和所述缺陷影响区域的比值确定所述晶圆中存储块的失效位元指标；对所述晶圆中存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数。
其中，缺陷影响区域为可能造成失效位元的范围。在该实施例中，可统计获得晶圆中每一存储块的缺陷面积指标和失效位元指标，以存储块为粒度，以每一存储块的缺陷面积指标和失效位元指标分别作为横纵坐标进行关联分析，获得关联系数。其中，对缺陷面积指标和失效位元指标进行关联分析，相较于图1所示实施例，能够使得不同的晶圆具有同等缩放程度，提高关联分析的可观察性。
在示例性实施例中，在对所述晶圆中存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数时，可包括以下步骤：将所述晶圆中包含异常数据的存储块剔除，获得目标存储块集合；对所述目标存储块集合中的存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数。
其中，在剔除晶圆中包含异常数据的存储块时，可包括以下情况的一种或多种：1)将所述晶圆中所述失效位元指标大于失效位元指标阈值的存储块进行剔除，获得所述目标存储块集合。2)将所述晶圆中失效位元数量大于失效位元数量阈值的存储块进行剔除， 获得所述目标存储块集合。
图4是根据一示例性实施例示出的关联分析过程的示意图。如图4所示，失效位元指标阈值τ用于滤掉一部份于制程中常出现过多失效位元的Chip(如图1中失效位元众多的格子)，如图4中所示211，这类Chip中的失效位元并非受到Defect直接影响所造成，去除掉此类Chip有助提高关联分析的精准度。通常情况下，失效位元指标阈值可满足下述条件：τ<FBC/2％。其中，根据区隔线41以下且FBc％>,DA％>0的数据进行关联分析，可获取一条回归线42，此关联系数大于关联系数阈值表示此晶圆显著异常。关联系数阈值为预设定的参数，通常关联系数阈值>0.5。
每一芯片(Chip)可划分为多个区域：A,B,C,D,E，依序最外圈为E区至最内圈为A区。而通常在晶圆制造中，晶圆的外圈比内圈更容易损坏，而这种损坏的主要原因并非Defect所引起的，因此可以将外圈(例如D,E)的数据忽略不做分析，以此来增加的关联分析的精准度。
在示例性实施例中，在步骤S112中，可获取所述晶圆的制程数据，所述制程数据包括结构层信息和所述结构层信息对应的制程信息；在所述关联系数大于关联系数阈值时，确定所述缺陷数据所处的结构层信息；根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因。
其中，关联系数大于关联系数阈值时，可确定缺陷数据出现的结构层信息，追溯该结构层信息经过了哪些制造步骤，依次可以锁定某一个或几个制造步骤有异常。
在示例性实施例中，在根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因时，可包括以下步骤：根据所述缺陷数据所处的结构层信息对应的制程信息获得所述制程信息的环境数据；对所述制程信息的环境数据进行分析，获得所述异常原因。
其中，当环境数据中表征空气中的微悬浮粒子的指标高于预设阈值时，可确定该环境异常为异常原因。
在示例性实施例中，在根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因时，可包括以下步骤：根据所述缺陷数据和所述失效位元的位置数据确定所述晶圆中未造成失效位元的缺陷数量；根据所述晶圆中未造成失效位元的缺陷数量和所述缺陷数据中缺陷总数量的比值确定为所述晶圆的缺陷清除率(Defect Cleaned Rate，DCR)；根据经验法则对所述晶圆的缺陷清除率进行评估；若评估结果为异常，则确定所述制程信息中包括清洗异常功能的步骤为所述异常原因。
其中，在晶圆的制程中，有些步骤拥有清除缺陷的功能。当这些步骤没有正常发挥清洗功能时(即发生异常)，可能造成缺陷并导致失效位元的产生。缺陷清除率DCR＝(Defect覆盖区域中没有任何Fail Bit的Defect的数量/(Defect总数量))。正常与异常状态下的DCR会有明显的变化，通过将计算得到的DCR与正常状态下的DCR进行比较即可评估是否发生异常。若有明显的变化，则评估结果为异常；若无明显的变化，则评估结果为正常。经验规则表明，68％的数据将分布在的第一个标准偏差之内，95％将落在第二个标准 差之内，和99.7％将落在均值的前三个标准偏差之内。可以将落在第一个标准偏差之内的DCR判定为正常，将落在第二个标准偏差和第三个标准差之内的DCR判定为异常。
应清楚地理解，本公开描述了如何形成和使用特定示例，但本公开的原理不限于这些示例的任何细节。相反，基于本公开公开的内容的教导，这些原理能够应用于许多其它实施例。
图5是根据一示例性实施例示出的一种晶圆缺陷的溯源方法的流程图。
如图5所示，本公开实施例的晶圆缺陷的溯源方法可以包括以下步骤。
在步骤S502中，从来源数据中获得缺陷影响区域。
其中，来源数据中，可包括范围数据，用于提供所有固定的参数，如下所示：
(1)Defect可能造成失效位元的范围(Defect Affected Regions,缺陷影响区域，DAR)；
(2)开始/结束监控：提供开启与停止监控的控制参数；
(3)门槛值、警示值：提供关联分析的参数，此参数可基于实际情况设定。
晶圆组数据：提供所有Wafer的批号、编号、各种相关日期等。
缺陷数据：提供defect的详细数据，包含绝对位置、相对位置、面积、种类、Layer、ADDR、…等。其中：
绝对位置:以一片wafer范围为基准的座标位置；
相对位置:以一颗chip范围为基准的座标位置；
种类：经由图形辨识系统所分析出来的类别；
Layer:指在Wafer中的某一层。每一个层可能会经过一个或多个制程的处理；
ADDR:用以记录此Defect是否为新出现的Defect。换句话说，它不存在于上一个比较旧的层。
失效位元位置数据：提供CP测试时所获取得的失效位元(fail bit,FB)位置数据。
chip_region：提供chip位置所在的区域。一般而言，一片wafer中的chips可被划分为A,B,C,D,E等数个区域。
在步骤S504中，获取一片已经过晶圆测试后且此流程未读取的晶圆数据(以下简称新晶圆数据)。
在步骤S506中，休息一个短暂的时间，再继续进行下一个处理。
在步骤S508中，循环于同一晶圆数据中取得一个新的存储块位置。
在步骤S510中，从缺陷数据中取得该存储块位置对应的缺陷数据，并计算出此存储块中所有缺陷的总面积(Defect Area，DA)。
在步骤S512中，从失效位元的位置数据中取得该存储块位置对应的失效位元数据，并计算出在此存储块中的失效位元数量(FB Count，FBc)。
在步骤S514中，将该存储块的DA和FBc作为一个数据点存储至分析数据。
其中，每一个data_point代表一个存储块的信息，包括了对应的存储块的DA、FBc、位置信息等。
在步骤S516中，若是最后的存储块(HB)，则执行步骤S518。否则执行S504。
在步骤S518中，进行关联分析。
本公开实施例中，可基于分析数据执行形如图1实施例中的步骤S110进行关联分析，并根据获得的关联系数追溯获得缺陷的异常原因。
本领域技术人员可以理解实现上述实施例的全部或部分步骤被实现为由CPU执行的计算机程序。在该计算机程序被CPU执行时，执行本公开提供的上述方法所限定的上述功能。所述的程序可以存储于一种计算机可读存储介质中，该存储介质可以是只读存储器，磁盘或光盘等。
此外，需要注意的是，上述附图仅是根据本公开示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
下述为本公开装置实施例，可以用于执行本公开方法实施例。对于本公开装置实施例中未披露的细节，请参照本公开方法实施例。
图6是根据一示例性实施例示出的一种晶圆缺陷的溯源装置的框图。本公开实施例提供的晶圆缺陷的溯源装置可以包括：缺陷数据模块602、失效位元数据模块604、缺陷面积统计模块606、失效位元数量模块608、关联系数模块610和缺陷溯源模块612。
在晶圆缺陷的溯源装置中，缺陷数据模块602可配置为获取晶圆的缺陷数据。
失效位元数据模块604可配置为获得所述晶圆的失效位元的位置数据。
缺陷面积统计模块606配置为根据所述缺陷数据确定所述晶圆中存储块的缺陷面积。
失效位元数量模块608可配置为根据所述失效位元的位置数据确定所述晶圆中存储块的失效位元数量。
关联系数模块610可配置为对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数。
缺陷溯源模块612可配置为根据所述关联系数确定所述晶圆的失效位元的异常原因。
根据本公开实施方式提供的晶圆缺陷的溯源装置，利用晶圆的缺陷数据和失效位元的位置数据建立联系，获得表征缺陷数据和失效位元之间关联关系的关联系数，能够基于关联系数判断缺陷数据是否为失效位元的形成原因，进而有助于基于晶圆的制程数据确定导致晶圆产生失效位元的异常原因，有助于尽快解决异常问题，提高晶圆的良率。
下面参考图7，其示出了适于用来实现本发明实施例的电子设备的计算机系统700的结构示意图。图7示出的电子设备的计算机系统700仅是一个示例，不应对本发明实施例的功能和使用范围带来任何限制。
如图7所示，计算机系统700包括中央处理单元(CPU)701，其可以根据存储在只读存储器(ROM)702中的程序或者从存储部分708加载到随机访问存储器(RAM)703中的程序而执行各种适当的动作和处理。在RAM 703中，还存储有系统操作所需的各种 程序和数据。CPU 701、ROM 702以及RAM 703通过总线704彼此相连。输入/输出(I/O)接口705也连接至总线704。
以下部件连接至I/O接口705：包括键盘、鼠标等的输入部分706；包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分707；包括硬盘等的存储部分708；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分709。通信部分709经由诸如因特网的网络执行通信处理。驱动器710也根据需要连接至I/O接口708。可拆卸介质711，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器710上，以便于从其上读出的计算机程序根据需要被安装入存储部分708。
特别地，根据本发明的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本发明的实施例包括一种计算机程序产品，其包括承载在计算机可读存储介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分709从网络上被下载和安装，和/或从可拆卸介质711被安装。在该计算机程序被中央处理单元(CPU)701执行时，执行本申请的系统中限定的上述功能。
需要说明的是，本发明所示的计算机可读存储介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本发明中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本发明中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读存储介质，该计算机可读存储介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读存储介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
附图中的流程图和框图，图示了按照本发明各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，上述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。 也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本发明实施例中所涉及到的单元可以通过软件的方式实现，也可以通过硬件的方式来实现，所描述的单元也可以设置在处理器中。其中，这些单元的名称在某种情况下并不构成对该单元本身的限定。
作为另一方面，本申请还提供了一种计算机可读存储介质，该计算机可读存储介质可以是上述实施例中描述的电子设备中所包含的；也可以是单独存在，而未装配入该电子设备中。上述计算机可读存储介质承载有一个或者多个程序，当上述一个或者多个程序被一个该电子设备执行时，使得该电子设备实现如上述实施例中所述的晶圆生产过程的侦测方法。
例如，所述的电子设备可以实现如图1中所示的：步骤S102，获取晶圆的缺陷数据。步骤S104，获得晶圆的失效位元的位置数据。步骤S106，根据缺陷数据确定晶圆中存储块的缺陷面积。步骤S108，根据失效位元的位置数据确定晶圆中存储块的失效位元数量。步骤S110，对晶圆中存储块的所述缺陷面积和失效位元数量进行处理，获得关联系数。步骤S112，根据关联系数确定该晶圆的失效位元的异常原因。
又如，所述的电子设备还可以实现如图5所示的各个步骤。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本发明的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
通过以上的实施方式的描述，本领域的技术人员易于理解，这里描述的示例实施方式可以通过软件实现，也可以通过软件结合必要的硬件的方式来实现。因此，根据本发明实施方式的技术方案可以以软件产品的形式体现出来，该软件产品可以存储在一个非易失性存储介质(可以是CD-ROM，U盘，移动硬盘等)中或网络上，包括若干指令以使得一台计算设备(可以是个人计算机、服务器、触控终端、或者网络设备等)执行根据本发明实施方式的方法。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本发明的其它实施方案。本申请旨在涵盖本发明的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本发明的一般性原理并包括本发明未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本发明的真正范围和精神由下面的权利要求指出。
应当理解的是，本发明并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本发明的范围仅由所附的权利要求来限制。

Claims (10)

  1. 一种晶圆缺陷的溯源方法，其特征在于，包括：
    获取晶圆的缺陷数据；
    获得所述晶圆的失效位元的位置数据；
    根据所述缺陷数据确定所述晶圆中存储块的缺陷面积；
    根据所述失效位元的位置数据确定所述晶圆中存储块的失效位元数量；
    对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数；
    根据所述关联系数确定所述晶圆的失效位元的异常原因。
  2. 如权利要求1所述的方法，其特征在于，对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数包括：
    根据所述缺陷数据获得所述晶圆的缺陷影响区域；
    根据所述晶圆中存储块的缺陷面积和所述缺陷影响区域的面积的比值确定所述晶圆中存储块的缺陷面积指标；
    根据所述晶圆中存储块的所述失效位元数量和所述缺陷影响区域的面积的比值确定所述晶圆中存储块的失效位元指标；
    对所述晶圆中存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数。
  3. 如权利要求2所述的方法，其特征在于，对所述晶圆中存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数包括：
    将所述晶圆中包含异常数据的存储块剔除，获得目标存储块集合；
    对所述目标存储块集合中的存储块的所述缺陷面积指标和相应的所述失效位元指标进行关联分析，获得所述关联系数。
  4. 如权利要求3所述的方法，其特征在于，将所述晶圆中包含异常数据的存储块剔除，获得目标存储块集合包括以下情况的一种或多种：
    将所述晶圆中所述失效位元指标大于失效位元指标阈值的存储块进行剔除，获得所述目标存储块集合；
    将所述晶圆中所述失效位元数量大于失效位元数量阈值的存储块进行剔除，获得所述目标存储块集合。
  5. 如权利要求1所述的方法，其特征在于，根据所述关联系数确定所述晶圆的失效位元的异常原因包括：
    获取所述晶圆的制程数据，所述制程数据包括结构层信息和所述结构层信息对应的制程信息；
    若所述关联系数大于关联系数阈值，则确定所述缺陷数据所处的结构层信息；
    根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因。
  6. 如权利要求5所述的方法，其特征在于，根据所述缺陷数据所处的结构层信息对 应的制程信息确定所述异常原因包括：
    根据所述缺陷数据所处的结构层信息对应的制程信息获得所述制程信息的环境数据；
    对所述制程信息的环境数据进行分析，获得所述异常原因。
  7. 如权利要求5所述的方法，其特征在于，根据所述缺陷数据所处的结构层信息对应的制程信息确定所述异常原因包括：
    根据所述缺陷数据和所述失效位元的位置数据确定所述晶圆中未造成失效位元的缺陷数量；
    根据所述晶圆中未造成失效位元的缺陷数量和所述缺陷数据中缺陷总数量的比值确定为所述晶圆的缺陷清除率；
    根据经验法则对所述晶圆的缺陷清除率进行评估；
    若评估结果为异常，则确定所述制程信息中包括清洗异常功能的步骤为所述异常原因。
  8. 一种晶圆缺陷的溯源装置，其特征在于，包括：
    缺陷数据模块，配置为获取晶圆的缺陷数据；
    失效位元数据模块，配置为获得所述晶圆的失效位元的位置数据；
    缺陷面积统计模块，配置为根据所述缺陷数据确定所述晶圆中存储块的缺陷面积；
    失效位元数量模块，配置为根据所述失效位元的位置数据确定所述晶圆中存储块的失效位元数量；
    关联系数模块，配置为对所述晶圆中存储块的所述缺陷面积和所述失效位元数量进行处理，获得关联系数；
    缺陷溯源模块，配置为根据所述关联系数确定所述晶圆的失效位元的异常原因。
  9. 一种电子设备，其特征在于，包括：
    一个或多个处理器；
    存储装置，用于存储一个或多个程序；
    当所述一个或多个程序被所述一个或多个处理器执行，使得所述一个或多个处理器实现如权利要求1-7中任一所述的方法。
  10. 一种计算机可读介质，其上存储有计算机程序，其特征在于，所述程序被处理器执行时实现如权利要求1-7中任一所述的方法。
PCT/CN2021/103716 2020-09-11 2021-06-30 晶圆缺陷的溯源方法、装置、电子设备及计算机可读介质 WO2022052592A1 (zh)

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