WO2022048243A1 - 半导体器件的制备方法 - Google Patents

半导体器件的制备方法 Download PDF

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Publication number
WO2022048243A1
WO2022048243A1 PCT/CN2021/100706 CN2021100706W WO2022048243A1 WO 2022048243 A1 WO2022048243 A1 WO 2022048243A1 CN 2021100706 W CN2021100706 W CN 2021100706W WO 2022048243 A1 WO2022048243 A1 WO 2022048243A1
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word line
isolation layer
active region
semiconductor device
oxygen
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French (fr)
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陈涛
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/401,551 priority Critical patent/US11882693B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

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  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for fabricating a semiconductor device.
  • DRAM Dynamic Random Access Memory
  • Each storage unit includes a transistor and a corresponding capacitor.
  • the amount of stored charge in the capacitor is used to represent 0 and 1. In order to avoid insufficient charge This results in data errors, requiring periodic refresh of the capacitors.
  • DRAM with a buried word line structure ie DRAM
  • buried wordline DRAM has been developed in recent years.
  • the buried word line is formed in the substrate and penetrates the active area in the substrate, so that part of the word line can be reused as the gate of the transistor of the memory cell, the transistor
  • the source and drain regions are formed in the substrate on both sides of the part of the word line.
  • the existing buried word line preparation method has problems such as complicated preparation steps, and the uneven thickness of the word line isolation layer formed during the preparation process is likely to cause leakage, which is likely to lead to poor yield of semiconductor devices.
  • the purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, and to provide a preparation method of a semiconductor device.
  • a method for fabricating a semiconductor device comprising:
  • a substrate is provided, on which a shallow trench isolation structure and an active region are formed, and an insulating material is filled in the shallow trench isolation structure;
  • a first isolation layer is formed in the active region by using an ion doping technique, and the first isolation layer surrounds a part of the active region;
  • a second word line structure is formed in the shallow trench isolation structure, and the first word line structure and the second word line structure are connected to form a buried word line structure extending along the surface of the substrate.
  • the forming the first isolation layer in the active region using an ion doping technique includes:
  • the substrate is annealed to allow the oxygen-containing ions to react with the material of the active region to form an insulating oxide to form the first isolation layer.
  • the forming the first isolation layer in the active region using an ion doping technique includes:
  • Oxygen ions are implanted into the inside of the active region through the first opening, the first mask layer is removed, and the bottom of the first isolation layer is formed by annealing;
  • Oxygen ions are implanted into the inside of the active region through the second opening, the second mask layer is removed, and the sidewalls of the first isolation layer, the bottom of the first isolation layer and the first isolation layer are formed by annealing.
  • the sidewalls of the isolation layer constitute the first isolation layer.
  • the energy of the implanted oxygen-containing ions is controlled to always maintain a constant value.
  • the energy of the implanted oxygen-containing ions is controlled to gradually decrease from large to small, so that the oxygen-containing ions are The ions are distributed vertically along the substrate.
  • the maximum energy of the oxygen-containing ions implanted through the second opening is equal to the energy of the oxygen-containing ions implanted through the first opening.
  • the forming a second word line structure in the shallow trench isolation structure includes:
  • a silicon film is filled in the first trench structure, and ion implantation is performed on the silicon film in the first trench structure to form the second word line structure.
  • the remaining insulating material in the shallow trench isolation structure forms a second isolation layer.
  • the substrate material is a low-doped monocrystalline silicon material
  • the silicon thin film filled in the first trench structure is a polycrystalline silicon material
  • ion implantation parameters are controlled, So that the difference between the resistivities of the first word line structure and the second word line structure formed is within a certain threshold range.
  • the first word line structure and the second word line structure are etched, a second trench is formed, and a deposition process is performed.
  • a cover layer is on the second trench.
  • the preparation method of the semiconductor device of the present disclosure adopts the ion doping technology to directly form the first isolation layer inside the active region of the substrate, forms the first word line structure through ion implantation in the active region surrounded by the first isolation layer, and A second word line structure is formed in the shallow trench isolation structure, and the first word line structure and the second word line structure are connected to form a buried word line structure extending along the surface of the substrate.
  • the advantage of this preparation method is that it does not need to etch the word line trenches in the active area, and the first word line structure is formed by ion implantation, which simplifies the preparation method of the word line structure in the active area, and can ensure that there are The thickness of the first isolation layer of the word line structure in the source region is uniform, and it is not easy to leak electricity, thereby ensuring good performance of the semiconductor device.
  • 1 is a top view of a semiconductor device
  • Fig. 2 is the cross-sectional schematic diagram of A-A in Fig. 1;
  • FIG. 3 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the disclosure
  • FIG. 4 is a top view of a substrate according to an embodiment of the disclosure.
  • FIG. 5 is a schematic cross-sectional view of the partial structure in the direction A-A in FIG. 4;
  • FIG. 6 is a top view of the semiconductor device forming the bottom of the first isolation layer
  • FIG. 7 is a schematic cross-sectional view of the semiconductor device of FIG. 6 in the direction A-A before removing the first mask layer;
  • FIG. 8 is a top view of a semiconductor device with sidewalls of a first isolation layer formed
  • FIG. 9 is a schematic cross-sectional view of the semiconductor device of FIG. 8 in the direction A-A before the second mask layer is removed;
  • FIG. 10 is a top view of the semiconductor device after forming the first word line structure
  • Figure 11 is a schematic cross-sectional view of a part in the direction A-A in Figure 10;
  • FIG. 12 shows a top view of the semiconductor device after forming the second isolation layer
  • Figure 13 is a schematic cross-sectional view of a part in the direction A-A in Figure 12;
  • FIG. 14 is a top view of the semiconductor device after filling the silicon film in the first trench structure
  • Figure 15 is a schematic cross-sectional view of a part in the direction A-A in Figure 14;
  • 16 is a top view of the semiconductor device after forming the second word line structure
  • Figure 17 is a schematic cross-sectional view of a part in the direction A-A in Figure 16;
  • 19 is a schematic cross-sectional view after the source and drain are formed
  • FIG. 20 is a schematic cross-sectional view after the capping layer is formed.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 is a schematic top view of a structure of a semiconductor device
  • FIG. 2 is a schematic cross-sectional view along the A-A direction in FIG. 1
  • the semiconductor device includes a substrate 1 on which a shallow trench isolation structure is provided, a plurality of active regions 20 are defined by the shallow trench isolation structure, and transistors are prepared in the active regions 20 .
  • the shallow trench isolation structure is filled with insulating material, thereby forming the isolation region 10 .
  • the substrate 1 is also provided with word lines 30 extending in the vertical direction.
  • the word line 30 runs through the isolation region 10 and the active region 20 , that is, the word line 30 includes a first word line structure 310 located in the active region and a second word line structure 320 located in the isolation region, and a first word line structure 320 located in the active region 20
  • the word line structure 310 can be multiplexed as the gate of the transistor, the source electrode 201 and the drain electrode 202 are provided on both sides of the gate, and a word line isolation layer 31, that is, a gate insulating layer, is also provided on the outer wall of the word line multiplexed as the gate. , used to be isolated from the source electrode 201 and the drain electrode 202 to form a transistor structure.
  • a word line isolation layer 32 is also provided on the outer wall of the word line at the part of the isolation region 10 for isolation from the substrate 1 , and a cover layer 6 is also provided above the word line 30 .
  • two transistors are arranged in series in one active region, and the source and drain of the two transistors are shared. Since the cross-sectional view shown in FIG. 2 has a symmetrical structure, only a part of it is marked. Those skilled in the art can understand that the same filling line in another part represents the same structure. In other embodiments, only one transistor may be provided in one active region. It should also be noted that, for the convenience of illustrating the word line structure, the capping layer 6 is not shown in FIG. 1 .
  • a related method for preparing the buried word line structure is to etch vertical word line trenches on the substrate 1 provided with the isolation region 10 and the active region 20 in advance, and then pass the ISSG (in-situ water Gas generation rapid thermal annealing process) in accordance with a certain proportion of H 2 and O 2 into the word line trench, using the bulb to heat up rapidly, H 2 and O 2 react on the silicon surface of the word line trench to generate oxygen radicals, using oxygen The radicals react with the silicon to form oxide spacers for the word lines.
  • the word line structure is then formed by depositing titanium nitride, tungsten, etc. within the oxide spacers.
  • the word line isolation layer 31 formed by the ISSG process often has a problem of uneven thickness, and when used as a gate insulating layer of a transistor, it is easy to cause leakage, thereby affecting the performance of the semiconductor device.
  • the present disclosure provides a method for fabricating a semiconductor device.
  • FIG. 3 a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure is provided.
  • the fabrication method includes:
  • step S100 a substrate 1 is provided, a shallow trench isolation structure 101 and an active region 20 are formed on the substrate 1, and an insulating material 102 is filled in the shallow trench isolation structure 101 to form an isolation region 10;
  • Step S200 a first isolation layer 330 is formed inside the active region 20 by using an ion doping technology, and the first isolation layer 330 surrounds part of the active region;
  • Step S300 performing ion implantation on the active region surrounded by the first isolation layer 330 to form the first word line structure 310;
  • a second word line structure 320 is formed in the shallow trench isolation structure 101 , and the first word line structure 310 and the second word line structure 320 are connected to form a buried word line structure extending along the surface of the substrate 1 .
  • the ion doping technology is used to directly form the first isolation layer 330 inside the active region 20 of the silicon substrate 1, and the active region wrapped by the first isolation layer 330 is directly formed.
  • a first word line structure 310 having a conductor characteristic is formed by ion implantation, thereby completing the preparation of the word line of the active region 20 .
  • a second word line structure 320 is formed in the shallow trench isolation structure, thereby completing the word line preparation of the isolation region 10 .
  • This method can form the part of the word line isolation layer without etching the word line trench in the active region 20, and the thickness of the word line isolation layer formed by the ion doping technology is uniform.
  • the word line isolation layer is used as a gate insulating layer, which has good insulation performance and is not easy to leak electricity, and can ensure good performance of the semiconductor device.
  • the method utilizes the existing substrate material to prepare the word line of the active region by ion implantation, without depositing the metal material of the word line, and also simplifies the preparation method of the word line in the active region.
  • a substrate 1 is provided.
  • FIG. 4 is a schematic top view of the structure of the substrate
  • FIG. 5 is a schematic cross-sectional view of the partial structure in FIG.
  • a shallow trench isolation structure 101 is formed on the substrate 1 , the shallow trench isolation structure 101 defines a plurality of active regions 20 in the substrate 1 , and an insulating material 102 is filled in the shallow trench isolation structure 101
  • An isolation region 10 is formed.
  • the substrate 1 is a semiconductor substrate, and the formation material of the substrate 1 includes but is not limited to a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate.
  • the semiconductor substrate is a single crystal substrate or a polycrystalline silicon substrate.
  • the crystal substrate can also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it can be an N-type polysilicon substrate or a P-type polysilicon substrate.
  • the substrate 1 is preferably made of a low-doped single-crystal silicon material (such as NTD-Si). Impurity streaks in conventional doping can be avoided.
  • the shallow trench isolation structure 101 is formed on the semiconductor substrate 1 by a shallow trench isolation (Shallow Trench Isolation, STI) technology. Specifically, a silicon nitride layer can be deposited on the substrate 1 first, and then the silicon nitride layer can be patterned to form a hard mask. Next, the substrate 1 is etched to form a steep shallow trench isolation structure 101 . Finally, the insulating material 102 is filled in the shallow trench isolation structure 101 to form the isolation region 10 .
  • the filled insulating material 102 may be silicon nitride or silicon oxide.
  • the shape of the active region 20 is defined by the shape of the isolation region 10.
  • the parallelogram-shaped active region 20 shown in FIG. 4 is only an illustration, and its shape can also be other shapes such as a rectangle, an ellipse, etc.
  • irregular edges may also be formed.
  • the present application does not specifically limit the shapes of the isolation region 10 and the active region 20 .
  • a first isolation layer 330 is formed inside the active region 20 by using an ion doping technology, and the first isolation layer 330 surrounds part of the active region.
  • the formation of the first isolation layer 330 by ion doping technology includes two process steps: 1) implantation of oxygen-containing ions, using an oxygen implanter to implant oxygen-containing ions into the active region, so as to generate a high voltage under the silicon surface layer. concentration of oxygen injection layer. 2) High temperature annealing, so that the implanted oxygen-containing ions react with silicon to form an insulating silicon dioxide isolation layer.
  • the oxygen-containing ions can be O + , O 2 + , HO + , H 2 O + and the like.
  • the oxygen-containing ions may further contain nitrogen ions, such as N + , N 2 + , etc., thereby forming a mixed insulating buried layer of silicon dioxide and silicon nitride.
  • the thickness of the isolation layer formed by this method is uniform, and when used as a gate isolation layer, it can have a good and stable insulating effect, and is not prone to leakage.
  • this step can be divided into two steps, firstly preparing the bottom 331 of the first isolation layer, The sidewalls 332 of the first isolation layer are then prepared.
  • step S200 may include the following sub-steps:
  • a first mask layer 51 having a first opening 510 is formed on the substrate 1 .
  • FIG. 7 it is a schematic cross-sectional view of a semiconductor device including a first mask layer 51 .
  • the shape of the first opening 510 of the first mask layer 51 is consistent with the shape of the bottom 331 of the first isolation layer to be formed, and the first opening 510 is located just above the bottom 331 of the first isolation layer to be formed, and the substrate 1 is other The places are covered by the first mask layer 51 . That is to say, the projection of the first opening 510 on the substrate 1 should be able to coincide with the projection of the final structure of the bottom 331.
  • the material of the first mask layer 51 can be photoresist, which can be formed by coating, exposure and development techniques. formed on the substrate 1.
  • the first mask layer 51 may also be a hard mask layer, such as silicon nitride, borophosphosilicate glass, or the like.
  • the formation method of the hard mask may be a deposition process such as chemical vapor deposition (CVD) and physical vapor deposition (PVD).
  • step S220 oxygen-containing ions are implanted into the active region 20 through the first opening 510 , the first mask layer 51 is removed, and the bottom 331 of the first isolation layer 330 is formed by annealing.
  • the implantation energy of oxygen-containing ions needs to be set according to the position and insulating properties of the first isolation layer 330 to be formed.
  • the energy of the oxygen-containing ions implanted in this step is controlled to always keep a constant value, so that the oxygen-containing ions are all implanted to the same depth, so that a horizontal silicon dioxide buried layer can be formed, that is, as shown in the figure
  • the bottom 331 structure of the first isolation layer is shown.
  • the parameter setting of the ion implantation can be simplified. It should be noted that the horizontal bottom 331 structure is only an ideal schematic description. During the actual process of ion implantation, ions will inevitably diffuse to a certain extent. For example, ions at the edge will have a tendency to diffuse outward. , the formation of a silicon dioxide buried layer is not a completely standard horizontal buried layer.
  • FIG. 6 shows a top view of the semiconductor device after the bottom of the first isolation layer is formed and the first mask layer is removed. It can be understood that FIG. 7 can be regarded as a partial view of the semiconductor device in FIG. 6 before the first mask layer is removed. Schematic cross-sectional view of the AA direction.
  • parameters such as annealing temperature, time, atmosphere, etc. can be set according to the actual situation of the device.
  • the annealing temperature may be 800-1500° C.
  • the annealing time may be 1-24 hours
  • the annealing atmosphere may be a mixed gas of Ar and O 2 or N 2 and O 2 .
  • a second mask layer 52 having a second opening 520 is formed on the substrate 1 .
  • FIG. 9 a schematic cross-sectional view of a semiconductor device including a second mask layer 52 is shown.
  • the second opening 520 of the second mask layer 52 is located just above the sidewall 332 of the first isolation layer 330 to be formed, and the rest of the substrate 1 is covered by the second mask layer 52 . That is to say, the projection of the second opening 520 on the substrate 1 should be able to coincide with the projection of the sidewall 332 of the first isolation layer 330 finally formed.
  • the material and forming process of the second mask layer 52 can be referred to the first mask layer 51, and the two can be the same or different.
  • the precision of the second mask layer 52 is extremely high, so it can be prepared by EUV photolithography.
  • step S240 oxygen-containing ions are re-implanted into the active region 20 through the second opening 520, the second mask layer 52 is removed, and the sidewalls 332 of the first isolation layer 330, the bottom 331 of the first isolation layer and the first isolation layer 330 are formed by annealing.
  • the isolation layer sidewalls 332 constitute the first isolation layer 330 .
  • the oxygen-containing ions implanted in this step should be vertically distributed in the substrate 1 and located directly above the edge of the bottom 331 structure formed in step S220, and the vertical sidewalls 332 and the bottom 331 are buried in layers The edges are connected to form a whole.
  • the implantation energy of the oxygen-containing ions determines the implantation depth.
  • the amount of the oxygen-containing ions implanted in this step is controlled.
  • the energy gradually decreases from large to small, so that the oxygen-containing ions are gradually implanted into the substrate 1 from deep to shallow and distributed along the vertical direction of the substrate 1;
  • the distribution of oxygen-containing ions at each vertical position is uniform, the vertical silicon dioxide sidewalls formed after annealing are uniform in thickness, and the performances of the sidewalls are basically the same.
  • the maximum energy of the oxygen-containing ions implanted in this step is equal to the energy of the oxygen-containing ions implanted through the first opening 510, so as to ensure that the implantation depth of the oxygen-containing ions for forming the sidewall 332 is consistent with the bottom 331, and the final formed
  • the sidewalls of the first isolation layer in the vertical direction may be connected to the bottom of the first isolation layer in the horizontal direction to form a complete structure of the first isolation layer. It should be noted that the vertical sidewall 332 is only an ideal schematic description. During the actual process of ion implantation, ions will inevitably diffuse to a certain extent. For example, ions at the edge will diffuse outward. Trend, the formation of iso-silicon dioxide buried layer is not a completely standard buried layer distributed along the thickness direction.
  • the removal method of the second mask layer 52 refers to the first mask layer 51, and parameters such as annealing temperature, time, atmosphere, etc. can be set according to the actual situation of the device.
  • FIG. 8 shows a top view of the semiconductor device after removing the second mask layer. It can be understood that FIG. 9 can be regarded as a schematic cross-sectional view of the semiconductor device in FIG. 8 in the direction A-A before the second mask layer is removed.
  • the preparation of the first isolation layer 330 of the active region 20 is completed, and the top view of the obtained semiconductor device is shown in FIG. 8 .
  • the preparation method does not need to etch the active region 20 and does not need to deposit the isolation layer, but completes the preparation of the isolation layer in one step through the ion doping technology, which greatly simplifies the preparation process.
  • step S300 ion implantation is performed on the active region surrounded by the first isolation layer 330 to form the first word line structure 310 located in the active region 20 .
  • FIG. 10 is a top view of the semiconductor device after the first word line structure 310 is formed
  • FIG. 11 is a schematic cross-sectional view of FIG.
  • the ion species implanted in this step can be P ions, N ions, B ions, or a combination of the above ions, and the specific ion species can be selected according to the performance of the semiconductor device to be prepared.
  • the type of ions to be implanted is determined according to the type of substrate and transistor. Since the first isolation layer 330 is surrounded by substrate silicon, that is, low-doped single-crystal silicon (eg NTD-Si), the doping precision is high and the amount of impurities introduced is small, which can avoid impurity stripes during conventional doping, so that the The doped material can achieve the required work function of the gate, and the resistivity can match the threshold voltage. It should be noted that, during ion implantation, an ion implantation window also needs to be formed, that is, a photoresist similar to that in step S200 can be used to form by exposure and development, and the specific process will not be repeated here. .
  • substrate silicon that is, low-doped single-crystal silicon (eg NTD-Si)
  • the doping precision is high and the amount of impurities introduced is small, which can avoid impurity stripes during conventional doping, so that the The doped material can achieve the required work function of the gate, and
  • Step S400 referring to FIGS. 10 to 17 , a second word line structure is formed in the shallow trench isolation structure.
  • the second word line structure can be prepared by the following steps:
  • Step S410 removing part of the insulating material in the shallow trench isolation structure to form the first trench structure 41.
  • part of the insulating material 102 in the shallow trench isolation structure can be removed by etching, the etching depth can be controlled, and the insulating material covering the inner wall of the shallow trench isolation structure 101 can be retained, and this part of the insulating material forms the second isolation layer 340.
  • the etching may be dry etching.
  • the thickness of the second isolation layer 340 can be set according to requirements.
  • FIG. 12 shows a top view of the semiconductor device after forming the second isolation layer 340
  • FIG. 13 is a schematic cross-sectional view partially taken along the A-A direction in FIG. 12 .
  • the insulating material that has been filled in the shallow trench isolation structure is used to prepare the second isolation layer, which is simple and easy to implement.
  • step S420 the silicon film 40 is filled in the first trench structure 41, and ion implantation is performed on the silicon film 40 in the first trench structure 41 to form a second word line structure.
  • FIG. 14 shows a top view of the semiconductor device after filling the silicon thin film 40 in the first trench structure 41
  • FIG. 15 is a schematic cross-sectional view partially taken along the A-A direction in FIG. 14 .
  • the filled silicon thin film 40 is located in the second isolation layer 340 , and ion implantation is performed on the silicon thin film 40 in the second isolation layer 340 to form the second word line structure 320 located in the isolation region 10 .
  • FIG. 16 is a top view of the semiconductor device after the second word line structure 320 is formed
  • FIG. 17 is a schematic cross-sectional view of FIG.
  • the filled silicon can be a polysilicon film grown by chemical vapor deposition or the like.
  • the polysilicon growth method is simple, and ideal resistance characteristics can also be obtained after ion implantation.
  • the method of ion implantation in this step refer to step S300.
  • first word line structure and the second word line structure are to be connected to form a buried word line structure extending along the surface of the substrate, ion implantation is performed on the active region surrounded by the first isolation layer 330 and the first
  • the ion implantation parameters are controlled so that the difference between the resistivities of the first word line structure and the second word line structure formed is within a certain threshold range, and the threshold range can be as far as possible. is small, so that the resistivities of the first word line structure 310 and the second word line structure 320 are as close or equal as possible, so that the performance of the final word line is stable and consistent.
  • Implantation parameters include, but are not limited to, ion type, ion concentration, and implantation energy.
  • both the above-mentioned steps S300 and S400 include the step of implanting silicon, in order to simplify the process, these two steps can also be performed simultaneously, that is, after the first isolation layer 330 is prepared, it is directly formed
  • the second isolation layer 340 is then ion-implanted to the monocrystalline silicon in the first isolation layer 330 and the polycrystalline silicon in the second isolation layer 340 simultaneously to form the first word line structure 310 and the second word line structure 320 at the same time.
  • the process parameters for the two regions during simultaneous implantation are the same, and the silicon material of the active region and the silicon material filled in the first trench structure are not necessarily exactly the same, and it should be possible to ensure the formation of the first word
  • the resistivities of the line structure 310 and the second word line structure 320 are as close as possible or equal to ensure stable and consistent performance of the formed word lines.
  • the finally formed first word line structure 310 and the second word line structure 320 are connected to form a buried word line structure extending along the surface of the substrate 1 , as shown in FIG. 16 .
  • preparation method of the semiconductor device of this embodiment may further include:
  • Step S600 etching the first word line structure 310 and the second word line structure 320 to obtain a second trench, as shown in FIG. 18 .
  • the manufacturing method of the semiconductor device of this embodiment may further include:
  • step S700 doping is performed on both sides of the second isolation layer 340 to form a source electrode and a drain electrode, as shown in FIG. 19 .
  • the manufacturing method of the semiconductor device of this embodiment may further include:
  • Step S800 as shown in FIG. 20 , a capping layer 6 is formed in the second trench to protect the word line.
  • the capping layer 6 may also cover the active region 20 to protect the active region 20 .
  • the material of the capping layer 6 may include one or a combination of silicon nitride, silicon oxide, silicon oxynitride or other insulating materials.
  • the second isolation layer 340 and the second word line structure 320 may be prepared first, and then the first isolation layer 330 and the first word line structure 310 may be prepared.
  • the source and drain can be prepared first, and then the second trench can be etched to form the capping layer 6 .
  • the above preparation method is described by taking two transistors arranged in one active area as shown in FIG. 1 and FIG. 2 as an example. Those skilled in the art can understand that when only one transistor is arranged in the active area, it can be prepared according to the same idea. Buried word lines, the specific process will not be repeated here
  • the buried word line isolation layer in the active region of the semiconductor device prepared by the preparation method of this embodiment has a uniform thickness, and is not prone to leakage when multiplexed into a transistor gate, thereby ensuring good performance of the semiconductor device.
  • the semiconductor device can be used in various storage products such as dynamic random access memory, and the application does not limit its specific application field.

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Abstract

一种半导体器件的制备方法。所述制备方法包括：提供一衬底，在所述衬底上形成有源区和浅沟槽隔离结构（S100）；采用离子掺杂技术在所述有源区的内部形成第一隔离层（S200），对第一隔离层内包围的有源区进行离子注入，形成第一字线结构（S300）；在浅沟槽隔离结构内形成第二字线结构，第一字线结构和第二字线结构连接形成沿所述衬底表面延伸的埋入式字线结构（S400）。

Description

半导体器件的制备方法
交叉引用
本公开要求于2020年9月7日提交的申请号为202010927242.0名称为“半导体器件的制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种半导体器件的制备方法。
背景技术
DRAM(DynamicRandomAccessMemory)，即动态随机存储器是较为常见的系统内存，其中每个存储单元(cell)包括一个晶体管和一个对应的电容，利用电容内存储电荷的多寡来代表0和1，为了避免电荷不足导致数据出错，需要周期性地刷新电容。为提升DRAM的集成度以加快对每个存储单元的操作速度，以及应对来自PC、智能手机、平板等市场对DRAM的强劲需求，近年来发展出了具有埋入式字线结构的DRAM(即buried wordline DRAM)以满足上述需求。
在具有埋入式字线结构的DRAM中，埋入式字线形成于衬底内并贯穿衬底内的有源区，从而使部分字线可以复用为存储单元的晶体管的栅极，晶体管的源漏区形成于该部分字线两侧的衬底中。现有的埋入式字线制备方法存在制备步骤繁琐等问题，且制备过程中形成的字线隔离层厚度不均匀易引起漏电，容易导致半导体器件良率差。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种半导体器件 的制备方法。
根据本公开的一个方面，提供一种半导体器件的制备方法，包括：
提供一衬底，在所述衬底上形成浅沟槽隔离结构和有源区，所述浅沟槽隔离结构内填充有绝缘材料；
采用离子掺杂技术在所述有源区内形成第一隔离层，所述第一隔离层包围部分所述有源区；
对所述第一隔离层包围的所述有源区进行离子注入，形成第一字线结构；
在所述浅沟槽隔离结构内形成第二字线结构，使所述第一字线结构和所述第二字线结构连接形成沿所述衬底表面延伸的埋入式字线结构。
在本公开的一种示例性实施例中，所述采用离子掺杂技术在所述有源区内形成第一隔离层包括：
采用注氧机向所述有源区内部注入含氧离子；
对所述衬底进行退火，使所述含氧离子与有源区的材料反应生成绝缘的氧化物，以形成所述第一隔离层。
在本公开的一种示例性实施例中，所述采用离子掺杂技术在所述有源区内形成第一隔离层包括：
在所述衬底上形成具有第一开口的第一掩模层；
通过所述第一开口向所述有源区的内部注入氧离子，去除所述第一掩模层，退火形成所述第一隔离层底部；
在所述衬底上形成具有第二开口的第二掩模层；
通过所述第二开口向所述有源区的内部注入氧离子，去除所述第二掩模层，退火形成所述第一隔离层侧壁，所述第一隔离层底部和所述第一隔离层侧壁构成所述第一隔离层。
在本公开的一种示例性实施例中，通过所述第一开口注入含氧离子的过程中，控制注入的所述含氧离子的能量始终保持一恒定值。
在本公开的一种示例性实施例中，通过所述第二开口注入含氧离子的过程中，控制注入的所述含氧离子的能量由大到小逐渐减小，以使所述含氧离子沿所述衬底竖直方向分布。
在本公开的一种示例性实施例中，通过所述第二开口注入的所述含 氧离子的最大能量等于通过所述第一开口注入的所述含氧离子的能量。
在本公开的一种示例性实施例中，所述在所述浅沟槽隔离结构内形成第二字线结构包括：
去除所述浅沟槽隔离结构内的部分所述绝缘材料，形成第一沟槽结构；
在所述第一沟槽结构内填充硅薄膜，对所述第一沟槽结构内的硅薄膜进行离子注入，形成所述第二字线结构。
在本公开的一种示例性实施例中，去除所述浅沟槽隔离结构内的部分所述绝缘材料后，所述浅沟槽隔离结构内剩余的所述绝缘材料形成第二隔离层。
在本公开的一种示例性实施例中，所述衬底材料为低掺杂的单晶硅材料，所述第一沟槽结构内填充的硅薄膜为多晶硅材料。
在本公开的一种示例性实施例中，对所述第一隔离层包围的有源区进行离子注入和对所述第一沟槽结构内的硅薄膜进行离子注入时，控制离子注入参数，以使形成的所述第一字线结构和第二字线结构的电阻率的差值在一定阈值范围内。
在本公开的一种示例性实施例中，在形成所述第二字线结构后，对所述第一字线结构和所述第二字线结构进行刻蚀，形成第二沟槽，沉积覆盖层于所述第二沟槽上。
本公开的半导体器件的制备方法采用离子掺杂技术在衬底有源区的内部直接形成第一隔离层，对第一隔离层包围的有源区通过离子注入形成第一字线结构，并在浅沟槽隔离结构内形成第二字线结构，第一字线结构和第二字线结构连接形成沿所述衬底表面延伸的埋入式字线结构。该制备方法的优点在于：不需要在有源区刻蚀字线沟槽，通过离子注入的方式形成第一字线结构，简化了有源区内的字线结构的制备方法，且可以保证有源区的字线结构的第一隔离层厚度均匀，不易漏电，保证良好的半导体器件性能。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种半导体器件的俯视图；
图2为图1中A-A向的截面示意图；
图3为本公开实施方式半导体器件的制备方法流程图；
图4为本公开实施方式衬底的俯视图；
图5为图4中局部结构在A-A向的截面示意图；
图6为形成第一隔离层底部的半导体器件的俯视图；
图7为图6半导体器件去除第一掩模层前在A-A向的截面示意图；
图8为形成第一隔离层侧壁的半导体器件的俯视图；
图9为图8半导体器件去除第二掩模层前在A-A向的截面示意图；
图10为形成第一字线结构后的半导体器件的俯视图；
图11为图10中局部在A-A向的截面示意图；
图12示出了形成第二隔离层后的半导体器件的俯视图；
图13为图12中局部在A-A向的截面示意图；
图14为在第一沟槽结构内填充硅薄膜后的半导体器件的俯视图；
图15为图14中局部在A-A向的截面示意图；
图16为形成第二字线结构后的半导体器件的俯视图；
图17为图16中局部在A-A向的截面示意图；
图18为形成第二沟槽后的截面示意图；
图19为形成源极和漏极后的截面示意图；
图20为形成覆盖层后的截面示意图。
图中：1、衬底；10、隔离区；101、浅沟槽隔离结构；102、绝缘材料；20、有源区；201、源极；202、漏极；30、字线；310、第一字线结构；320、第二字线结构；330、第一隔离层；331、第一隔离层底部；332、第一隔离层侧壁；340、第二隔离层；40、硅薄膜；41、第一沟槽结构； 51、第一掩模层；510、第一开口；52、第二掩模层；520、第二开口；6、覆盖层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
图1所示为半导体器件的一种结构俯视示意图，图2所示为图1中A-A向的截面示意图。参考图1和图2，该半导体器件包括衬底1，衬底1上设有浅沟槽隔离结构，由浅沟槽隔离结构定义出多个有源区20，有源区20制备有晶体管。浅沟槽隔离结构内填充有绝缘材料，由此形成隔离区10。衬底1上还设有沿竖向延伸的字线30。字线30贯穿隔离区10和有源区20，即字线30包含位于有源区的第一字线结构310和位于隔离区的第二字线结构320，位于有源区20部分的第一字线结构310可以复用为晶体管的栅极，栅极两侧设有源极201和漏极202，在复用为栅极的字线外壁还设置有字线隔离层31，即栅绝缘层，用以与源极201和漏极202隔离，以此形成晶体管结构。位于隔离区10部分的字线外壁也设置有字线隔离层32，用以与衬底1隔离，字线30上方还设置有覆盖层6。需要说明的是，图1和图2所示的示例性实施方式中，一个有源区串联设置有两个晶体管，两个晶体管的源极和漏极共用。由于图2所示的截面图为对称结构，因此仅对其中一部分进行了标记，本领域技术人员可以理解，另一部分相同填充线表示相同的结构，以下附图同理，后续将不再赘述。在其他实施方式中，一个有源区也可以只设置一个晶体管。还需说明的是，为了方便示出字线结构，图1中未显示覆盖层6。
制备埋入式字线结构的一种相关的方法是，在预先设置有隔离区10和有源区20的衬底1上刻蚀出竖向的字线沟槽，然后通过ISSG(原位水气生成快速热退火工艺)按照一定比例在字线沟槽中通入H 2和O 2，利用灯泡快速升温，H 2和O 2在字线沟槽的硅表面反应生成氧自由基， 利用氧自由基与硅反应生成字线的氧化隔离层。然后通过在氧化隔离层内沉积氮化钛和钨等形成字线结构。该方法在形成字线结构时，需要在隔离区10和有源区20上刻蚀字线沟槽，然后在字线沟槽内制备字线隔离层和字线，工艺步骤繁琐，因此成本较高且加工效率难以提升。另一方面，通过ISSG工艺形成的字线隔离层31常会出现厚度不均匀的问题，作为晶体管的栅绝缘层时易导致漏电，从而影响半导体器件的性能。
基于此，本公开提供一种半导体器件的制备方法，参考图3，为本公开实施方式的半导体器件的制备方法流程图，该制备方法包括：
步骤S100，提供一衬底1，在衬底1上形成浅沟槽隔离结构101和有源区20，浅沟槽隔离结构101内填充绝缘材料102形成隔离区10；
步骤S200，采用离子掺杂技术在有源区20的内部形成第一隔离层330，第一隔离层330内部包围部分有源区；
步骤S300，对第一隔离层330内包围的有源区进行离子注入，以形成第一字线结构310；
步骤S400，在浅沟槽隔离结构101内形成第二字线结构320，使第一字线结构310和第二字线结构320连接形成沿衬底1表面延伸的埋入式字线结构。
该制备方法在形成有源区20部分的字线结构时，采用离子掺杂技术在硅衬底1有源区20的内部直接形成第一隔离层330，第一隔离层330包裹的有源区再通过离子注入形成具有导体特性的第一字线结构310，由此完成有源区20的字线制备。然后在浅沟槽隔离结构内形成第二字线结构320，由此完成隔离区10的字线制备。该方法不需要在有源区20刻蚀字线沟槽就可以形成该部分的字线隔离层，而且通过离子掺杂技术形成的字线隔离层厚度均匀，当该部分字线复用为晶体管栅极时，该字线隔离层作为栅绝缘层，其绝缘性能良好，不易漏电，能够保证良好的半导体器件的性能。同时本方法利用现有的衬底材料通过离子注入就可以制备出有源区的字线，无需沉积字线金属材料，也简化了有源区的字线制备方法。
下面参考图4-图16，对本公开实施方式的制备方法逐步进行详细说明：
步骤S100，提供一衬底1，参考图4和图5，图4为衬底的俯视结构示意图，图5为图4中局部结构在A-A向的截面示意图。如图所示，在衬底1上形成浅沟槽隔离结构101，浅沟槽隔离结构101在衬底1中定义出多个有源区20，在浅沟槽隔离结构101内填充绝缘材料102形成隔离区10。
衬底1为半导体衬底，衬底1的形成材料包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，半导体衬底为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。在本申请实施方式中，衬底1优选采用低掺杂的单晶硅材料(如NTD-Si)，该衬底材料电阻率均匀性好，后续掺杂时的精度高，引入的杂质少，能够避免常规掺杂时的杂质条纹。
浅沟槽隔离结构101通过浅槽隔离(Shallow Trench Isolation，STI)技术在半导体衬底1上形成。具体而言，可以先在衬底1上沉积一层氮化硅层，然后图案化此氮化硅层形成硬掩膜。接着蚀刻衬底1，形成陡峭的浅沟槽隔离结构101。最后，在浅沟槽隔离结构101内填入绝缘材料102形成隔离区10。填充的绝缘材料102可为氮化硅或氧化硅等。
有源区20的形状由隔离区10的形状所定义，图4所示的平行四边形的有源区20仅为一种示意，其形状还可以为矩形、椭圆形等其他形状，在实际的产品结构中，由于浅沟槽隔离结构101刻蚀工艺精度的影响，也可能形成不规则的边缘。本申请不对隔离区10和有源区20的形状进行特殊限定。
步骤S200，采用离子掺杂技术在有源区20的内部形成第一隔离层330，第一隔离层330包围部分有源区。
本步骤中采用离子掺杂技术形成第一隔离层330包括两个工艺步骤：1)含氧离子注入，采用注氧机向有源区内部注入含氧离子，用以在硅表层下产生一个高浓度的注氧层。2)高温退火，使注入的含氧离子与硅反应形成绝缘的二氧化硅隔离层。其中，含氧离子可以是O +、O 2 +、HO +、H 2O +等。在一些实施方式中，含氧离子中还可以进一步包含氮离子，如N +、N 2 +等，由此还可以形成二氧化硅和氮化硅的混合绝缘埋层。由该方 法形成的隔离层厚度均匀，用作栅隔离层时能够起到良好稳定的绝缘效果，不易发生漏电。
在本示例性实施方式中，为了在有源区20形成如图2所示的沟槽状的第一隔离层31，本步骤可以分为两步进行，先制备第一隔离层的底部331，然后制备第一隔离层的侧壁332。具体地，步骤S200可以包含以下子步骤：
步骤S210，在衬底1上形成具有第一开口510的第一掩模层51。参考图7，为包括第一掩模层51的半导体器件的截面示意图。第一掩模层51的第一开口510与要形成的第一隔离层的底部331形状一致，且第一开口510正好位于要形成的第一隔离层底部331的正上方，而衬底1其他地方都被第一掩模层51覆盖。也就是说，第一开口510在衬底1的投影与最终形成的底部331结构的投影应当能够重合，第一掩模层51的材料可以是光刻胶，可以通过涂覆、曝光显影技术在衬底1上形成。第一掩模层51也可以是硬掩模层，如氮化硅、硼磷硅玻璃等。硬掩模的形成方法可以是化学气相沉积(CVD)、物理气相沉积(PVD)等沉积工艺。
步骤S220，继续参考图7，通过第一开口510向有源区20的内部注入含氧离子，去除第一掩模层51，退火形成第一隔离层330的底部331。
在该步骤中，需要根据要形成的第一隔离层330的位置和绝缘性能设定含氧离子的注入能量。注入能量越大形成的二氧化硅埋层位置越深，反之位置越浅。当然，注入能量与深度之间并非线性关系，需要根据要形成的半导体器件的结构和性能进行合理的选择。在本实施方式中，控制该步骤注入的含氧离子的能量始终保持一恒定值，使得含氧离子都被注入到同一深度，由此可以形成水平的二氧化硅埋层，即形成如图所示的第一隔离层底部331结构。由于该步骤注入的能量始终为一恒定值，因此可以简化离子注入的参数设置。需要说明的是，水平的底部331结构仅为一种理想的示意性的描述，在离子注入的实际过程中，离子会不可避免的发生一定的扩散，例如边缘的离子会有向外扩散的趋势，形成等二氧化硅埋层并非为完全标准的水平埋层。
在该步骤中，第一掩模层51的材料时光刻胶时，可以直接剥离去除。当第一掩模层51为硬掩模时，去除方法可以是干法刻蚀。图6示出了形 成第一隔离层底部并去除第一掩模层后的半导体器件的俯视图，可以理解的是，图7可以看做是图6半导体器件在去除第一掩模层之前局部在A-A向的截面示意图。
在该步骤中，退火的温度、时间、气氛等参数可以根据器件的实际情况进行设置。例如退火的温度可以为800-1500℃，退火时间可以为1-24小时，退火气氛可以为Ar与O 2或N 2与O 2的混合气体。
步骤S230，在衬底1上形成具有第二开口520的第二掩模层52。参考图9，为包括第二掩模层52的半导体器件的截面示意图。第二掩模层52的第二开口520正好位于要形成的第一隔离层330的侧壁332正上方，而衬底1其他地方都被第二掩模层52覆盖。也就是说，第二开口520在衬底1的投影与最终形成的第一隔离层330侧壁332的投影应当能够重合。第二掩模层52的材料和形成工艺可以参照第一掩模层51，二者可以相同也可以不同。
由于该步骤第一隔离层330的侧壁332尺寸非常小，对第二掩模层52的精度要求极高，因此可通过极紫外光光刻的方法制备。
步骤S240，通过第二开口520向有源区20的内部再注入含氧离子，去除第二掩模层52，退火形成第一隔离层330的侧壁332，第一隔离层底部331和第一隔离层侧壁332构成第一隔离层330。
为了形成竖向侧壁，该步骤注入的含氧离子应当竖直分布在衬底1中，且位于步骤S220中形成的底部331结构的边缘正上方，该竖向侧壁332与底部331埋层的边缘相连，二者形成一个整体。如前所示，含氧离子的注入能量决定其注入深度，在本实施方式中，作为一种优选方式，通过第二开口520注入含氧离子的过程中，控制本步骤注入的含氧离子的能量由大到小逐渐减小，使得含氧离子由深至浅逐步被注入到衬底1内且沿衬底1竖直方向分布；同时控制注入过程中含氧离子浓度基本保持一致，以使竖向各个位置处的含氧离子分布均匀，退火后形成的竖向的二氧化硅侧壁厚度均匀，且侧壁各处性能基本一致。进一步的，本步骤注入的含氧离子的最大能量等于通过第一开口510注入的含氧离子的能量，这样可以确保用于形成侧壁332的含氧离子注入深度与底部331一致，最终形成的竖直方向的第一隔离层侧壁可以与水平方向的第一隔 离层底部相连，形成完整的第一隔离层结构。需要说明的是，竖直的侧壁332仅为一种理想的示意性的描述，在离子注入的实际过程中，离子会不可避免的发生一定的扩散，例如边缘的离子会有向外扩散的趋势，形成等二氧化硅埋层并非为完全标准的沿厚度方向分布的埋层。
在该步骤中，第二掩模层52的去除方法参照第一掩模层51，退火的温度、时间、气氛等参数可以根据器件的实际情况进行设置。图8示出了去除第二掩模层后的半导体器件的俯视图，可以理解的是，图9可以看做是图8半导体器件在去除第二掩模层之前局部在A-A向的截面示意图。
经过上述步骤S210-S240，即完成了有源区20的第一隔离层330的制备，得到的半导体器件的俯视图如图8所示。该制备方法不需要对有源区20进行刻蚀，也不需要沉积隔离层，而是通过离子掺杂技术一步就完成了隔离层的制备，大大简化了制备工艺。
步骤S300，对第一隔离层330内包围的有源区进行离子注入，以形成位于有源区20的第一字线结构310。该步骤形成的第一字线结构310可以参考图10和图11，图10为形成第一字线结构310后的半导体器件的俯视图，图11为图10中局部在A-A向的截面示意图。本步骤注入的离子种类可以为P离子、N离子、B离子等离子或以上多种离子的组合，具体的离子种类可根据拟制备的半导体器件性能进行选择。
本步骤中，注入的离子类型根据衬底和晶体管类型决定。由于第一隔离层330内包围的为衬底硅，即低掺杂的单晶硅(如NTD-Si)，因此掺杂精度高，引入杂质少，能够避免常规掺杂时的杂质条纹，使掺杂后的材料能够达到栅极所需的功函数，电阻率能够匹配阈值电压。需要说明的是，在进行离子注入时，也需要形成离子注入窗口，即可以采用与步骤S200中类似的光刻胶通过曝光显影的方式形成，具体过程此处不再赘述。。
步骤S400，参考图10～图17，在浅沟槽隔离结构内形成第二字线结构。
本步骤中，第二字线结构可以通过以下步骤制备：
步骤S410，去除浅沟槽隔离结构内的部分绝缘材料，形成第一沟槽 结构41。具体而言，可以通过刻蚀的方法去除浅沟槽隔离结构内的部分绝缘材料102，控制刻蚀深度，保留覆盖浅沟槽隔离结构101内壁的绝缘材料，这部分绝缘材料形成第二隔离层340。刻蚀可以是干法刻蚀。第二隔离层340的厚度可以根据需求设置。图12示出了形成第二隔离层340后的半导体器件的俯视图，图13为图12中局部在A-A向的截面示意图。该步骤中利用已经填充在浅沟槽隔离结构内的绝缘材料制备第二隔离层，简便易行。
步骤S420，在第一沟槽结构41内填充硅薄膜40，对第一沟槽结构41内的硅薄膜40进行离子注入，形成第二字线结构。图14示出了在第一沟槽结构41内填充硅薄膜40后的半导体器件的俯视图，图15为图14中局部在A-A向的截面示意图。填充的硅薄膜40位于第二隔离层340内，对第二隔离层340内的硅薄膜40进行离子注入，以形成位于隔离区10的第二字线结构320。该步骤形成的第二字线结构320可以参考图16和图17，图16为形成第二字线结构320后的半导体器件的俯视图，图17为图16中局部在A-A向的截面示意图。
该步骤中，填充的硅可以为多晶硅薄膜，通过化学气相沉积等方式生长。多晶硅生长方式简单，且离子注入后同样能够得到理想的电阻特性，该步骤的离子注入的方法参照步骤S300。
进一步地，由于第一字线结构和第二字线结构要连接形成沿衬底表面延伸的埋入式字线结构，所以对第一隔离层330包围的有源区进行离子注入和对第一沟槽结构内硅薄膜40进行离子注入时，控制离子注入参数，以使形成的第一字线结构和第二字线结构的电阻率的差值在一定阈值范围内，该阈值范围可以尽可能的小，以使第一字线结构310和第二字线结构320的电阻率尽可能相近或相等，从而使得最终形成的字线性能稳定一致。注入参数包括但不限于离子类型、离子浓度和注入能量等。
在一种实施例中，由于上述步骤S300和步骤S400中都包含对硅进行注入的步骤，为了简化工艺，这两个步骤还可以同时进行，即在第一隔离层330制备好后，直接形成第二隔离层340，然后再同时对第一隔离层330内的单晶硅和第二隔离层340内的多晶硅进行离子注入，同时形成第一字线结构310和第二字线结构320。需要说明的是，同时注入 时针对两个区域的工艺参数是相同的，而有源区的硅材和第一沟槽结构内填充的硅材不一定完全一样，应当能确保形成的第一字线结构310和第二字线结构320的电阻率尽可能相近或相等，以保证形成的字线性能稳定一致。
经过上述步骤，最终形成的第一字线结构310和第二字线结构320连接形成沿衬底1表面延伸的埋入式字线结构，如图16所示。
进一步的，本实施方式的半导体器件的制备方法还可以包括：
步骤S600，对第一字线结构310和第二字线结构320进行刻蚀，以得到第二沟槽，如图18所示。
进一步地，本实施方式的半导体器件的制备方法还可以包括：
步骤S700，在第二隔离层340两侧进行掺杂形成源极和漏极，如图19所示。
进一步地，本实施方式的半导体器件的制备方法还可以包括：
步骤S800，如图20所示，在第二沟槽内形成覆盖层6，用以对字线进行保护。覆盖层6还可以覆盖在有源区20上，以对有源区20进行保护。覆盖层6的材料可包括氮化硅、氧化硅、氮氧化硅或其他绝缘材料中的一种或者多种的组合。
需要说明的是，上述步骤编号并非对实施步骤的限定，本领域技术人员完全可以根据本申请的思路改变实施顺序。例如，在一种实施方式中，也可以先制备第二隔离层340和第二字线结构320，再制备第一隔离层330和第一字线结构310。再例如，可以先制备源漏极，再刻蚀第二沟槽并形成覆盖层6。
上述制备方法是以图1和图2所示一个有源区设置两个晶体管为例进行了说明，本领域技术人员可以理解，当有源区只设置一个晶体管时，完全可以按照相同的思路制备埋入式字线，具体过程此处不再赘述
本实施方式的制备方法制备出的半导体器件的有源区的埋入式字线隔离层厚度均匀，复用为晶体管栅极时不易漏电，保证了半导体器件的良好性能。该半导体器件可以用于动态随机存储器等多种存储产品中，本申请不限制其具体应用领域。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标 的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

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  1. 一种半导体器件的制备方法，其中，包括：
    提供一衬底，在所述衬底上形成浅沟槽隔离结构和有源区，所述浅沟槽隔离结构内填充有绝缘材料；
    采用离子掺杂技术在所述有源区内形成第一隔离层，所述第一隔离层包围部分所述有源区；
    对所述第一隔离层包围的所述有源区进行离子注入，形成第一字线结构；
    在所述浅沟槽隔离结构内形成第二字线结构，使所述第一字线结构和所述第二字线结构连接形成沿所述衬底表面延伸的埋入式字线结构。
  2. 根据权利要求1所述的半导体器件的制备方法，其中，所述采用离子掺杂技术在所述有源区内形成第一隔离层包括：
    采用注氧机向所述有源区内部注入含氧离子；
    对所述衬底进行退火，使所述含氧离子与有源区的材料反应生成绝缘的氧化物，以形成所述第一隔离层。
  3. 根据权利要求2所述的半导体器件的制备方法，其中，所述采用离子掺杂技术在所述有源区内形成第一隔离层包括：
    在所述衬底上形成具有第一开口的第一掩模层；
    通过所述第一开口向所述有源区的内部注入氧离子，去除所述第一掩模层，退火形成所述第一隔离层底部；
    在所述衬底上形成具有第二开口的第二掩模层；
    通过所述第二开口向所述有源区的内部注入氧离子，去除所述第二掩模层，退火形成所述第一隔离层侧壁，所述第一隔离层底部和所述第一隔离层侧壁构成所述第一隔离层。
  4. 根据权利要求3所述的半导体器件的制备方法，其中，通过所述第一开口注入含氧离子的过程中，控制注入的所述含氧离子的能量始终保持一恒定值。
  5. 根据权利要求4所述的半导体器件的制备方法，其中，通过所述第二开口注入含氧离子的过程中，控制注入的所述含氧离子的能量由大到小逐渐减小，以使所述含氧离子沿所述衬底竖直方向分布。
  6. 根据权利要求5所述的半导体器件的制备方法，其中，通过所述第二开口注入的所述含氧离子的最大能量等于通过所述第一开口注入的所述含氧离子的能量。
  7. 根据权利要求1中任一项所述的半导体器件的制备方法，其中，所述在所述浅沟槽隔离结构内形成第二字线结构包括：
    去除所述浅沟槽隔离结构内的部分所述绝缘材料，形成第一沟槽结构；
    在所述第一沟槽结构内填充硅薄膜，对所述第一沟槽结构内的硅薄膜进行离子注入，形成所述第二字线结构。
  8. 根据权利要求7所述的半导体器件的制备方法，其中，去除所述浅沟槽隔离结构内的部分所述绝缘材料后，所述浅沟槽隔离结构内剩余的所述绝缘材料形成第二隔离层。
  9. 根据权利要求7所述的半导体器件的制备方法，其中，所述衬底材料为低掺杂的单晶硅材料，所述第一沟槽结构内填充的硅薄膜为多晶硅材料。
  10. 根据权利要求7所述的半导体器件的制备方法，其中，对所述第一隔离层包围的有源区进行离子注入和对所述第一沟槽结构内的硅薄膜进行离子注入时，控制离子注入参数，以使形成的所述第一字线结构和第二字线结构的电阻率的差值在一定阈值范围内。
  11. 根据权利要求1所述的半导体器件的制备方法，其中，在形成所述第二字线结构后，对所述第一字线结构和所述第二字线结构进行刻蚀，形成第二沟槽，沉积覆盖层于所述第二沟槽上。
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