WO2022048231A1 - 随机数产生电路 - Google Patents

随机数产生电路 Download PDF

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Publication number
WO2022048231A1
WO2022048231A1 PCT/CN2021/099839 CN2021099839W WO2022048231A1 WO 2022048231 A1 WO2022048231 A1 WO 2022048231A1 CN 2021099839 W CN2021099839 W CN 2021099839W WO 2022048231 A1 WO2022048231 A1 WO 2022048231A1
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Prior art keywords
random number
generating circuit
control signal
random
bit position
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English (en)
French (fr)
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范习安
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/438,433 priority Critical patent/US20230062156A1/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, a random number generating circuit.
  • the encryption module in order to improve its security performance, it is necessary to provide a random number with good randomness as a seed, so as to form a pseudo-random number sequence.
  • the randomness of the random numbers generated by the current random number generating circuit still needs to be improved.
  • the random number generating circuit realizes and improves the randomness of the random number.
  • An embodiment of the present disclosure provides a random number generating circuit, including: a random number generator configured to output several first random numbers in each rollover period; a control signal generating module configured to receive a trigger signal , and output a control signal corresponding to the different first random numbers based on the trigger signal; the multi-selection module is configured to receive the first random number and the control signal corresponding to the first random number signal, adjust at least one bit position of the first random number based on the control signal, obtain a second random number, and output several second random numbers.
  • the random number generator is an n-bit random number generator, and the several first random numbers are 2 n -1 first random numbers; the random number generator has nth An output terminal, and each of the first output terminals has a fixed bit position, and n is an integer greater than 1.
  • the multiple selection module includes: a chip selection input terminal for receiving the control signal; a data input terminal connected to the n first output terminals for receiving the first random number ;
  • the multi-selection module has N different bit position adjustment modes, and each of the bit position adjustment modes corresponds to one of the control signals, wherein N is an integer greater than 1; the multi-selection module is also configured as , and adjust the bit positions of the data of the n first output terminals to obtain the second random number.
  • the multi-selection module includes: N adjustment units, each of the adjustment circuits defines a bit position adjustment mode; each of the adjustment units has the data input terminal, and each Each of the adjustment units has the chip select input terminal.
  • the bit position arrangement of the data of the n first output terminals is a first bit position arrangement
  • each of the adjustment units has n second output terminals
  • the data of the n second output terminals are arranged in bit positions.
  • the bit position arrangement is a second bit position arrangement; each of the second bit position arrangements is different, and the second bit position arrangement is different from the first bit position arrangement.
  • the N adjustment units are configured such that, in the N second bit position arrangements, the position of the second output terminal corresponding to the data of one bit is different, and the data of the remaining bits corresponds to the position of the second output terminal. The positional arrangement of the second output end remains unchanged.
  • At least one of the second bit position arrangements is the same as the first bit position arrangements.
  • the N is greater than or equal to n.
  • control signal generation module includes: an m-bit counter; wherein the relationship between N and m satisfies: N ⁇ 2 m ⁇ 1, m is any natural number, and N is any natural number greater than or equal to 2.
  • control signal generation module is further configured such that the different first random numbers are the first random numbers in different rollover periods; in the same rollover period The control signal remains unchanged; the control signal corresponding to one rollover period is different from the control signal corresponding to the adjacent rollover period.
  • the random number generator is further configured to output a rollover signal after completing each rollover period; the control signal generating module receives the rollover signal as the trigger signal.
  • control signal generation module is further configured such that the different first random numbers include the first random numbers in each of the rollover periods, and within the same rollover period , the control signals corresponding to different first random numbers are different.
  • the random number generator is further configured to receive a driving clock signal to generate the first random number; the control signal generating module is further configured to receive the driving clock signal as the trigger Signal.
  • control signal generating module includes: an M-bit pseudo-random number generating circuit, and the pseudo-random number generating circuit and the random number generator receive the same driving clock signal.
  • the random number generator includes a linear feedback shift register.
  • Embodiments of the present disclosure provide a random number generating circuit with superior structural performance, including a random number generator, a control signal generating module, and a multi-selection module.
  • the random number generator outputs a number of first random numbers
  • the control signal generating module is directed to the multi-selection
  • the module provides control signals corresponding to different first random numbers, and the multi-selection module adjusts at least one bit position of the first random number after receiving the control signal, and obtains a second random number, which is compared with the first random number. It has better randomness, thereby improving the randomness of random numbers generated by the random number generating circuit.
  • the multi-selection module has N different bit position adjustment methods, so there are N kinds of bit position adjustment methods for the first random number. Based on the first random number with one random sequence, N kinds of random sequences can be generated. The second random number further increases the random sequence of random numbers and further improves the randomness of random numbers.
  • Figure 1 is a schematic diagram of seven different circuit structures
  • FIG. 2 is a functional block diagram of a random number generating circuit provided by an embodiment of the present disclosure
  • FIG. 3 is a functional block diagram of a random number generating circuit provided by another embodiment of the present disclosure.
  • Fig. 4 is the circuit structure schematic diagram of the random number generator in Fig. 3;
  • Fig. 5 is the structural representation of the multi-selection module in Fig. 4;
  • Fig. 6 is a kind of structural representation of the control signal generation module in Fig. 4;
  • Fig. 7 is another kind of structural schematic diagram of the control signal generation module in Fig. 4;
  • FIG. 8 is another schematic structural diagram of the control signal generating module in FIG. 4 .
  • each random number generating circuit needs to be set up, and each random number generating circuit has a different tap position. For example, for a 7-bit LFSR, there are 7 different tap positions, then Seven LFSRs with different tap positions are designed to realize seven random sequences, each of which can generate 2 7 -1 random numbers to increase the randomness of random numbers.
  • FIG. 1 is a schematic diagram of seven different circuit structures. As shown in Figure 1, the seven different circuit diagrams marked 1-7 have different corresponding tap positions.
  • the random number generating circuit includes: seven series-connected flip-flops 10.
  • the device 10 is a D flip-flop, and the output of the previous stage flip-flop 10 is used as the input of the subsequent stage flip-flop 10, and each flip-flop 10 receives the driving clock signal clk; the XOR gate 11, the two inputs of the XOR gate 11 The terminals are respectively connected with the input terminal and the output terminal of a flip-flop 10, and the output terminal of the XOR gate 11 is used as the input terminal of another flip-flop 10; the position of the XOR gate 11 determines the tap position of the random number generating circuit; From left to right, the flip-flops 10 are referred to as the zeroth stage/first stage...the sixth stage flip-flop 10, and the output of each flip-flop 10 is correspondingly D[0]D[1]...D[6].
  • the random number generating circuit generates the random number of the first random sequence: the tap position is the zeroth level flip-flop 10, and the output of the random number generating circuit is arranged in order of D[0 ]D[6]D[5]D[4]D[3]D[2]D[1].
  • the random number generating circuit generates random numbers of the second random sequence: the tap position is the first-level flip-flop 10, and the output of the random number generating circuit is arranged in order of D[1 ]D[0]D[6]D[5]D[4]D[3]D[2].
  • the random number generating circuit generates a random number of the third random sequence: the tap position is the second-level flip-flop 10, and the output of the random number generating circuit is arranged in order of D[2 ]D[1]D[0]D[6]D[5]D[4]D[3].
  • the random number generating circuit generates random numbers of the fourth random sequence: the tap position is the third-level register 10, and the output of the random number generating circuit is arranged according to the level of the bits as D[3] D[2]D[1]D[0]D[6]D[5]D[4].
  • the random number generating circuit generates random numbers of the fifth random sequence: the tap position is the fourth level register 10, and the output of the random number generating circuit is arranged in order of D[4] D[3]D[2]D[1]D[0]D[6]D[5].
  • the random number generating circuit generates random numbers of the sixth random sequence: the tap position is the fifth-level register 10, and the output of the random number generating circuit is arranged in order of D[5] D[4]D[3]D[2]D[1]D[0]D[6].
  • the random number generating circuit generates random numbers of the seventh random sequence: the tap position is the sixth-level register 10, and the output of the random number generating circuit is arranged according to the level of the bits as D[6] D[5]D[4]D[3]D[2]D[1]D[0].
  • An embodiment of the present disclosure provides a random number generating circuit, including a random number generator, a control signal generating module, and a multiple selection module, where the multiple selection module can be used to reorder the bit positions of the first random number generated by the random number generator , thereby increasing the random sequence of random numbers generated by the random number generating circuit and improving the randomness of the random numbers.
  • FIG. 2 is a functional block diagram of a random number generating circuit according to an embodiment of the present disclosure.
  • the random number generating circuit includes: a random number generator 101, configured to output several first random numbers in each rollover period; a control signal generating module 102, configured to: receiving the trigger signal CLK2, and outputting control signals Sel corresponding to different first random numbers based on the trigger signal CLK2; the multi-selection module 103 is configured to receive the first random number and the control signal Sel corresponding to the first random number, Adjust at least one bit position of the first random number based on the control signal Sel, obtain a second random number, and output several second random numbers.
  • the random number generator 101 is an n-bit random number generator.
  • the several first random numbers are 2 n ⁇ 1 first random numbers; the random number generator 101 receives the driving clock signal CLK1 to generate the first random numbers.
  • the period in which the random number generator 101 generates all different first random numbers is the rollover period.
  • the random number generator 101 has n first output terminals, and each of the first output terminals has a fixed bit position, where n is an integer greater than 1, such as 4, 7, 10, and so on.
  • the random number generator 101 can be a linear feedback shift register, and includes n flip-flops connected in series, the output of each flip-flop is one of the n first output terminals, and the output of each flip-flop is located at the The bit positions are different.
  • each first output terminal (that is, The output terminals of each flip-flop), and the arrangement of the bit positions of the first output terminals from high to low can be D[0], D[n-1], D[n-2], D[n-3 ]...
  • the order of D[2], D[1], n is greater than 3.
  • the random number generator 101 may generate a first random number of a random sequence, that is, the random number generator 101 may be a linear shift register with fixed tap positions. It can be understood that, in other embodiments, the random number generator can also generate the first random number with multiple random sequences.
  • the control signal generating module 102 has a trigger terminal 112 for receiving the trigger signal CLK2, and also has a signal output terminal 122 for outputting the control signal Sel.
  • the trigger signal CLK2 is associated with the random number generator 101 . In this way, the synchronization of the change of the control signal Sel when the first random number changes can be improved.
  • control signal generating module 102 may be configured such that different first random numbers are first random numbers in different rollover periods; in the same rollover period, the control signal Sel remains unchanged; a count The control signal Sel corresponding to the full cycle is different from the control signal Sel corresponding to the adjacent full cycle.
  • the multi-selection module 103 adjusts the bit positions of several first random numbers in the same rollover period in the same way, that is, the method for obtaining the second random number based on the first random number is the same, which is beneficial to Reduce circuit complexity.
  • the trigger signal CLK2 may be a trigger driving clock signal, and the clock period of the trigger driving clock signal is the same as the rollover period.
  • the trigger signal CLK2 can also be provided by the output of the random number generator 101 , that is, the random number generator 101 outputs a rollover signal after completing one rollover period, and the control signal generation module 102 receives the rollover signal as a trigger signal.
  • control signal generating module 102 may be configured such that the different first random numbers include the first random numbers in each rollover period, and within the same rollover period, the different first random numbers correspond to The control signal Sel is different.
  • the multiple selection module 103 can also adjust the bit position of each first random number in the same rollover period in different ways, which is beneficial to further increase the second Randomness of random numbers. More specifically, since the control signals Sel in the same rollover period are also different, the randomness of the first random numbers of different rollover periods can be increased, and the randomness of the first random numbers of the same rollover period can also be increased. .
  • the random number generator 101 receives the driving clock signal CLK1 to generate a first random number, and the control signal generating module 102 receives the driving clock signal CLK1 as the trigger signal CLK2.
  • the multiple selection module 103 includes: a chip selection input terminal 113 for receiving the control signal Sel; a data input terminal connected to the n first output terminals for receiving the first random number; the multiple selection module 103 has N different bit position adjustment modes, and each bit position adjustment mode corresponds to a control signal, where N is an integer greater than 1; the multi-selection module 103 is further configured to: adjust the bit positions of the n first output terminals , to get the second random number.
  • the multiple selection module 103 includes a data output terminal OUT[n-1:0], and outputs an n-bit second random number.
  • the random sequence of the second random number output by the multiple selection module 103 is increased by N times.
  • control signal generating module 102 can be reasonably set according to N to ensure that the type of the generated control signal Sel meets the requirements.
  • N is greater than or equal to n, which is beneficial to increase the random sequence of the second random number.
  • the bit positions of the data of the n first output terminals are arranged as the first bit position, and the data output by the output terminal of the multi-selection module 103 may have N second bit positions, and each second bit position is arranged based on A bit position adjustment method is obtained after adjusting the first bit position.
  • At least one second bit position arrangement is the same as the first bit position arrangement. It should also be noted that, in other embodiments, N may also be 1.
  • the multi-selection module 103 may also be configured to: for each of the N second bit position arrangements, the positions of the outputs of the multi-selection module 103 corresponding to one bit of data are different , while the positional arrangement of the output terminals of the multi-selection module 103 corresponding to the data of the remaining bits remains unchanged.
  • the first bit position is arranged as D[0], D[n-1], D[n-2]....D[3], D[2], D[1 ];
  • the arrangement of the second bit position includes a variety of arrangements in Table 1.
  • the position of the output end of the multiple selection module 103 corresponding to the data of at least two bits may also be different.
  • the bits of the data corresponding to each first output terminal can change, and there are C n n-1 changes in total according to different permutations and combinations, that is, N and n satisfy: N ⁇ C n n-1 , that is, N ⁇ n ⁇ (n-1) ⁇ (n-2)...2 ⁇ 1.
  • N may be the same as n.
  • N may also be smaller than n.
  • the random number generator 101 outputs a binary first random number
  • the corresponding multi-selection module 103 outputs a binary second random number
  • the multi-selection module 103 can reorder the bits of the first random number, more random sequences are generated, and the randomness of the random number of the random number generating circuit is improved.
  • the circuit structure of this embodiment is simpler and the power consumption is lower.
  • Another embodiment of the present disclosure further provides a random number generating circuit, which is substantially the same as that of the foregoing embodiment, and the main differences include a more detailed description of each module.
  • the random number generating circuit provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as the foregoing embodiments, reference may be made to the foregoing embodiments, which will not be described in detail below.
  • FIG. 3 is a functional block diagram of a random number generating circuit provided by another embodiment of the present disclosure.
  • the random number generating circuit includes: an n-ibt random number generator 201 having n first output terminals 211 ; a control signal generating module 202 ; a multi-selection module 203 , which has Chip select input terminal and data input terminal, the multi-select module 203 has a data output terminal OUT[n-1:0].
  • the multiple selection module 203 includes: N adjustment units 204, each adjustment unit 204 defines a bit position adjustment method; and each adjustment unit 204 has a data input terminal, and each adjustment unit 204 has a chip select input terminal. Each adjustment unit 204 is configured to receive the control signal Sel, and the adjustment unit 204 corresponding to the control signal Sel outputs a second random number.
  • each adjustment unit 204 is the data output terminal OUT[n-1:0] of the multi-select module 203, and the control signal Sel is used as the chip selection signal of the adjustment unit 204, and the corresponding chip selection signal is selected based on the control signal Sel
  • the output terminal of the adjustment unit 204 is used as the data output terminal OUT[n-1:0] of the multi-select module 203 .
  • each of the n first output terminals 211 is marked as D[n-1], D[n-2]....D[3], D[ 2], D[1], D[0].
  • the bit position arrangement of the data of the n first output terminals 211 is the first bit position arrangement, for example, D[0]D[n-1]D[n-2]....D[3]D[2]D[ 1].
  • Each adjustment unit 204 has n second output terminals 214, and the bit positions of the data of the n second output terminals 214 are arranged in the second bit position arrangement, the second bit position arrangements are different, and the second bit position arrangement Different from the first bit position arrangement, for example, the second bit position arrangement can be D[n-1]D[n-2]....D[3]D[2]D[1]D[0], etc.
  • the number of adjustment units 204 is the same as the number of bits of the first random number of the random number generator 201 , that is, N and n are the same. In other embodiments, the number of adjustment units may be greater or less than the number of bits of the random number generator.
  • FIG. 4 is a schematic diagram of the circuit structure of the random number generator 201 provided in this embodiment.
  • the random number generator 201 is a linear shift register, including: n flip-flops 211 , an XOR gate 231 , an input terminal and an output terminal of a flip-flop 211 as two input terminals of the XOR gate 231 , and The output terminal of the XOR gate 231 is connected to the input terminal of another flip-flop 211 .
  • the position of the XOR gate 231 defines the tap position of the random number generator 201, and the output terminal of each flip-flop 211 serves as a first output terminal 211 (refer to FIG. 3).
  • the flip-flops 211 are sequentially recorded as the zeroth-level flip-flop, the first-level flip-flop, the second-level flip-flop...the n-1th-level flip-flop.
  • the random number generator 201 takes the random number generator 201 as a 7-bit random number generator and a binary 7-bit random number generator as an example for detailed description, 127 first random numbers are generated in one rollover period. .
  • the random number generator 201 has 7 flip-flops 211, and the position of the XOR gate 231 determines the bit position arrangement of the data of the n first output terminals 211.
  • the 7 first outputs The bit positions of the data of the terminal 211 are arranged as D[0]D[6]D[5]D[4]D[3]D[2]D[1].
  • the input terminal and the output terminal of the XOR gate 231 may also be connected to other flip-flops correspondingly.
  • FIG. 5 is a schematic structural diagram of the multi-selection module 203 provided in this embodiment, including seven adjustment units 204 (refer to FIG. 3 ). The n first output terminals 211 are used as the input terminals of each adjustment unit 204. For the sake of simplicity of illustration, the input terminals of each adjustment unit 204 in FIG. 5 are replaced by 0 for D[0] and 1 for D[1 ], and so on, and the second output terminal 214 replaces D[0] with 0, and so on. It should be noted that the data marked as D[0] is the data of the zeroth first output terminal 211, the data marked as D[1] is the data of the first first output terminal 211, and so on.
  • different adjustment units 204 are marked with 20/21/22/23/24/25/26.
  • the arrangement of the second output terminals of each adjustment unit 204 is different.
  • the second output terminal of the adjustment unit 204 marked as 20 outputs
  • the data output by the second output terminal of the adjustment unit 204 marked as 21 is D[ 1]D[0]D[6]D[5]D[4]D[3]D[2].
  • the random number generator 201 has a fixed tap position
  • the multi-selection module 203 is applied to simulate random numbers generated by adjusting the tap positions of the random number generator 201 .
  • the multiple selection module 203 has n different adjustment units 204 .
  • the adjustment unit 204 marked as 21 is used to simulate the LFSR whose tap position of the random number generator 201 in FIG. 4 is at the zeroth stage flip-flop
  • the adjustment unit 204 marked as 22 is used to simulate the tap in FIG. 4
  • the adjustment unit 204 marked as 23 is used to simulate the LFSR of the flip-flop of the second stage in FIG. 4 , and so on.
  • the random number generator 201 is a 7-bit random number generator as an example.
  • the random number generator may also be a random number generator of any bit, such as 3-bit, 4-bit, 10-bit, 20-bit and so on.
  • control signal generating module 202 includes: an m-bit counter 212; wherein, the relationship between N and m satisfies: N ⁇ 2 m ⁇ 1, m is any natural number, and N is any natural number greater than or equal to 2. Specifically, results where m is greater than or equal to lgN/lg2+1 are rounded down. For example, when N is 7, m is greater than or equal to 3.
  • the m-bit counter 212 includes m flip-flops 222; the trigger signal CLK2 is used as the clock input signal of the flip-flop 222 of the first stage, and the output end of the flip-flop 222 of the previous stage is used as the next flip-flop 222
  • the clock input signal of 222, the output terminals of the m flip-flops 222 jointly output the control signal Sel.
  • the counter 212 when N is 7, includes three flip-flops 222, which are respectively marked as DFF#0, DFF#1, and DFF#2.
  • the random number generator 201 is further configured to output a rollover signal after completing each rollover period, and the control signal generating module 202 receives the rollover signal as a trigger signal. In this way, in the same rollover period, the control signal Sel remains unchanged; the control signals Sel corresponding to different rollover periods are different.
  • control signal generation module 202 is a 3-bit counter with three output terminals S0/S1/S2, and the control signal Sel is shown in Table 2:
  • S2 (most significant bit)
  • S1 S0 (lowest bit)
  • the random number generator 201 generates a number of first random numbers, and the control signal Sel remains unchanged at 0, and the adjustment unit 204 marked as 20 in the corresponding multi-selection module 203 is selected, and its first
  • the second output terminal 214 outputs a plurality of second random numbers, and the sequence of the second random numbers is the same as that of the first random numbers.
  • the random number generator 201 After the first full cycle is completed, the random number generator 201 outputs a full signal, which is used as the trigger signal of the counter, S2S1S0 changes from 000 to 001, the control signal Sel changes from 0 to 1, and the corresponding adjustment is marked as 21
  • the unit 204 is selected, and in the second rollover period, the second output terminal of the adjustment unit 203 marked as 21 inputs a plurality of second random numbers, and the order of the second random numbers is different from the order of the first random numbers.
  • control signal Sel output by the counter output terminal is the value corresponding to the previous full cycle + 1, so that the second output terminal of another adjustment unit 203 is selected as the output of the multi-selection module 203. end.
  • the trigger signal of the counter is the same as the driving clock signal of the random number generator 201 .
  • different first random numbers correspond to different control signals Sel, so in each rollover period, different adjustment units 204 can also be called to rearrange the bit positions, thereby further increasing the randomness
  • the randomness of numbers is conducive to generating more random sequences.
  • the working principle of the random number generation circuit is as follows:
  • the random number generator 201 In each rollover period, the random number generator 201 generates the first random number, the control signal Sel output by the counter is 0, and the adjustment unit 204 marked with 20 is selected to generate the second random number; the random number generator 201 generates the first random number; Two random numbers, the control signal Sel output by the counter is 1, and the adjustment unit 204 with the label 21 is selected to generate the second random number; the control signal Sel output by the counter is 2, and the adjustment unit 204 with the label 22 is selected to generate the second random number ; And so on; when the control signal output by the counter is 7, the counter starts counting from 0 again.
  • the number of adjustment units 204 in the multi-selection module 203 may be the same as the number of first random numbers generated in each rollover period, and the counter is set according to the number of adjustment circuits 203 . It should be noted that the aforementioned control signal Sel and the correspondingly selected adjustment unit 204 are only examples, and it is only necessary to ensure that different control signals Sel correspond to different adjustment units 204 selected.
  • control signal generating module 202 may be an M-bit pseudo-random number generating circuit, and the pseudo-random number generating circuit and the random number generator 201 receive the same driving clock signal CLK. Compared with the counter, the control signal output by the pseudo-random number generating circuit is more random, so the adjustment units 204 corresponding to different first random numbers are correspondingly more random.
  • the pseudo-random number generating circuit includes M D flip-flops 232 and a first XOR gate 231.
  • the pseudo-random number generating circuit has output terminals S0/S1/S2, and the signal of the output terminal is used as a control signal.
  • the random number generating circuit provided in this embodiment is based on a random number generator 201 having a fixed random sequence, and can generate random numbers having N different random sequences, which improves the security of using the random number generating circuit.
  • the random number generating circuit provided by the present disclosure has a simple structure and low power consumption, and reorders at least one bit position of several first random numbers output by the random number generator through a multi-selection module to obtain a second random number, thereby increasing the The random sequence of random numbers generated by the random number generating circuit generates more random sequences and improves the randomness of random numbers.

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Abstract

一种随机数产生电路，包括：随机数发生器（101），被配置为，在每一计满周期内输出若干个第一随机数；控制信号生成模块（102），被配置为，接收触发信号（CLK2），并基于触发信号（CLK2）输出与不同的第一随机数对应的控制信号（Sel）；多选模块（103），被配置为，接收第一随机数以及与第一随机数对应的控制信号（Sel），基于控制信号（Sel）对第一随机数的至少一个比特位置进行调整，获取第二随机数，并输出若干第二随机数。

Description

随机数产生电路
本公开要求在2020年09月02日提交中国专利局、申请号为202010911973.6、发明名称为“随机数产生电路”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及但不限于一种随机数产生电路。
背景技术
处于信息时代的今天，关于信息的安全问题成为信息产品很关键的部分，加密模块是否具有良好的安全性能成为目前关注的重点之一。
对于加密模块而言，为了提高其安全性能需要提供具有良好随机性的随机数作为种子，从而形成伪随机数列。然而，目前的随机数产生电路产生的随机数的随机性仍然有待提高。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供的一种随机数产生电路实现了，提高随机数的随机性。本公开实施例提供一种随机数产生电路，包括：随机数发生器，被配置为，在每一计满周期内输出若干个第一随机数；控制信号生成模块，被配置为，接收触发信号，并基于所述触发信号输出与不同的所述第一随机数对应的控制信号；多选模块，被配置为，接收所述第一随机数以及与所述第一随机数对应的所述控制信号，基于所述控制信号对所述第一随机数的至少一个比特位置进行调整，获取第二随机数，并输出若干所述第二随机数。
在一些实施例中，所述随机数发生器为n-bit随机数发生器，所述若干个第一随机数为2 n-1个第一随机数；所述随机数发生器具有n个第一输出端，且每一所述第一输出端具有固定的比特位置，n为大于1的整数。
在一些实施例中，所述多选模块包括：片选输入端，用于接收所述控制信号；数据输入端，与n个所述第一输出端连接，用于接收所述第一随机数；所述多选模块具有N种不同比特位置调整方式，且每一所述比特位置调整方式与一所述控制信号对应，其中，N为大于1的整数；所述多选模块还被配置为，对所述n个第一输出端的数据的比特位置进行调整，以获取所述第二随机数。
在一些实施例中，所述多选模块包括：N个调整单元，每一所述调整电路定义一所述比特位置调整方式；每一所述调整单元均具有所述数据输入端，且每一所述调整单元均具有所述片选输入端。
在一些实施例中，所述n个第一输出端的数据的比特位置排列为第一比特位置排列，每一所述调整单元具有n个第二输出端，所述n个第二输出端的数据的比特位置排列为第二比特位置排列；每一所述第二比特位置排列各不相同，且所述第二比特位置排列与所述第一比特位置排列不同。
在一些实施例中，N个所述调整单元被配置为，N个所述第二比特位置排列中，一个比特位的数据对应的所述第二输出端的位置不同，其余比特位的数据对应的所述第二输出端的位置排列不变。
在一些实施例中，至少一个所述第二比特位置排列与所述第一比特位置排列相同。
在一些实施例中，所述N大于或等于n。
在一些实施例中，所述控制信号生成模块包括：m-bit计数器；其中，N与m的关系满足：N≤2 m-1，m为任意自然数，N为大于等于2的任意自然数。
在一些实施例中，所述控制信号生成模块还被配置为，所述不同的第一随机数为在不同的所述计满周期内的所述第一随机数；在同一所述计满周期内，所述控制信号不变；一所述计满周期对应的所述控制信号与相邻的所述计满周期对应的所述控制信号不同。
在一些实施例中，所述随机数发生器还被配置为，完成每一所述计满周期则输出计满信号；所述控制信号生成模块接收所述计满信号作为所述触发信号。
在一些实施例中，所述控制信号生成模块还被配置为，所述不同的第一随机数包括每一所述计满周期内的所述第一随机数，在同一所述计满周期内，不 同的所述第一随机数对应的所述控制信号不同。
在一些实施例中，所述随机数发生器还被配置为，接收驱动时钟信号产生所述第一随机数；所述控制信号生成模块还被配置为，接收所述驱动时钟信号作为所述触发信号。
在一些实施例中，所述控制信号生成模块包括：M-bit伪随机数产生电路，且所述伪随机数产生电路与所述随机数发生器接收同一驱动时钟信号。
在一些实施例中，所述随机数发生器包括线性反馈移位寄存器。
本公开实施例提供一种结构性能优越的随机数产生电路，包括随机数发生器、控制信号生成模块以及多选模块，随机数发生器输出若干第一随机数，且控制信号生成模块向多选模块提供与不同第一随机数对应的控制信号，多选模块接收控制信号后对第一随机数的至少一个比特位置进行调整，获取第二随机数，第二随机数与第一随机数相比具有更好的随机性，从而提高随机数产生电路产生的随机数的随机性。
另外，多选模块具有N种不同比特位置调整方式，因此对于第一随机数的比特位置调整方式具有N种，基于具有一种随机序列的第一随机数而言，可以产生N种随机序列的第二随机数，从而进一步的增加了随机数的随机序列，进一步的提高了随机数的随机性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为7种不同的电路结构示意图；
图2为本公开一实施例提供的随机数产生电路的功能框图；
图3为本公开另一实施例提供的随机数产生电路的功能框图；
图4为图3中的随机数发生器的电路结构示意图；
图5为图4中多选模块的结构示意图；
图6为图4中控制信号生成模块的一种结构示意图；
图7为图4中控制信号生成模块的另一种结构示意图；
图8为图4中控制信号生成模块的又一种结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
由背景技术可知，现有技术的随机数产生电路的随机性仍有待提高。
分析发现，目前的随机数产生电路虽然对输出进行了乱序处理，但是前后数之间还是具有一定的前后关系，很难做到真正意义上的随机。以线性移位寄存器((Linear Feedback Shift Registers，LFSR)作为随机数产生电路，以产生7-bit的随机数作为示例。对于一个固定的随机数产生电路而言，其抽头(the output of affect on the input，tap)位置是固定的，那么这个随机数产生电路只能产生一种随机序列，在一个计数周期内前后数的顺序是固定的，其中影响下一个状态的比特位置叫做抽头位置。
若需要产生多种随机序列，则需要设置多种随机数产生电路，且每一随机数产生电路的抽头位置不同，例如，对于7-bit的LFSR而言具有7种不同的抽头位置，则可设计7个具有不同抽头位置的LFSR，从而实现7种随机序列，每一种随机序列可产生2 7-1个随机数，以增加随机数的随机性。
图1为7种不同的电路结构示意图，如图1所示，标示1-7的7种不同的电路图各自对应的抽头位置不同，随机数产生电路包括：7个串联的触发器10，该触发器10为D触发器，且前一级触发器10的输出作为后一级触发器10的输 入，且各触发器10接收驱动时钟信号clk；异或门11，异或门11的两个输入端分别与一触发器10的输入端与输出端连接，且异或门11的输出端作为另一触发器10的输入端；该异或门11的位置决定随机数产生电路的抽头位置；从左往右将触发器10称为第零级/第一级……第六级触发器10，且各触发器10的输出相应即为D[0]D[1]……D[6]。
对于标示为1的电路图，该随机数产生电路产生第一种随机序列的随机数：抽头位置为第零级触发器10，随机数产生电路的输出按照比特位的高低依次排布为D[0]D[6]D[5]D[4]D[3]D[2]D[1]。
对于标示为2的电路图，该随机数产生电路产生第二种随机序列的随机数：抽头位置为第一级触发器10，随机数产生电路的输出按照比特位的高低依次排布为D[1]D[0]D[6]D[5]D[4]D[3]D[2]。
对于标示为3的电路图，该随机数产生电路产生第三种随机序列的随机数：抽头位置为第二级触发器10，随机数产生电路的输出按照比特位的高低依次排布为D[2]D[1]D[0]D[6]D[5]D[4]D[3]。
对于标示为4的电路图，该随机数产生电路产生第四种随机序列的随机数：抽头位置为第三级寄存器10，随机数产生电路的输出按照比特位的高低依次排布为D[3]D[2]D[1]D[0]D[6]D[5]D[4]。
对于标示为5的电路图，该随机数产生电路产生第五种随机序列的随机数：抽头位置为第四级寄存器10，随机数产生电路的输出按照比特位的高低依次排布为D[4]D[3]D[2]D[1]D[0]D[6]D[5]。
对于标示为6的电路图，该随机数产生电路产生第六种随机序列的随机数：抽头位置为第五级寄存器10，随机数产生电路的输出按照比特位的高低依次排布为D[5]D[4]D[3]D[2]D[1]D[0]D[6]。
对于标示为7的电路图，该随机数产生电路产生第七种随机序列的随机数：抽头位置为第六级寄存器10，随机数产生电路的输出按照比特位的高低依次排布为D[6]D[5]D[4]D[3]D[2]D[1]D[0]。
由上述分析不难发现，为达到不同的随机序列，需要改过电路图的抽头位置，即需要提供7种电路，增加电路复杂性。此外，由上述分析可知，对于随 机数的比特位固定的电路而言，且抽头位置可变化的量也是固定的，导致可变化的随机序列的数量也是固定的，如图1为产生7-bit的随机数，那么抽头位置变化的最大量也是7，能够产生的随机序列的最大种类也是7，因此采用这种方式来增加随机序列的能力也是有限的。
本公开实施例提供一种随机数产生电路，包括随机数发生器、控制信号生成模块以及多选模块，该多选模块可用于对随机数发生器产生的第一随机数的比特位置进行重新排序，从而增加随机数产生电路产生的随机数的随机序列，提高随机数的随机性。
图2为本公开一实施例提供的随机数产生电路的功能框图。
参考图2，本实施例中，随机数产生电路包括：随机数发生器101，被配置为，在每一计满周期内输出若干个第一随机数；控制信号生成模块102，被配置为，接收触发信号CLK2，并基于触发信号CLK2输出与不同的第一随机数对应的控制信号Sel；多选模块103，被配置为，接收第一随机数以及与第一随机数对应的控制信号Sel，基于控制信号Sel对第一随机数的至少一个比特位置进行调整，获取第二随机数，并输出若干所述第二随机数。
以下将结合附图对本实施例提供的随机数产生电路进行详细说明。
随机数发生器101为n-bit随机数发生器，相应的，若干个第一随机数为2 n-1个第一随机数；随机数发生器101接收驱动时钟信号CLK1产生第一随机数。其中，随机数发生器101产生所有不同的第一随机数的周期为计满周期。
随机数发生器101具有n个第一输出端，且每一所述第一输出端具有固定的比特位置，n为大于1的整数，例如为4、7、10等。随机数发生器101可以为线性反馈移位寄存器，且包括n个串联的触发器，每一个触发器的输出端作为n个第一输出端中的一个，且每一触发器的输出端所处的比特位置不同。
在一个例子中，以D[0]、D[1]、D[2]……D[n-3]、D[n-2]、D[n-1]标示各第一输出端(即各触发器的输出端)，且各第一输出端的比特位置从高到低的排布可以为以D[0]、D[n-1]、D[n-2]、D[n-3]……D[2]、D[1]的顺序，n大于3。本实施例中，随机数发生器101可产生一种随机序列的第一随机数，也就是说，随机数发生器101可以为具有固定抽头位置的线性移位寄存器。可以理解的是， 在其他实施例中，随机数发生器也可以产生具有多种随机序列的第一随机数。
控制信号生成模块102具有用于接收触发信号CLK2的触发端112，且还具有用于输出控制信号Sel的信号输出端122。
为了提高控制信号Sel与第一输出端输出数据的同步性，本实施例中，触发信号CLK2与随机数发生器101相关联。如此，可以提高第一随机数发生变化时控制信号Sel变化的同步性。
在一个例子中，控制信号生成模块102可以被配置为，不同的第一随机数为在不同的计满周期内的第一随机数；在同一计满周期内，控制信号Sel不变；一计满周期对应的控制信号Sel与相邻的计满周期对应的控制信号Sel不同。如此，在同一计满周期内，多选模块103对同一计满周期内的若干第一随机数的比特位置调整的方式相同，即基于第一随机数获取第二随机数的方式相同，有利于降低电路的复杂程度。
触发信号CLK2可以为触发驱动时钟信号，且触发驱动时钟信号的时钟周期与计满周期相同。或者，触发信号CLK2也可以由随机数发生器101输出提供，即随机数发生器101完成一个计满周期则输出计满信号，控制信号生成模块102接收该计满信号作为触发信号。
在另一个例子中，控制信号生成模块102可以被配置为，不同的第一随机数包括每一计满周期内的第一随机数，在同一计满周期内，不同的第一随机数对应的控制信号Sel不同。如此，由于在单个计满周期内，控制信号Sel不同，因此多选模块103对同一计满周期内的每一第一随机数的比特位置调整方式也可以不同，从而有利于进一步的增加第二随机数的随机性。更具体地，由于同一计满周期内的控制信号Sel也不相同，能够在增加不同计满周期的第一随机数的随机性的同时，还增加同一计满周期的第一随机数的随机性。
随机数发生器101接收驱动时钟信号CLK1产生第一随机数，控制信号生成模块102接收该驱动时钟信号CLK1作为触发信号CLK2。
本实施例中，多选模块103包括：片选输入端113，用于接收控制信号Sel；数据输入端，与n个第一输出端连接，用于接收第一随机数；多选模块103具有N种不同比特位置调整方式，且每一比特位置调整方式与一控制信号对应， 其中，N为大于1的整数；多选模块103还被配置为：对n个第一输出端的比特位置进行调整，以获取第二随机数。
多选模块103包括数据输出端OUT[n-1：0]，输出n-bit的第二随机数。
相较于随机数产生电路101产生的第一随机性的随机序列而言，多选模块103输出的第二随机数的随机序列增加了N倍。
控制信号Sel的种类大于或等于N，保证会用到所有的不同比特位置调整方式来调整第一随机数的比特位置，从而增加第二随机数的随机序列。因此，可以根据N合理设置控制信号生成模块102，保证产生的控制信号Sel的种类符合需求。
本实施例中，N大于或等于n，有利于增加第二随机数的随机序列。具体地，n个第一输出端的数据的比特位置排列为第一比特位置排列，多选模块103的输出端输出的数据可以具有N个第二比特位置排列，每一第二比特位置排列为基于一种比特位置调整方式对第一比特位置进行调整后获取的。
需要说明的是，为了保留随机数发生器101产生的第一随机数的随机序列，至少一个第二比特位置排列与第一比特位置排列相同。还需要说明的是，在其他实施例中，N也可以为1。
此外，为了减小多选模块103的电路复杂度，多选模块103还可以被配置为：对于N各第二比特位置排列中，一个比特位的数据对应的多选模块103的输出端的位置不同，而其余比特位的数据对应的多选模块103的输出端的位置排列不变。举例来说，由最高位到最低位，第一比特位置排列为D[0]、D[n-1]、D[n-2]….D[3]、D[2]、D[1]；由最高位到最低位，第二比特位置排列包括表一中的多种排列方式。
1 D[0] D[n-1] D[n-2] D[n-3] … D[3] D[2] D[1]
2 D[1] D[0] D[n-1] D[n-2] … D[4] D[3] D[2]
3 D[2] D[1] D[0] D[n-1] … D[5] D[4] D[3]
… … … … … … … … …
n-1 D[n-2] D[n-3] D[n-4] D[n-5] … D[1] D[0] D[n]
n D[n-1] D[n-2] D[n-3] D[n-4] … D[2] D[1] D[0]
表一
可以理解的是，在其他实施例中，也可以为至少两个比特位的数据对应的多选模块103的输出端的位置不同。对于n个第一输出端而言，各第一输出端对应的数据的比特位均可以发生变化，根据不同的排列组合一共具有C n n-1种变化，也就是说，N与n满足：N≤C n n-1，即，N≤n×(n-1)×(n-2)…2×1。
为了降低多选模块103的复杂度，N可以与n相同。
可以理解的是，在其他实施例中，N也可以小于n。
本实施例中，随机数发生器101输出二进制的第一随机数，相应的多选模块103输出二进制第二随机数。
本实施例提供的随机数产生电路，由于多选模块103能够对第一随机数的比特位进行重新排序，从而产生更多的随机序列，提高随机数产生电路的随机数的随机性。此外，相较于需要多种具有不同抽头位置的随机数发生器而言，本实施例的电路结构更为简单，且功耗更低。
本公开另一实施例还提供一种随机数产生电路，该随机数产生电路与前述的实施例的大致相同，主要区别包括对各模块做了更详细的说明。以下将结合附图对本公开另一实施例提供的随机数产生电路进行详细说明，与前述实施例相同或者相应的部分，可参考前述实施例，以下将不做详细赘述。
图3为本公开另一实施例提供的随机数产生电路的功能框图。
参考图3，本实施例中，随机数产生电路包括：n-ibt的随机数发生器201，具有n个第一输出端211；控制信号生成模块202；多选模块203，多选模块203具有片选输入端以及数据输入端，多选模块203具有数据输出端OUT[n-1:0]。
多选模块203包括：N个调整单元204，每一调整单元204定义一比特位置调整方式；且每一调整单元204均具有数据输入端，且每一调整单元204均具有片选输入端。每一调整单元204被配置为，接收控制信号Sel，且与控制信号Sel对应的调整单元204输出第二随机数。
也就是说，每一调整单元204的输出端均为多选模块203的数据输出端 OUT[n-1:0]，且控制信号Sel作为调整单元204的片选信号，基于控制信号Sel选中对应的调整单元204的输出端作为多选模块203的数据输出端OUT[n-1:0]。
按照各自输出的数据的比特位置，将n个第一输出端211中的每一第一输出端211标记为D[n-1]、D[n-2]….D[3]、D[2]、D[1]、D[0]。
n个第一输出端211的数据的比特位置排列为第一比特位置排列，例如为D[0]D[n-1]D[n-2]….D[3]D[2]D[1]。每一调整单元204具有n个第二输出端214，且n个第二输出端214的数据的比特位置排列为第二比特位置排列，第二比特位置排列各不相同，且第二比特位置排列与第一比特位置排列不同，例如第二比特位置排列可以为D[n-1]D[n-2]….D[3]D[2]D[1]D[0]等，有关第二比特位置排列以及第一比特位置排列的详细说明，可参考前述实施例。
本实施例中，以调整单元204的数量与随机数产生器201的第一随机数的比特位数量相同作为示例，即N与n相同。在其他实施例中，调整单元的数量可以大于或小于随机数发生器的比特位数量。
图4为本实施例提供的随机数发生器201的电路结构示意图。
参考图4，随机数发生器201为线性移位寄存器，包括：n个触发器211，异或门231，一触发器211的输入端以及输出端作为异或门231的两个输入端，且异或门231的输出端连接另一触发器211的输入端。异或门231的位置定义随机数发生器201的抽头位置，每一触发器211的输出端作为一第一输出端211(参考图3)。
根据串联的顺序，触发器211依次记为第零级触发器、第一级触发器、第二级触发器…第n-1级触发器。
本实施例中，以随机数发生器201为7-bit随机数发生器，且为二进制的7-bit随机数发生器作为示例进行详细说明，在一个计满周期内产生127个第一随机数。图4中，随机数发生器201具有7个触发器211，且异或门231的位置决定了n个第一输出端211的数据的比特位置排列，例如，图4中，7个第一输出端211的数据的比特位置排列为D[0]D[6]D[5]D[4]D[3]D[2]D[1]。
需要说明的是，在其他实施例中，异或门231的输入端、输出端也可以与其他的触发器相应连接。
图5为本实施例提供的多选模块203的结构示意图，包括7个调整单元204(参考图3)。n个第一输出端211作为每一调整单元204的输入端，为了便于图示的简洁性，图5中每一调整单元204的输入端以0代替D[0]、以1代替D[1]，依次类推，且第二输出端214以0代替D[0]，依次类推。需要说明的是，标示为D[0]的标示为第零个第一输出端211的数据，标示为D[1]的为第一个第一输出端211的数据，依次类推。
图5中，为了便于说明，以20/21/22/23/24/25/26标示不同的调整单元204。每一调整单元204的第二输出端的排列方式不同，作为示例，按照从上往下的排列表示各数据的比特位由高到低的排序，标示为20的调整单元204的第二输出端输出的数据为D[0]D[6]D[5]D[4]D[3]D[2]D[1]，标示为21的调整单元204的第二输出端输出的数据为D[1]D[0]D[6]D[5]D[4]D[3]D[2]。
本实施例中，随机数发生器201具有固定的抽头位置，多选模块203应用于模拟随机数发生器201的抽头位置调整产生的随机数。相应的，多选模块203具有n种不同的调整单元204。如图5所示，标示为21的调整单元204用于模拟图4中随机数发生器201的抽头位置在第零级触发器的LFSR，标示为22的调整单元204用于模拟图4中抽头位置在第一级触发器的LFSR，标示为23的调整单元204用于模拟图4中抽头位置在第二级触发器的LFSR，依次类推。
需要说明的是，本实施例中以随机数发生器201为7-bit的随机数发生器作为示例。在其他实施例中，随机数发生器也可以为任意bit的随机数法发生器，如3-bit、4-bit、10-bit、20-bit等。
本实施例中，控制信号生成模块202包括：m-bit计数器212；其中，N与m的关系满足：N≤2 m-1，m为任意自然数，N为大于等于2的任意自然数。具体地，m大于或等于lgN/lg2+1的结果向下取整。举例来说，N为7时，m大于或等于3。
如图6所示，m-bit计数器212包括m个触发器222；触发信号CLK2作为第一级的触发器222的时钟输入信号，前一级的触发器222的输出端作为后一即触发器222的时钟输入信号，m个触发器222的输出端共同输出控制信号Sel。
本实施例中，N为7，则计数器212包括三个触发器222，分别标示为DFF#0、DFF#1、DFF#2。
随机数发生器201还被配置为，完成每一计满周期则输出计满信号，控制信号生成模块202接收该计满信号作为触发信号。如此，在同一计满周期内，控制信号Sel不变；不同的计满周期对应的控制信号Sel不同。
本实施例中，控制信号生成模块202为3-bit计数器，具有三个输出端S0/S1/S2，控制信号Sel如表二所示：
S2(最高比特位) S1 S0(最低比特位) Sel
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
表二
以下将结合附图对本实施例提供的随机数产生电路的工作原理进行说明：
在第一个计满周期内，随机数发生器201产生若干第一随机数，且控制信号Sel保持不变为0，相应的多选模块203中标示为20的调整单元204被选中，其第二输出端214输出若干第二随机数，各第二随机数的顺序与第一随机数的顺序相同。
第一计满周期完成，随机数发生器201输出计满信号，该计满信号作为计数器的触发信号，S2S1S0由000变为001，控制信号Sel由0变为1，相应的标示为21的调整单元204被选中，在第二个计满周期内，标示为21的调整单元203的第二输出端输入若干第二随机数，各第二随机数的顺序与第一随机数的顺序不同。
依次类推，每一次计满周期完成后，计数器输出端输出的控制信号Sel为上一个计满周期对应的数值+1，从而选中另一个调整单元203的第二输出端作为 多选模块203的输出端。
如此，对于7个计满周期而言，每个计满周期内的第二随机数的顺序都发生了变化，第二随机数的随机序列为7种，从而增加了随机数产生电路产生的随机数的随机性。
在另一例子中，如图7所示，计数器的触发信号与随机数发生器201的驱动时钟信号相同。在每个计满周期内，不同的第一随机数对应不同的控制信号Sel，因此在每个计满周期内也能调用不同的调整单元204进行比特位置的重新排列，从而进一步的增加了随机数的随机性，有利于产生更多的随机序列。随机数产生电路的工作原理如下：
在每一个计满周期内，随机数发生器201产生第一个随机数，计数器输出的控制信号Sel为0，选中标号为20的调整单元204产生第二随机数；随机数发生器201产生第二个随机数，计数器输出的控制信号Sel为1，选中标号为21的调整单元204产生第二随机数；计数器输出的控制信号Sel为2，选中标号为22的调整单元204产生第二随机数；依次类推；当计数器输出的控制信号为7之后，计数器又重新从0开始计数。可以理解的是，多选模块203中的调整单元204的数量可以与每一计满周期产生的第一随机数的数量相同，且根据调整电路203的数量设置计数器。需要说明的是，前述的控制信号Sel与对应选中的调整单元204仅为示例，只有保证不同的控制信号Sel对应选中不同的调整单元204即可。
在又一个例子中，如图8所示，控制信号生成模块202可以为：M-bit伪随机数产生电路，且伪随机数产生电路与随机数发生器201接收同一驱动时钟信号CLK。相较于计数器而言，伪随机数产生电路输出的控制信号更具有随机性，因此不同的第一随机数对应的调整单元204也相应更具有随机性。
伪随机数产生电路包括M个D触发器232以及第一异或门231，伪随机数产生电路具有输出端S0/S1/S2，该输出端的信号作为控制信号。
本实施例提供的随机数产生电路，基于一种具有固定随机序列的随机数发生器201，能够产生具有N种不同随机序列的随机数，提高了使用该随机数产生电路的安全性。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开所提供的随机数产生电路，结构简单，功耗低，通过多选模块对随机数发生器输出的若干第一随机数的至少一个比特位置进行重新排序，获取第二随机数，从而增加随机数产生电路产生的随机数的随机序列，产生更多的随机序列，提高随机数的随机性。

Claims (15)

  1. 一种随机数产生电路，其中，包括：
    随机数发生器，被配置为，在每一计满周期内输出若干个第一随机数；
    控制信号生成模块，被配置为，接收触发信号，并基于所述触发信号输出与不同的所述第一随机数对应的控制信号；
    多选模块，被配置为，接收所述第一随机数以及与所述第一随机数对应的所述控制信号，基于所述控制信号对所述第一随机数的至少一个比特位置进行调整，获取第二随机数，并输出若干所述第二随机数。
  2. 如权利要求1所述的随机数产生电路，其中，所述随机数发生器为n-bit随机数发生器，所述若干个第一随机数为2 n-1个第一随机数；所述随机数发生器具有n个第一输出端，且每一所述第一输出端具有固定的比特位置，n为大于1的整数。
  3. 如权利要求2所述的随机数产生电路，其中，所述多选模块包括：
    片选输入端，用于接收所述控制信号；
    数据输入端，与n个所述第一输出端连接，用于接收所述第一随机数；
    所述多选模块具有N种不同比特位置调整方式，且每一所述比特位置调整方式与一所述控制信号对应，其中，N为大于或等于1的整数；所述多选模块还被配置为，对所述n个第一输出端的数据的比特位置进行调整，以获取所述第二随机数。
  4. 如权利要求3所述的随机数产生电路，其中，所述多选模块包括：N个调整单元，每一所述调整电路定义一所述比特位置调整方式；每一所述调整单元均具有所述数据输入端，且每一所述调整单元均具有所述片选输入端。
  5. 如权利要求4所述的随机数产生电路，其中，所述n个第一输出端的数据的比特位置排列为第一比特位置排列，每一所述调整单元具有n个第二输出端，所述n个第二输出端的数据的比特位置排列为第二比特位置排列；每一所述第二比特位置排列各不相同，且所述第二比特位置排列与所述第一比特位置排列不同。
  6. 如权利要求5所述的随机数产生电路，其中，N个所述调整单元被配置 为，N个所述第二比特位置排列中，一个比特位的数据对应的所述第二输出端的位置不同，其余比特位的数据对应的所述第二输出端的位置排列不变。
  7. 如权利要求5所述的随机数产生电路，其中，至少一个所述第二比特位置排列与所述第一比特位置排列相同。
  8. 如权利要求4所述的随机数产生电路，其中，所述N大于或等于n。
  9. 如权利要求3所述的随机数产生电路，其中，所述控制信号生成模块包括：m-bit计数器；其中，N与m的关系满足：N≤2m-1，m为任意自然数，N为大于等于2的任意自然数。
  10. 如权利要求1所述的随机数产生电路，其中，所述控制信号生成模块还被配置为，所述不同的第一随机数为在不同的所述计满周期内的所述第一随机数；在同一所述计满周期内，所述控制信号不变；一所述计满周期对应的所述控制信号与相邻的所述计满周期对应的所述控制信号不同。
  11. 如权利要求10所述的随机数产生电路，其中，所述随机数发生器还被配置为，完成每一所述计满周期则输出计满信号；所述控制信号生成模块接收所述计满信号作为所述触发信号。
  12. 如权利要求1所述的随机数产生电路，其中，所述控制信号生成模块还被配置为，所述不同的第一随机数包括每一所述计满周期内的所述第一随机数，在同一所述计满周期内，不同的所述第一随机数对应的所述控制信号不同。
  13. 如权利要求12所述的随机数产生电路，其中，所述随机数发生器还被配置为，接收驱动时钟信号产生所述第一随机数；所述控制信号生成模块还被配置为，接收所述驱动时钟信号作为所述触发信号。
  14. 如权利要求1所述的随机数产生电路，其中，所述控制信号生成模块包括：M-bit伪随机数产生电路，且所述伪随机数产生电路与所述随机数发生器接收同一驱动时钟信号。
  15. 如权利要求1所述的随机数产生电路，其中，所述随机数发生器包括线性反馈移位寄存器。
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