WO2022041586A1 - 一种功率因数校正电路及其控制装置和控制方法 - Google Patents

一种功率因数校正电路及其控制装置和控制方法 Download PDF

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Publication number
WO2022041586A1
WO2022041586A1 PCT/CN2020/137444 CN2020137444W WO2022041586A1 WO 2022041586 A1 WO2022041586 A1 WO 2022041586A1 CN 2020137444 W CN2020137444 W CN 2020137444W WO 2022041586 A1 WO2022041586 A1 WO 2022041586A1
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Prior art keywords
switch
circuit
control
control signal
switch transistor
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PCT/CN2020/137444
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English (en)
French (fr)
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韦康
陈涛
许双全
刘宏森
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杭州中恒电气股份有限公司
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Publication of WO2022041586A1 publication Critical patent/WO2022041586A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4225—Arrangements for improving power factor of AC input using a non-isolated boost converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the field of switching power supply power electronics, in particular to a power factor correction circuit, a control device and a method.
  • the front stage often uses a totem pole bridgeless PFC (Power Factor Correction) circuit to shape the input AC current, so that the input current is an approximate sine wave in the same phase as the input voltage to achieve It is possible that the input power is close to 1.
  • the traditional totem pole bridgeless PFC circuit is shown in Figure 1, which usually adopts the critical control mode or the continuous control mode.
  • the continuous control mode has high requirements for transistor characteristics, and the reverse recovery of Si-MOS cannot reliably realize the continuous control mode.
  • Only the third-generation semiconductor devices such as GAN and SIC can be used. However, the third-generation semiconductor devices have small specifications and cost. Problems such as high reliability and doubtful reliability cannot be used in batches.
  • the critical control mode is to turn off the transistor when the inductor current is infinitely close to zero, the current continues to flow through the body diode of the transistor, and the reverse recovery characteristics of the body diode of the transistor are used to achieve soft switching. Recovery is uncontrollable, making it difficult to control the totem-pole bridgeless PFC circuit to operate in critical mode.
  • one of the objectives of the present invention is to provide a power factor correction circuit, which is turned on or off to control the power factor correction through the first rectifier circuit when receiving the control signal output by the external controller
  • the circuit works in the critical mode, and the control signal is obtained by the external controller according to the first level output by the first detection circuit or the second level output by the second detection circuit, which can effectively control the power factor correction circuit to work in the critical mode.
  • a power factor correction circuit comprising: a boost inductor, a first rectifier circuit, a first detection circuit, a second detection circuit, a second rectifier circuit and a filter circuit;
  • One end of the boost inductor is connected to one end of the AC transmission network, and the other end is connected to the midpoint of the first rectifier circuit, and is used for boosting the voltage output from the AC transmission network;
  • One end of the first rectifier circuit is connected to one end of the filter circuit, the other end is connected to the other end of the filter circuit, and the control end is connected to an external controller for receiving the control output by the external controller.
  • the signal is turned on or off to control the power factor correction circuit to work in a critical mode, wherein the control signal is output by the external controller when the first level or the second level is received;
  • One end of the first detection circuit is connected to one end of the filter circuit, the other end is connected to the midpoint of the first rectifier circuit, and the output end is connected to the external controller for when the first outputting a first level to the external controller when the current at the midpoint of the rectifier circuit is reversed;
  • One end of the second detection circuit is connected to the other end of the filter circuit, the other end is connected to the midpoint of the first rectifier circuit, and the output end is connected to the external controller, for when the first A second level is output to the external controller when the current at the midpoint of a rectifier circuit is reversed;
  • the second rectifier circuit one end of which is connected to one end of the filter circuit, the other end is connected to the other end of the filter circuit, and the midpoint is connected to the other end of the AC transmission network;
  • the first rectifier circuit and the second rectifier circuit are used for converting the AC voltage output from the AC power transmission network into a pulsating DC voltage
  • the filter circuit is used for filtering the AC voltage in the pulsating DC voltage.
  • the first rectifier circuit includes:
  • the first switch tube includes a first control end, a first source end and a first drain end, the first control end is connected to the external controller, and the first drain end is connected to one end of the filter circuit, so the first source end is connected to the other end of the boost inductor;
  • a second switch tube includes a second control end, a second source end and a second drain end, the second control end is connected to the external controller, and the second drain end is connected to the other end of the boost inductor , the second source end is connected to the other end of the filter circuit;
  • the first control terminal and the second control terminal are used to receive a control signal from an external controller, and the first switch tube and the second switch tube are alternately turned on under the control of the control signal to control the power factor correction
  • the circuit operates in a critical mode, and in the critical mode, the body diode of the first switch transistor or the second switch transistor changes from a reverse recovery state to an off state.
  • the first detection circuit includes a first current limiting resistor, a first energy storage capacitor, a first Zener diode and a first discharge resistor;
  • the first current limiting resistor and the first energy storage capacitor are connected in series between the midpoint of the first rectifier circuit and the anode of the first Zener diode, and the first Zener diode and the first discharge resistors are connected in parallel, and the anode and cathode of the first Zener diode are respectively connected to the external controller and one end of the filter circuit;
  • the anode of the first Zener diode is used when the current at the midpoint of the first rectifier circuit flows from the boost inductor to the second switch tube and changes from the second switch tube to the boost tube outputting the first level to the external controller when inductive.
  • the second detection circuit includes a second current limiting resistor, a second energy storage capacitor, a second Zener diode and a second discharge resistor;
  • the second current limiting resistor and the second energy storage capacitor are connected in series between the midpoint of the first rectifier circuit and the anode of the second Zener diode, and the second Zener diode and the second discharge resistors are connected in parallel, and the anode and cathode of the second Zener diode are respectively connected to the external controller and the other end of the filter circuit;
  • the anode of the second Zener diode is used for when the current at the midpoint of the first rectifier circuit flows from the boost inductor to the first switch tube and changes from the first switch tube to the boost tube
  • the second level is output to the external controller when inductive.
  • first switch transistor and the second switch transistor are respectively any one of Si_MOS, SIC_MOS, GAN_MOS and IGBT.
  • the second rectifier circuit includes:
  • the third switch tube includes a third control end, a third source end and a third drain end, the third control end is connected to the external controller, and the third drain end is connected to one end of the filter circuit, so the third source end is connected to the other end of the AC transmission network;
  • a fourth switch tube includes a fourth control end, a fourth source end and a fourth drain end, the fourth control end is connected to the external controller, and the fourth drain end is connected to another part of the AC transmission network one end, the fourth source end is connected to the other end of the filter circuit;
  • the third control terminal and the fourth control terminal are used for receiving a control signal from an external controller, and under the control of the control signal, the third switch tube and the fourth switch tube are alternately turned on to control the power transmission from the AC power.
  • the third switch tube and the fourth switch tube are turned off and turned on respectively during the positive half cycle of the AC output of the grid, and the third switch tube and the fourth switch tube are respectively turned off during the negative half cycle of the AC output from the AC transmission network.
  • the fourth switch tube is turned on and off respectively.
  • the third switch transistor and the fourth switch transistor are respectively any one of Si_MOS, SIC_MOS, GAN_MOS, IGBT and diode.
  • the filter circuit includes a bus capacitor, and the positive electrode and the negative electrode of the bus capacitor are respectively connected to the first detection circuit and the second detection circuit.
  • Another object of the present invention is to provide a control device for a power factor correction circuit, through which the controller outputs a switch control signal when receiving the first level output by the first detection circuit or the second level output by the second detection circuit,
  • the first rectifier circuit is controlled to be turned on or off, so that the power factor correction circuit works in a critical mode, which is stable and reliable.
  • a control device for a power factor correction circuit comprising an AC transmission network, a controller, and a power factor correction circuit that is one of the objectives of the present invention, wherein the controller is respectively connected to the first rectifier circuit and the second rectifier circuit.
  • the first detection circuit and the second detection circuit for outputting switch control signals to the first rectifier circuit and the second rectifier circuit to control the first rectifier circuit and the second rectifier circuit
  • Two rectifier circuits are turned on or off, and when the first level or the second level is received, a switch control signal is output to control the first rectifier circuit to be turned on or off to make the power factor correction circuit Works in critical mode.
  • the third object of the present invention is to provide a control method for a power factor correction circuit, which controls the phase and AC of the current waveform of the boost inductor by alternately turning on or off the first switch and the second switch.
  • the envelope phase of the input waveform of the power transmission network is matched, and the reverse recovery of the body diodes of the first switch tube and the second switch tube is controllable at the same time, thereby controlling the power factor correction circuit to work in a critical mode.
  • the controller In the positive half cycle of the AC input of the AC transmission network, the controller outputs a first control signal to the third switch transistor and the fourth switch transistor, and the third switch transistor and the fourth switch transistor respond to the first control signal respectively. turn off and on;
  • the controller outputs a second control signal to the first switch tube and the second switch tube when the on-time of the first switch tube reaches a preset first turn-on time, the first switch tube and the The second switch tubes are all turned off in response to the second control signal;
  • the controller outputs a third control signal to the first switch tube and the second switch tube when receiving the second level, and the first switch tube and the second switch tube respond to the third control The signal is turned off and turned on respectively;
  • the controller outputs a second control signal to the first switch transistor and the second switch transistor when the on-time of the second switch transistor reaches a preset second on-time time, and the first switch transistor and the The second switch tubes are all turned off in response to the second control signal;
  • the controller outputs a fourth control signal to the first switch transistor and the second switch transistor when the off-time of the second switch transistor reaches a preset first off-time, and the first switch transistor
  • the tube and the second switch tube are respectively turned on and off in response to the fourth control signal;
  • the controller In the negative half cycle of the AC input of the AC transmission network, the controller outputs a fifth control signal to the third switch transistor and the fourth switch transistor, and the third switch transistor and the fourth switch transistor respond to the first switch transistor.
  • a control signal is turned on and off respectively;
  • the controller outputs a second control signal to the first switch transistor and the second switch transistor when the on-time of the second switch transistor reaches a preset third on-time time, and the first switch transistor and the The second switch tubes are all turned off in response to the second control signal;
  • the controller outputs a fourth control signal to the first switch tube and the second switch tube when receiving the first level, and the first switch tube and the second switch tube respond to the fourth control The signal is turned on and off respectively;
  • the controller outputs a second control signal to the first switch transistor and the second switch transistor when the on-time of the first switch transistor reaches a preset fourth on-time time, and the first switch transistor Both the tube and the second switch tube are turned off in response to the second control signal;
  • the controller outputs a third control signal to the first switch tube and the second switch tube when the time when the first switch tube is turned off reaches a preset second turn-off time, and the first switch tube
  • the transistor and the second switch transistor are respectively turned off and on in response to the third control signal.
  • the present invention uses the control signal generated by the external controller according to the first level output by the first detection circuit or the second level output by the second detection circuit, and the first rectifier circuit turns on or off when receiving the control signal to effectively control
  • the power factor correction circuit works in the critical mode, the circuit is simple, efficient and reliable.
  • Fig. 1 is a kind of totem pole bridgeless PFC circuit
  • FIG. 2 is a circuit schematic diagram of a power factor correction circuit according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of a control device of a power factor correction circuit according to Embodiment 2 of the present invention.
  • 100 power factor correction circuit
  • 110 first rectifier circuit
  • 120 first detection circuit
  • 130 second detection circuit
  • 140 second rectifier circuit
  • 150 controller
  • 160 filter circuit
  • AC AC power grid
  • the current limiting resistor, the discharge resistor and the load resistor in each embodiment are all resistor networks, which may be a single resistor element, or a circuit in which several resistor elements with different and/or the same resistance value are connected in series and/or parallel.
  • Piezoelectric inductance is an inductive network, which can be an inductive element, or a circuit in which several inductive elements with different and/or the same resistance are connected in series and/or parallel.
  • the energy storage capacitor is a capacitive network, which can be a capacitive element or It can be a series and/or parallel circuit of several capacitive elements with different and/or the same resistance value.
  • the various embodiments may be combined with each other to form other embodiments not shown in the following description.
  • Embodiment 1 provides a power factor correction circuit 100, which can effectively control the power factor correction circuit 100 to work in a critical mode, with high efficiency and reliability.
  • the power factor correction circuit 100 includes a boost inductor L1, a first The rectification circuit 110 , the first detection circuit 120 , the second detection circuit 130 , the second rectification circuit 140 and the filter circuit 160 .
  • One end of the boost inductor L1 is connected to one end of the alternating current transmission network AC, and the other end is connected to the midpoint of the first rectifier circuit 110 for boosting the voltage output from the alternating current transmission network AC.
  • One end of the first rectifier circuit 110 is connected to one end of the filter circuit 160 , the other end is connected to the other end of the filter circuit 160 , and the control end is connected to the external controller 150 for receiving the control signal output by the external controller 150 . It is turned on or off to control the power factor correction circuit 100 to work in the critical mode, and the control signal is output by the external controller 150 when the first level or the second level is received.
  • One end of the first detection circuit 120 is connected to one end of the filter circuit 160 , the other end is connected to the midpoint of the first rectifier circuit 110 , and the output end is connected to the external controller 150 for when the midpoint of the first rectifier circuit 110 is The first level is output to the external controller 150 when the current is reversed.
  • One end of the second detection circuit 130 is connected to the other end of the filter circuit 160 , the other end is connected to the midpoint of the first rectifier circuit 110 , and the output end is connected to the external controller 150 for when the midpoint of the first rectifier circuit 110
  • the second level is output to the external controller 150 when the current is reversed.
  • One end of the second rectifier circuit 140 is connected to one end of the filter circuit 160 , the other end is connected to the other end of the filter circuit 160 , and the midpoint is connected to the other end of the alternating current transmission network AC.
  • the first rectifier circuit 110 and the second rectifier circuit 140 convert the AC voltage output from the AC power grid AC into a pulsating DC voltage, and the filter circuit 160 filters the AC voltage in the pulsating DC voltage.
  • the first switch Q1 and the second switch Q2 are turned on or off alternately to control the envelope phase of the current waveform of the boost inductor L1 and the envelope phase of the input waveform of the alternating current transmission network AC It can also eliminate the uncontrollability of the reverse recovery of the body diode of the first switch transistor Q1, so that the control power factor correction circuit 100 can work in the critical mode, and can also reduce the loss caused by reverse recovery, which is efficient and reliable.
  • the first detection circuit 120 has the same structure as the second detection circuit 130, and can be produced in a modularized manner, which is convenient for installation and replacement.
  • the first rectifier circuit 110 includes a first switch transistor Q1 and a second switch transistor Q2.
  • the first switch tube Q1 includes a first control terminal, a first source terminal and a first drain terminal, the first control terminal is connected to the external controller 150, the first drain terminal is connected to one end of the filter circuit 160, and the first source terminal is connected to the booster the other end of the inductor L1.
  • the second switch tube Q2 includes a second control terminal, a second source terminal and a second drain terminal. The second control terminal is connected to the external controller 150, the second drain terminal is connected to the other end of the boost inductor L1, and the second source terminal is connected to the external controller 150. the other end of the filter circuit 160 .
  • the first control terminal and the second control terminal are used to receive the control signal of the external controller 150. Under the control of the control signal, the first switch transistor Q1 and the second switch transistor Q2 are turned on alternately, so as to control the power factor correction circuit 100 to work at a critical level. mode, in the critical mode, the body diode of the first switch transistor Q1 or the second switch transistor Q2 changes from a reverse recovery state to an off state.
  • the first switch transistor Q1 and the second switch transistor Q2 are both Si_MOS transistors, that is, a silicon-based super-node MOS is used, which can effectively reduce the circuit cost.
  • the first switch transistor Q1 and the second switch transistor Q2 may be any one of semiconductor switching devices such as IGBT, SIC, GAN, and IGBT, respectively.
  • the first detection circuit 120 includes a first current limiting resistor R1, a first energy storage capacitor C1, a first Zener diode Z1 and a first discharge resistor R2.
  • the first current limiting resistor R1 and the first energy storage capacitor C1 are connected in series between the midpoint of the first rectifier circuit 110 and the anode of the first Zener diode Z1, the first Zener diode Z1 and the first discharge resistor R2 are connected in parallel, and
  • the anode and cathode of the first Zener diode Z1 are connected to one end of the external controller 150 and the filter circuit 160, respectively.
  • the anode of the first Zener diode Z1 outputs the first level to External controller 150.
  • the second detection circuit 130 includes a second current limiting resistor R3, a second energy storage capacitor C2, a second Zener diode Z2 and a second discharge resistor R4.
  • the second current limiting resistor R3 and the second energy storage capacitor C2 are connected in series between the midpoint of the first rectifier circuit 110 and the anode of the second Zener diode Z2, the second Zener diode Z2 is connected in parallel with the second discharge resistor R4, and
  • the anode and the cathode of the second Zener diode Z2 are connected to the other ends of the external controller 150 and the filter circuit 160, respectively.
  • the anode of the second Zener diode Z2 is used to output the second voltage when the current at the midpoint of the first rectifier circuit 110 flows from the boost inductor L1 to the first switch transistor Q1 and changes from the first switch transistor Q1 to the boost inductor L1 Flat to external controller 150.
  • the second rectifier circuit 140 includes a third switch transistor Q3 and a fourth switch transistor Q4.
  • the third switch tube Q3 includes a third control terminal, a third source terminal and a third drain terminal, the third control terminal is connected to the external controller 150, the third drain terminal is connected to one end of the filter circuit 160, and the third source terminal is connected to the AC The other end of the transmission grid AC.
  • the fourth switch transistor Q4 includes a fourth control end, a fourth source end and a fourth drain end, the fourth control end is connected to the external controller 150, the fourth drain end is connected to the other end of the alternating current transmission network AC, and the fourth source end The other end of the filter circuit 160 is connected.
  • the third control terminal and the fourth control terminal are used to receive the control signal of the external controller 150. Under the control of the control signal, the third switching transistor Q3 and the fourth switching transistor Q4 are turned on alternately, so as to control the alternating current from the alternating current transmission network AC. The third switching transistor Q3 and the fourth switching transistor Q4 are respectively turned off and on during the positive half cycle of the output, and the third switching transistor Q3 and the fourth switching transistor Q4 are respectively turned on and on during the negative half cycle of the AC output from the AC transmission network AC. off.
  • the third switch transistor Q3 and the fourth switch transistor Q4 are both Si_MOS transistors, that is, a silicon-based super node MOS is used, which can effectively reduce the circuit cost.
  • the third switch transistor Q3 and the fourth switch transistor Q4 may be any one of semiconductor switching devices such as IGBT, SIC, GAN, and diode, respectively.
  • the filter circuit 160 includes a bus capacitor C3, and the positive electrode and the negative electrode of the bus capacitor C3 are connected to the first detection circuit 120 and the second detection circuit 130, respectively.
  • the power factor correction circuit further includes a load circuit.
  • the load circuit includes a load resistor R5 , and the load resistor R5 is connected in parallel with the filter circuit 160 . It should be noted that the load circuit is not limited to the above type.
  • the level of the positive electrode of the second Zener diode Z2 with respect to the level of the negative electrode of the bus capacitor C3 is denoted as the ZVS2 level.
  • the working principle of the power factor correction circuit 100 in the positive half cycle of the AC input of the AC transmission network AC is as follows: in the positive half cycle of the AC input of the AC transmission network AC, the third switch Q3 and the fourth switch Q4 are respectively controlled by the control signal. off and on.
  • the power factor correction circuit 100 works when the AC input of the AC transmission network AC changes from a negative half cycle to a positive half cycle, the first switch Q1 and the second switch Q2 are respectively turned off and on under the control of the control signal, and the AC voltage is applied
  • the level of the midpoint of the first rectifier circuit 110 is zero relative to the level of the negative electrode of the bus capacitor C3
  • the current in the boost inductor L1 increases linearly from zero, and the current flows from the AC power grid.
  • the AC flows to the boost inductor L1 flows to the second switch transistor Q2, flows to the fourth switch transistor Q4, and flows to the AC power transmission network AC, and the level of ZVS2 is zero.
  • the first switch Q1 and the second switch Q2 are both turned off under the control of the control signal, and the midpoint of the first rectifier circuit 110 is turned off.
  • the body diode of the first switch transistor Q1 is turned on and charges the second energy storage capacitor C2 at the same time, and the current flows from the AC transmission network AC to the boost inductor L1 to the first switch transistor Q1 and flows to the busbar
  • the capacitor C3 flows to the fourth switch transistor Q4 and flows to the AC transmission network AC, while the current flows from the AC transmission network AC to the boost inductor L1 to the second energy storage capacitor C2 to the second Zener diode Z2 to the fourth switch transistor Q4 and flows to the AC transmission network.
  • AC, ZVS2 level is the forward voltage drop of the second Zener diode Z2.
  • the first switch tube Q1 and the second switch tube Q2 are respectively turned on and off under the control of the control signal.
  • the current decreases linearly, the second energy storage capacitor C2 is in the charging state, the current flows from the AC transmission network AC to the boost inductor L1, flows to the first switching transistor Q1, flows to the bus capacitor C3, flows to the fourth switching transistor Q4 and flows to the AC transmission network AC, ZVS2 level zero.
  • both the first switch Q1 and the second switch Q2 are turned off, that is, the first switch Q1 and the second switch Q2 are rising
  • the current in the boost inductor L1 does not drop to zero, it is turned off in advance.
  • the body diode of the first switch transistor Q1 is reversely recovered, because the current in the boost inductor L1 cannot change abruptly, and the current in the boost inductor L1 reverses at the same time.
  • the junction capacitance of the second switch tube Q2 is discharged, the junction capacitance of the first switch tube Q1 is charged, the second energy storage capacitor C2 is discharged, and the current flows from the first switch tube Q1 to the boost inductor L1 to the AC transmission network AC and flows to the fourth switch
  • the tube Q4 flows to the bus capacitor C3 and flows to the first switch tube Q1, and at the same time, the current flows from the second energy storage capacitor C2 to the boost inductor L1 to the alternating current transmission network AC, and flows to the fourth switch tube Q4 to the second discharge resistor R4 to the second energy storage capacitor.
  • C2, ZVS2 level is negative level.
  • the current at the midpoint of the first rectifier circuit 110 flows from the boost inductor L1 to the first switch transistor Q1, and changes from the first switch transistor Q1 to the boost inductor L1, and the current in the boost inductor L1 flows from the AC power grid to the
  • the midpoint of the first rectifier circuit 110 changes to flow from the midpoint of the first rectifier circuit 110 to the AC transmission network AC, that is, the current in the boost inductor L1 is reversed, and the positive output of the second Zener diode Z2 is opposite to the bus capacitance.
  • the level of the negative electrode of C3 is dropped to the second level of the negative level to the external controller 150 .
  • the first switch transistor Q1 and the second switch transistor Q2 are respectively turned off and on under the control signal of the external controller 150, the body diode of the first switch transistor Q1 changes from the reverse recovery state to the off state, and the boost inductor L1
  • the current recovered from the AC power transmission network AC flows to the midpoint of the first rectifier circuit 110, and the current of the midpoint of the first rectifier circuit 110 flows from the boost inductor L1 to the second switch transistor Q2, while both ends of the second switch transistor Q2
  • the voltage drop is zero, and the level of the anode of the second Zener diode Z2 is also zero relative to the level of the cathode of the bus capacitor C3.
  • the first switch transistor Q1 and the second switch transistor Q2 are cyclically operated under the control of the control signal in the following working cycles: when the first switch transistor Q1 is turned on for a predetermined period of time When the first conduction time is set, both the first switch tube Q1 and the second switch tube Q2 are turned off; when the ZVS2 level is a negative level, the first switch tube Q1 is turned off, and the second switch tube Q2 is turned on; When the on-time of the two switches Q2 reaches the preset second on-time, both the first switch Q1 and the second switch Q2 are turned off; when the off-time of the second switch Q2 reaches the preset first During the off time, the first switch tube Q1 is turned on, and the second switch tube Q2 is turned off.
  • the envelope phase of the current waveform of the boost inductor L1 can be effectively controlled and the alternating current
  • the envelope phases of the input waveforms of the power transmission network AC are matched, and at the same time, the reverse recovery of the body diode of the first switch transistor Q1 is controllable, and the reverse loss of the first switch transistor Q1 is reduced.
  • the power factor correction circuit 100 operates in the negative half cycle of the AC input of the AC power transmission network AC.
  • the principle is: in the negative half cycle of the AC input of the AC transmission network AC, the third switch Q3 and the fourth switch Q4 are respectively turned on and off under the control of the control signal.
  • the first switch transistor Q1 and the second switch transistor Q2 work cyclically under the control of the control signal in the following working cycles: when the second switch transistor Q2 is turned on for a preset time During the third conduction time, both the first switch Q1 and the second switch Q2 are turned off; when the ZVS1 level is negative, the first switch Q1 is turned on, and the second switch Q2 is turned off; when the first switch When the turn-on time of the tube Q1 reaches the preset fourth turn-on time, both the first switch tube Q1 and the switch tube are turned off; when the turn-off time of the first switch tube Q1 reaches the preset second turn-off time, The first switch tube Q1 is turned off, and the second switch tube Q2 is turned on.
  • the second embodiment provides a control device for the power factor correction circuit 100.
  • FIG. 3 which includes the AC transmission network AC, the controller 150, and the power factor correction circuit 100 of the first embodiment.
  • the controller 150 is connected to the first The rectifier circuit 110 , the second rectifier circuit 140 , the first detection circuit 120 and the second detection circuit 130 are used to output switch control signals to the first rectifier circuit 110 and the second rectifier circuit 140 to control the first rectifier circuit 110 and the second rectifier circuit 140
  • the second rectifier circuit 140 is turned on or off, and when receiving the first level or the second level, it outputs a switch control signal to control the first rectifier circuit 110 to be turned on or off, so that the power factor correction circuit 100 operates in the critical mode , so that the whole loop runs in the critical mode, which is stable and reliable.
  • the controller 150 is respectively connected to the anode of the first Zener diode Z1, the anode of the second Zener diode Z2, the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4.
  • the controller 150 includes four control terminals (c_1, c_2, c_3 and c_4) and two receiving terminals (r_1 and r_2).
  • the switch control signal is output to the first switch tube Q1 through the control terminal c_1, the switch control signal is output to the second switch tube Q2 through the control terminal c_2, the switch control signal is output to the third switch tube Q3 through the control terminal c_3, and the switch control signal is controlled by
  • the terminal c_4 is output to the fourth switch transistor Q4.
  • the first level output by the first detection circuit 120 is received by the receiving terminal r_1, and the second level output by the second detection circuit 130 is received by the receiving terminal r_2.
  • the switch control signal output by the controller 150 includes a first control signal, a second control signal, a third control signal, a fourth control signal and a fifth control signal. Both the first control signal and the fifth control signal are output to the third switch tube Q3 through the control terminal c_3, and are both output to the fourth switch tube Q4 through the control terminal c_4.
  • the second control signal, the third control signal and the fourth control signal are all output to the first switch transistor Q1 through the control terminal c_1, and are all output to the second switch transistor Q2 through the control terminal c_2.
  • the first control signal is: the third switch tube Q3 is turned off, and the fourth switch tube Q4 is turned on.
  • the second control signal is: the first switch tube Q1 is turned off, and the second switch tube Q2 is turned off.
  • the third control signal is: the first switch tube Q1 is turned off, and the second switch tube Q2 is turned on.
  • the fourth control signal is: the first switch tube Q1 is turned on, and the second switch tube Q2 is turned off.
  • the fifth control signal is: the third switch tube Q3 is turned on, and the fourth switch tube Q4 is turned off.
  • the controller 150 outputs the first control signal to the third switch transistor Q3 and the fourth switch transistor Q4.
  • the controller 150 outputs a second control signal to the first switch when the on-time of the first switch Q1 reaches the preset first on-time or the on-time of the second switch Q2 reaches the preset second on-time.
  • the controller 150 When receiving the second level, the controller 150 outputs a third control signal to the first switch transistor Q1 and the second switch transistor Q2.
  • the controller 150 outputs a fourth control signal to the first switch transistor Q1 and the second switch transistor Q2 when the off time of the second switch transistor Q2 reaches the preset first off time.
  • the controller 150 outputs the fifth control signal to the third switch transistor Q3 and the fourth switch transistor Q4.
  • the controller 150 outputs the second control signal to the first switch when the on-time of the second switch Q2 reaches the preset third on-time or when the on-time of the first switch Q1 reaches the preset fourth on-time.
  • the controller 150 outputs a third control signal to the first switch transistor Q1 and the second switch transistor Q2 when the off time of the first switch transistor Q1 reaches a preset second off time period.
  • the controller 150 outputs a fourth control signal to the first switch transistor Q1 and the second switch transistor Q2 when receiving the first level.
  • the envelope phase of the current waveform of the boost inductor L1 can be controlled to match the envelope phase of the input waveform of the alternating current transmission network AC, and at the same time, the The reverse recovery of the body diodes of the first switch Q1 and the second switch Q2 is controllable, thereby controlling the power factor correction circuit 100 to work in a critical mode.
  • a control method of the power factor correction circuit 100 can be obtained, and the control method includes:
  • the controller 150 outputs the first control signal to the third switch Q3 and the fourth switch Q4, and the third switch Q3 and the fourth switch Q4 respond to the first control signal respectively turn off and on;
  • the controller 150 outputs a second control signal to the first switch transistor Q1 and the second switch transistor Q2 when the on-time of the first switch transistor Q1 reaches a preset first on-time time, and the first switch transistor Q1 and the second switch transistor Q1 Tube Q2 is turned off in response to the second control signal;
  • the controller 150 outputs a third control signal to the first switch tube Q1 and the second switch tube Q2 when receiving the second level, and the first switch tube Q1 and the second switch tube Q2 are turned off and turned on respectively in response to the third control signal. Pass;
  • the controller 150 outputs a second control signal to the first switch transistor Q1 and the second switch transistor Q2 when the on-time of the second switch transistor Q2 reaches a preset second on-time time, and the first switch transistor Q1 and the second switch transistor Q1 Tube Q2 is turned off in response to the second control signal;
  • the controller 150 outputs a fourth control signal to the first switch transistor Q1 and the second switch transistor Q2 when the off-time of the second switch transistor Q2 reaches the preset first off time period.
  • the first switch transistor Q1 and the second switch transistor Q1 The tube Q2 is turned on and off respectively in response to the fourth control signal;
  • the controller 150 outputs the fifth control signal to the third switch Q3 and the fourth switch Q4, and the third switch Q3 and the fourth switch Q4 respond to the first control signal respectively turn on and off;
  • the controller 150 outputs a second control signal to the first switch transistor Q1 and the second switch transistor Q2 when the on-time of the second switch transistor Q2 reaches the preset third on-time time, and the first switch transistor Q1 and the second switch transistor Q1 Tube Q2 is turned off in response to the second control signal;
  • the controller 150 outputs a fourth control signal to the first switch transistor Q1 and the second switch transistor Q2 when receiving the first level, and the first switch transistor Q1 and the second switch transistor Q2 are turned on and off respectively in response to the fourth control signal ;
  • the controller 150 outputs a second control signal to the first switch Q1 and the second switch Q2 when the on-time of the first switch Q1 reaches the preset fourth on-time, and the first switch Q1 and the second switch Tube Q2 is turned off in response to the second control signal;
  • the controller 150 outputs a third control signal to the first switch Q1 and the second switch Q2 when the first switch Q1 is turned off at a preset second off time, and the first switch Q1 and the second switch The tube Q2 is turned off and turned on respectively in response to the third control signal.
  • modules and units included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be realized; in addition, each functional module and unit The specific names are only for the convenience of distinguishing from each other, and are not used to limit the protection scope of the present invention.

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Abstract

一种功率因数校正电路（100），该电路包括升压电感（L1）、第一整流电路（110）、第一检测电路（120）、第二检测电路（130）、第二整流电路（140）和滤波电路（160），第一整流电路（110）在接收由外部控制器（150）输出的控制信号时导通或关断以控制功率因数校正电路（100）工作在临界模式，控制信号由外部控制器（150）在接收到第一检测电路（120）输出的第一电平或第二检测电路输出的第二电平时输出；第一整流电路（110）和第二整流电路（140）用于将从交流输电网输出的交流电压转换为脉动直流电压；滤波电路（160）用于过滤脉动直流电压中的交流电压。

Description

一种功率因数校正电路及其控制装置和控制方法 技术领域
本发明涉及开关电源电力电子领域，尤其涉及一种功率因数校正电路、控制装置及方法。
背景技术
针对目前超高效的一次模块，前级往往采用图腾柱无桥PFC(Power Factor Correction，即功率因数校正)电路对输入AC电流进行整形，使输入电流为与输入电压同相位的近似正弦波以达到输入功率接近1的可能。传统的图腾柱无桥PFC电路如图1所示，通常采用临界控制模式或者连续控制模式。连续控制模式对晶体管特征要求较高，Si-MOS的反向恢复无法可靠实现连续控制模式，只能采用GAN、SIC等第三代半导体器件，但第三代半导体器件因使用规格不大、成本高、可靠性存疑等问题无法批量使用。临界控制模式是在电感电流无限接近零时关断晶体管，电流继续流经晶体管的体二极管，利用晶休管的体二极管的反向恢复特性实现软开关，然而由于流经晶体管体二极管的反向恢复是不可控的，使得难以控制图腾柱无桥PFC电路工作在临界模式。
发明内容
为了克服现有技术的不足，本发明的目的之一在于提供一种功率因数校正电路，其通过第一整流电路在接收由外部控制器输出的控制信号时导通或关断以控制功率因数校正电路工作在临界模式，该控制信号由外部控制器根据第一检测电路输出的第一电平或第二检测电路输出的第二电平得到，可以 有效控制功率因数校正电路工作在临界模式。
本发明的目的之一采用以下技术方案实现：
一种功率因数校正电路，包括：升压电感、第一整流电路、第一检测电路、第二检测电路、第二整流电路和滤波电路；
所述升压电感，其一端连接至交流输电网的一端，另一端与所述第一整流电路的中点连接，用于将从交流输电网输出的电压进行升压；
所述第一整流电路，其一端连接至所述滤波电路的一端，另一端连接至所述滤波电路的另一端，且控制端连接至外部控制器，用于在接收由外部控制器输出的控制信号时导通或关断以控制所述功率因数校正电路工作在临界模式，其中，所述控制信号由外部控制器在接收到第一电平或第二电平时输出；
所述第一检测电路，其一端连接至所述滤波电路的一端，另一端连接至所述第一整流电路的中点，且输出端连接至所述外部控制器，用于当所述第一整流电路的中点的电流反向时输出第一电平至所述外部控制器；
所述第二检测电路，其一端连接至所述滤波电路的另一端，另一端连接至所述第一整流电路的中点，且输出端连接至所述外部控制器，用于当所述第一整流电路的中点的电流反向时输出第二电平至所述外部控制器；
所述第二整流电路，其一端连接至所述滤波电路的一端，另一端连接至所述滤波电路的另一端，其中点连接至所述交流输电网的另一端；
所述第一整流电路和所述第二整流电路，用于将从所述交流输电网输出的交流电压转换为脉动直流电压；
所述滤波电路用于过滤所述脉动直流电压中的交流电压。
进一步地，所述第一整流电路包括：
第一开关管，包括第一控制端、第一源端和第一漏端，所述第一控制端连接至所述外部控制器，所述第一漏端连接所述滤波电路的一端，所述第一源端连接所述升压电感的另一端；
第二开关管，包括第二控制端、第二源端和第二漏端，所述第二控制端连接至所述外部控制器，所述第二漏端连接所述升压电感的另一端，所述第二源端连接所述滤波电路的另一端；
所述第一控制端和所述第二控制端用于接收外部控制器的控制信号，在控制信号控制下所述第一开关管和第二开关管交替导通，以控制所述功率因数校正电路工作在临界模式，在所述临界模式中，所述第一开关管或所述第二开关管的体二极管由反向恢复状态变为截止状态。
进一步地，所述第一检测电路包括第一限流电阻、第一储能电容、第一稳压二极管和第一放电电阻；
所述第一限流电阻和第一储能电容串联在所述第一整流电路的中点和所述第一稳压二极管的正极之间，所述第一稳压二极管和所述第一放电电阻并联，且所述第一稳压二极管的正极和负极分别连接至所述外部控制器和所述滤波电路的一端；
所述第一稳压二极管的正极用于当所述第一整流电路的中点的电流从所述升压电感流向所述第二开关管变为从所述第二开关管流向所述升压电感时输出所述第一电平至所述外部控制器。
进一步地，所述第二检测电路包括第二限流电阻、第二储能电容、第二稳压二极管和第二放电电阻；
所述第二限流电阻和第二储能电容串联在所述第一整流电路的中点和所述第二稳压二极管的正极之间，所述第二稳压二极管和所述第二放电电阻并 联，且所述第二稳压二极管的正极和负极分别连接至所述外部控制器和所述滤波电路的另一端；
所述第二稳压二极管的正极用于当所述第一整流电路的中点的电流从所述升压电感流向所述第一开关管变为从所述第一开关管流向所述升压电感时输出所述第二电平至所述外部控制器。
进一步地，所述第一开关管和所述第二开关管分别为Si_MOS、SIC_MOS、GAN_MOS和IGBT中的任意一种。
进一步地，所述第二整流电路包括：
第三开关管，包括第三控制端、第三源端和第三漏端，所述第三控制端连接至所述外部控制器，所述第三漏端连接所述滤波电路的一端，所述第三源端连接至所述交流输电网的另一端；
第四开关管，包括第四控制端、第四源端和第四漏端，所述第四控制端连接至所述外部控制器，所述第四漏端连接至所述交流输电网的另一端，所述第四源端连接所述滤波电路的另一端；
所述第三控制端和所述第四控制端用于接收外部控制器的控制信号，在控制信号控制下所述第三开关管和第四开关管交替导通以控制在从所述交流输电网的交流输出正半周时所述第三开关管和所述第四开关管分别关断和导通，以及在从所述交流输电网的交流输出负半周时所述第三开关管和所述第四开关管分别导通和关断。
进一步地，所述第三开关管和所述第四开关管分别为Si_MOS、SIC_MOS、GAN_MOS、IGBT和二极管中的任意一种。
进一步地，所述滤波电路包括母线电容，所述母线电容的正极和负极分别连接所述第一检测电路和所述第二检测电路。
本发明的目的之二在于提供一种功率因数校正电路的控制装置，通过控制器在接收到第一检测电路输出的第一电平或第二检测电路输出的第二电平时输出开关控制信号，以控制第一整流电路导通或关断使功率因数校正电路工作在临界模式，稳定可靠。
本发明的目的之二采用以下技术方案实现：
一种功率因数校正电路的控制装置，包括交流输电网、控制器以及本发明的目的之一的功率因数校正电路，其中，所述控制器分别连接所述第一整流电路、所述第二整流电路、所述第一检测电路和所述第二检测电路，用于输出对所述第一整流电路和所述第二整流电路的开关控制信号，以控制所述第一整流电路和所述第二整流电路导通或关断，以及在接收到所述第一电平或所述第二电平时输出开关控制信号以控制所述第一整流电路导通或关断使所述功率因数校正电路工作在临界模式。
本发明的目的之三在于提供一种功率因数校正电路的控制方法，其通过第一开关管和第二开关管交替地导通或关断以控制升压电感的电流波形的包络相位与交流输电网的输入波形的包络相位相吻合，同时使第一开关管和第二开关管的体二极管反向恢复可控，进而控制功率因数校正电路工作在临界模式。
本发明的目的之三采用以下技术方案实现：
在交流输电网的交流输入正半周中，控制器输出第一控制信号至第三开关管和第四开关管，所述第三开关管和所述第四开关管响应所述第一控制信号分别关断和导通；
所述控制器在所述第一开关管导通的时间达到预设的第一导通时间时输出第二控制信号至第一开关管和第二开关管，所述第一开关管和所述第二开 关管响应所述第二控制信号均关断；
所述控制器在接收到第二电平时输出第三控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第三控制信号分别关断和导通；
所述控制器在所述第二开关管导通的时间达到预设的第二导通时间时输出第二控制信号至第一开关管和第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
所述控制器在所述第二开关管关断的时间达到预设的第一关断时间时输出第四控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第四控制信号分别导通和关断；
在交流输电网的交流输入负半周中，控制器输出第五控制信号至所述第三开关管和所述第四开关管，所述第三开关管和所述第四开关管响应所述第一控制信号分别导通和关断；
所述控制器在所述第二开关管导通的时间达到预设的第三导通时间时输出第二控制信号至第一开关管和第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
所述控制器在接收到第一电平时输出第四控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第四控制信号分别导通和关断；
所述控制器在所述第一开关管导通的时间达到预设的第四导通时间时输出第二控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
所述控制器在所述第一开关管关断的时间达到预设的第二关断时间时输 出第三控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第三控制信号分别关断和导通。
相比现有技术，本发明的有益效果在于：
本发明通过外部控制器根据第一检测电路输出的第一电平或第二检测电路输出的第二电平产生的控制信号，第一整流电路在接收控制信号时导通或关断进而有效控制功率因数校正电路工作在临界模式，电路简单，高效可靠。
附图说明
图1为一种图腾柱无桥PFC电路；
图2为本发明实施例一的功率因数校正电路的电路原理图；
图3为本发明实施例二的功率因数校正电路的控制装置的结构示意图。
图中：100、功率因数校正电路；110、第一整流电路；120、第一检测电路；130、第二检测电路；140、第二整流电路；150、控制器；160、滤波电路；AC、交流输电网。
具体实施方式
以下将结合附图，对本发明进行更为详细的描述，需要说明的是，以下参照附图对本发明进行的描述仅是示意性的，而非限制性的。各个实施例中的限流电阻、放电电阻和负载电阻均为电阻网络，可以是一个电阻元件，也可以是由若干个阻值不同和/或相同的电阻元件串联和/或并联的电路，升压电感为电感网络，可以是一个电感元件，也可以是由若干个阻值不同和/或相同的电感元件串联和/或并联的电路，储能电容为电容网络，可以是一个电容元件，也可以是由若干个阻值不同和/或相同的电容元件串联和/或并联的电路。各个不同实施例之间可以进行相互组合，以构成未在以下描述中示出的 其他实施例。
实施例一
实施例一提供了一种功率因数校正电路100，可以有效地控制功率因数校正电路100工作在临界模式，高效可靠，请参照图2所示，功率因数校正电路100包括升压电感L1、第一整流电路110、第一检测电路120、第二检测电路130、第二整流电路140和滤波电路160。升压电感L1的一端连接至交流输电网AC的一端，另一端与第一整流电路110的中点连接，用于将从交流输电网AC输出的电压进行升压。
第一整流电路110的一端连接至滤波电路160的一端，另一端连接至滤波电路160的另一端，且控制端连接至外部控制器150，用于在接收由外部控制器150输出的控制信号时导通或关断以控制功率因数校正电路100工作在临界模式，控制信号由外部控制器150在接收到第一电平或第二电平时输出。
第一检测电路120的一端连接至滤波电路160的一端，另一端连接至第一整流电路110的中点，且输出端连接至外部控制器150，用于当第一整流电路110的中点的电流反向时输出第一电平至外部控制器150。
第二检测电路130的一端连接至滤波电路160的另一端，另一端连接至第一整流电路110的中点，且输出端连接至外部控制器150，用于当第一整流电路110的中点的电流反向时输出第二电平至外部控制器150。
第二整流电路140的一端连接至滤波电路160的一端，另一端连接至滤波电路160的另一端，其中点连接至交流输电网AC的另一端。
第一整流电路110和第二整流电路140将从交流输电网AC输出的交流电压转换为脉动直流电压，滤波电路160过滤脉动直流电压中的交流电压。
在其他的一些实施例中，通过第一开关管Q1和第二开关管Q2交替地导通或关断以控制升压电感L1的电流波形的包络相位与交流输电网AC的输入波形的包络相位相吻合，同时可以消除第一开关管Q1的体二极管反向恢复的不可控性，使控制功率因数校正电路100可以工作在临界模式，还能减小反向恢复引起的损耗，高效可靠，并且第一检测电路120与第二检测电路130结构相同，可以进行模块化生产，方便安装及更换。
第一整流电路110包括第一开关管Q1和第二开关管Q2。第一开关管Q1包括第一控制端、第一源端和第一漏端，第一控制端连接至外部控制器150，第一漏端连接滤波电路160的一端，第一源端连接升压电感L1的另一端。第二开关管Q2包括第二控制端、第二源端和第二漏端，第二控制端连接至外部控制器150，第二漏端连接升压电感L1的另一端，第二源端连接滤波电路160的另一端。
第一控制端和第二控制端用于接收外部控制器150的控制信号，在控制信号控制下第一开关管Q1和第二开关管Q2交替导通，以控制功率因数校正电路100工作在临界模式，在临界模式中，第一开关管Q1或第二开关管Q2的体二极管由反向恢复状态变为截止状态。
本实施例中第一开关管Q1和第二开关管Q2均为Si_MOS管，即采用硅基的超级节MOS，可以有效降低电路成本。
作为可选的技术方案，第一开关管Q1和第二开关管Q2可以分别为IGBT、SIC、GAN和IGBT等半导体开关器件中的任意一种。
第一检测电路120包括第一限流电阻R1、第一储能电容C1、第一稳压二极管Z1和第一放电电阻R2。第一限流电阻R1和第一储能电容C1串联在第一整流电路110的中点和第一稳压二极管Z1的正极之间，第一稳压二极 管Z1和第一放电电阻R2并联，且第一稳压二极管Z1的正极和负极分别连接至外部控制器150和滤波电路160的一端。第一稳压二极管Z1的正极当第一整流电路110的中点的电流从升压电感L1流向第二开关管Q2变为从第二开关管Q2流向升压电感L1时输出第一电平至外部控制器150。
第二检测电路130包括第二限流电阻R3、第二储能电容C2、第二稳压二极管Z2和第二放电电阻R4。第二限流电阻R3和第二储能电容C2串联在第一整流电路110的中点和第二稳压二极管Z2的正极之间，第二稳压二极管Z2和第二放电电阻R4并联，且第二稳压二极管Z2的正极和负极分别连接至外部控制器150和滤波电路160的另一端。第二稳压二极管Z2的正极用于当第一整流电路110的中点的电流从升压电感L1流向第一开关管Q1变为从第一开关管Q1流向升压电感L1时输出第二电平至外部控制器150。
第二整流电路140包括第三开关管Q3和第四开关管Q4。第三开关管Q3包括第三控制端、第三源端和第三漏端，第三控制端连接至外部控制器150，第三漏端连接滤波电路160的一端，第三源端连接至交流输电网AC的另一端。第四开关管Q4包括第四控制端、第四源端和第四漏端，第四控制端连接至外部控制器150，第四漏端连接至交流输电网AC的另一端，第四源端连接滤波电路160的另一端。
第三控制端和第四控制端用于接收外部控制器150的控制信号，在控制信号控制下第三开关管Q3和第四开关管Q4交替导通，以控制在从交流输电网AC的交流输出正半周时第三开关管Q3和第四开关管Q4分别关断和导通，以及在从交流输电网AC的交流输出负半周时第三开关管Q3和第四开关管Q4分别导通和关断。
本实施例中第三开关管Q3和第四开关管Q4均为Si_MOS管，即采用硅 基的超级节MOS，可以有效降低电路成本。
作为可选的技术方案，第三开关管Q3和第四开关管Q4可以分别为IGBT、SIC、GAN和二极管等半导体开关器件中的任意一种。
滤波电路160包括母线电容C3，母线电容C3的正极和负极分别连接第一检测电路120和第二检测电路130。
功率因数校正电路还包括负载电路，本实施例中负载电路包括负载电阻R5，负载电阻R5与滤波电路160并联。需要注意的是，负载电路不限于上述类型。
将第二稳压二极管Z2的正极的电平相对于母线电容C3的负极的电平记为ZVS2电平。功率因数校正电路100在交流输电网AC的交流输入正半周中的工作原理为：在交流输电网AC的交流输入正半周中，第三开关管Q3和第四开关管Q4在控制信号控制下分别关断和导通。在功率因数校正电路100工作在交流输电网AC的交流输入从负半周变为正半周时，第一开关管Q1和第二开关管Q2在控制信号控制下分别关断和导通，交流电压施加在升压电感L1两端，第一整流电路110的中点的电平相对与母线电容C3的负极的电平为零，升压电感L1中的电流从零开始线性上升，电流从交流输电网AC流向升压电感L1流向第二开关管Q2流向第四开关管Q4流向交流输电网AC，ZVS2电平为零。
当第二开关管Q2导通的时间达到预设的第二导通时间时，第一开关管Q1和第二开关管Q2在控制信号控制下均关断，第一整流电路110的中点的电压快速上升至母线电容C3电压时，第一开关管Q1的体二极管导通，同时向第二储能电容C2充电，电流从交流输电网AC流向升压电感L1流向第一开关管Q1流向母线电容C3流向第四开关管Q4流向交流输电网AC，同时 电流从交流输电网AC流向升压电感L1流向第二储能电容C2流向第二稳压二极管Z2流向第四开关管Q4流向交流输电网AC，ZVS2电平为第二稳压二极管Z2的正向导通压降。
当第二开关管Q2关断的时间达到预设的第一关断时间时，第一开关管Q1和第二开关管Q2在控制信号控制下分别导通和关断，升压电感L1中的电流线性下降，第二储能电容C2处于充电状态，电流从交流输电网AC流向升压电感L1流向第一开关管Q1流向母线电容C3流向第四开关管Q4流向交流输电网AC，ZVS2电平为零。
当第一开关管Q1导通的时间达到预设的第一导通时间时，第一开关管Q1和第二开关管Q2均关断，即将第一开关管Q1和第二开关管Q2在升压电感L1中的电流未下降到零时提前关断，此时第一开关管Q1的体二极管反向恢复，因为升压电感L1中的电流不能突变，升压电感L1中的电流反向同时给第二开关管Q2的结电容放电、第一开关管Q1的结电容充电，第二储能电容C2放电，电流从第一开关管Q1流向升压电感L1流向交流输电网AC流向第四开关管Q4流向母线电容C3流向第一开关管Q1，同时电流从第二储能电容C2流向升压电感L1流向交流输电网AC流向第四开关管Q4流向第二放电电阻R4流向第二储能电容C2，ZVS2电平为负电平。
此时第一整流电路110的中点的电流从升压电感L1流向第一开关管Q1变为从第一开关管Q1流向升压电感L1，升压电感L1中的电流从交流输电网AC流向第一整流电路110的中点变为从第一整流电路110的中点流向交流输电网AC，即升压电感L1中的电流发生反向，第二稳压二极管Z2的正极输出相对于母线电容C3的负极的电平降为负电平的第二电平至外部控制器150。第一开关管Q1和第二开关管Q2在外部控制器150的控制信号下分 别关断和导通，第一开关管Q1的体二极管由反向恢复状态变为截止状态，升压电感L1中的电流恢复为从交流输电网AC流向第一整流电路110的中点，第一整流电路110的中点的电流从升压电感L1流向第二开关管Q2，同时第二开关管Q2的两端压降为零，第二稳压二极管Z2的正极的电平相对于母线电容C3的负极的电平也为零。
此后，在交流输电网AC的交流输入正半周中，第一开关管Q1和第二开关管Q2在控制信号控制下循环工作在以下工作周期中：当第一开关管Q1导通的时间达到预设的第一导通时间时，第一开关管Q1和第二开关管Q2均关断；当ZVS2电平为负电平时，第一开关管Q1关断，第二开关管Q2导通；当第二开关管Q2导通的时间达到预设的第二导通时间时，第一开关管Q1和第二开关管Q2均关断；当第二开关管Q2关断的时间达到预设的第一关断时间时，第一开关管Q1导通，第二开关管Q2关断。
通过上述第一开关管Q1和第二开关管Q2的交替导通或关断，可以在交流输电网AC的交流输入正半周中，有效地控制升压电感L1的电流波形的包络相位与交流输电网AC的输入波形的包络相位相吻合，同时使得第一开关管Q1的体二极管反向恢复可控，降低第一开关管Q1的反向损耗。
同样地，在将第一稳压二极管Z1的正极的电平相对于母线电容C3的正极的电平记为ZVS1电平，功率因数校正电路100在交流输电网AC的交流输入负半周中的工作原理为：交流输电网AC的交流输入负半周中，第三开关管Q3和第四开关管Q4在控制信号控制下分别导通和关断，当第一整流电路110的中点的电流从升压电感L1流向第二开关管Q2变为从第二开关管Q2流向升压电感L1时，ZVS1电平为负电平，第一稳压二极管Z1的正极输出相对于母线电容C3的正极的电平降为负电平的第一电平至外部控制器 150，第一开关管Q1和第二开关管Q2在外部控制器150的控制信号下分别导通和关断，第二开关管Q2的体二极管由反向恢复状态变为截止状态，升压电感L1中的电流恢复为从交流输电网AC流向第一整流电路110的中点，第一整流电路110的中点的电流从升压电感L1流向第一开关管Q1，同时第一开关管Q1的两端压降为零，第一稳压二极管Z1的正极的电平相对于母线电容C3的正极的电平也为零。
在交流输电网AC的交流输入负半周中，第一开关管Q1和第二开关管Q2在控制信号控制下循环工作在以下工作周期中：当第二开关管Q2导通的时间达到预设的第三导通时间时，第一开关管Q1和第二开关管Q2均关断；当ZVS1电平为负电平时，第一开关管Q1导通，第二开关管Q2关断；当第一开关管Q1导通的时间达到预设的第四导通时间时，第一开关管Q1和开关管均关断；当第一开关管Q1关断的时间达到预设的第二关断时间时，第一开关管Q1关断，第二开关管Q2导通。
实施例二
实施例二提供了一种功率因数校正电路100的控制装置，请参照图3所示，包括交流输电网AC、控制器150以及实施例一的功率因数校正电路100，控制器150分别连接第一整流电路110、第二整流电路140、第一检测电路120和第二检测电路130，用于输出对第一整流电路110和第二整流电路140的开关控制信号，以控制第一整流电路110和第二整流电路140导通或关断，以及在接收到第一电平或第二电平时输出开关控制信号以控制第一整流电路110导通或关断使功率因数校正电路100工作在临界模式，使环路整个运行在临界模式下，稳定可靠。
优选地，控制器150分别连接第一稳压二极管Z1的正极、第二稳压二 极管Z2的正极、第一开关管Q1、第二开关管Q2、第三开关管Q3和第四开关管Q4。
控制器150包括四个控制端(c_1、c_2、c_3和c_4)和两个接收端(r_1和r_2)。开关控制信号通过控制端c_1输出至第一开关管Q1，开关控制信号通过控制端c_2输出至第二开关管Q2，开关控制信号通过控制端c_3输出至第三开关管Q3，开关控制信号通过控制端c_4输出至第四开关管Q4。第一检测电路120输出的第一电平由接收端r_1接收，第二检测电路130输出的第二电平由接收端r_2接收。
控制器150输出的开关控制信号包括第一控制信号、第二控制信号、第三控制信号、第四控制信号和第五控制信号。第一控制信号和第五控制信号均通过控制端c_3输出至第三开关管Q3，并且均通过控制端c_4输出至第四开关管Q4。第二控制信号、第三控制信号和第四控制信号均通过控制端c_1输出至第一开关管Q1，并且均通过控制端c_2输出至第二开关管Q2。
第一控制信号为：第三开关管Q3关断，第四开关管Q4导通。
第二控制信号为：第一开关管Q1关断，第二开关管Q2关断。
第三控制信号为：第一开关管Q1关断，第二开关管Q2导通。
第四控制信号为：第一开关管Q1导通，第二开关管Q2关断。
第五控制信号为：第三开关管Q3导通，第四开关管Q4关断。
在交流输电网AC的交流输入正半周中，控制器150输出第一控制信号至第三开关管Q3和第四开关管Q4。控制器150在第一开关管Q1导通的时间达到预设的第一导通时间或者第二开关管Q2导通的时间达到预设的第二导通时间时，输出第二控制信号至第一开关管Q1和第二开关管Q2。控制器150在接收到第二电平时，输出第三控制信号至第一开关管Q1和第二开关管 Q2。控制器150在第二开关管Q2关断的时间达到预设的第一关断时间时输出第四控制信号至第一开关管Q1和第二开关管Q2。
在交流输电网AC的交流输入负半周中，控制器150输出第五控制信号至第三开关管Q3和第四开关管Q4。控制器150在第二开关管Q2导通的时间达到预设的第三导通时间或者第一开关管Q1导通的时间达到预设的第四导通时间时，输出第二控制信号至第一开关管Q1和第二开关管Q2。控制器150在第一开关管Q1关断的时间达到预设的第二关断时间时，输出第三控制信号至第一开关管Q1和第二开关管Q2。控制器150在接收到第一电平时输出第四控制信号至第一开关管Q1和第二开关管Q2。
通过第一开关管Q1和第二开关管Q2交替地导通或关断可以控制升压电感L1的电流波形的包络相位与交流输电网AC的输入波形的包络相位相吻合，同时使第一开关管Q1和第二开关管Q2的体二极管反向恢复可控，进而控制功率因数校正电路100工作在临界模式。
实施例三
根据实施例二的电路结构和工作原理，可以得到一种功率因数校正电路100的控制方法，该控制方法包括：
在交流输电网AC的交流输入正半周中，控制器150输出第一控制信号至第三开关管Q3和第四开关管Q4，第三开关管Q3和第四开关管Q4响应第一控制信号分别关断和导通；
控制器150在第一开关管Q1导通的时间达到预设的第一导通时间时输出第二控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第二控制信号均关断；
控制器150在接收到第二电平时时输出第三控制信号至第一开关管Q1和第 二开关管Q2，第一开关管Q1和第二开关管Q2响应第三控制信号分别关断和导通；
控制器150在第二开关管Q2导通的时间达到预设的第二导通时间时输出第二控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第二控制信号均关断；
控制器150在第二开关管Q2关断的时间达到预设的第一关断时间时输出第四控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第四控制信号分别导通和关断；
在交流输电网AC的交流输入负半周中，控制器150输出第五控制信号至第三开关管Q3和第四开关管Q4，第三开关管Q3和第四开关管Q4响应第一控制信号分别导通和关断；
控制器150在第二开关管Q2导通的时间达到预设的第三导通时间时输出第二控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第二控制信号均关断；
控制器150在接收到第一电平时输出第四控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第四控制信号分别导通和关断；
控制器150在第一开关管Q1导通的时间达到预设的第四导通时间时输出第二控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第二控制信号均关断；
控制器150在第一开关管Q1关断的时间达到预设的第二关断时间时输出第三控制信号至第一开关管Q1和第二开关管Q2，第一开关管Q1和第二开关管Q2响应第三控制信号分别关断和导通。
值得注意的是，上述实施例中，所包括的各个模块和单元只是按照功能逻 辑进行划分的，但并不局限于上述的划分，只要能够实现相应的功能即可；另外，各功能模块和单元的具体名称也只是为了便于相互区分，并不用于限制本发明的保护范围。
对本领域的技术人员来说，可根据以上描述的技术方案以及构思，做出其它各种相应的改变以及形变，而所有的这些改变以及形变都应该属于本发明权利要求的保护范围之内。

Claims (10)

  1. 一种功率因数校正电路，其特征在于，包括：升压电感、第一整流电路、第一检测电路、第二检测电路、第二整流电路和滤波电路；
    所述升压电感，其一端连接至交流输电网的一端，另一端与所述第一整流电路的中点连接，用于将从交流输电网输出的电压进行升压；
    所述第一整流电路，其一端连接至所述滤波电路的一端，另一端连接至所述滤波电路的另一端，且控制端连接至外部控制器，用于在接收由外部控制器输出的控制信号时导通或关断以控制所述功率因数校正电路工作在临界模式，其中，所述控制信号由外部控制器在接收到第一电平或第二电平时输出；
    所述第一检测电路，其一端连接至所述滤波电路的一端，另一端连接至所述第一整流电路的中点，且输出端连接至所述外部控制器，用于当所述第一整流电路的中点的电流反向时输出第一电平至所述外部控制器；
    所述第二检测电路，其一端连接至所述滤波电路的另一端，另一端连接至所述第一整流电路的中点，且输出端连接至所述外部控制器，用于当所述第一整流电路的中点的电流反向时输出第二电平至所述外部控制器；
    所述第二整流电路，其一端连接至所述滤波电路的一端，另一端连接至所述滤波电路的另一端，其中点连接至所述交流输电网的另一端；
    所述第一整流电路和所述第二整流电路，用于将从所述交流输电网输出的交流电压转换为脉动直流电压；
    所述滤波电路用于过滤所述脉动直流电压中的交流电压。
  2. 如权利要求1所述的功率因数校正电路，其特征在于，所述第一整流电路包括：
    第一开关管，包括第一控制端、第一源端和第一漏端，所述第一控制端 连接至所述外部控制器，所述第一漏端连接所述滤波电路的一端，所述第一源端连接所述升压电感的另一端；
    第二开关管，包括第二控制端、第二源端和第二漏端，所述第二控制端连接至所述外部控制器，所述第二漏端连接所述升压电感的另一端，所述第二源端连接所述滤波电路的另一端；
    所述第一控制端和所述第二控制端用于接收外部控制器的控制信号，在控制信号控制下所述第一开关管和第二开关管交替导通，以控制所述功率因数校正电路工作在临界模式，在所述临界模式中，所述第一开关管或所述第二开关管的体二极管由反向恢复状态变为截止状态。
  3. 如权利要求2所述的功率因数校正电路，其特征在于，所述第一检测电路包括第一限流电阻、第一储能电容、第一稳压二极管和第一放电电阻；
    所述第一限流电阻和第一储能电容串联在所述第一整流电路的中点和所述第一稳压二极管的正极之间，所述第一稳压二极管和所述第一放电电阻并联，且所述第一稳压二极管的正极和负极分别连接至所述外部控制器和所述滤波电路的一端；
    所述第一稳压二极管的正极用于当所述第一整流电路的中点的电流从所述升压电感流向所述第二开关管变为从所述第二开关管流向所述升压电感时输出所述第一电平至所述外部控制器。
  4. 如权利要求2所述的功率因数校正电路，其特征在于，所述第二检测电路包括第二限流电阻、第二储能电容、第二稳压二极管和第二放电电阻；
    所述第二限流电阻和第二储能电容串联在所述第一整流电路的中点和所述第二稳压二极管的正极之间，所述第二稳压二极管和所述第二放电电阻并联，且所述第二稳压二极管的正极和负极分别连接至所述外部控制器和所述 滤波电路的另一端；
    所述第二稳压二极管的正极用于当所述第一整流电路的中点的电流从所述升压电感流向所述第一开关管变为从所述第一开关管流向所述升压电感时输出所述第二电平至所述外部控制器。
  5. 如权利要求2所述的功率因数校正电路，其特征在于，所述第一开关管和所述第二开关管分别为Si_MOS、SIC_MOS、GAN_MOS和IGBT中的任意一种。
  6. 如权利要求1所述的功率因数校正电路，其特征在于，所述第二整流电路包括：
    第三开关管，包括第三控制端、第三源端和第三漏端，所述第三控制端连接至所述外部控制器，所述第三漏端连接所述滤波电路的一端，所述第三源端连接至所述交流输电网的另一端；
    第四开关管，包括第四控制端、第四源端和第四漏端，所述第四控制端连接至所述外部控制器，所述第四漏端连接至所述交流输电网的另一端，所述第四源端连接所述滤波电路的另一端；
    所述第三控制端和所述第四控制端用于接收外部控制器的控制信号，在控制信号控制下所述第三开关管和第四开关管交替导通，以控制在从所述交流输电网的交流输出正半周时所述第三开关管和所述第四开关管分别关断和导通，以及在从所述交流输电网的交流输出负半周时所述第三开关管和所述第四开关管分别导通和关断。
  7. 如权利要求6所述的功率因数校正电路，其特征在于，所述第三开关管和所述第四开关管分别为Si_MOS、SIC_MOS、GAN_MOS、IGBT和二极管中的任意一种。
  8. 如权利要求1所述的功率因数校正电路，其特征在于，所述滤波电路包括母线电容，所述母线电容的正极和负极分别连接所述第一检测电路和所述第二检测电路。
  9. 一种功率因数校正电路的控制装置，其特征在于，包括交流输电网、控制器以及如权利要求1至8任一项所述的功率因数校正电路，其中，所述控制器分别连接所述第一整流电路、所述第二整流电路、所述第一检测电路和所述第二检测电路，用于输出对所述第一整流电路和所述第二整流电路的开关控制信号以控制所述第一整流电路和所述第二整流电路导通或关断，以及在接收到所述第一电平或所述第二电平时输出开关控制信号以控制所述第一整流电路导通或关断使所述功率因数校正电路工作在临界模式。
  10. 一种功率因数校正电路的控制方法，其特征在于，其包括以下步骤：
    在交流输电网的交流输入正半周中，控制器输出第一控制信号至第三开关管和第四开关管，所述第三开关管和所述第四开关管响应所述第一控制信号分别关断和导通；
    所述控制器在所述第一开关管导通的时间达到预设的第一导通时间时输出第二控制信号至第一开关管和第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
    所述控制器在接收到第二电平时输出第三控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第三控制信号分别关断和导通；
    所述控制器在所述第二开关管导通的时间达到预设的第二导通时间时输出第二控制信号至第一开关管和第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
    所述控制器在所述第二开关管关断的时间达到预设的第一关断时间时输出第四控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第四控制信号分别导通和关断；
    在交流输电网的交流输入负半周中，控制器输出第五控制信号至所述第三开关管和所述第四开关管，所述第三开关管和所述第四开关管响应所述第一控制信号分别导通和关断；
    所述控制器在所述第二开关管导通的时间达到预设的第三导通时间时输出第二控制信号至第一开关管和第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
    所述控制器在接收到第一电平时输出第四控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第四控制信号分别导通和关断；
    所述控制器在所述第一开关管导通的时间达到预设的第四导通时间时输出第二控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第二控制信号均关断；
    所述控制器在所述第一开关管关断的时间达到预设的第二关断时间时输出第三控制信号至所述第一开关管和所述第二开关管，所述第一开关管和所述第二开关管响应所述第三控制信号分别关断和导通。
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