WO2022033132A1 - 一种ook调制解调系统 - Google Patents

一种ook调制解调系统 Download PDF

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Publication number
WO2022033132A1
WO2022033132A1 PCT/CN2021/097806 CN2021097806W WO2022033132A1 WO 2022033132 A1 WO2022033132 A1 WO 2022033132A1 CN 2021097806 W CN2021097806 W CN 2021097806W WO 2022033132 A1 WO2022033132 A1 WO 2022033132A1
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signal
modulation
edge
ook
circuit
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PCT/CN2021/097806
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English (en)
French (fr)
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时传飞
吴建刚
应峰
陶园林
刘燕涛
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屹世半导体(上海)有限公司
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Priority claimed from CN202010807680.3A external-priority patent/CN111970220A/zh
Priority claimed from CN202021677172.XU external-priority patent/CN212381235U/zh
Application filed by 屹世半导体(上海)有限公司 filed Critical 屹世半导体(上海)有限公司
Publication of WO2022033132A1 publication Critical patent/WO2022033132A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/04—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits

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  • the invention relates to the field of signal modulation and demodulation, in particular to an OOK modulation and demodulation system.
  • the transmission media may be long-distance transmission lines, optocouplers, capacitors and other media. Due to the bad phenomena such as signal distortion and loss on the transmission channel, it is difficult for the baseband signal to receive the complete input signal at the receiving end. Therefore, OOK modulation is often used to move the signal spectrum to the high frequency where the transmission medium can pass. , so that the input signal is transmitted in the form of carrier wave, and finally a demodulation link is added at the receiver to demodulate the signal from the carrier wave.
  • OOK (On-Off Keying) modulation also known as binary amplitude keying modulation, uses a unipolar non-return-to-zero code sequence to control the opening and closing of the sinusoidal carrier.
  • the amplitude keying method is widely used in optical fiber communication systems and isolated circuit systems.
  • OOK modulation when OOK modulation is used, bit errors will occur when the frequency of the carrier signal is low, and the transmission signal cannot be sampled, and the edge delay between the input signal edge and the sampled carrier signal will also cause the PWD of the decoded signal to be uncontrollable. Therefore, the traditional OOK modulation method has the disadvantages of large PWD pulse width distortion, poor output eye diagram and high bit error rate.
  • the purpose of the present invention is to provide an OOK modulation and demodulation system, which includes a modulation module, a channel and a demodulation module, and adopts the processing method of edge synchronization, which solves the problem of inconsistent pulse widths before and after modulation-demodulation, reduces the The pulse width distortion is small and the bit error rate is reduced.
  • one aspect of the present invention provides an OOK modulation and demodulation system, including a modulation module, a channel and a demodulation module;
  • the modulation module includes an OOK modulator and a secondary modulation unit, and the OOK modulator is used for modulation of an input signal , output a primary modulation signal, the secondary modulation unit is connected with the OOK modulator, used to capture the edge pulse of the input signal and process the primary modulation signal to form a secondary modulation signal, the secondary modulation The signal is aligned with at least one edge of the input signal;
  • the channel is connected to the modulation module and the demodulation module, and is used for transmitting the secondary modulation signal to the demodulation module;
  • the demodulation module includes A demodulator and a signal restoration unit, the demodulator is used for demodulating the secondary modulated signal to obtain a demodulated signal, the signal restoration unit is connected with the demodulator, and is used for processing the demodulated signal after An output signal with the same pulse width as the input
  • the secondary modulation unit includes a double-edge pulse circuit and a first logic circuit; the double-edge pulse circuit is connected to the input signal, and generates double edges on the rising edge and the falling edge of the input signal. a pulse signal; the first logic circuit is connected to the double-edge pulse circuit and the OOK modulator, receives and processes the double-edge pulse signal and the first-level modulation signal, and outputs a single-edge alignment of the input signal of the secondary modulation signal.
  • the first logic circuit in the above system is an addition circuit.
  • the signal restoration unit in the above system includes a single-edge delay circuit.
  • the signal restoration unit in the above system includes a single-edge pulse circuit and a second logic circuit;
  • the single-edge pulse circuit is connected to the demodulator, receives the demodulated signal, and in the demodulated signal The rising edge or the falling edge generates a single-edge pulse signal;
  • the second logic circuit is connected to the single-edge pulse circuit and the demodulator, receives and processes the single-edge pulse signal and the demodulation signal, and outputs
  • the output signal has the same pulse width as the input signal.
  • the second logic circuit in the above system is a subtraction circuit.
  • the modulation module in the above system further includes a preprocessing unit, the preprocessing unit is located at the front end of the OOK modulator and the secondary modulation unit, and is used for preprocessing the input signal to form a relative
  • the preprocessed signal delayed by the single edge of the signal is output to the OOK modulator and the secondary modulation unit; the demodulation module does not include the signal restoration unit.
  • the preprocessing unit in the above system is a single edge delay circuit.
  • the secondary modulation unit includes a double-edge pulse circuit and a third logic circuit;
  • the double-edge pulse circuit is connected to the preprocessing unit, receives the preprocessed signal, and executes the preprocessed signal The rising edge and falling edge of the double edge pulse signal are generated;
  • the third logic circuit is connected with the double edge pulse circuit and the OOK modulator, receives and processes the double edge pulse signal and the first-level modulation signal,
  • the secondary modulation signal is output that is aligned with both edges of the input signal.
  • the third logic circuit in the above system is an addition circuit.
  • the pulse width of the double edge pulse circuit in the above system is equal to the pulse width of the modulated clock signal.
  • the demodulation module in the above system further includes a shaping circuit.
  • FIG. 1 is a schematic structural diagram of an OOK modulation and demodulation system in accordance with a preferred embodiment of the present invention
  • FIG. 2 is a waveform diagram of signals at all levels using an OOK modulation and demodulation system in accordance with a preferred embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of an OOK modulation and demodulation system in accordance with another preferred embodiment of the present invention.
  • Fig. 4 is the signal waveform diagram of each level of adopting the OOK modulation and demodulation system that conforms to another preferred embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an OOK modulation and demodulation system in accordance with another preferred embodiment of the present invention.
  • FIG. 6 is a signal waveform diagram of each stage using the OOK modulation and demodulation system according to another preferred embodiment of the present invention.
  • first, second, third, etc. may be used in this disclosure to describe various pieces of information, such information should not be limited by these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information, without departing from the scope of the present disclosure.
  • word "if” as used herein can be interpreted as "at the time of” or "when” or "in response to determining.”
  • FIG. 1 it is a schematic structural diagram of an OOK modulation and demodulation system according to a preferred embodiment of the present invention, including a modulation module, a channel and a demodulation module.
  • the modulation module includes an OOK modulator and a secondary modulation unit, wherein the OOK modulator is a traditional OOK modulator, receives an input signal and a clock signal, and modulates the input signal through the OOK modulator to output a primary modulation signal. Different from the traditional OOK modulator, the OOK modulator modulates the input signal to generate a first-level modulation signal, but this modulated signal is not directly transmitted through the channel, but is input to the second-level modulation unit for further processing.
  • the OOK modulator is a traditional OOK modulator, receives an input signal and a clock signal, and modulates the input signal through the OOK modulator to output a primary modulation signal.
  • the OOK modulator modulates the input signal to generate a first-level modulation signal, but this modulated signal is not directly transmitted through the channel, but is input to the second-level modulation unit for further processing.
  • the secondary modulation unit is connected to the OOK modulator, receives the input signal and the primary modulation signal, and captures the edge pulses of the input signal and processes the primary modulation signal to form a secondary modulation signal aligned with at least one edge of the input signal.
  • the fact that the secondary modulation signal is aligned with the input signal at least one edge does not mean that each pulse of the secondary modulation signal has at least one edge (rising edge/falling edge) aligned with the edge of the input signal, but at the input. In each pulse period corresponding to the signal, at least one pulse of the secondary modulation signal is aligned with the rising edge or the falling edge of the input signal.
  • the secondary modulated signal is the modulated signal.
  • the channel is connected with the modulation module and the demodulation module, and is used for transmitting the secondary modulation signal to the demodulation module.
  • the present invention does not limit the specific implementation of the channel, such as inductance, optocoupler, capacitor, twisted pair and other media, and is not restricted to a specific channel form, and different channel forms are within the scope of protection of this patent .
  • the demodulation module includes a demodulator, and the demodulator receives the secondary modulation signal and is used for demodulating the secondary modulation signal to obtain the demodulated signal, and does not directly input the demodulated signal after obtaining the demodulation signal, and the demodulation module also includes a signal restoration unit, The signal restoration unit is connected with the demodulator, and is used for processing the demodulation signal, removing the part of the demodulation signal that is higher than the pulse width of the input signal, and restoring the demodulation signal to an output signal with the same pulse width as the input signal.
  • the input signal modulated by the OOK modulator is subjected to secondary processing by the secondary modulation module, so as to obtain a secondary modulation signal aligned with at least a single edge of the input signal, and transmit the signal to the demodulation module for demodulation.
  • the module is reprocessed by the signal restoration unit to restore the pulse width of the output signal and obtain an output signal with the same pulse width as the output signal, thereby realizing the edge synchronization between the input signal and the output signal, effectively reducing the
  • the problems of pulse width distortion and bit error rate of the signal before and after modulation-demodulation are solved.
  • the secondary modulation unit includes a double edge pulse circuit and a first logic circuit;
  • the double edge pulse circuit receives the input signal, captures the rising edge and the falling edge of the input signal, A pulse signal is generated on the rising and falling edges of the input signal, that is, a double-edge pulse signal;
  • the first logic circuit is connected to the double-edge pulse circuit and the OOK modulator, receives and processes the double-edge pulse signal and the first-level modulation signal, and uses The double-edge pulse signal is added to the first-level modulation signal.
  • the output second-level modulation signal is the same as the one described above.
  • the input signal is single-edge-aligned. As mentioned above, single-edge-alignment does not mean that each pulse of the secondary modulation signal has an edge (rising edge/falling edge) aligned with the edge of the input signal. Within each pulse period, the secondary modulation signal has a pulse aligned with the rising edge or falling edge of the input signal.
  • the present invention does not specifically limit the specific implementation of the double-edge pulse circuit, and any circuit that captures the rising and falling edges of a signal and forms a pulse signal at the rising and falling edges is within the protection scope of the present invention.
  • the first logic circuit is an addition circuit, and through the addition circuit, the double edge pulse signal is added to the first-level modulation signal, so as to obtain the same value as the input signal.
  • Single edge aligned secondary modulation signal is added to the first-level modulation signal, so as to obtain the same value as the input signal.
  • Single edge aligned secondary modulation signal is aligned with the rising edge of the input signal.
  • the present invention does not specifically limit the addition circuit, and any circuit that realizes signal addition is within the protection scope of the present invention.
  • the signal restoration unit includes a single-edge delay circuit.
  • the demodulator receives the secondary modulation signal, which is used to demodulate the secondary modulation signal to obtain the demodulated signal
  • the signal restoration unit the single edge delay circuit, receives the demodulated signal.
  • the demodulated signal is delayed by a pulse width through a single-edge delay circuit, thereby removing the part of the demodulated signal that is higher than the pulse width of the input signal, and restoring the demodulated signal to an output signal with the same pulse width as the input signal.
  • the pulse width delayed by the single-edge delay circuit is equal to a pulse width of the double-edge pulse circuit.
  • FIG. 2 it is a signal waveform diagram of each stage of the OOK modulation and demodulation system using the above-mentioned embodiment.
  • V1 is the input signal
  • the pulse width is t1
  • Clock is the clock signal.
  • the OOK modulator receives the input signal V1 and the clock signal Clock, and obtains the first-level modulation signal V2 after modulation.
  • the first-level modulation signal Compared with the loss of the edge pulse of the input signal, in the traditional OOK modulation and demodulation system, the first-level modulation signal is directly transmitted and demodulated through the channel to obtain a demodulated signal, which will have a large pulse width distortion. .
  • the novel OOK modulation and demodulation system of the present invention performs secondary processing on the primary modulation signal in the secondary modulation unit of the modulation module. Specifically, first, the double edge pulse circuit receives the input signal and captures the rising edge of the input signal. and the falling edge, and generate a double-edge pulse signal V3 at the rising edge and the falling edge.
  • the pulse width of the double-edge pulse signal is t2.
  • the second modulation unit in the secondary modulation unit A logic circuit, preferably an addition circuit, adds the double-edge pulse signal V3 and the first-level modulation signal V2 to obtain the second-level modulation signal V4, because the double-edge pulse signal V3 captures the rising edge and falling edge of the input signal Therefore, it can be seen from the figure that in each pulse period of the input signal, the secondary modulation signal V4 has a pulse signal aligned with the rising edge of the input signal, and after the falling edge of the input signal, the The secondary modulation signal V4 also has an additional signal with a pulse width of t2.
  • the secondary modulation signal V4 is transmitted to the demodulation module through the channel, and the demodulator demodulates the secondary modulation signal V4 to obtain the demodulated signal V5.
  • the pulse width of the demodulated signal V5 is t3.
  • the signal restoration unit which is preferably a unilateral delay circuit.
  • the present invention does not limit the value of the pulse width t2.
  • t2 is equal to or close to a pulse width of the Clock signal. Too long t2 will affect the number of pulses in the secondary modulation signal, and the signal may not be normal. is demodulated; if t2 is too short, it may be filtered out as a burr. Therefore, it is preferable that t2 is equal to or close to a pulse width of the Clock signal to have the best effect.
  • the signal restoration unit includes a single-edge pulse circuit and a second logic circuit; the single-edge pulse circuit is connected to the demodulator, and receives the After the demodulator demodulates the demodulated signal, the single-edge pulse circuit generates a single-edge pulse signal on the rising edge or the falling edge of the demodulated signal, preferably, a single-edge pulse signal is generated on the rising edge of the demodulated signal, and the single-edge pulse signal is generated.
  • the pulse width of the signal is equal to one pulse width of the above-mentioned double-edge pulse circuit;
  • the second logic circuit is connected with the single-edge pulse circuit and the demodulator, receives the single-edge pulse signal and the demodulated signal and processes it, and outputs the same as the input signal. Output signal with equal pulse width.
  • the second logic circuit is a subtraction circuit, and the single-edge pulse signal is subtracted from the demodulated signal to obtain an output signal with the same pulse width as the input signal.
  • the present invention does not specifically limit the subtraction circuit, and any circuit for realizing signal subtraction is within the protection scope of the present invention.
  • FIG. 4 it is a signal waveform diagram of each stage of the OOK modulation and demodulation system using the above-mentioned embodiment.
  • V1 is the input signal
  • the pulse width is t1
  • Clock is the clock signal.
  • the OOK modulator receives the input signal V1 and the clock signal Clock, and after modulation, the first-level modulation signal V2 is obtained, and the double-edge pulse circuit receives the input signal.
  • the pulse width of the double-edge pulse signal is t2
  • the first logic circuit in the second-level modulation unit adds the double-edge pulse signal V3 and the first-level modulation signal V2 to obtain the second-level modulation signal V4, because the double-edge pulse signal V3 captures the rising edge of the input signal and the Therefore, it can be seen from the figure that in each pulse period of the input signal, the secondary modulation signal V4 has a pulse signal aligned with the rising edge of the input signal, and after the falling edge of the input signal, The secondary modulation signal V4 also has an additional signal with a pulse width of t2.
  • the secondary modulation signal V4 is transmitted to the demodulation module through the channel, and the demodulator demodulates the secondary modulation signal V4 to obtain the demodulated signal V5.
  • the pulse width of the demodulated signal V5 is t3.
  • the signal restoration unit is a single-edge pulse circuit and a second logic circuit
  • the single-edge pulse circuit is connected to the demodulator, and is demodulated after demodulation by the demodulator.
  • the second logic circuit preferably, a subtraction circuit, is connected with the single-edge pulse circuit and the demodulator, and receives the single-edge pulse signal V6 and demodulator.
  • the modulation module further includes a preprocessing unit, and the preprocessing unit is located at the front end of the OOK modulator and the secondary modulation unit, and is responsible for the input signal. After preprocessing is performed to form a preprocessing signal delayed by a single edge relative to the input signal, it is output to the OOK modulator and the secondary modulation unit for processing.
  • the signal modulated by the modulator is the preprocessing signal preprocessed by the preprocessing unit; in this implementation, the demodulation module does not include a signal restoration unit, that is, after the signal is demodulated by the demodulator, an output signal with the same pulse width as the input signal can be directly obtained.
  • the preprocessing unit is a single-edge delay circuit, which preprocesses the input signal to form a single-edge delayed preprocessing signal relative to the input signal.
  • the secondary modulation unit includes a double edge pulse circuit and a third logic circuit;
  • the double edge pulse circuit is connected to the preprocessing unit, receives the preprocessing signal, and captures the preprocessing signal.
  • the rising and falling edges of the signal generate double-edge pulse signals on the rising and falling edges of the preprocessed signal;
  • the third logic circuit is connected to the double-edge pulse circuit and the OOK modulator to receive and process the double-edge pulse signals and the first-level modulation. Signal.
  • the input signal is preprocessed, it is then modulated by the OOK modulator and post-processed by the secondary modulation unit, and the secondary modulation signal output by the secondary modulation unit is aligned with both edges of the input signal.
  • the double edge alignment described in this embodiment does not mean that the rising edge and falling edge of the secondary modulation signal and the input signal are aligned on the same time axis.
  • the width is equal, that is, after the entire input signal is shifted backwards along the time axis, within one cycle of the input signal, the rising edge of one pulse and the falling edge of another pulse of the secondary modulation signal are aligned with the rising edge and falling edge of the input signal respectively. Therefore, after the secondary modulation signal is transmitted to the demodulation module through the channel, the fundamental signal obtained by directly demodulating the secondary modulation signal has the same pulse width as the input signal, and no subsequent processing is required.
  • the third logic circuit is an adding circuit.
  • FIG. 6 it is a signal waveform diagram of each stage of the OOK modulation and demodulation system using the above embodiment.
  • V1 is the input signal
  • the pulse width is t1
  • Clock is the clock signal.
  • the input signal is preprocessed by the preprocessing unit, and a single-edge delayed preprocessing signal V1' is input, and the delayed pulse width is t0.
  • the OOK modulator receives the pre-processing signal V1' and the clock signal Clock, and obtains the first-level modulation signal V2 after modulation.
  • the third logic circuit adds the double-edge pulse signal V3 and the first-level modulation signal V2 to obtain the second-level modulation signal V4. Since the double-edge pulse signal V3 captures the rising and falling edges of the preprocessed signal, the preprocessing Compared with the input signal V1, the signal V1' has a single-edge delay.
  • the demodulation module further includes a shaping circuit.
  • the shaping circuit mainly lies in the post-processing of the output signal to further improve the quality of the output signal.
  • a burr removal filter is used.
  • the embodiments of the present invention are all within the protection scope of the present invention. In this embodiment, adding a shaping circuit helps to improve the quality of the output signal, and the shaping circuit can also be omitted.
  • the OOK modulation and demodulation system of the present invention mainly solves the problem of edge synchronization and alignment of the input signal and the output signal to ensure that the demodulated signal has no duty cycle distortion problem, which can be understood as OOK modulation with automatic edge alignment.
  • Other modified modulation modes or implementation forms with similar principles shall fall within the protection scope of this patent.
  • a double-edge pulse circuit is added after the traditional OOK modulator to capture the edge signal lost during modulation, and a single-edge processing circuit is added after the traditional demodulator during demodulation to remove or increase the edge signal.
  • the input signal is pre-processed before modulation and then modulated, without the need for processing during demodulation, so as to achieve input-output signal edge synchronization and eliminate the problems of large pulse width distortion and high bit error rate.

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Abstract

一种OOK调制解调系统，包括调制模块、信道与解调模块，调制模块包括OOK调制器及二级调制单元，OOK调制器用于输入信号的调制，输出一级调制信号，二级调制单元与OOK调制器连接，用于捕获输入信号的边沿脉冲并处理一级调制信号形成与输入信号至少单边沿对齐的二级调制信号；信道与调制模块及解调模块连接，用于将二级调制信号传输至解调模块；解调模块包括解调器与信号还原单元，解调器用于将二级调制信号解调获得解调信号，信号还原单元与解调器连接，用于处理解调信号后获得与输入信号等脉宽的输出信号。可以实现输入信号和输出信号边沿同步、对齐以保证解调出的信号无占空比失真问题，减少误码率。

Description

一种OOK调制解调系统 技术领域
本发明涉及信号调制解调领域，尤其涉及一种OOK调制解调系统。
背景技术
信号在传递过程中，其传输媒介可能是长距离传输线、光耦、电容等媒介。由于在传输信道上信号会发生信号失真、损耗等恶劣现象，使得基带信号很难在接收端接收到完整的输入信号，因此，常使用OOK调制将信号频谱搬移至传输媒介可以通过的高频处，这样将输入信号已载波的方式进行传输，最后在接收器处增加解调环节，将信号从载波中解调出来。OOK(On-Off Keying)调制又称为二进制振幅键控调制，以单极性不归零码序列来控制正弦载波的开启与关闭。由于该调制方式的实现简单，在光纤通信系统、隔离电路系统中，振幅键控方式却获得广泛应用。但采用OOK调制时在载波信号频率低时会出现误码，无法采样到传输信号，并且输入信号边沿与采样载波信号的边沿延时也会导致解码信号的PWD不可控。因此传统OOK调制方式存在PWD脉宽失真大，输出眼图差及误码率高等缺点。
发明内容
为了解决上述问题，本发明的目的在于提供一种OOK调制解调系统，包括调制模块、信道与解调模块，采用边沿同步的处理方式，解决了调制-解调前后脉宽不一致的问题，减小了脉宽失真，减少了误码率。
具体地，本发明一方面提供一种OOK调制解调系统，包括调制模块、信道与解调模块；所述调制模块包括OOK调制器及二级调制单元，所述OOK调制器用于输入信号的调制，输出一级调制信号，所述二级调制单元与所述OOK调制器连接，用于捕获所述输入信号的边沿脉冲并处理所述一级调制信号形成二级调制信号，所述二级调制信号与所述输入信号至少单边沿对齐；所述信道与所述调制模块及所述解调模块连接，用于将所述二级调制信号传输至所述解调模块；所述解调模块包括解调器与信号还原单元，所述解 调器用于将所述二级调制信号解调获得解调信号，所述信号还原单元与所述解调器连接，用于处理所述解调信号后获得与所述输入信号等脉宽的输出信号。
优选地，上述系统中所述二级调制单元包括双边沿脉冲电路与第一逻辑电路；所述双边沿脉冲电路与所述输入信号连接，在所述输入信号的上升沿和下降沿产生双边沿脉冲信号；所述第一逻辑电路与所述双边沿脉冲电路及所述OOK调制器连接，接收并处理所述双边沿脉冲信号与所述一级调制信号，输出与所述输入信号单边沿对齐的所述二级调制信号。
优选地，上述系统中所述第一逻辑电路为加法电路。
优选地，上述系统中所述信号还原单元包括单边沿延迟电路。
优选地，上述系统中所述信号还原单元包括单边沿脉冲电路与第二逻辑电路；所述单边沿脉冲电路与所述解调器连接，接收所述解调信号，在所述解调信号的上升沿或下降沿产生单边沿脉冲信号；所述第二逻辑电路与所述单边沿脉冲电路连接及所述解调器连接，接收并处理所述单边沿脉冲信号及所述解调信号，输出与所述输入信号等脉宽的输出信号。
优选地，上述系统中所述第二逻辑电路为减法电路。
优选地，上述系统中所述调制模块还包括预处理单元，所述预处理单元位于所述OOK调制器与所述二级调制单元的前端，用于输入信号的预处理，形成相对所述输入信号单边沿延迟的预处理信号，输出至所述OOK调制器及所述二级调制单元；所述解调模块不包括所述信号还原单元。
优选地，上述系统中所述预处理单元为单边沿延迟电路。
优选地，上述系统中所述二级调制单元包括双边沿脉冲电路及第三逻辑电路；所述双边沿脉冲电路与所述预处理单元连接，接收所述预处理信号，在所述预处理信号的上升沿和下降沿产生双边沿脉冲信号；所述第三逻辑电路与所述双边沿脉冲电路及所述OOK调制器连接，接收并处理所述双边沿脉冲信号与所述一级调制信号，输出与所述输入信号双边沿对齐的所述二级调制信号。
优选地，上述系统中所述第三逻辑电路为加法电路。
优选地，上述系统中所述双边沿脉冲电路的脉冲宽度与调制时钟信号脉宽相等。
优选地，上述系统中所述解调模块还包括整形电路。
采用了上述技术方案后，与现有技术相比，具有以下有益效果：
1.实现了输入信号与输出信号的边沿同步；
2.减小了调制-解调前后信号的脉宽失真与误码率问题。
附图说明
图1为符合本发明一优选实施例的OOK调制解调系统的结构示意图；
图2为采用符合本发明一优选实施例的OOK调制解调系统的各级信号波形图；
图3为符合本发明另一优选实施例的OOK调制解调系统的结构示意图；
图4为采用符合本发明另一优选实施例的OOK调制解调系统的各级信号波形图；
图5为符合本发明另一优选实施例的OOK调制解调系统的结构示意图；
图6为采用符合本发明另一优选实施例的OOK调制解调系统的各级信号波形图。
具体实施方式
以下结合附图与具体实施例进一步阐述本发明的优点。
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
在本公开使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本公开。在本公开和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本公开可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本公开范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
在后续的描述中，使用用于表示元件的诸如“模块”、“部件”或“单元”的后缀仅为了有利于本发明的说明，其本身并没有特定的意义。因此，“模块”与“部件”可以混合地使用。
参阅附图1，为符合本发明一优选实施例的OOK调制解调系统的结构示意图，包括调制模块、信道与解调模块。
调制模块包括OOK调制器及二级调制单元，其中，OOK调制器为传统OOK调制器，接收输入信号与时钟信号，经过OOK调制器对输入信号调制后输出一级调制信号。不同于传统OOK调制器，OOK调制器对输入信号进行调制后产生一级调制信号，但此调制信 号并不直接通过信道传输，而是将其输入至二级调制单元进行进一步处理。
二级调制单元与OOK调制器连接，接收输入信号与一级调制信号，二级调制单元捕获输入信号的边沿脉冲并处理一级调制信号形成与输入信号至少单边沿对齐的二级调制信号。需要说明的是，二级调制信号与输入信号至少单边沿对齐并不是指二级调制信号的每个脉冲都至少有一个边沿(上升沿/下降沿)与输入信号的边沿对齐，而是在输入信号对应的每个脉冲周期内，二级调制信号都至少有一个脉冲与输入信号上升沿对齐或下降沿对齐。该二级调制信号即为调制完成的信号。
信道与调制模块及解调模块连接，用于将二级调制信号传输至解调模块。本发明并不限制信道的具体实现方式，如电感、光耦、电容、双绞线等介质均可，并不拘泥于某种具体的信道形式，不同的信道形式都在本专利保护范围之内。
解调模块包括解调器，解调器接收二级调制信号，用于将二级调制信号解调获得解调信号，获取解调信号后并不直接输入，解调模块还包括信号还原单元，信号还原单元与解调器连接，用于处理解调信号，去除解调信号中高于输入信号脉宽的部分，将解调信号还原为与输入信号等脉宽的输出信号。
通过此技术方案，通过二级调制模块对经过OOK调制器调制的输入信号进行二级处理，从而获得与输入信号至少单边沿对齐的二级调制信号，并经信号传输至解调模块，解调模块在进行解调器解调后经过信号还原单元的再处理，还原输出信号的脉宽，获得与输出信号等脉宽的输出信号，从而实现输入信号与输出信号的边沿同步，有效地减小了调制-解调前后信号的脉宽失真与误码率问题。
基于上述实施例，符合本发明的一优选实施例中，所述二级调制单元包括双边沿脉冲电路与第一逻辑电路；双边沿脉冲电路接收输入信号，捕获输入信号的上升沿与下降沿，在输入信号的上升沿和下降沿产生脉冲信号，即双边沿脉冲信号；第一逻辑电路与该双边沿脉冲电路及OOK调制器连接，接收并处理双边沿脉冲信号与一级调制信号，将该双边沿脉冲信号与一级调制信号相加，由于该双边沿脉冲信号为输入信号的上升沿和下降沿处的脉冲信号，因此，经过第一逻辑电路后，输出的二级调制信号与所述输入信号单边沿对齐，同上所述，单边沿对齐并不是指二级调制信号的每个脉冲都有一个边沿(上升沿/下降沿)与输入信号的边沿对齐，而是在输入信号对应的每个脉冲周期内，二级调制信号都有一个脉冲与输入信号上升沿对齐或下降沿对齐。
本发明不对双边沿脉冲电路的具体实现方式进行特别限定，任何捕获信号上升沿与下降沿并在上升沿与下降沿形成脉冲信号的电路均在本发明的保护范围内。
基于上述实施例，符合本发明的一优选实施例中，所述第一逻辑电路为加法电路， 通过该加法电路，将双边沿脉冲信号加到一级调制信号上，从而获得与所述输入信号单边沿对齐的二级调制信号。进一步的，该在输入信号对应的每个脉冲周期内，二级调制信号都有一个脉冲与输入信号上升沿对齐。通过该加法电路与双边沿脉冲电路，将在OOK调制器调制输入信号时丢失的边沿信号捕获形成带有输入信号边沿信号的二级调制信号。
本发明不对加法电路进行特别限定，任何实现信号相加的电路均在本发明的保护范围内。
基于上述实施例，符合本发明的一优选实施例中，信号还原单元包括单边沿延迟电路。二级调制信号通过信道传输到解调模块后，解调器接收二级调制信号，用于将二级调制信号解调获得解调信号，信号还原单元即单边沿延迟电路接收该解调信号，通过单边沿延迟电路使解调信号延迟一个脉冲宽度，从而去除解调信号中高于输入信号脉宽的部分，将解调信号还原为与输入信号等脉宽的输出信号。进一步的，该单边延迟电路延迟的脉冲宽度与双边沿脉冲电路的一个脉冲宽度相等。
参阅图2，为采用上述实施例的OOK调制解调系统的各级信号波形图。V1为输入信号，脉冲宽度为t1，Clock为时钟信号，首先OOK调制器接收输入信号V1、时钟信号Clock，经过调制后获得一级调制信号V2，从图2中可以看到，一级调制信号相对于输入信号丢失了边沿脉冲，在传统OOK调制解调系统中，直接将该一级调制信号通过信道传输并解调，从而获得解调信号，该解调信号将存在较大的脉宽失真。因此，本发明的新型OOK调制解调系统在调制模块的二级调制单元中对该一级调制信号进行二级处理，具体的，首先双边沿脉冲电路接收输入信号，捕获该输入信号的上升沿与下降沿，并在上升沿与下降沿处产生双边沿脉冲信号V3，双边沿脉冲信号的脉冲宽度为t2，获得具有输入信号边沿信息的双边沿脉冲信号V3后，二级调制单元中的第一逻辑电路，优选地，为加法电路，将双边沿脉冲信号V3与一级调制信号V2相加，从而获得二级调制信号V4，由于该双边沿脉冲信号V3捕获了输入信号的上升沿与下降沿，因此，从图中可以看到在输入信号的每一个脉冲周期内，该二级调制信号V4都具有一个与该输入信号上升沿对齐的脉冲信号，而在输入信号的下降沿之后，该二级调制信号V4还多出一个t2脉冲宽度的信号。二级调制信号V4经过信道传输至解调模块，解调器对二级调制信号V4进行解调，获得解调信号V5，解调信号V5的脉冲宽度为t3，由于二级调制信号V4与输入信号V1单边沿对齐，因此，解调信号V5与输入信号V1上升沿对齐，而下降沿处则具有t2的延迟，即在每个周期内，解调信号V5比输入信号V1多了t2脉冲宽度，即t3＝t1+t2。获得解调信号V5后，进入信号还原单元，优选地，为单边延迟电路，该单边延迟电路对解调信号 进行延迟处理，延迟宽度为t4，t4＝t2，从而经过单元延迟电路的输出信号Vout脉冲宽度为t5＝t3-t4＝t3-t2＝t1，即输出信号与输入信号脉冲宽度相等。通过本发明的边沿同步的OOK调制解调系统，保证了t1＝t5，从而解决了调制-解调前后脉宽不一致的情况，脉宽失真小，减少了误码率。
需要说明的是，本发明并不限制脉冲宽度t2的值，优选地，t2与Clock时钟信号的一个脉宽相等或接近，t2过长会影响二级调制信号中脉冲个数，信号可能无法正常被解调出来；t2过短有可能被当作毛刺被滤除。因此优选t2与Clock时钟信号的一个脉宽相等或接近时具有最好效果。
参阅图3为符合本发明另一优选实施例的OOK调制解调系统的结构示意图，所述信号还原单元包括单边沿脉冲电路与第二逻辑电路；单边沿脉冲电路与解调器连接，接收经解调器解调后解调信号，单边沿脉冲电路在解调信号的上升沿或下降沿产生单边沿脉冲信号，优选地，在解调信号的上升沿产生单边沿脉冲信号，该单边沿脉冲信号的脉冲宽度与上述双边沿脉冲电路的一个脉冲宽度相等；第二逻辑电路与单边沿脉冲电路连接及解调器连接，接收单边沿脉冲信号及解调信号并进行处理，输出与所述输入信号等脉宽的输出信号。优选地，所述第二逻辑电路为减法电路，通过解调信号减去该单边沿脉冲信号，从而获得与所述输入信号等脉宽的输出信号。本发明不对减法电路进行特别限定，任何实现信号相减的电路均在本发明的保护范围内。
参阅图4，为采用上述实施例的OOK调制解调系统的各级信号波形图。与图2相同，V1为输入信号，脉冲宽度为t1，Clock为时钟信号，首先OOK调制器接收输入信号V1、时钟信号Clock，经过调制后获得一级调制信号V2，双边沿脉冲电路接收输入信号，捕获该输入信号的上升沿与下降沿，并在上升沿与下降沿处产生双边沿脉冲信号V3，双边沿脉冲信号的脉冲宽度为t2，获得具有输入信号边沿信息的双边沿脉冲信号V3后，二级调制单元中的第一逻辑电路，将双边沿脉冲信号V3与一级调制信号V2相加，从而获得二级调制信号V4，由于该双边沿脉冲信号V3捕获了输入信号的上升沿与下降沿，因此，从图中可以看到在输入信号的每一个脉冲周期内，该二级调制信号V4都具有一个与该输入信号上升沿对齐的脉冲信号，而在输入信号的下降沿之后，该二级调制信号V4还多出一个t2脉冲宽度的信号。二级调制信号V4经过信道传输至解调模块，解调器对二级调制信号V4进行解调，获得解调信号V5，解调信号V5的脉冲宽度为t3，由于二级调制信号V4与输入信号V1单边沿对齐，因此，解调信号V5与输入信号V1上升沿对齐，而下降沿处则具有t2的延迟，即在每个周期内，解调信号V5比输入信号V1多了t2脉冲宽度，即t3＝t1+t2。获得解调信号V5后，进入信号还原单元，本实施例中信号还原单元为 单边沿脉冲电路与第二逻辑电路，单边沿脉冲电路与解调器连接，接收经解调器解调后解调信号，单边沿脉冲电路在解调信号的上升沿或下降沿产生单边沿脉冲信号V6，优选地，在解调信号的上升沿产生单边沿脉冲信号，该单边沿脉冲信号V6的脉冲宽度t4’与上述双边沿脉冲电路的一个脉冲宽度t2相等，t4’＝t2；第二逻辑电路，优选地，为减法电路，与单边沿脉冲电路连接及解调器连接，接收单边沿脉冲信号V6及解调信号V5并进行处理，使解调信号V5与单边沿脉冲信号V6相减，从而获得输出信号Vout，输出信号的脉冲宽度为t5＝t3-t4’＝t3-t2＝t1，即输出信号与输入信号脉宽相等。通过本发明的边沿同步的OOK调制解调系统，保证了t1＝t5，从而解决了调制-解调前后脉宽不一致的情况，脉宽失真小，减少了误码率。
参阅图5为符合本发明另一优选实施例的OOK调制解调系统的结构示意图，所述调制模块还包括预处理单元，预处理单元位于OOK调制器与二级调制单元的前端，对输入信号进行预处理形成相对输入信号单边沿延迟的预处理信号后，再输出至OOK调制器及二级调制单元进行处理，调制器调制的信号为经预处理单元预处理的预处理信号；在本实施例的OOK调制解调系统中，解调模块不包括信号还原单元，即信号经过解调器解调后可直接获得与输入信号等脉宽的输出信号。
基于上述实施例，符合本发明的一优选实施例中，所述预处理单元为单边沿延迟电路，对输入信号进行预处理形成相对输入信号单边沿延迟的预处理信号。
基于上述实施例，符合本发明的一优选实施例中，所述二级调制单元包括双边沿脉冲电路及第三逻辑电路；双边沿脉冲电路与预处理单元连接，接收预处理信号，捕获预处理信号的上升沿与下降沿，在预处理信号的上升沿和下降沿产生双边沿脉冲信号；第三逻辑电路与双边沿脉冲电路及OOK调制器连接，接收并处理双边沿脉冲信号与一级调制信号。本实施例中，输入信号经过预处理后，再经过OOK调制器调制及二级调制单元的后处理，二级调制单元输出的二级调制信号与输入信号双边沿对齐。本实施例所述的双边沿对齐并不是指二级调制信号与输入信号在同一时间轴上上升沿与下降沿对齐，而是指在输入信号的一个周期内，二级调制信号与输入信号脉宽相等，即将输入信号整体沿时间轴向后平移后，在输入信号的一个周期内，二级调制信号的一个脉冲上升沿与另一个脉冲下降沿与该输入信号的上升沿下降沿分别对齐。因此，将该二级调制信号经过信道传输至解调模块后，直接对该二级调制信号解调获得的基波信号即与输入信号等脉宽，无需进行后续处理。
基于上述实施例，符合本发明的一优选实施例中，第三逻辑电路为加法电路。
参阅图6，为采用上述实施例的OOK调制解调系统的各级信号波形图。V1为输入信 号，脉冲宽度为t1，Clock为时钟信号，首先，输入信号经过预处理单元进行预处理，输入单边沿延迟的预处理信号V1’，延迟的脉冲宽度为t0，该预处理信号的脉宽为t1’＝t1-t0。OOK调制器接收预处理信号V1’、时钟信号Clock，经过调制后获得一级调制信号V2，双边沿脉冲电路接收预处理信号V1’，捕获该预处理信号V1’的上升沿与下降沿，并在上升沿与下降沿处产生双边沿脉冲信号V3，双边沿脉冲信号的脉冲宽度为t2，其中t2＝t0，获得具有预处理信号边沿信息的双边沿脉冲信号V3后，二级调制单元中的第三逻辑电路，将双边沿脉冲信号V3与一级调制信号V2相加，从而获得二级调制信号V4，由于该双边沿脉冲信号V3捕获了预处理信号的上升沿与下降沿，而预处理信号V1’相比输入信号V1具有单边沿延迟，因此，从图中可以看到在输入信号的每一个脉冲周期内，若将输入信号V1整体沿时间轴向后平移t0，在输入信号V1的一个周期内，二级调制信号的一个脉冲上升沿与另一个脉冲下降沿与该输入信号的上升沿下降沿分别对齐，进而二级调制信号V4经过信道传输至解调模块，解调器对二级调制信号V4进行解调后，获得解调信号V5的脉冲宽度t3＝t1’+t2＝t1-t0+t0＝t1，解调器解调得到的基波信号与输入信号脉宽相等，可直接作为输出信号Vout输出。通过本发明的边沿同步的OOK调制解调系统，保证了t3＝t1，从而解决了调制-解调前后脉宽不一致的情况，脉宽失真小，减少了误码率。
基于上述实施例，符合本发明的一优选实施例中，所述解调模块还包括整形电路。整形电路，主要在于对输出信号的后处理，进一步提高输出信号的质量，如采用毛刺消除滤波器，本发明并不限制整形电路的具体实现方式与内容，只要是对输出信号后处理提高信号质量的实施方式都在本发明的保护范围内，在本实施例中增加整形电路有助于提高输出信号质量，整形电路也可以省略。
本发明的OOK调制解调系统主要解决输入信号和输出信号边沿同步、对齐以保证解调出的信号无占空比失真问题，可理解为边沿自动对齐的OOK调制，采用该调制-解调方式原理相类似的其他变形的调制方式或者实施形式，都应在本专利保护范围之内。
采用本发明的技术方案，在传统OOK调制器后增加双边沿脉冲电路捕获调制时丢失的边沿信号，而在解调时在传统解调器后增加单边沿处理电路对增加的边沿信号进行去除或在调制前对输入信号预处理后再进行调制，而无需在解调时再进行处理，从而实现输入-输出信号边沿同步，消除脉宽失真大、误码率高的问题。
应当注意的是，本发明的实施例有较佳的实施性，且并非对本发明作任何形式的限制，任何熟悉该领域的技术人员可能利用上述揭示的技术内容变更或修饰为等同的有效实施例，但凡未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何修改或等同变化及修饰，均仍属于本发明技术方案的范围内。

Claims (12)

  1. 一种OOK调制解调系统，其特征在于，包括调制模块、信道与解调模块；
    所述调制模块包括OOK调制器及二级调制单元，所述OOK调制器用于输入信号的调制，输出一级调制信号，所述二级调制单元与所述OOK调制器连接，用于捕获所述输入信号的边沿脉冲并处理所述一级调制信号形成二级调制信号，所述二级调制信号与所述输入信号至少单边沿对齐；
    所述信道与所述调制模块及所述解调模块连接，用于将所述二级调制信号传输至所述解调模块；
    所述解调模块包括解调器与信号还原单元，所述解调器用于将所述二级调制信号解调获得解调信号，所述信号还原单元与所述解调器连接，用于处理所述解调信号后获得与所述输入信号等脉宽的输出信号。
  2. 如权利要求1所述的OOK调制解调系统，其特征在于，所述二级调制单元包括双边沿脉冲电路与第一逻辑电路；
    所述双边沿脉冲电路与所述输入信号连接，在所述输入信号的上升沿和下降沿产生双边沿脉冲信号；
    所述第一逻辑电路与所述双边沿脉冲电路及所述OOK调制器连接，接收并处理所述双边沿脉冲信号与所述一级调制信号，输出与所述输入信号单边沿对齐的所述二级调制信号。
  3. 如权利要求2所述的OOK调制解调系统，其特征在于，所述第一逻辑电路为加法电路。
  4. 如权利要求3所述的OOK调制解调系统，其特征在于，所述信号还原单元包括单边沿延迟电路。
  5. 如权利要求3所述的OOK调制解调系统，其特征在于，所述信号还原单元包括单边沿脉冲电路与第二逻辑电路；
    所述单边沿脉冲电路与所述解调器连接，接收所述解调信号，在所述解调信号的上升沿或下降沿产生单边沿脉冲信号；
    所述第二逻辑电路与所述单边沿脉冲电路连接及所述解调器连接，接收并处理所述单边沿脉冲信号及所述解调信号，输出与所述输入信号等脉宽的输出信号。
  6. 如权利要求5所述的OOK调制解调系统，其特征在于，所述第二逻辑电路为减法电 路。
  7. 如权利要求1所述的OOK调制解调系统，其特征在于，所述调制模块还包括预处理单元，所述预处理单元位于所述OOK调制器与所述二级调制单元的前端，用于输入信号的预处理，形成相对所述输入信号单边沿延迟的预处理信号，输出至所述OOK调制器及所述二级调制单元；所述解调模块不包括所述信号还原单元。
  8. 如权利要求7所述的OOK调制解调系统，其特征在于，所述预处理单元为单边沿延迟电路。
  9. 如权利要求8所述的OOK调制解调系统，其特征在于，所述二级调制单元包括双边沿脉冲电路及第三逻辑电路；
    所述双边沿脉冲电路与所述预处理单元连接，接收所述预处理信号，在所述预处理信号的上升沿和下降沿产生双边沿脉冲信号；
    所述第三逻辑电路与所述双边沿脉冲电路及所述OOK调制器连接，接收并处理所述双边沿脉冲信号与所述一级调制信号，输出与所述输入信号双边沿对齐的所述二级调制信号。
  10. 如权利要求9所述的OOK调制解调系统，其特征在于，所述第三逻辑电路为加法电路。
  11. 如权利要求2-6任一所述的OOK调制解调系统，其特征在于，所述双边沿脉冲电路的脉冲宽度与调制时钟信号脉宽相等。
  12. 如权利要求1-10任一所述的OOK调制解调系统，其特征在于，所述解调模块还包括整形电路。
PCT/CN2021/097806 2020-08-12 2021-06-02 一种ook调制解调系统 WO2022033132A1 (zh)

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CN101595703A (zh) * 2007-01-30 2009-12-02 松下电器产业株式会社 调制装置和解调装置
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CN111970220A (zh) * 2020-08-12 2020-11-20 屹世半导体(上海)有限公司 一种ook调制解调系统
CN212381235U (zh) * 2020-08-12 2021-01-19 屹世半导体(上海)有限公司 一种ook调制解调系统

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CN101595703A (zh) * 2007-01-30 2009-12-02 松下电器产业株式会社 调制装置和解调装置
CN104506241A (zh) * 2014-12-26 2015-04-08 武汉邮电科学研究院 双臂驱动四级脉冲幅度调制器及方法
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