WO2022032470A1

WO2022032470A1 - Transmission electron microscope high-resolution in-situ liquid-phase temperature change chip and production method therefor

Info

Publication number: WO2022032470A1
Application number: PCT/CN2020/108368
Authority: WO
Inventors: 廖洪钢; 江友红
Original assignee: 厦门超新芯科技有限公司
Priority date: 2020-08-11
Filing date: 2020-08-11
Publication date: 2022-02-17

Abstract

A transmission electron microscope high-resolution in-situ liquid-phase temperature change chip (1) and a production method therefor. A lower substrate (3) of the chip (1) is provided with a supporting layer (15), a freezing layer, a first insulating layer (16), a heating layer (8), a second insulating layer (17), channels (18), and a central window (52); the freezing layer has four contact electrodes (11), a semiconductor refrigeration film (19), and an electrically conductive metal film (20); in the area where the central window (52) and the semiconductor refrigeration film (19) are located, the channels (18) are formed after silicon is etched away, and the supporting layer (15) covers the channels (18); the semiconductor refrigeration film (19) and the electrically conductive metal film (20) are both provided on the supporting layer (15); a metal film (20) is deposited, with the central window (52) as the center, on the supporting layer (15); the front end of the semiconductor refrigeration film (19) is lapped on the metal film (20), and the rear end is connected to the four contact electrodes (11); the freezing layer and the heating layer (8) are separated by the first insulating layer (16); the heating layer (8) has two contact electrodes (11) and a helical circular heating wire (9); the heating wire (9) is located above the semiconductor refrigeration film (19); and multiple small holes are formed in the center window (52). The chip (1) has advantages that the temperature control range is large, the temperature change rate is high, and in-situ dynamic observation can be achieved.

Description

A kind of transmission electron microscope high-resolution in-situ liquid phase temperature change chip and preparation method thereof

technical field

The invention relates to the field of liquid phase chips, in particular to a transmission electron microscope high-resolution in-situ liquid phase temperature change chip and a preparation method thereof.

Background technique

In situ chip transmission electron microscopy, a new technology developed in the field of transmission electron microscopy in recent years, has been able to observe the morphology evolution and molecular structure changes of substances in solution environment at the atomic scale under in situ conditions. The chemical reaction process in the liquid environment is of great significance for studying the reaction principle and controlling the reaction process. The existing TEM freezing technology is characterized by rapidly cooling the sample, the solvent molecules become glassy, and the sample is also frozen instantaneously, so as to obtain a more realistic sample morphology. Due to the limitation of the freezing state of the sample, we can often only observe a single static state when the sample is frozen, and cannot observe the entire three-dimensional dynamic change process of the sample in the real solution environment, which makes our research on the real reaction system limited. great limitation. The single state of matter after freezing and the inability to achieve alternate transformation is the biggest obstacle to its application.

SUMMARY OF THE INVENTION

In order to overcome the above-mentioned bottleneck of science and technology, it is necessary to design a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy. The present invention provides a liquid phase freezing environment through semiconductor refrigeration, and uses the Joule heat of the heating wire to thaw, and the cooling and heating effects can be used with accurate currents. Free and flexible alternation of freeze-thaw of solution-phase samples can be realized.

In order to achieve the above purpose, the present invention provides a high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy. The material of the sheet is a silicon substrate with silicon nitride or silicon oxide on both sides, and the upper sheet has two sample injection ports and a central window 1. It is characterized in that the lower sheet is provided with a support layer, a freezing layer, an insulating layer 1, The heating layer, the insulating layer 2, the tunnel and the central window 2; the freezing layer is provided with four contact electrodes, a semiconductor refrigeration film of not less than one level and a conductive metal film, of which the four contact electrodes are placed on the edge of the chip; in the central window 2. In the area where the semiconductor refrigeration film is located, the silicon is etched away, leaving a channel, and the support layer covers the channel; the semiconductor refrigeration film and the conductive metal film are placed on the support layer on the channel, and do not directly contact the silicon substrate; The center window 2 is the center, and a circle of metal films is deposited on the support layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the back end is connected to the four contact electrodes on the freezing layer; if it is at least two-stage semiconductor refrigeration film , then the rear end is connected to the semiconductor refrigeration films of all levels with metal films in turn, until the last level of semiconductor refrigeration films is connected to the four contact electrodes on the freezing layer; the freezing layer and the heating layer are separated by the insulating layer 1, and the heating layer is connected to the outside Separated by the insulating layer 2; the heating layer has two contact electrodes and a spiral annular heating wire, and the heating wire is located above the semiconductor refrigeration film;

The area of the upper sheet is slightly smaller than that of the lower sheet, the central window 1 of the upper sheet and the central window 2 of the lower sheet are aligned, and both the central window 1 and the central window 2 have a plurality of small holes.

Further, the outer dimension of the lower piece is 2*2-10*10mm; preferably, the outer dimension of the lower piece is 4*8mm;

Optionally, the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;

Optionally, the thickness of the silicon nitride or silicon oxide is 5-200nm;

Optionally, the thickness of the silicon substrate is 50-500 μm.

Further, a circle-shaped metal film is deposited on the support layer;

Optionally, the support layer is silicon nitride or silicon oxide with a thickness of 0.5-5 μm.

Further, the freezing layer is set to two groups of equivalent circuits, and the two groups of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; one group of loops in the two groups of equivalent circuits is responsible for power supply and cooling, Another set of loops is responsible for real-time monitoring of the current value of semiconductor refrigeration;

Optionally, the shape of the semiconductor refrigeration film of the freezing layer is a regular rectangle; the length is 0.2-0.8mm, the width is 0.1-0.4mm, and the thickness is 50nm-500nm; preferably, the semiconductor in the semiconductor refrigeration film is n-type semiconductors and p-type semiconductors, where n-type semiconductors are n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; is polysilicon, p-type bismuth telluride, p-type silicon germanium, or p-type antimony telluride;

Optionally, the conductive metal in the conductive metal film is gold, silver or copper, with a thickness of 50nm-300nm;

Optionally, the size of the outer square of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the size of the inner square is 5 μm*5 μm-100 μm*100 μm.

Further, both the insulating layer 1 and the insulating layer 2 are one layer, and the thickness is 30-150 nm; preferably, the insulating layer 1 and the insulating layer 2 are made of silicon nitride, silicon oxide or aluminum oxide.

Further, the outer diameter of the spiral annular heating wire of the heating layer is 0.15-0.5mm, and the thickness is 50nm-500nm;

Optionally, the spiral annular heating wire adopts metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide;

Optionally, the shape of the helical annular heating wire on the heating layer is relatively symmetrical, and the heating wires are left with gaps and are not connected to each other; the heating wire in the center of the heating layer is placed on the intermediate insulating layer, and is not directly connected to the freezing layer contact.

Further, the channel is square; preferably, the length of the channel is 4-7mm; the width is 0.25-0.9mm;

Optionally, the central window 1 and the central window 2 are square central windows; preferably, the size of the square central window is 5 μm*5 μm-100 μm*100 μm; more preferably, the size of the square central window is 20 μm *50μm;

Optionally, the size of the pores is 0.5 μm-5 μm.

Further, the preparation method of the top sheet is,

S1. Using the photolithography process, transfer the central window pattern from the photolithography mask to the Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then develop the wafer in a positive film developer A-1;

Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;

More preferably, the exposure time is 15s;

S2. Using the reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is put into acetone to soak, and finally a large amount of Rinse with deionized water to remove the photoresist to obtain wafer A-2;

S3. Using the UV laser direct writing process, transfer the small hole pattern of the central window from the photolithography mask to the front side of the wafer A-2, then develop it in a positive film developer, and then rinse the surface with deionized water. Obtain wafer A-3;

Preferably, the development time is 50s;

S4. Using the reactive ion etching process, the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S5. Put the back side of wafer A-4 into potassium hydroxide solution for wet etching, and etch until only the film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain a crystal circle A-5;

Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;

More preferably, the time of etching is 2h;

S6. Using the photolithography process, transfer the bonding layer pattern from the photolithography mask to the front side of wafer A-5, then develop it in a positive-gel developer, and then rinse and clean the surface with deionized water to obtain wafer A -6;

Preferably, the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;

More preferably, the exposure time is 15s;

S7. Using the thermal evaporation coating process, the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;

Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;

More preferably, the metal is In, Sn or Al;

S8. Laser scribing the wafer A-7, and dividing it into independent chips is the loading.

Further, the preparation method of described lower tablet is,

S1. Prepare Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

Preferably, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

S2. Using the photolithography process, transfer the film carrier pattern in the freezing zone from the photolithography mask to the front side of the above-mentioned wafer, then develop it in a positive-gel developer, and then clean the surface with deionized water to obtain wafer B-1;

Preferably, the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;

More preferably, the exposure time is 20s;

S3. Using the reactive ion etching process, etch the central window and the silicon nitride or silicon oxide at the freezing area on the silicon nitride layer on the back of the wafer B-1, and then turn the back of the wafer upward. It was soaked in acetone successively, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2;

Preferably, the length of the frozen layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50-500 nm;

S4. Put the backside of wafer B-2 into a potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out wafer 2, rinse it with a large amount of deionized water, and dry it to obtain Wafer B-3;

Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;

More preferably, the etching temperature is 80°C; the etching time is 2h;

S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;

Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

S6. Using the photolithography process, transfer the metal film pattern from the photolithography mask to the front side of the wafer B-4, then develop it in a positive-gel developer, and then rinse the surface with deionized water to obtain the wafer B- 5;

S7. Use DC magnetron sputtering to sputter a conductive metal film on the front of wafer B-5, then put the front of wafer B-7 into acetone to soak and peel, and finally rinse with deionized water , remove the photoresist and leave the metal film to obtain wafer B-6;

Preferably, the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;

S8. Using the photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;

Preferably, the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

S9. Use RF magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone to soak and peel, and finally use deionization Rinse with water to remove the photoresist, leaving the n-type semiconductor refrigeration film to obtain wafer B-8;

S10. Using the photolithography process, transfer the p-type semiconductor pattern from the photolithography mask to the front side of the wafer B-8, and then develop it in a positive gel developer, and then rinse and clean the surface with deionized water to obtain wafer B -9;

Preferably, the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

S11. Use RF magnetron sputtering to sputter a p-type semiconductor refrigeration film on the front of wafer B-9, then put the front of wafer B-9 into acetone to soak and peel, and finally use deionization Rinse with water to remove the photoresist, leaving the p-type semiconductor refrigeration film to obtain wafer B-10;

Preferably, the p-type semiconductor adopts bismuth telluride or antimony telluride;

S12. utilize the PECVD process to grow a layer of silicon nitride or silicon oxide or aluminum oxide on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;

Preferably, the thickness of the insulating layer is 30-150 nm;

S13. Use electron beam evaporation to evaporate a layer of metal heating wire on the front of wafer B-11, then put the front of wafer B-11 into acetone to soak and peel, and finally rinse with deionized water to remove Photoresist, leaving the metal heating wire to obtain wafer B-12;

Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

S14. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of wafer B-12 as an insulating layer to obtain wafer B-13;

Preferably, the thickness of the insulating layer is 30-150 nm;

S15. Use the UV laser direct writing lithography process to transfer the small hole pattern of the central window from the lithography mask to the front side of the wafer B-13, then develop it in a positive gel developer, and then rinse it with deionized water. surface to obtain wafer B-14;

Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;

S16. Using the reactive ion etching process, the silicon nitride or silicon oxide is etched at the small holes on the back of the wafer B-14, and then the wafer B-14 is soaked in acetone with the front side up, and finally used Rinse with acetone, remove the photoresist, and obtain wafer B-15;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S17. The wafer B-15 is laser diced and divided into independent chips, which are the next wafers.

The present invention provides a method for preparing the transmission electron microscope high-resolution in-situ liquid phase cryochip, which is characterized in that:

The preparation method of the top sheet is,

Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;

More preferably, the exposure time is 15s;

S3. Using the UV laser direct writing process, transfer the small hole pattern of the center window from the photolithography mask to the front side of the wafer A-2, and then develop it in a positive film developer, and then rinse and clean the surface with deionized water. Obtain wafer A-3;

Preferably, the development time is 50s;

Preferably, the size of the small hole is 0.5 μm-5 μm;

More preferably, the time of etching is 2h;

More preferably, the exposure time is 15s;

More preferably, the metal is In, Sn or Al;

S8. Laser scribing the wafer A-7, and dividing it into independent chips is the loading;

The preparation method of the lower tablet is,

S2. Using the photolithography process, transfer the film carrier pattern in the freezing area from the photolithography mask to the front side of the above-mentioned wafer, then develop it in a positive-gel developer, and then clean the surface with deionized water to obtain wafer B-1;

More preferably, the exposure time is 20s;

More preferably, the etching temperature is 80°C; the etching time is 2h;

Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

S6. Using the photolithography process, transfer the metal thin film pattern from the photolithography mask to the front side of the wafer B-4, then develop it in a positive-gel developer, and then rinse and clean the surface with deionized water to obtain the wafer B- 5;

S8. Using the photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;

S10. Using the photolithography process, transfer the p-type semiconductor pattern from the photolithography mask to the front side of the wafer B-8, then develop it in a positive-gel developer, and then rinse the surface with deionized water to obtain wafer B -9;

Preferably, the thickness of the insulating layer is 30-150 nm;

S13. Use electron beam evaporation to evaporate a layer of metal heating wire on the front side of wafer B-11, then put the front side of wafer B-11 into acetone to soak and peel, and finally rinse with deionized water to remove Photoresist, leaving the metal heating wire to obtain wafer B-12;

Preferably, the thickness of the insulating layer is 30-150 nm;

S15. Using the UV laser direct writing lithography process, the pinhole pattern of the central window is transferred from the lithography mask to the front side of the wafer B-13, then developed in a positive-gel developer, and then rinsed with deionized water. surface to obtain wafer B-14;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S17. Laser scribing the wafer B-15, and dividing it into independent chips is the next chip;

Assembly: Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.

The small holes are formed by etching the insulating layer 1, the insulating layer 2 and the support layer. Multiple layers of silicon nitride (support layer, insulating layer 1 and insulating layer 2) are deposited on the central window 2. The thickness of the silicon nitride is too large and requires etching to thin the window silicon nitride for electron microscope observation.

The chip has the advantages of a large temperature control range (the temperature range can reach -120°C to +100°C, and the highest can reach +1000°C), the temperature changing rate is fast, and in-situ dynamic observation can be realized. The conventional products only have a single function of heating and cooling or freezing and cooling.

The temperature control area of the chip of the invention is small (100μm*100μm-500μm*500μm area), and the heat insulation treatment is designed, so that the heat transfer is small, so the micro-area rapid temperature control can be realized.

Description of drawings

FIG. 1 is a schematic diagram of the back surface channel of the lower part of the chip of the present invention.

FIG. 2 is a schematic view of the front structure of the lower part of the chip of the present invention.

FIG. 3 is a schematic diagram of the structure of each layer of the chip of the present invention.

FIG. 4 is a schematic structural diagram of the assembled chip of the present invention.

FIG. 5 is an enlarged view of the upper-chip center window of the chip of the present invention.

FIG. 6 is an enlarged view of the bottom center window of the chip of the present invention.

FIG. 7 is an electron microscope image of a sample observed using the chip of the present invention.

Fig. 8 is a temperature standard curve diagram obtained by using the chip of the present invention.

detailed description

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present invention and should not be construed as limiting the present invention. If no specific technology or condition is indicated in the examples, the technology or condition described in the literature in the field or the product specification is used. The reagents or instruments used without the manufacturer's indication are conventional products that can be obtained from the market.

A high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy, the structure of which is that an upper sheet and a lower sheet are combined by a metal bonding layer to form an ultra-thin chamber by self-sealing; the upper sheet and the lower sheet are made of nitrogen on both sides A silicon substrate made of silicon carbide or silicon oxide, the upper sheet has two injection ports and a central viewing window 1, and is characterized in that the lower sheet is provided with a support layer, a freezing layer, an insulating layer 1, a heating layer, an insulating layer 2, and a channel. And the central window 2; the freezing layer is provided with four contact electrodes, no less than one level of semiconductor refrigeration film and conductive metal film, wherein the four contact electrodes are placed on the edge of the chip; in the central window 2 and the area where the semiconductor refrigeration film is located, After the silicon is etched away, a channel is left, and the support layer covers the channel; the semiconductor refrigeration film and the conductive metal film are placed on the support layer on the channel, and are not in direct contact with the silicon substrate; the center window 2 is centered on the support layer. A circle of metal film is deposited on the layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the rear end is connected to the four contact electrodes on the freezing layer; if it is at least two-stage semiconductor refrigeration film, the rear end is sequentially made of metal The film connects all levels of semiconductor refrigeration films until the last level of semiconductor refrigeration films is connected to the four contact electrodes on the freezing layer; the freezing layer and the heating layer are separated by the insulating layer 1, and the heating layer is separated from the outside by the insulating layer 2; heating The layer has two contact electrodes and a spiral annular heating wire, and the heating wire is located above the semiconductor refrigeration film;

Optionally, the thickness of the silicon nitride or silicon oxide is 5-200nm;

Optionally, the thickness of the silicon substrate is 50-500 μm.

Further, a circle-shaped metal film is deposited on the support layer;

Further, the freezing layer is set as two sets of equivalent circuits, and the two sets of equivalent circuits are controlled by separate current source meters and voltage source meters respectively; a set of loops in the two sets of equivalent circuits is responsible for power supply and cooling, Another set of loops is responsible for real-time monitoring of the current value of semiconductor refrigeration;

Optionally, the size of the pores is 0.5 μm-5 μm.

The preparation method of the top sheet is,

More preferably, the exposure time is 15s;

Preferably, the development time is 50s;

Preferably, the size of the small hole is 0.5 μm-5 μm;

More preferably, the time of etching is 2h;

More preferably, the exposure time is 15s;

More preferably, the metal is In, Sn or Al;

The preparation method of the lower tablet is,

More preferably, the exposure time is 20s;

More preferably, the etching temperature is 80°C; the etching time is 2h;

Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

S12. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;

Preferably, the thickness of the insulating layer is 30-150 nm;

Preferably, the size of the small hole is 0.5 μm-5 μm;

According to the structure of FIG. 1-FIG. 6, the following chips are fabricated. Among them, 1 is the high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy; 2 is the upper film; 3 is the lower film; 4 is the metal bonding layer; 5 is the central window; 51 is the central window of the upper film; 6 is the small hole; 7 is the injection port; 8 is the heating layer, 9 is the heating wire; 10 is the central area of the heating wire; 11 is the four contact electrodes; 12 is the silicon substrate; 13 and 14 are silicon nitride 15 is a support layer; 16 is an insulating layer 1; 17 is an insulating layer 2; 18 is a channel; 19 is a semiconductor refrigeration film; 191 is an n-type semiconductor refrigeration film; 192 is a p-type semiconductor refrigeration film; Conductive metal film.

Example 1: Preparation of high-resolution in-situ liquid phase temperature-changing chip for transmission electron microscopy

The preparation method of the top sheet is,

S1. Using the photolithography process (exposure for 15s in the hard contact mode of the UV lithography machine), transfer the central window pattern from the photolithography mask to the Si(100) crystal with silicon nitride or silicon oxide layers on both sides Circle A, and then develop for 50s in a positive gel developer to obtain wafer A-1; the thickness of the silicon nitride or silicon oxide layer is 5-200nm;

S3. Using the UV laser direct writing process, transfer the pinhole pattern of the center window from the photolithography mask to the front side of wafer A-2, then develop it in a positive-gel developer for 50s, and then rinse the surface with deionized water. , to obtain wafer A-3;

S4. Using reactive ion etching process, the thickness of silicon nitride at the small hole on the back of wafer A-3 is etched to 10nm-15nm, and the size of the small hole is 0.5μm-5μm; -3 was soaked in acetone with the front side facing up, and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;

S5. Put the backside of wafer A-4 into a potassium hydroxide solution with a mass percentage concentration of 20% for wet etching (the etching temperature is 80° C. and the time is 2h), and the etching is performed until the front side is only Leaving the film window, take out wafer A-4 and rinse with a large amount of deionized water to obtain wafer A-5;

S6. Using the photolithography process (exposure for 15s in the hard contact mode of the UV lithography machine), transfer the bonding layer pattern from the photolithography mask to the front side of the wafer A-5, and then develop it in the positive gel developer for 50s , and then rinse the surface with deionized water to obtain wafer A-6;

S7. Using the thermal evaporation coating process, the wafer A-6 is vapor-deposited with a metal bonding material to form a metal bonding layer with a thickness of 50-2000 nm to obtain wafer A-7; the metal is a low melting point metal; a low melting point metal is In, Sn or Al;

The preparation method of the lower tablet is,

S2. Using the photolithography process (exposure for 20s in the hard contact mode of the UV lithography machine, and the photoresist is AZ5214E), transfer the carrier film pattern in the freezing area from the photolithography mask to the front side of the above wafer, and then apply the positive photoresist After developing in the developer solution for 65s, the surface was cleaned with deionized water to obtain wafer B-1;

S3. Using the reactive ion etching process, etch the central window and the silicon nitride or silicon oxide at the freezing area on the silicon nitride layer on the back of the wafer B-1, and then turn the back of the wafer upward. Soak in acetone successively, rinse with acetone at last, remove the photoresist, and obtain wafer B-2; the length of the frozen layer semiconductor refrigeration film is 0.2-0.8mm, the width is 0.1-0.4mm, and the thickness is 50nm -500nm;

S4. Put the backside of wafer B-2 into a potassium hydroxide solution with a concentration of 20% by mass to carry out wet etching (the etching temperature is 80°C, and the etching time is 2h), until the bare After the leaked base silicon is completely etched, the wafer 2 is taken out, rinsed with a large amount of deionized water, and then blown dry to obtain wafer B-3;

S5. Using the PECVD process, silicon oxide or silicon nitride with a thickness of 0.5-5 μm is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;

S7. Use DC magnetron sputtering to sputter a conductive metal film on the front of wafer B-5, then put the front of wafer B-7 into acetone to soak and peel, and finally rinse with deionized water , remove the photoresist, leave the metal film, and obtain wafer B-6; the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;

S8. Using the photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7; the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

S9. Use RF magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone to soak and peel, and finally use deionization Rinse with water, remove the photoresist, leave the n-type semiconductor refrigeration film, and obtain wafer B-8; the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type type zinc telluride or n-type bismuth selenide;

S10. Using the photolithography process, transfer the p-type semiconductor pattern from the photolithography mask to the front side of the wafer B-8, and then develop it in a positive gel developer, and then rinse and clean the surface with deionized water to obtain wafer B -9; the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

S11. Use RF magnetron sputtering to sputter a p-type semiconductor refrigeration film on the front of wafer B-9, then put the front of wafer B-9 into acetone to soak and peel, and finally use deionization Rinse with water, remove the photoresist, leave a p-type semiconductor refrigeration film, and obtain wafer B-10; the p-type semiconductor adopts bismuth telluride or antimony telluride;

S12. Using the PECVD process, a layer of silicon nitride or silicon oxide or aluminum oxide with a thickness of 30-150 nm is grown on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;

S13. Use electron beam evaporation to evaporate a layer of metal heating wire on the front of wafer B-11, then put the front of wafer B-11 into acetone to soak and peel, and finally rinse with deionized water to remove Photoresist, leaving a metal heating wire to obtain wafer B-12; the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide; the The thickness of the metal heating wire is 50nm-500nm;

S14. Using the PECVD process, grow a layer of silicon nitride or silicon oxide or aluminum oxide with a thickness of 30-150nm on the metal heating wire of wafer B-12 as an insulating layer to obtain wafer B-13;

S15. Using the UV laser direct writing lithography process (the photoresist is AZ5214E; the output power is 260W/us), the small hole pattern of the center window is transferred from the photolithography mask to the front side of the wafer B-13, and then the Develop in a positive gel developer, and then rinse and clean the surface with deionized water to obtain wafer B-14;

S16. Using the reactive ion etching process, silicon nitride or silicon oxide is etched at the small holes on the back of the wafer B-14 (the size of the small holes is 0.5 μm-5 μm), and then the small holes of the wafer B-14 are etched. Soak it in acetone face up, and finally rinse it with acetone to remove the photoresist to obtain wafer B-15;

Example 2: The use of transmission electron microscope high-resolution in-situ liquid phase temperature change chip

The supersaturated calcium hydroxide aqueous solution (containing trace calcium hydroxide particles in the solution) was injected into the injection port of the high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy prepared in Example 1. Warm software, set the chip temperature to -30 °C, and obtain the electron microscope image in Figure 7. It can be seen from A and B in Figure 7 that as the temperature increases, the solution temperature increases, the solute solubility gradually decreases, and calcium hydroxide solid is precipitated. Nanoparticles are calcium hydroxide solids precipitated during the increase in chip temperature. By controlling the power of the chip, the temperature of the solution in the chip can be monitored and controlled in real time. This temperature range can be reached for both liquid phase reactions.

Example 3: Temperature Standard Curve

The transmission electron microscope high-resolution in-situ liquid phase temperature change chip is used to measure the temperature reached by the chip under different output powers by using a thermometer to obtain a temperature standard curve, and then accurately control the temperature by accurately adjusting the output power of the power supply equipment. The results are shown in Figure 8. The slope of the line graph in FIG. 8 roughly reflects the temperature change rate of 5-6°C per second, indicating that the temperature change rate is fast. The temperature range can reach -120°C to +100°C, and the maximum can reach +1000°C, indicating that the chip of the present invention has a large temperature control range, and can be used from low temperature to high temperature. The conventional products only have a single function of heating and cooling or freezing and cooling.

Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Variations, modifications, substitutions, and alterations to the above-described embodiments are possible within the scope of the present invention without departing from the scope of the present invention.

Claims

A high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy, the structure of which is that an upper sheet and a lower sheet are combined by a metal bonding layer to form an ultra-thin chamber by self-sealing; the upper sheet and the lower sheet are made of nitrogen on both sides A silicon substrate made of silicon carbide or silicon oxide, the upper sheet has two injection ports and a central viewing window 1, and is characterized in that the lower sheet is provided with a support layer, a freezing layer, an insulating layer 1, a heating layer, an insulating layer 2, and a channel. And the central window 2; the freezing layer is provided with four contact electrodes, no less than one level of semiconductor refrigeration film and conductive metal film, wherein the four contact electrodes are placed on the edge of the chip; in the central window 2 and the area where the semiconductor refrigeration film is located, After the silicon is etched away, a channel is left, and the support layer covers the channel; the semiconductor refrigeration film and the conductive metal film are placed on the support layer on the channel, and are not in direct contact with the silicon substrate; the center window 2 is centered on the support layer. A circle of metal film is deposited on the layer; the front end of the semiconductor refrigeration film is placed on the metal film, and the rear end is connected to the four contact electrodes on the freezing layer; if it is at least two-stage semiconductor refrigeration film, the rear end is sequentially made of metal The film connects all levels of semiconductor refrigeration films until the last level of semiconductor refrigeration films is connected to the four contact electrodes on the freezing layer; the freezing layer and the heating layer are separated by the insulating layer 1, and the heating layer is separated from the outside by the insulating layer 2; heating The layer has two contact electrodes and a spiral annular heating wire, and the heating wire is located above the semiconductor refrigeration film;

The area of the upper sheet is slightly smaller than that of the lower sheet, the central window 1 of the upper sheet and the central window 2 of the lower sheet are aligned, and both the central window 1 and the central window 2 have a plurality of small holes.
The high-resolution in-situ liquid phase temperature change chip according to claim 1, wherein the outer dimension of the lower piece is 2*2-10*10mm; preferably, the outer dimension of the lower piece is 4* 8mm;

Optionally, the thickness of the metal bonding layer is 50nm-2000nm; the material of the metal bonding layer is a low melting point metal; preferably, the material of the metal bonding layer is In, Sn or Al;

Optionally, the thickness of the silicon nitride or silicon oxide is 5-200nm;

Optionally, the thickness of the silicon substrate is 50-500 μm.
The high-resolution in-situ liquid phase temperature change chip of claim 1, wherein a circle-shaped metal film is deposited on the support layer;

Optionally, the support layer is silicon nitride or silicon oxide with a thickness of 0.5-5 μm.
The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy according to claim 1, wherein the freezing layer is configured as two sets of equivalent circuits, and the two sets of equivalent circuits use separate current source meters and voltage sources respectively. Meter control; one group of circuits in the two groups of equivalent circuits is responsible for power supply and refrigeration, and the other group of circuits is responsible for real-time monitoring of the current value during semiconductor refrigeration;

Optionally, the shape of the semiconductor refrigeration film of the freezing layer is a regular rectangle; the length is 0.2-0.8mm, the width is 0.1-0.4mm, and the thickness is 50nm-500nm; preferably, the semiconductor in the semiconductor refrigeration film is n-type semiconductors and p-type semiconductors, where n-type semiconductors are n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide; is polysilicon, p-type bismuth telluride, p-type silicon germanium, or p-type antimony telluride;

Optionally, the conductive metal in the conductive metal film is gold, silver or copper, with a thickness of 50nm-300nm;

Optionally, the size of the outer square of the conductive metal film is 100 μm*100 μm-500 μm*500 μm, and the size of the inner square is 5 μm*5 μm-100 μm*100 μm.
The high-resolution in-situ liquid phase temperature change chip according to claim 1, wherein the insulating layer 1 and the insulating layer 2 are all one layer, and the thickness is 30-150 nm; preferably, the insulating layer 1 and the insulating layer are 2 are made of silicon nitride or silicon oxide or aluminum oxide.
The high-resolution in-situ liquid phase temperature change chip according to claim 1, wherein the outer diameter of the spiral annular heating wire of the heating layer is 0.15-0.5 mm, and the thickness is 50-500 nm;

Optionally, the spiral annular heating wire adopts metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide;

Optionally, the shape of the helical annular heating wire on the heating layer is relatively symmetrical, and the heating wires are left with gaps and are not connected to each other; the heating wire in the center of the heating layer is placed on the intermediate insulating layer, and is not directly connected to the freezing layer contact.
The high-resolution in-situ liquid phase temperature change chip of TEM as claimed in claim 1, wherein the channel is square; preferably, the length of the channel is 4-7mm; the width is 0.25-0.9mm;

Optionally, the central window 1 and the central window 2 are square central windows; preferably, the size of the square central window is 5 μm*5 μm-100 μm*100 μm; more preferably, the size of the square central window is 20 μm *50μm;

Optionally, the size of the pores is 0.5 μm-5 μm.
The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy according to claim 1, wherein the preparation method of the upper chip is,

S1. Using the photolithography process, transfer the central window pattern from the photolithography mask to the Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then develop the wafer in a positive film developer A-1;

Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;

More preferably, the exposure time is 15s;

S2. Using the reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is put into acetone to soak, and finally a large amount of Rinse with deionized water to remove the photoresist to obtain wafer A-2;

S3. Using the UV laser direct writing process, transfer the small hole pattern of the central window from the photolithography mask to the front side of the wafer A-2, then develop it in a positive film developer, and then rinse the surface with deionized water. Obtain wafer A-3;

Preferably, the development time is 50s;

S4. Using the reactive ion etching process, the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S5. Put the back side of wafer A-4 into potassium hydroxide solution for wet etching, and etch until only the film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain a crystal circle A-5;

Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;

More preferably, the time of etching is 2h;

S6. Using the photolithography process, transfer the bonding layer pattern from the photolithography mask to the front side of wafer A-5, then develop it in a positive-gel developer, and then rinse and clean the surface with deionized water to obtain wafer A -6;

Preferably, the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;

More preferably, the exposure time is 15s;

S7. Using the thermal evaporation coating process, the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;

Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;

More preferably, the metal is In, Sn or Al;

S8. Laser scribing the wafer A-7, and dividing it into independent chips is the loading.
The high-resolution in-situ liquid phase temperature change chip for transmission electron microscopy according to claim 1, wherein the preparation method of the lower film is,

S1. Prepare Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

Preferably, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

S2. Using the photolithography process, transfer the film carrier pattern in the freezing zone from the photolithography mask to the front side of the above-mentioned wafer, then develop it in a positive-gel developer, and then clean the surface with deionized water to obtain wafer B-1;

Preferably, the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;

More preferably, the exposure time is 20s;

S3. Using the reactive ion etching process, etch the central window and the silicon nitride or silicon oxide at the freezing area on the silicon nitride layer on the back of the wafer B-1, and then turn the back of the wafer upward. It was soaked in acetone successively, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2;

Preferably, the length of the frozen layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50-500 nm;

S4. Put the backside of wafer B-2 into a potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out wafer 2, rinse it with a large amount of deionized water, and dry it to obtain Wafer B-3;

Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;

More preferably, the etching temperature is 80°C; the etching time is 2h;

S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;

Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

S6. Using the photolithography process, transfer the metal film pattern from the photolithography mask to the front side of the wafer B-4, then develop it in a positive-gel developer, and then rinse the surface with deionized water to obtain the wafer B- 5;

S7. Use DC magnetron sputtering to sputter a conductive metal film on the front of wafer B-5, then put the front of wafer B-7 into acetone to soak and peel, and finally rinse with deionized water , remove the photoresist and leave the metal film to obtain wafer B-6;

Preferably, the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;

S8. Using the photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;

Preferably, the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

S9. Use RF magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone to soak and peel, and finally use deionization Rinse with water to remove the photoresist, leaving the n-type semiconductor refrigeration film to obtain wafer B-8;

Preferably, the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

S10. Using the photolithography process, transfer the p-type semiconductor pattern from the photolithography mask to the front side of the wafer B-8, and then develop it in a positive gel developer, and then rinse and clean the surface with deionized water to obtain wafer B -9;

Preferably, the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

S11. Use RF magnetron sputtering to sputter a p-type semiconductor refrigeration film on the front of wafer B-9, then put the front of wafer B-9 into acetone to soak and peel, and finally use deionization Rinse with water to remove the photoresist, leaving the p-type semiconductor refrigeration film to obtain wafer B-10;

Preferably, the p-type semiconductor adopts bismuth telluride or antimony telluride;

S12. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;

Preferably, the thickness of the insulating layer is 30-150 nm;

S13. Use electron beam evaporation to evaporate a layer of metal heating wire on the front of wafer B-11, then put the front of wafer B-11 into acetone to soak and peel, and finally rinse with deionized water to remove Photoresist, leaving the metal heating wire to obtain wafer B-12;

Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

S14. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of wafer B-12 as an insulating layer to obtain wafer B-13;

Preferably, the thickness of the insulating layer is 30-150 nm;

S15. Using the UV laser direct writing lithography process, transfer the small hole pattern of the central window from the lithography mask to the front side of the wafer B-13, then develop it in a positive gel developer, and then rinse it with deionized water. surface to obtain wafer B-14;

Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;

S16. Using the reactive ion etching process, the silicon nitride or silicon oxide is etched at the small holes on the back of the wafer B-14, and then the wafer B-14 is soaked in acetone with the front side up, and finally used Rinse with acetone, remove the photoresist, and obtain wafer B-15;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S17. The wafer B-15 is laser diced and divided into independent chips, which are the next wafers.
A method for preparing a transmission electron microscope high-resolution in-situ liquid phase cryochip according to any one of claims 1-9, characterized in that,

The preparation method of the top sheet is,

S1. Using the photolithography process, transfer the central window pattern from the photolithography mask to the Si(100) wafer A with silicon nitride or silicon oxide layers on both sides, and then develop the wafer in a positive film developer A-1;

Preferably, the photolithography process is exposure in the hard contact mode of an ultraviolet photolithography machine; the thickness of the silicon nitride or silicon oxide layer is 5-200nm; the development time is 50s;

More preferably, the exposure time is 15s;

S2. Using the reactive ion etching process, a central window is etched on the silicon nitride layer on the front side of the wafer A-1, and then the front side of the wafer A-1 is put into acetone to soak, and finally a large amount of Rinse with deionized water to remove the photoresist to obtain wafer A-2;

S3. Using the UV laser direct writing process, transfer the small hole pattern of the central window from the photolithography mask to the front side of the wafer A-2, then develop it in a positive film developer, and then rinse the surface with deionized water. Obtain wafer A-3;

Preferably, the development time is 50s;

S4. Using the reactive ion etching process, the thickness of silicon nitride at the small holes on the back of wafer A-3 is etched to 10nm-15nm, and then the front side of wafer A-3 is placed in acetone and soaked in acetone. , and finally rinsed with acetone to remove the photoresist to obtain wafer A-4;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S5. Put the back side of wafer A-4 into potassium hydroxide solution for wet etching, and etch until only the film window is left on the front side, take out wafer A-4 and rinse with a large amount of deionized water to obtain a crystal circle A-5;

Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 80°C, and the time is 1.5-4h;

More preferably, the time of etching is 2h;

S6. Using the photolithography process, transfer the bonding layer pattern from the photolithography mask to the front side of wafer A-5, then develop it in a positive-gel developer, and then rinse and clean the surface with deionized water to obtain wafer A -6;

Preferably, the lithography process is exposure in the hard contact mode of the UV lithography machine; the development time is 50s;

More preferably, the exposure time is 15s;

S7. Using the thermal evaporation coating process, the wafer A-6 is evaporated with a metal bonding material to form a metal bonding layer, and the wafer A-7 is obtained;

Preferably, the metal is a low melting point metal; the thickness of the metal bonding layer is 50-2000 nm;

More preferably, the metal is In, Sn or Al;

S8. Laser scribing the wafer A-7, and dividing it into independent chips is the loading;

The preparation method of the lower tablet is,

S1. Prepare Si(100) wafer B with silicon nitride or silicon oxide layers on both sides;

Preferably, the thickness of the silicon nitride or silicon oxide layer is 5-200 nm;

S2. Using the photolithography process, transfer the film carrier pattern in the freezing zone from the photolithography mask to the front side of the above-mentioned wafer, then develop it in a positive-gel developer, and then clean the surface with deionized water to obtain wafer B-1;

Preferably, the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;

More preferably, the exposure time is 20s;

S3. Using the reactive ion etching process, etch the central window and the silicon nitride or silicon oxide at the freezing area on the silicon nitride layer on the back of the wafer B-1, and then turn the back of the wafer upward. It was soaked in acetone successively, and finally rinsed with acetone to remove the photoresist to obtain wafer B-2;

Preferably, the length of the frozen layer semiconductor refrigeration film is 0.2-0.8 mm, the width is 0.1-0.4 mm, and the thickness is 50-500 nm;

S4. Put the backside of wafer B-2 into a potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out wafer 2, rinse it with a large amount of deionized water, and dry it to obtain Wafer B-3;

Preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;

More preferably, the etching temperature is 80°C; the etching time is 2h;

S5. Using the PECVD process, silicon oxide or silicon nitride is grown on the front side of the etched silicon wafer of wafer B-3 to obtain wafer B-4;

Preferably, the thickness of silicon oxide or silicon nitride is 0.5-5 μm;

S6. Using the photolithography process, transfer the metal film pattern from the photolithography mask to the front side of the wafer B-4, then develop it in a positive-gel developer, and then rinse the surface with deionized water to obtain the wafer B- 5;

S7. Use DC magnetron sputtering to sputter a conductive metal film on the front of wafer B-5, then put the front of wafer B-7 into acetone to soak and peel, and finally rinse with deionized water , remove the photoresist and leave the metal film to obtain wafer B-6;

Preferably, the conductive metal is gold, silver or copper, and the thickness is 50nm-300nm;

S8. Using the photolithography process, the n-type semiconductor pattern is transferred from the photolithography mask to the front side of the wafer B-6, and then developed in a positive-gel developer, and then rinsed with deionized water to clean the surface to obtain wafer B -7;

Preferably, the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

S9. Use RF magnetron sputtering to sputter a layer of n-type semiconductor refrigeration film on the front side of wafer B-7, then put the front side of wafer B-7 into acetone to soak and peel, and finally use deionization Rinse with water to remove the photoresist, leaving the n-type semiconductor refrigeration film to obtain wafer B-8;

Preferably, the n-type semiconductor adopts n-type bismuth telluride, n-type silicon germanium, n-type lead telluride, n-type zinc telluride or n-type bismuth selenide;

S10. Using the photolithography process, transfer the p-type semiconductor pattern from the photolithography mask to the front side of the wafer B-8, and then develop it in a positive gel developer, and then rinse and clean the surface with deionized water to obtain wafer B -9;

Preferably, the p-type semiconductor adopts polysilicon, p-type bismuth telluride, p-type silicon germanium or p-type antimony telluride;

S11. Use RF magnetron sputtering to sputter a p-type semiconductor refrigeration film on the front of wafer B-9, then put the front of wafer B-9 into acetone to soak and peel, and finally use deionization Rinse with water to remove the photoresist, leaving the p-type semiconductor refrigeration film to obtain wafer B-10;

Preferably, the p-type semiconductor adopts bismuth telluride or antimony telluride;

S12. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the semiconductor refrigeration film of wafer B-10 as an insulating layer to obtain wafer B-11;

Preferably, the thickness of the insulating layer is 30-150 nm;

S13. Use electron beam evaporation to evaporate a layer of metal heating wire on the front side of wafer B-11, then put the front side of wafer B-11 into acetone to soak and peel, and finally rinse with deionized water to remove Photoresist, leaving the metal heating wire to obtain wafer B-12;

Preferably, the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;

S14. Using the PECVD process, a layer of silicon nitride, silicon oxide or aluminum oxide is grown on the metal heating wire of wafer B-12 as an insulating layer to obtain wafer B-13;

Preferably, the thickness of the insulating layer is 30-150 nm;

S15. Use the UV laser direct writing lithography process to transfer the small hole pattern of the central window from the lithography mask to the front side of the wafer B-13, then develop it in a positive gel developer, and then rinse it with deionized water. surface to obtain wafer B-14;

Preferably, the photoresist used in the UV laser direct writing process is AZ5214E; the output power is 260W/us;

S16. Using the reactive ion etching process, the silicon nitride or silicon oxide is etched at the small holes on the back of the wafer B-14, and then the wafer B-14 is soaked in acetone with the front side up, and finally used Rinse with acetone, remove the photoresist, and obtain wafer B-15;

Preferably, the size of the small hole is 0.5 μm-5 μm;

S17. Laser scribing the wafer B-15, and dividing it into independent chips is the next chip;

Assembly: Assemble the obtained upper and lower films under a microscope, and align the central windows of the upper and lower films.