WO2022028148A1 - 一种双频低噪声放大器电路、低噪声放大器及设备 - Google Patents

一种双频低噪声放大器电路、低噪声放大器及设备 Download PDF

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WO2022028148A1
WO2022028148A1 PCT/CN2021/102683 CN2021102683W WO2022028148A1 WO 2022028148 A1 WO2022028148 A1 WO 2022028148A1 CN 2021102683 W CN2021102683 W CN 2021102683W WO 2022028148 A1 WO2022028148 A1 WO 2022028148A1
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circuit
sub
noise amplifier
dual
low
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PCT/CN2021/102683
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English (en)
French (fr)
Inventor
郑耀华
何敏君
李平
苏强
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广州慧智微电子有限公司
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Publication of WO2022028148A1 publication Critical patent/WO2022028148A1/zh
Priority to US18/064,263 priority Critical patent/US20230108382A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a dual-frequency low-noise amplifier circuit, a low-noise amplifier and equipment.
  • the available wireless spectrum is gradually diversified.
  • electronic devices such as smart phones, PDAs, personal digital assistants and other electronic devices need to support multiple frequency bands.
  • the radio frequency receiving end of electronic equipment it is not only required to support multi-frequency bands, but also to support multi-channel reception, which requires higher and higher integration of the radio frequency receiver, and at the same time, the complexity of the radio frequency receiver is increasing. .
  • the LNA is the most critical part of the RF receiver.
  • the number of components required to support the low noise amplifier in the multi-band receiver is large, which is not conducive to high integration, and the cost is high; in addition, in the current design, the noise figure and gain are sacrificed. Obtaining broadband characteristics is not conducive to achieving optimal performance in each frequency band.
  • Embodiments of the present application provide a dual-frequency low-noise amplifier circuit, a low-noise amplifier, and equipment, which can realize low-noise amplification of a dual-band signal through the reconstruction of a switching frequency selection circuit, and can also achieve a noise coefficient in each frequency band. , gain and linearity performance are in the optimal state.
  • an embodiment of the present application provides a dual-frequency low-noise amplifier circuit, the dual-frequency low-noise amplifier circuit includes an amplifier sub-circuit and a switch frequency selection circuit; wherein,
  • the amplifying sub-circuit is used for gain amplifying the to-be-amplified radio frequency signal to obtain the amplified radio frequency signal, and output the amplified radio frequency signal;
  • the switch frequency selection circuit is connected to the amplifying sub-circuit, and is used to control the switch state in the switch frequency selection circuit based on the target frequency band corresponding to the radio frequency signal to be amplified, so that the dual-frequency low noise amplifier The circuit satisfies optimal performance at the target frequency band.
  • the switch frequency selection circuit includes an input matching subcircuit, an output matching subcircuit and a degenerate inductor subcircuit; wherein,
  • the input matching sub-circuit is connected to the input end of the amplifying sub-circuit, and is used for selecting an input matching mode corresponding to the target frequency band; and based on the input matching mode, the radio frequency signal to be amplified is transmitted into the input matching mode.
  • the amplifying sub-circuit ;
  • the output matching sub-circuit is connected to the output end of the amplifying sub-circuit, and is used for selecting an output matching mode corresponding to the target frequency band; and transmitting the amplified radio frequency signal based on the output matching mode;
  • the degenerate inductance sub-circuit is connected to the input end of the amplifying sub-circuit, and is used for selecting a degenerate inductance mode corresponding to the target frequency band; and based on the degenerate inductance mode, cooperates with the amplifying sub-circuit to execute the The gain amplification of the radio frequency signal to be amplified is described.
  • the target frequency band is a high frequency
  • the input matching subcircuit selects a first input mode; and based on the first input mode, transmits the to-be-amplified radio frequency signal into the amplifying subcircuit;
  • the output matching subcircuit selects a first output mode; and based on the first output mode, transmits the amplified radio frequency signal;
  • the degenerate inductance sub-circuit selects a first degenerate inductance mode; and based on the first degenerate inductance mode, cooperates with the amplifying sub-circuit to perform gain amplification on the radio frequency signal to be amplified.
  • the target frequency band when the target frequency band is a low frequency,
  • the input matching subcircuit selects a second input mode; and based on the second input mode, the radio frequency signal to be amplified is transmitted into the amplifying subcircuit;
  • the output matching subcircuit selects a second output mode; and based on the second output mode, transmits the amplified radio frequency signal;
  • the degenerate inductance sub-circuit selects a second degenerate inductance mode; and based on the second degenerate inductance mode, cooperates with the amplifying sub-circuit to perform gain amplification on the radio frequency signal to be amplified.
  • the input matching sub-circuit includes at least a first inductor and a first bypass switch; wherein the first inductor can be controlled to be in the bypass/disconnect state by controlling the on/off state of the first bypass switch. normal state.
  • the degenerate inductor sub-circuit includes at least a second inductor and a second bypass switch; wherein the second inductor can be controlled to be in the bypass/open state by controlling the on/off state of the second bypass switch. normal state.
  • the output matching sub-circuit includes at least a choke capacitor component and an output capacitor component; wherein,
  • the choke capacitor assembly at least includes a choke inductor and a third capacitor group, and the choke inductor and the third capacitor group are connected in parallel; wherein, the third capacitor group includes at least a third capacitor and a third capacitor group a connection switch, the third connection switch is used to control whether the third capacitor group affects the electrical parameters of the choke capacitor assembly;
  • the output capacitor assembly includes a fourth capacitor and a fifth capacitor group, and the fourth capacitor and the fifth capacitor group are connected in series; wherein, the fifth capacitor group at least includes a fifth capacitor and a fourth connection switch, The fourth connection switch is used to control whether the fifth capacitor group affects the electrical parameters of the output capacitor assembly.
  • the dual-frequency low-noise amplifier circuit further includes a DC blocking capacitor connected between the input matching sub-circuit and the amplifying sub-circuit.
  • the amplifying sub-circuit includes two amplifying transistors, and the two amplifying transistors are connected by a cascode structure.
  • an embodiment of the present application provides a low-noise amplifier, where the low-noise amplifier at least includes the dual-frequency low-noise amplifier circuit described in the first aspect.
  • an embodiment of the present application provides an electronic device, where the electronic device at least includes the low noise amplifier described in the second aspect.
  • Embodiments of the present application provide a dual-frequency low-noise amplifier circuit, a low-noise amplifier, and a device, wherein the dual-frequency low-noise amplifier circuit includes an amplifying sub-circuit and a switch frequency selection circuit; wherein the amplifying sub-circuit is used to treat the Amplifying the radio frequency signal for gain amplification, obtaining the amplified radio frequency signal, and outputting the amplified radio frequency signal; the switch frequency selection circuit is connected to the amplifying sub-circuit, and is used for the corresponding signal based on the radio frequency signal to be amplified.
  • the dual-frequency low-noise amplifier circuit can meet the optimal performance in the target frequency band.
  • the low-noise amplification of the dual-frequency signal is realized through the reconfigurable structure of the dual-frequency low-noise amplifier circuit, and parameters such as noise figure, gain and linearity can be optimized in each frequency band.
  • FIG. 1 is a schematic structural diagram of a dual-frequency low-noise amplifier circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of another dual-frequency low-noise amplifier circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of an equivalent circuit of a dual-frequency low-noise amplifier circuit provided by an embodiment of the present application; FIG. 1;
  • FIG. 4 is a schematic diagram 2 of an equivalent circuit of a dual-frequency low-noise amplifier circuit provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a low noise amplifier provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • a low noise amplifier is an amplifier with a very low noise figure. It is generally used as a high-frequency or intermediate-frequency preamplifier for various radio receivers, and an amplifier circuit for high-sensitivity electronic detection equipment.
  • the low noise amplifier is the most critical part of the radio frequency receiver.
  • the conventional multi-band receivers that require a low noise amplifier are mainly divided into two types. One requires an independent low noise amplifier for each frequency band to amplify the received signal.
  • the low-noise amplifier of each frequency band is optimized for the noise figure, gain and linearity of each frequency band; another kind of broadband low-noise amplifier is required to support multiple frequency band amplification, so that the received signals of multiple frequency bands can be Amplify.
  • Each frequency band requires an independent low-noise amplifier, so the number of low-noise amplifiers with optimal narrow-band performance will be proportional to the frequency band and the number of channels, resulting in a large number of devices, which is not conducive to high integration and high cost;
  • Multi-band amplification is performed through a broadband low-noise amplifier.
  • the broadband low-noise amplifier often sacrifices noise figure and gain to obtain broadband characteristics, which is not conducive to achieving optimal performance for each frequency band, including noise figure, gain and gain. Linearity.
  • An adjustable source degenerate inductance is a circuit including at least one inductor to degenerate the gain transistor and having a variable inductance.
  • Noise figure measures the noise level of the amplifier itself. This coefficient is a parameter that characterizes the deterioration degree of the noise performance of the amplifier. The bigger the better, the bigger the value is, the bigger the noise is in the transmission process, which reflects the unsatisfactory characteristics of the device or the channel.
  • an embodiment of the present application provides a dual-frequency low-noise amplifier circuit
  • the dual-frequency low-noise amplifier circuit includes an amplifying sub-circuit and a degenerate inductor sub-circuit; wherein the amplifying sub-circuit is used for a radio frequency signal to be amplified performing gain amplification to obtain an amplified radio frequency signal, and outputting the amplified radio frequency signal; the degraded inductance sub-circuit is connected to the amplifying sub-circuit for selecting a degraded inductance corresponding to the to-be-amplified radio frequency signal and based on the degenerated inductance mode, cooperate with the amplifying sub-circuit to complete the gain amplification of the to-be-amplified radio frequency signal.
  • the low-noise amplification of the dual-frequency signal is realized, and parameters such as noise figure, gain and linearity can be optimized in each frequency band.
  • FIG. 1 shows a schematic structural diagram of a dual-frequency low-noise amplifier circuit 10 provided by an embodiment of the present application.
  • the The dual-frequency low-noise amplifier circuit 10 includes an amplifier sub-circuit 101 and a switch frequency selection circuit; wherein,
  • the amplifying sub-circuit 101 is used for gain amplifying the to-be-amplified radio frequency signal to obtain the amplified radio frequency signal, and output the amplified radio frequency signal;
  • a switch frequency selection circuit connected to the amplifying sub-circuit 101, is used to control the switch state in the switch frequency selection circuit based on the target frequency band corresponding to the RF signal to be amplified, so that the dual-frequency low noise amplifier circuit Optimal performance is met in the target frequency band.
  • the dual-frequency low-noise amplifier circuit 10 can perform low-noise amplification on the input radio frequency signal, and mainly includes an amplifying sub-circuit 101 and a switching frequency selection circuit.
  • the essence of the amplifying sub-circuit 101 is a transistor that realizes signal amplification, and mainly plays the role of gain amplification of the RF signal to be amplified;
  • the switch frequency selection circuit is reconfigurable, and by controlling the switch state in the switch frequency selection circuit, it can be Therefore, the gain amplification of the dual-frequency low-noise amplifier circuit for the radio frequency signals to be amplified in different frequency bands is at the best performance.
  • the number of transistors included in the amplifying sub-circuit 101 is different according to different actual requirements. If the amplifying sub-circuit 101 includes two amplifying transistors, a cascode structure may be used. Therefore, in some embodiments, the amplifying sub-circuit 101 includes two amplifying transistors, and the two amplifying transistors are connected through a cascode structure.
  • the amplifying sub-circuit 101 includes at least three amplifying transistors, these amplifying transistors may be connected in a manner of stacking tubes (ie, a cascade structure). Therefore, in some embodiments, the amplifying circuit includes at least three amplifying transistors, and the at least three amplifying transistors are connected in a cascade configuration.
  • an amplifying transistor it generally includes three pins, ie, a source stage, a gate stage and a drain stage. If the amplifying sub-circuit 101 includes two amplifying transistors, as shown in FIG. 1 , the two amplifying transistors can be connected through a cascode cascade structure; if the amplifying sub-circuit 101 includes three or more amplifying transistors, Then these transistors need to be connected in a stack of tubes.
  • the switch states in the switch frequency selection circuit are different, so that the dual-frequency low noise amplifier circuit is optimal for amplifying the radio frequency signals to be amplified.
  • the switch frequency selection circuit includes an input matching sub-circuit 103, an output matching sub-circuit 104 and a degenerate inductance sub-circuit 102; wherein,
  • the input matching sub-circuit 103 is connected to the input end of the amplifying sub-circuit 101, and is used to select an input matching mode corresponding to the target frequency band; and based on the input matching mode, transmit the RF signal to be amplified. Enter the amplifying sub-circuit 101;
  • the output matching sub-circuit 104 is connected to the output end of the amplifying sub-circuit 101, and is used for selecting an output matching mode corresponding to the target frequency band; and transmitting the amplified radio frequency signal based on the output matching mode;
  • the degenerate inductance sub-circuit 102 is connected to the input end of the amplifying sub-circuit 101, and is used for selecting a degenerate inductance mode corresponding to the target frequency band; and based on the degenerate inductance mode, it cooperates with the amplifying sub-circuit to execute Amplifying the gain of the radio frequency signal to be amplified.
  • the essence of the degenerate inductance sub-circuit 102 is a reconfigurable source degenerate inductance device, and the main function is to provide the amplifying sub-circuit 101 with a reconfigurable degenerate inductance.
  • the degraded inductance sub-circuit 102 can provide the amplifying sub-circuit 101 with different degraded inductances under different degraded inductance modes, so as to cooperate with the amplifying sub-circuit 101 to complete the high-frequency/low-frequency RF signal to be amplified. gain.
  • the dual-frequency low-noise amplifier circuit 10 further includes an input matching sub-circuit 103 and an output matching sub-circuit 104, which respectively provide appropriate impedances to transmit corresponding radio frequency signals. Since the input signal of the dual-frequency low noise amplifier may be in a high frequency band or a low frequency band, the input matching sub-circuit 103 and the output matching sub-circuit 104 also include different modes.
  • an input matching mode corresponding to the RF signal to be amplified can be selected, so as to transmit the RF signal to be amplified with an appropriate impedance; in the output matching sub-circuit 104, the amplified RF signal can be selected and amplified Corresponding input matching mode to transmit the amplified RF signal with suitable impedance.
  • the dual-frequency low-noise amplifier circuit 10 may include four sub-circuits, an input matching sub-circuit 103 , an amplifier sub-circuit, a degenerate inductance sub-circuit 102 and an output matching sub-circuit 104 .
  • the amplifier sub-circuit completes the amplification of the radio frequency signal to be amplified
  • the input matching sub-circuit 103, the degenerate inductance sub-circuit 102 and the output matching sub-circuit 104 respectively complete the input matching, cooperative amplification and output of the radio frequency signal through the mode corresponding to the radio frequency signal. matching function.
  • the radio frequency signal to be amplified may be a high frequency signal. Therefore, in some embodiments, the target frequency band is high frequency,
  • the input matching sub-circuit 103 selects a first input mode; and based on the first input mode, transmits the to-be-amplified radio frequency signal into the amplifying sub-circuit 101;
  • the output matching subcircuit 104 selects a first output mode; and transmits the amplified radio frequency signal based on the first output mode;
  • the degenerate inductance sub-circuit 102 selects a first degenerate inductance mode; and based on the first degenerate inductance mode, cooperates with the amplifying sub-circuit 101 to complete the gain amplification of the to-be-amplified radio frequency signal.
  • the radio frequency signal to be amplified may also be a low frequency signal. Therefore, in some embodiments, the target frequency band is a low frequency
  • the input matching sub-circuit 103 selects a second input mode; and based on the second input mode, transmits the to-be-amplified radio frequency signal into the amplifying sub-circuit 101;
  • the output matching sub-circuit 104 selects a second output mode; and transmits the amplified radio frequency signal based on the second output mode;
  • the degenerate inductance sub-circuit 102 selects a second degenerate inductance mode; and based on the second degenerate inductance mode, cooperates with the amplifying sub-circuit 101 to perform gain amplification on the to-be-amplified radio frequency signal.
  • all of the sub-circuits include at least two circuit modes. Specifically, when the input matching sub-circuit 103 selects the first input mode, the degenerate inductance sub-circuit 102 selects the first degenerate inductance mode, and the output matching sub-circuit 104 selects the first output mode, the overall dual-frequency low-noise amplifier circuit can complete the Amplification of high-frequency signals; when the input matching sub-circuit 103 selects the second input mode, the degenerate inductance sub-circuit 102 selects the second degenerate inductance mode, and the output matching sub-circuit 104 selects the second output mode, the overall dual-frequency low noise The amplifier circuit can complete the amplification of the low frequency signal.
  • the input matching sub-circuit 103 includes at least a first inductor 1031 and a first bypass switch 1032 ; wherein the on/off state of the first bypass switch 1032 can be controlled to control the The first inductor 1031 is in a bypass/normal state.
  • the input matching sub-circuit 103 includes at least a first inductor 1031 and a first bypass switch 1032, and the first bypass switch 1032 can bypass the first inductor 1031 when closed. That is to say, if the first bypass switch 1032 is in the off state, the first inductor 1031 is a part of the input matching sub-circuit 103, and the circuit parameters of the first inductor 1031 will affect the circuit parameters of the input matching sub-circuit 103; When the bypass switch 1032 is closed, the first inductor 1031 is bypassed. At this time, the first inductor 1031 no longer affects the circuit parameters of the input matching sub-circuit 103 .
  • the input matching sub-circuit 103 may also include other specific components according to actual use requirements, such as other fixed inductors or other switches, which will not be described in detail here.
  • the connection state of the first inductor 1031 can be flexibly adjusted, and the specific circuit parameters of the input matching sub-circuit 103 can also be flexibly adjusted. Therefore, in some embodiments, when the first bypass switch 1032 is in the closed state, it is confirmed that the input matching sub-circuit 103 is in the first input mode; when the first bypass switch 1032 is in the open state In the case of the state, it is confirmed that the input matching sub-circuit 103 is in the second input mode.
  • the first bypass switch 1032 when the first bypass switch 1032 is in the closed state, the first inductor 1031 is bypassed, and the input matching sub-circuit 103 is in the first input mode, which can provide the input impedance corresponding to the high-frequency signal;
  • the circuit switch 1032 When the circuit switch 1032 is in an off state, the first inductor 1031 is in a connected state, and the input matching sub-circuit 103 is in a second input mode, which can provide an input impedance corresponding to a low-frequency signal.
  • the degenerate inductor sub-circuit 102 includes at least a second inductor 1021 and a second bypass switch 1022 ; wherein the on/off state of the second bypass switch 1022 can be controlled to control the The second inductor 1021 is in a bypass/normal state.
  • the degenerated inductor sub-circuit 102 includes a second inductor 1021 and a second bypass switch 1022, and the second bypass switch 1022 can bypass the second inductor 1021 when it is closed. That is to say, if the second bypass switch 1022 is in the off state, the second inductor 1021 is part of the degenerate inductor sub-circuit 102, and the circuit parameters of the second inductor will affect the circuit parameters of the degenerate inductor sub-circuit 102; When the circuit switch 1022 is closed, the second inductance 1021 is bypassed, and at this time, the second inductance 1021 no longer affects the circuit parameters of the degraded inductance sub-circuit 102 .
  • the degraded inductor sub-circuit 102 may also include other specific components according to actual use requirements, such as other fixed-connected inductors or other switches, which will not be described in detail here.
  • the connection state of the second inductor 1021 can be flexibly adjusted, and the specific circuit parameters of the degenerated inductor sub-circuit 102 can also be flexibly adjusted. Therefore, in some embodiments, when the second bypass switch 1022 is in a closed state, it is confirmed that the degenerated inductance sub-circuit 102 is in the first degenerated inductance mode; when the second bypass switch 1022 is in an open state In the case of the ON state, it is confirmed that the degenerated inductance sub-circuit 102 is in the second degenerated inductance mode.
  • the second bypass switch 1022 when the second bypass switch 1022 is in the closed state, the second inductor 1021 is bypassed, and the degenerated inductor sub-circuit 102 is in the first degenerated inductor mode, which can provide the amplifier sub-circuit 101 with the degradation corresponding to the high-frequency signal.
  • the amplifying sub-circuit 101 provides a suitable gain coefficient and noise coefficient for the high-frequency radio frequency signal, and realizes the low-noise amplification of the radio frequency signal to be amplified; when the second bypass switch 1022 is in the off state, the second The inductor 1021 is in the connected state, and the degraded inductor sub-circuit 102 is in the second degenerated inductance mode, which can provide the amplifying sub-circuit 101 with a degraded inductance corresponding to the low-frequency signal, so that the amplifying sub-circuit 101 provides a suitable gain for the low-frequency radio frequency signal coefficient and noise figure to achieve low-noise amplification of the RF signal to be amplified.
  • the output matching sub-circuit 104 at least includes a choke capacitor component 1041 and an output capacitor component 1042; wherein,
  • the choke capacitor assembly 1041 at least includes a choke inductor 10411 and a third capacitor group, and the choke inductor 10411 and the third capacitor group are connected in parallel; wherein, the third capacitor group includes at least a third capacitor 10412 and a third connection switch 10413, the third connection switch 10413 is used to control whether the third capacitor group affects the electrical parameters of the choke capacitor assembly 1041;
  • the output capacitor assembly 1042 at least includes a fourth capacitor 10421 and a fifth capacitor group, and the fourth capacitor 10421 and the fifth capacitor group are connected in series; wherein, the fifth capacitor group includes a fifth capacitor 10422 and a fifth capacitor group.
  • Four connection switches 10423 , the fourth connection switch 10423 is used to control whether the fifth capacitor group 1042 affects the circuit parameters of the output capacitor component 1042 .
  • the output matching sub-circuit 104 includes two parts, namely, a choke capacitor component 1041 and an output capacitor component 1042, and the choke inductor 10411 and the third capacitor group are connected in parallel.
  • the choke capacitor assembly 1041 includes a parallel choke inductor 10411 and a third capacitor group.
  • the third capacitor group is provided with a third capacitor 10412 and a third connection switch 10413, and the third connection switch 10413 can control the Whether the third capacitor group affects the electrical parameters of the choke capacitor component 1041 . That is to say, when the third connection switch 10413 is closed, the circuit parameters of the third capacitor group affect the electrical components of the choke capacitor assembly 1041; when the third connection switch 10413 is opened, the circuit parameters of the third capacitor group do not Electrical components that affect the choke capacitor component 1041 .
  • the output capacitor component 1042 includes a fourth capacitor 10421 and a fifth capacitor group connected in series, and the fifth capacitor group further includes a fifth capacitor 10422 and a fourth connection switch 10423.
  • the fourth connection switch 10423 mainly controls the fifth capacitor Whether the capacitor bank affects the circuit parameters of the output capacitor component 1042 . That is to say, when the fourth connection switch 10423 is closed, due to the existence of the fifth capacitor 10422, the performance parameters of the fifth capacitor group affect the circuit parameters of the output capacitor assembly 1042; when the fourth connection switch 10423 is closed, the fifth capacitor 10422 does not affect the circuit parameters of the fifth capacitor group, so the performance parameters of the fifth capacitor group do not affect the circuit parameters of the output capacitor element 1042 .
  • the output matching sub-circuit 104 may also include other specific components according to actual usage requirements, such as other fixed inductors or other switches, which will not be described in detail here.
  • the output matching sub-circuit 104 when the third connection switch 10413 is in the closed state and the fourth connection switch 10423 is in the closed state, the output matching sub-circuit 104 is in the first output mode and can provide the output impedance corresponding to the high frequency signal; When the 10413 is in the disconnected state and the fourth connection switch 10423 is in the disconnected state, the output matching sub-circuit 104 is in the second output mode, capable of providing an output impedance corresponding to the low-frequency signal.
  • the dual-frequency low noise amplifier circuit 10 further includes a DC blocking capacitor 105 , and the DC blocking capacitor 105 is connected between the input matching sub-circuit 103 and the amplifying sub-circuit 101 .
  • a DC blocking capacitor 105 is also required, which is mainly used to perform DC blocking processing on the radio frequency signal, and is connected between the input matching sub-circuit 103 and the amplifying sub-circuit 101.
  • the reconfigurable dual-frequency low-noise amplifier circuit 10 proposed in the embodiment of the present application is simple to implement, facilitates integration, and saves layout area. Optimum performance in noise figure, gain, and linearity is achieved within each frequency band. At the same time, the reconfigurable method can be applied to multi-band low-noise amplifiers.
  • an embodiment of the present application provides a dual-frequency low-noise amplifier circuit
  • the dual-frequency low-noise amplifier circuit includes an amplifying sub-circuit and a switch frequency selection circuit; wherein, the amplifying sub-circuit is used for a radio frequency signal to be amplified Gain amplification is performed to obtain an amplified radio frequency signal, and the amplified radio frequency signal is output; the switch frequency selection circuit is connected to the amplifying sub-circuit, and is used for the target frequency band corresponding to the to-be-amplified radio frequency signal, By controlling the switch state in the switch frequency selection circuit, the dual-frequency low noise amplifier circuit can satisfy the optimal performance in the target frequency band. In this way, through the reconfigurable structure of the low-noise amplifier circuit, the low-noise amplification of the dual-frequency signal is realized, and parameters such as noise figure, gain and linearity can be optimized in each frequency band.
  • the dual-frequency low-noise amplifier circuit 10 includes an adjustable input matching part 201 (equivalent to the aforementioned input matching sub-circuit), an amplifier tube part 202 (equivalent to the aforementioned amplifying sub-circuit), and an adjustable source degenerate inductance part 203 (equivalent to the aforementioned degenerate inductor sub-circuit) , an adjustable output matching part 204 (equivalent to the aforementioned output matching sub-circuit) and a DC blocking capacitor 205 .
  • the adjustable input matching part 201 includes an inductor 2011, an inductor 2012 and a switch 2013, wherein one end of the inductor 2011 is a signal input end, and the other end is connected in series with the inductor 2012; in addition, the inductor 2012 can be bypassed by the switch 2013;
  • Amplifying tube part 202 includes amplifying tube 2021 and amplifying tube 2022, and amplifying tube 2021 and amplifying tube 2022 are connected by a cascode structure; in addition, according to actual needs, amplifying tube 2021 and amplifying tube 2022 are additionally provided with separate bias voltages , the bias voltages are Vg1 and Vg2 respectively;
  • the DC blocking capacitor 205 is arranged between the adjustable input matching part 201 and the amplifier tube part 202. Specifically, one end of the DC blocking capacitor 205 is connected to the inductor 2012, and the other end is connected to the source stage of the amplifier tube 2021;
  • the adjustable bias voltage part 203 includes an inductor 2031, an inductor 2032 and a switch 2033, wherein one end of the inductor 2031 is grounded, the other end is connected in series with the inductor 2032, and the other end of the switch 2033 is connected to the amplifier tube 2021; in addition, the inductor 2032 can be switched 2033 bypass;
  • the adjustable output matching part 204 includes a first part and a second part; wherein, the first part includes a choke inductor 2041, a capacitor 2042, a capacitor 2043 and a switch 2044, the capacitor 2042 and the capacitor 2043 are connected in series with the choke inductor 2041, and the switch 204
  • the second part includes a capacitor 2045, a capacitor 2046, a capacitor 2047 and a switch 2048, the capacitor 2046 is connected in parallel with the capacitor 2047 and then connected in series with the capacitor 2045, and the switch 2048 is arranged on the branch of the capacitor 2046;
  • the first part and the second part are in parallel state. Specifically, one end of the choke inductor 2041 is connected to the amplifier tube 2022 and the other end is connected to the positive electrode; the other end of the capacitor 2047 can output the amplified radio frequency signal.
  • the dual-frequency low noise amplifier circuit 10 includes an amplifying tube part 202 , an adjustable source degeneration inductance part 203 , an adjustable input matching part 201 and an adjustable output matching part 204 .
  • the adjustable input matching part 201 is two inductances connected in series, one of which can be bypassed by a switch, so that the input inductance can be increased or decreased;
  • the choke inductance of the adjustable output matching part 204 is a part of the output matching,
  • the choke inductance is connected in parallel with the capacitor, and the capacitor part can be switched by a switch, so that the inductance of the equivalent inductance of the choke inductance and the parallel capacitor can be increased or decreased.
  • the adjustable output matching part 204 is also divided into output Capacitor, two capacitors are connected in parallel, which can be switched by a switch, and then connected in series with another capacitor, so that the capacitance of the output capacitor can be increased or decreased;
  • the adjustable source degradation inductance part is two inductances connected in series, which can be passed through One of the inductances is bypassed by the switch, so that the inductance of the source degeneration inductance can be increased or decreased;
  • the amplifying tube part 202 can be a traditional cascode structure, and can also be in the form of multiple stacked tubes.
  • the above adjustable input matching part 201 and the adjustable source degeneration inductance part 203 work together to achieve better noise figure matching in each corresponding frequency band, while the adjustable output matching part 204 can achieve in each corresponding frequency band. better gain and linearity.
  • FIG. 3 shows a schematic diagram 1 of an equivalent circuit of a dual-frequency low-noise amplifier circuit provided by an embodiment of the present application.
  • the switch 2013 in the adjustable input matching part 201 is turned on to form an equivalent resistance 2013-1, the equivalent resistance is small, and the inductance 2012 is connected in parallel and then in series with the inductance 2011, so that the total inductance It can be equivalent to the inductor 2011;
  • the switch 2044 in the adjustable output matching part 204 is closed to form an equivalent capacitor 2044-1, which has a smaller equivalent capacitance, which is connected in series with the capacitor 2042 and the capacitor 2043 and then in parallel with the choke inductor 2041.
  • the switch 2048 is closed to form an equivalent capacitor 2048-1, the equivalent capacitance is small, and the capacitor 2046 is connected in series with the capacitor 2047 in parallel with the capacitor.
  • 2045 are connected in series, so that the total capacitance can be equivalent to the parallel action of the capacitor 2045 and the capacitor 2047;
  • the switch 2033 in the adjustable source degeneration inductance part 203 is turned on to form an equivalent resistance 2033-1, and the equivalent resistance is small, It is connected in parallel with the inductor 2032 and then connected in series with the inductor 2031 , so that the total inductance can be equivalent to the inductor 2031 .
  • the adjustable input matching part 201 and the adjustable source degeneration inductance part 203 work together to achieve better noise figure matching in the high frequency band, while the adjustable output matching part 204 achieves better gain and Linearity.
  • FIG. 4 shows an equivalent circuit diagram 2 of a dual-frequency low-noise amplifier circuit provided by an embodiment of the present application.
  • the switch 2013 in the adjustable input matching part 201 is closed to form a capacitor 2013-2, the equivalent capacitance is small, which is connected in parallel with the inductor 2012 and then in series with the inductor 2011, so that the total inductance can be equal to The effect is the superposition of the inductor 2011 and the inductor 2012; the switch 2044 in the adjustable output matching part 204 is turned on to form an equivalent resistor 2044-2, the equivalent resistance is small, and the capacitor 2042 and the capacitor 2043 are connected in series with the choke inductor 2041 are connected in parallel, so that the total inductance can be equivalent to the combined action of the choke inductance 2041, the capacitor 2042 and the capacitor 2043.
  • the switch 2048 is turned on to form an equivalent resistance 2048-2.
  • the capacitor 2046 is connected in series with the capacitor 2047 and then connected in series with the capacitor 2045, so that the total capacitance can be equivalent to the combined effect of the capacitor 2046, the capacitor 2047 and the capacitor 2045;
  • the switch 2033 in the adjustable source degradation inductance part 203 is closed to form a capacitor 2033 -2, the equivalent capacitance is small, it is connected in parallel with the inductance 2032 and then in series with the inductance 2031, so that the total inductance can be equivalent to the inductance 2031 and the inductance 2932.
  • the adjustable input matching part 201 and the adjustable source degeneration inductance part 203 work together to achieve better noise figure matching in the low frequency band, while the adjustable output matching part 204 achieves better gain and linearity in the low frequency band .
  • the adjustable input matching part 201 adds an inductor and a switch in parallel on the original basis, and then connects it in series with the original part to realize multiple inductors.
  • the adjustable output matching part 204 is based on the original, the choke inductance part increases the capacitance and the switch in series, and then connects with the original part in parallel, so as to realize the equivalent increase or decrease of multiple inductances.
  • the output capacitor part adds capacitors and switches in series with branches and then connects to the original part in parallel to realize the equivalent increase or decrease of multiple capacitances;
  • the adjustable source degenerate inductance part 203 adds inductance and switches series branches on the original basis. And then parallel with the original part.
  • the adjustable input matching part 201 and the adjustable source degeneration inductance part 203 jointly realize noise figure matching for multiple frequency bands, and the adjustable input matching part can realize the optimal gain and linearity in multiple frequency bands.
  • the embodiment of the present application provides another dual-frequency low-noise amplifier circuit, and the foregoing embodiments are explained through this embodiment, and the low-noise amplification of the dual-frequency signal is realized through the reconfigurable structure of the low-noise amplifier circuit, Moreover, parameters such as noise figure, gain and linearity can be optimized in each frequency band.
  • FIG. 5 shows a schematic structural diagram of the low noise amplifier 30 provided by the embodiment of the present application.
  • the low-noise amplifier 30 includes at least the dual-frequency low-noise amplifier circuit 10 described in the foregoing embodiments, and the low-noise amplification of the dual-frequency signal is realized through the reconfigurable structure of the low-noise amplifier circuit, and Parameters such as noise figure, gain and linearity can be optimized in each frequency band.
  • FIG. 6 shows a schematic structural diagram of an electronic device 40 provided by an embodiment of the present application.
  • the electronic device 40 includes at least the low-noise amplifier 30 described in the foregoing embodiments.
  • the reconfigurable structure of the low-noise amplifier circuit realizes low-noise amplification of dual-frequency signals, and can perform low-noise amplification in each
  • the parameters such as noise figure, gain and linearity in the frequency band are in an optimal state.
  • the dual-frequency low-noise amplifier circuit includes an amplifying sub-circuit and a switching frequency selection circuit; wherein, the amplifying sub-circuit is used to gain amplify the to-be-amplified radio frequency signal, obtain the amplified radio frequency signal, and convert the amplified radio frequency signal Output; switch frequency selection circuit, which is connected to the amplifier sub-circuit, and is used to control the switch state in the switch frequency selection circuit based on the target frequency band corresponding to the radio frequency signal to be amplified, so that the dual-frequency low noise amplifier circuit can satisfy the maximum frequency in the target frequency band. excellent performance.
  • the low-noise amplification of the dual-frequency signal is realized through the reconfigurable structure of the dual-frequency low-noise amplifier circuit, and parameters such as noise figure, gain and linearity can be achieved in an optimal state in each frequency band.

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Abstract

本申请实施例提供了一种双频低噪声放大器电路、低噪声放大器及设备，所述双频低噪声放大器电路包括放大子电路和开关选频电路；其中，所述放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；所述开关选频电路，与所述放大子电路相连，用于基于所述待放大射频信号对应的目标频段，通过控制所述开关选频电路中的开关状态，使得所述双频低噪声放大器电路在所述目标频段下满足最优性能。这样，通过低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。

Description

一种双频低噪声放大器电路、低噪声放大器及设备
相关申请的交叉引用
本申请要求在2020年08月07日提交中国专利局、申请号为202010790745.8、申请名称为“一种双频低噪声放大器电路、低噪声放大器及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种双频低噪声放大器电路、低噪声放大器及设备。
背景技术
随着第五代移动通信技术(Fifth Generation，5G)的发展，可选择的无线频谱逐渐多样化，此时比如智能手机、掌上电脑、个人数字助理等电子设备需要支持多种频段工作。然而，对于电子设备的射频接收端来说，不仅要求支持多频段，还要求支持多通道接收，这对射频接收机的集成度要求越来越高，同时射频接收机的复杂度越来越大。
低噪声放大器是射频接收机最关键的部分。但是目前的相关技术方案中，支持多频段接收机中的低噪声放大器所需的器件数量多，不利于高度集成，而且成本较高；另外，在目前的设计中还会牺牲噪声系数以及增益来获得宽带特性，不利于每个频段实现最优的性能。
发明内容
本申请实施例提供了一种双频低噪声放大器电路、低噪声放大器及设备，通过开关选频电路的重构能够实现对双频段信号的低噪声放大，同时还能够实现每个频段内噪声系数、增益和线性度等性能处于最优状态。
本申请实施例的技术方案是这样实现的：
第一方面，本申请实施例提供了一种双频低噪声放大器电路，该双频低噪声放大器电路包括放大子电路和开关选频电路；其中，
所述放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；
所述开关选频电路，与所述放大子电路相连，用于基于所述待放大射频信号对应的目标频段，通过控制所述开关选频电路中的开关状态，使得所述双频低噪声放大器电路在所述目标频段下满足最优性能。
在一些实施例中，所述开关选频电路包括输入匹配子电路、输出匹配子电路和退化电感子电路；其中，
所述输入匹配子电路，与所述放大子电路的输入端相连，用于选择与所述目标频段对应的输入匹配模式；并基于所述输入匹配模式，将所述待放大射频信号传输进入所述放大子电路；
所述输出匹配子电路，与所述放大子电路的输出端相连，用于选择与所述目标频段对应的输出匹配模式；并基于所述输出匹配模式传输所述放大后射频信号；
所述退化电感子电路，与所述放大子电路的输入端相连，用于选择与所述目标频段对应的退化电感模式；并基于所述退化电感模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
在一些实施例中，在所述目标频段为高频的情况下，
所述输入匹配子电路，选择第一输入模式；并基于所述第一输入模式，将所述待放大射频信号传输进入所述放大子电路；
所述输出匹配子电路，选择第一输出模式；并基于所述第一输出模式，传输所述放大后射频信号；
所述退化电感子电路，选择第一退化电感模式；并基于所述第一退化电感模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
在一些实施例中，在所述目标频段为低频的情况下，
所述输入匹配子电路，选择第二输入模式；并基于所述第二输入模式，将 所述待放大射频信号传输进入所述放大子电路；
所述输出匹配子电路，选择第二输出模式；并基于所述第二输出模式，传输所述放大后射频信号；
所述退化电感子电路，选择第二退化电感模式；并基于所述第二退化电感模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
在一些实施例中，所述输入匹配子电路至少包括第一电感和第一旁路开关；其中，通过控制第一旁路开关的闭合/断开状态能够控制所述第一电感处于旁路/正常的状态。
在一些实施例中，在所述第一旁路开关处于闭合状态的情况下，确认所述输入匹配子电路处于第一输入模式；
在所述第一旁路开关处于断开状态的情况下，确认所述输入匹配子电路处于第二输入模式。
在一些实施例中，所述退化电感子电路至少包括第二电感和第二旁路开关；其中，通过控制第二旁路开关的闭合/断开状态能够控制所述第二电感处于旁路/正常的状态。
在一些实施例中，在所述第二旁路开关处于闭合状态的情况下，确认所述退化电感子电路处于第一退化电感模式；
在所述第二旁路开关处于断开状态的情况下，确认所述退化电感子电路处于第二退化电感模式。
在一些实施例中，所述输出匹配子电路至少包括扼流电容组件和输出电容组件；其中，
所述扼流电容组件至少包括扼流电感和第三电容组，且所述扼流电感和所述第三电容组并联；其中，所述第三电容组中至少包括有第三电容和第三连接开关，所述第三连接开关用于控制所述第三电容组是否影响所述扼流电容组件的电学参数；
所述输出电容组件包括第四电容和第五电容组，且所述第四电容和所述第五电容组串联；其中，所述第五电容组至少包括有第五电容和第四连接开关， 所述第四连接开关用于控制所述第五电容组是否影响所述输出电容组件的电学参数。
在一些实施例中，在所述第三连接开关处于断开状态且所述第四连接开关处于关闭的情况下，确认所述输出匹配子电路处于第一输出模式；
在所述第三连接开关处于闭合状态且所述第四连接开关处于开启的情况下，确认所述输出匹配子电路处于第二输出模式。
在一些实施例中，所述双频低噪声放大器电路还包括隔直流电容，所述隔直流电容连接在所述输入匹配子电路和所述放大子电路之间。
在一些实施例中，所述放大子电路包括两个放大晶体管，所述两个放大晶体管通过共源共栅结构进行连接。
第二方面，本申请实施例提供了一种低噪声放大器，该低噪声放大器至少包括如第一方面所述的双频低噪声放大器电路。
第三方面，本申请实施例提供了一种电子设备，该电子设备至少包括如第二方面所述的低噪声放大器。
本申请实施例提供了一种双频低噪声放大器电路、低噪声放大器及设备，所述双频低噪声放大器电路包括放大子电路和开关选频电路；其中，所述放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；所述开关选频电路，与所述放大子电路相连，用于基于所述待放大射频信号对应的目标频段，通过控制所述开关选频电路中的开关状态，使得所述双频低噪声放大器电路在所述目标频段下满足最优性能。这样，通过双频低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。
附图说明
图1为本申请实施例提供的一种双频低噪声放大器电路的结构示意图；
图2为本申请实施例提供的另一种双频低噪声放大器电路的结构示意图；
图3为本申请实施例提供的一种双频低噪声放大器电路的等效电路示意图 图一；
图4为本申请实施例提供的一种双频低噪声放大器电路的等效电路示意图图二；
图5为本申请实施例提供的一种低噪声放大器的结构示意图；
图6为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
随着5G移动通信技术的发展，在可选择的无线频谱多样化的情况下，移动终端需要支持多种频段工作，这样对于终端的射频接收端来说，不仅要求支持多频段，还要求支持多通道接收，这对终端射频接收机的集成度要求越来越高，且终端射频接收机的复杂度越来越大。
低噪声放大器是指噪声系数很低的放大器。一般用作各类无线电接收机的高频或中频前置放大器，以及高灵敏度电子探测设备的放大电路。低噪声放大器是射频接收机最关键的部分，常规支持多频段的接收机中要求低噪声放大器的做法主要分为两种，一种要求每个频段需要独立的低噪声放大器对接收信号进行放大，每个频段的低噪声放大器对每个频段的噪声系数、增益和线性度是实现最优的；另外一种要求支持多种频段放大的宽带低噪声放大器，这样对多种频段的接收信号都可以实现放大。
然而，上面支持多频段接收机中要求的低噪声放大器的方法缺点在于：
(1)每个频段要求独立的低噪声放大器，这样在窄带性能最优的低噪声放大器个数会与频段和通道数成正比，造成器件数量多，不利于高度集成，且成本较高；
(2)通过宽带低噪声放大器进行多频段放大，设计中宽带低噪声放大器往往会牺牲噪声系数以及增益来获得宽带特性，这样不利于针对每个频段实现最优的性能，包括噪声系数、增益和线性度。
可调源退化电感是包括用以使得增益晶体管退化并且具有可变电感的至少一个电感器的电路。
噪声系数来衡量放大器本身的噪声水平。该系数表征放大器的噪声性能恶化程度的一个参量，并不是越大越好，它的值越大，说明在传输过程中掺入的噪声也就越大，反映了器件或者信道特性的不理想。
基于此，本申请实施例提供了一种双频低噪声放大器电路，所述双频低噪声放大器电路包括放大子电路和退化电感子电路；其中，所述放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；所述退化电感子电路，与所述放大子电路相连，用于选择与所述待放大射频信号对应的退化电感模式；并基于所述退化电感模式，与所述放大子电路配合完成对所述待放大射频信号进行增益放大。这样，通过低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。
下面结合附图及具体实施例对本申请作进一步详细的说明。
本申请实施例提供的一种双频低噪声放大器电路10，参见图1，其示出了本申请实施例提供的一种双频低噪声放大器电路10的结构示意图，如图1所示，该双频低噪声放大器电路10包括放大子电路101和开关选频电路；其中，
该放大子电路101，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；
开关选频电路，与所述放大子电路101相连，用于基于所述待放大射频信号对应的目标频段，通过控制所述开关选频电路中的开关状态，使得所述双频低噪声放大器电路在所述目标频段下满足最优性能。
需要说明的是，双频低噪声放大器电路10能够对输入的射频信号进行低噪声放大，主要包含放大子电路101和开关选频电路。其中，放大子电路101的本质是实现信号放大的晶体管，主要起到对待放大射频信号进行增益放大的作用；开关选频电路是可重构的，通过控制开关选频电路中的开关状态，能够使得所述双频低噪声放大器电路对不同频段的待放大射频信号的增益放大处于最 佳性能。
还需要说明的是，根据实际需求不同，放大子电路101中包含的晶体管的数量不同，如果放大子电路101中包括两个放大晶体管，那么可以采用共源共栅结构。因此，在一些实施例中，所述放大子电路101包括两个放大晶体管，所述两个放大晶体管通过共源共栅结构进行连接。
除此之外，如果放大子电路101中包括至少三个放大晶体管，那么这些放大晶体管可以通过叠管(即级联结构)的方式进行连接。因此，在一些实施例中，所述放大电路包括至少三个放大晶体管，所述至少三个放大晶体管以级联结构进行连接。
也就是说，对于放大晶体管，一般包括三个管脚，即源级、栅极和漏级。如果放大子电路101包括两个放大晶体管，如图1所示，那么这两个放大晶体管可以通过共源共栅级联结构进行连接；如果放大子电路101包括三个或者更多的放大晶体管，则这些晶体管需要以叠管的方式进行连接。
这样，针对不同频段的待放大射频信号，开关选频电路中的开关状态不同，从而使得双频低噪声放大器电路对待放大射频信号的放大处于最佳。
进一步地，所述开关选频电路包括输入匹配子电路103、输出匹配子电路104和退化电感子电路102；其中，
所述输入匹配子电路103，与所述放大子电路101的输入端相连，用于选择与所述目标频段对应的输入匹配模式；并基于所述输入匹配模式，将所述待放大射频信号传输进入所述放大子电路101；
所述输出匹配子电路104，与所述放大子电路101的输出端相连，用于选择与所述目标频段对应的输出匹配模式；并基于所述输出匹配模式传输所述放大后射频信号；
所述退化电感子电路102，与所述放大子电路101的输入端相连，用于选择与所述目标频段对应的退化电感模式；并基于所述退化电感模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
需要说明的是，退化电感子电路102的本质是可重构的源退化电感器件， 主要作用为放大子电路101提供可重构的退化电感。具体来说，退化电感子电路102可以在不同的退化电感模式下，为放大子电路101提供不同的退化电感，从而与所述放大子电路101配合完成对高频/低频的待放大射频信号的增益。
需要说明的是，电路的阻抗匹配关系着整体电路的性能，错误的阻抗匹配将使电路不稳定，同时会使电路效率降低和非线性加大。因此，在双频低噪声放大器电路10中，还包括输入匹配子电路103和输出匹配子电路104，分别提供合适的阻抗以传输相应的射频信号。由于双频低噪声放大器的输入信号可以是高频段的，也可以是低频段的，所以输入匹配子电路103和输出匹配子电路104同样也包括不同的模式。
具体地，输入匹配子电路103中，可以选择与待放大射频信号对应的输入匹配模式，以利用合适的阻抗传输所述待放大射频信号；输出匹配子电路104中，可以选择与放大后射频信号对应的输入匹配模式，以利用合适的阻抗传输所述放大后射频信号。
综上所述，双频低噪声放大器电路10可以包括四个子电路，输入匹配子电路103、放大器子电路、退化电感子电路102和输出匹配子电路104。其中，放大器子电路完成对待放大射频信号的放大，输入匹配子电路103、退化电感子电路102和输出匹配子电路104分别通过与射频信号相应的模式完成与射频信号的输入匹配、配合放大和输出匹配的功能。
还需要说明的是，待放大射频信号可以是高频信号。因此，在一些实施例中，所述目标频段为高频，
所述输入匹配子电路103，选择第一输入模式；并基于所述第一输入模式，将所述待放大射频信号传输进入所述放大子电路101；
所述输出匹配子电路104，选择第一输出模式；并基于所述第一输出模式，传输所述放大后射频信号；
所述退化电感子电路102，选择第一退化电感模式；并基于所述第一退化电感模式，与所述放大子电路101配合完成对所述待放大射频信号进行增益放大。
除此之外，所述待放大射频信号也可以为低频信号。因此，在一些实施例中，所述目标频段为低频，
所述输入匹配子电路103，选择第二输入模式；并基于所述第二输入模式，将所述待放大射频信号传输进入所述放大子电路101；
所述输出匹配子电路104，选择第二输出模式；并基于所述第二输出模式，传输所述放大后射频信号；
所述退化电感子电路102，选择第二退化电感模式；并基于所述第二退化电感模式，与所述放大子电路101配合执行对所述待放大射频信号的增益放大。
需要说明的是，除了放大子电路101之外，通过重构选频电路中开关状态的改变，使得其中的子电路都包括至少两种电路模式。具体地，在输入匹配子电路103选择第一输入模式、退化电感子电路102选择第一退化电感模式且输出匹配子电路104选择第一输出模式的情况下，整体双频低噪声放大电路能够完成对高频信号的放大；在输入匹配子电路103选择第二输入模式、退化电感子电路102选择第二退化电感模式且输出匹配子电路104选择第二输出模式的情况下，整体双频低噪声放大电路能够完成对低频信号的放大。
在一种具体的设计方式中，所述输入匹配子电路103至少包括第一电感1031和第一旁路开关1032；其中，通过控制第一旁路开关1032的闭合/断开状态能够控制所述第一电感1031处于旁路/正常的状态。
需要说明的是，输入匹配子电路103中至少包括第一电感1031和第一旁路开关1032，第一旁路开关1032在闭合时能够使第一电感1031旁路。也就是说，如果第一旁路开关1032处于断开状态，第一电感1031是输入匹配子电路103的一部分，第一电感1031的电路参数会影响输入匹配子电路103的电路参数；但是第一旁路开关1032闭合时，第一电感1031被旁路，此时第一电感1031不再影响输入匹配子电路103的电路参数。
除此之外，输入匹配子电路103还会根据实际使用需求包括其他具体的元器件，例如其他固定连接的电感，或者其他开关，在此不做赘述。
这样，通过控制第一旁路开关1032可以灵活调整第一电感1031的连接状 态，也就可以灵活调整输入匹配子电路103的具体电路参数。因此，在一些实施例中，在所述第一旁路开关1032处于闭合状态的情况下，确认所述输入匹配子电路103处于第一输入模式；在所述第一旁路开关1032处于断开状态的情况下，确认所述输入匹配子电路103处于第二输入模式。
也就是说，当第一旁路开关1032处于闭合状态下，第一电感1031被旁路，输入匹配子电路103处于第一输入模式，能够提供与高频信号相应的输入阻抗；当第一旁路开关1032处于断开状态下，第一电感1031处于连接状态，输入匹配子电路103处于第二输入模式，能够提供与低频信号相应的输入阻抗。
在一种具体的设计方式中，所述退化电感子电路102至少包括第二电感1021和第二旁路开关1022；其中，通过控制第二旁路开关1022的闭合/断开状态能够控制所述第二电感1021处于旁路/正常的状态。
需要说明的是，退化电感子电路102中包括第二电感1021和第二旁路开关1022，第二旁路开关1022在闭合时能够使第二电感1021旁路。也就是说，如果第二旁路开关1022处于断开状态，第二电感1021是退化电感子电路102的一部分，第二电感的电路参数会影响退化电感子电路102的电路参数；但是第二旁路开关1022闭合时，第二电感1021被旁路，此时第二电感1021不再影响退化电感子电路102的电路参数。
除此之外，退化电感子电路102还会根据实际使用需求包括其他具体的元器件，例如其他固定连接的电感，或者其他开关，在此不做赘述。
这样，通过控制第二旁路开关1022可以灵活调整第二电感1021的连接状态，也就可以灵活调整退化电感子电路102的具体电路参数。因此，在一些实施例中，在所述第二旁路开关1022处于闭合状态的情况下，确认所述退化电感子电路102处于第一退化电感模式；在所述第二旁路开关1022处于断开状态的情况下，确认所述退化电感子电路102处于第二退化电感模式。
也就是说，当第二旁路开关1022处于闭合状态下，第二电感1021被旁路，退化电感子电路102处于第一退化电感模式，能够给放大子电路101提供与高频信号相应的退化电感，以使得所述放大子电路101为高频的射频信号提供合 适的增益系数和噪声系数，实现待放大射频信号的低噪声放大；当第二旁路开关1022处于断开状态下，第二电感1021处于连接状态，退化电感子电路102处于第二退化电感模式，能够给放大子电路101提供与低频信号相应的退化电感，以使得所述放大子电路101为低频的射频信号提供合适的增益系数和噪声系数，以实现待放大射频信号的低噪声放大。
在一种具体的设计方式中，所述输出匹配子电路104至少包括扼流电容组件1041和输出电容组件1042；其中，
所述扼流电容组件1041至少包括扼流电感10411和第三电容组，且所述扼流电感10411和所述第三电容组并联；其中，所述第三电容组中至少包括有第三电容10412和第三连接开关10413，所述第三连接开关10413用于控制所述第三电容组是否影响所述扼流电容组件1041的电学参数；
所述输出电容组件1042至少包括第四电容10421和第五电容组，且所述第四电容10421和所述第五电容组串联；其中，所述第五电容组包括有第五电容10422和第四连接开关10423，所述第四连接开关10423用于控制所述第五电容组1042是否影响所述输出电容组件1042的电路参数。
需要说明的是，输出匹配子电路104包括两个部分，分别是扼流电容组件1041和输出电容组件1042，且所述扼流电感10411和所述第三电容组并联。
对于扼流电容组件1041，其中包括并联状态的扼流电感10411和第三电容组，第三电容组中设有第三电容10412和第三连接开关10413，且第三连接开关10413能够控制所述第三电容组是否影响所述扼流电容组件1041的电学参数。也就是说，当第三连接开关10413闭合时，第三电容组的电路参数影响着扼流电容组件1041的电学组件；当第三连接开关10413断开时，第三电容组的电路参数并不影响扼流电容组件1041的电学组件。
对于输出电容组件1042，其中包括串联的第四电容10421和第五电容组，且第五电容组中又包括第五电容10422和第四连接开关10423，此时第四连接开关10423主要控制第五电容组是否影响所述输出电容组件1042的电路参数。也就是说，当第四连接开关10423闭合时，由于第五电容10422的存在，第五 电容组的性能参数影响着输出电容组件1042的电路参数；当第四连接开关10423闭合时，第五电容10422并不影响第五电容组的电路参数，所以第五电容组的性能参数并不影响输出电容组件1042的电路参数。
除此之外，输出匹配子电路104还会根据实际使用需求包括其他具体的元器件，例如其他固定连接的电感，或者其他开关，在此不做赘述。
这样，通过控制第三连接开关10413和第四连接开关10423可以灵活调整输出匹配子电路104的具体电路参数。因此，在一些实施例中，在所述第三连接开关10413处于断开状态且所述第四连接开关10423处于断开状态的情况下，确认所述输出匹配子电路104处于第一输出模式；所述第三连接开关10413处于闭合状态且所述第四连接开关10423处于闭合状态的情况下，确认所述输出匹配子电路104处于第二输出模式。
也就是说，当第三连接开关10413处于闭合状态且第四连接开关10423处于闭合下，输出匹配子电路104处于第一输出模式，能够提供与高频信号相应的输出阻抗；当第三连接开关10413处于断开状态且第四连接开关10423处于断开状态下，输出匹配子电路104处于第二输出模式，能够提供与低频信号相应的输出阻抗。
进一步地，在一些实施例中，所述双频低噪声放大器电路10还包括隔直流电容105，所述隔直流电容105连接在所述输入匹配子电路103和所述放大子电路101之间。
需要说明的是，对于双频低噪声放大器电路10中，还需要有隔直流电容105，主要用于对射频信号进行隔直流处理，连接在输入匹配子电路103和放大子电路101之间。
综上所述，本申请实施例提出的可重构的双频低噪声放大器电路10实现简单、利于集成、节省版图面积，单个低噪声放大器通过可重构实现了双频，有针对性地对每个频段内实现噪声系数、增益和线性度等性能最优。同时，该可重构的方法可适用多频段低噪声放大器。
基于此，本申请实施例提供了一种双频低噪声放大器电路，所述双频低噪 声放大器电路包括放大子电路和开关选频电路；其中，所述放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；所述开关选频电路，与所述放大子电路相连，用于基于所述待放大射频信号对应的目标频段，通过控制所述开关选频电路中的开关状态，使得所述双频低噪声放大器电路在所述目标频段下满足最优性能。这样，通过低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。
在本申请的又一实施例中，参见图2，其示出了本申请实施例提供的另一种双频低噪声放大器电路10的结构示意图，如图2所示，双频低噪声放大器电路10包括可调输入匹配部分201(相当于前述的输入匹配子电路)、放大管部分202(相当于前述的放大子电路)、可调源退化电感部分203(相当于前述的退化电感子电路)、可调输出匹配部分204(相当于前述的输出匹配子电路)和隔直流电容205。
其中，可调输入匹配部分201包括电感2011、电感2012和开关2013，其中，电感2011的一端为信号输入端，另一端与电感2012串联；另外，电感2012可以被开关2013旁路；
放大管部分202中包括放大管2021和放大管2022，放大管2021和放大管2022通过共源共栅结构连接；另外，根据实际需要，放大管2021和放大管2022另外设置有单独的偏置电压，偏置电压分别为Vg1和Vg2；
隔直流电容205设置在可调输入匹配部分201和放大管部分202之间，具体地，隔直流电容205的一端连接电感2012，另一端连接放大管2021的源级；
可调偏置电压部分203包括电感2031、电感2032和开关2033，其中，电感2031的一端接地，另一端与电感2032串联，开关2033的另一端连接到放大管2021；另外，电感2032可以被开关2033旁路；
可调输出匹配部分204包括第一部分和第二部分；其中，第一部分包括扼流电感2041、电容2042、电容2043和开关2044，电容2042和电容2043串联后与扼流电感2041并联，且开关204等设置在电容2042和电容2043之间；第 二部分包括电容2045、电容2046、电容2047和开关2048，电容2046与电容2047并联后与电容2045串联，且开关2048设置在电容2046的支路上；第一部分和第二部分处于并联状态，具体的，扼流电感2041的一端接放大管2022，另一端接正极；电容2047的另一端可输出放大后的射频信号。
也就是说，双频低噪声放大器电路10包括放大管部分202、可调源退化电感部分203、可调输入匹配部分201和可调输出匹配部分204。可调输入匹配部分201为两个电感串联，其中一个电感可通过开关旁路，这样可实现输入电感量的增大或减小；可调输出匹配部分204的扼流电感，为输出匹配一部分，同时，扼流电感与电容并联，电容部分可通过开关实现切换，这样可实现扼流电感与并联电容等效电感的电感量增大或减小，另外，可调输出匹配部分204还分为输出电容，其中两个电容并联，可通过开关实现切换，再与另外一个电容串联，这样可实现输出电容的电容量增大或减小；可调源退化电感部分为两个电感串联，其中可通过开关旁路其中一个电感，这样可实现源退化电感的电感量增大或减小；放大管部分202，可为传统的共源共栅结构，也可为多个叠管的方式。以上可调输入匹配部分201和可调源退化电感部分203共同作用，在对应的每个频段内实现较好的噪声系数匹配，而可调输出匹配部分204，在对应的每个频段内可实现较好的增益和线性度。
双频低噪声放大器电路10工作在高频时，参见图3，其示出了本申请实施例提供的一种双频低噪声放大器电路的等效电路示意图一。如图3所示，可调输入匹配部分201中的开关2013开启，形成一个等效电阻2013-1，等效的电阻量较小，与电感2012并联再与电感2011串联，这样总的电感量可等效为电感2011；可调输出匹配部分204中的开关2044关闭，形成一个等效电容2044-1，等效的电容量较小，与电容2042和电容2043串联再与扼流电感2041并联，这样总的电感量可等效为扼流电感2041，同时，开关2048关闭，形成一个等效电容2048-1，等效的电容量较小，与电容2046串联后与电容2047并联再与电容2045串联，这样总的电容量可等效为电容2045与电容2047并联作用；可调源退化电感部分203中的开关2033开启，形成一个等效电阻2033-1，等效的电 阻量较小，与电感2032并联再与电感2031串联，这样总的电感量可等效为电感2031。这样，可调输入匹配部分201和可调源退化电感部分203共同作用，在高频频段实现较好的噪声系数匹配，而可调输出匹配部分204，在高频频段内实现较好的增益和线性度。
可重构的双频低噪声放大器电路10工作在低频时，参见图4，其示出了本申请实施例提供的一种双频低噪声放大器电路的等效电路图二。如图4所示，可调输入匹配部分201中的开关2013关闭，形成一个电容2013-2，等效的电容量较小，与电感2012并联再与电感2011串联，这样总的电感量可等效为电感2011和电感2012叠加；可调输出匹配部分204中的开关2044开启，形成一个等效电阻2044-2，等效的电阻量较小，与电容2042和电容2043串联再与扼流电感2041并联，这样总的电感量可等效为扼流电感2041、电容2042和电容2043的共同作用，同时，开关2048开启，形成一个等效电阻2048-2，等效的电阻量较小，与电容2046串联后与电容2047并联再与2045串联，这样总的电容量可等效为电容2046、电容2047和电容2045共同作用；可调源退化电感部分203中的开关2033关闭，形成一个电容2033-2，等效的电容量较小，与电感2032并联再与电感2031串联，这样总的电感量可等效为电感2031和电感2932。这样，可调输入匹配部分201和可调源退化电感部分203共同作用，在低频频段实现较好的噪声系数匹配，而可调输出匹配部分204，在低频频段内实现较好的增益和线性度。
同时，以上方法可适用多频段低噪声放大器，根据本申请可重构的方法，可调输入匹配部分201在原有基础上，增加电感与开关并联枝节后再与原有部分串联，实现多个电感量增大或减小；可调输出匹配部分204在原有的基础上，扼流电感部分增加电容与开关串联枝节后再与原有部分并联，实现多个电感量等效增大或减小，同时，输出电容部分增加电容与开关串联枝节后再与原有部分并联，实现多个电容量等效增大或减小；可调源退化电感部分203在原有基础上，增加电感与开关串联枝节后再与原有部分并联。这样，可调输入匹配部分201和可调源退化电感部分203共同针对多个频段实现噪声系数匹配，而可 调输入匹配部分可实现多个频段内增益和线性度最优。
本申请实施例提供了另一种双频低噪声放大器电路，通过本实施例对前述实施例进行了解释说明，通过低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。
在本申请的又一实施例中，见图5，其示出了本申请实施例提供的低噪声放大器30的结构示意图。如图5所示，所述低噪声放大器30至少包括前述实施例所述的双频低噪声放大器电路10，通过低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。
在本申请的再一实施例中，见图6，其示出了本申请实施例提供的电子设备40的结构示意图。如图6所示，所述电子设备40至少包括前述实施例所述的低噪声放大器30，通过低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够在每个频段内实现噪声系数、增益和线性度等参数处于最优状态。
需要说明的是，在本申请中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
本申请所提供的几个方法实施例中所揭露的方法，在不冲突的情况下可以任意组合，得到新的方法实施例。
本申请所提供的几个产品实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的产品实施例。
本申请所提供的几个方法或设备实施例中所揭露的特征，在不冲突的情 况下可以任意组合，得到新的方法实施例或设备实施例。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请实施例中，双频低噪声放大器电路包括放大子电路和开关选频电路；其中，放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将放大后射频信号进行输出；开关选频电路，与放大子电路相连，用于基于待放大射频信号对应的目标频段，通过控制开关选频电路中的开关状态，使得双频低噪声放大器电路在目标频段下满足最优性能。这样，通过双频低噪声放大器电路的可重构结构实现了对双频信号的低噪声放大，而且能够实现每个频段内实现噪声系数、增益和线性度等参数处于最优状态。

Claims (14)

  1. 一种双频低噪声放大器电路，所述双频低噪声放大器电路包括放大子电路和开关选频电路；其中，
    所述放大子电路，用于对待放大射频信号进行增益放大，得到放大后射频信号，并将所述放大后射频信号进行输出；
    所述开关选频电路，与所述放大子电路相连，用于基于所述待放大射频信号对应的目标频段，通过控制所述开关选频电路中的开关状态，使得所述双频低噪声放大器电路在所述目标频段下满足最优性能。
  2. 根据权利要求1所述的双频低噪声放大器电路，其中，所述开关选频电路包括输入匹配子电路、输出匹配子电路和退化电感子电路；其中，
    所述输入匹配子电路，与所述放大子电路的输入端相连，用于选择与所述目标频段对应的输入匹配模式；并基于所述输入匹配模式，将所述待放大射频信号传输进入所述放大子电路；
    所述输出匹配子电路，与所述放大子电路的输出端相连，用于选择与所述目标频段对应的输出匹配模式；并基于所述输出匹配模式传输所述放大后射频信号；
    所述退化电感子电路，与所述放大子电路的输入端相连，用于选择与所述目标频段对应的退化电感模式；并基于所述退化电感模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
  3. 根据权利要求2所述的双频低噪声放大器电路，其中，在所述目标频段为高频的情况下，
    所述输入匹配子电路，选择第一输入模式；并基于所述第一输入模式，将所述待放大射频信号传输进入所述放大子电路；
    所述输出匹配子电路，选择第一输出模式；并基于所述第一输出模式，传输所述放大后射频信号；
    所述退化电感子电路，选择第一退化电感模式；并基于所述第一退化电感 模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
  4. 根据权利要求3所述的双频低噪声放大器电路，其中，在所述目标频段为低频的情况下，所述输入匹配子电路，选择第二输入模式；并基于所述第二输入模式，将所述待放大射频信号传输进入所述放大子电路；
    所述输出匹配子电路，选择第二输出模式；并基于所述第二输出模式，传输所述放大后射频信号；
    所述退化电感子电路，选择第二退化电感模式；并基于所述第二退化电感模式，与所述放大子电路配合执行对所述待放大射频信号的增益放大。
  5. 根据权利要求4所述的双频低噪声放大器电路，其中，
    所述输入匹配子电路至少包括第一电感和第一旁路开关；其中，通过控制第一旁路开关的闭合/断开状态能够控制所述第一电感处于旁路/正常的状态。
  6. 根据权利要求5所述的双频低噪声放大器电路，其中，
    在所述第一旁路开关处于闭合状态的情况下，确认所述输入匹配子电路处于第一输入模式；
    在所述第一旁路开关处于断开状态的情况下，确认所述输入匹配子电路处于第二输入模式。
  7. 根据权利要求4所述的双频低噪声放大器电路，其中，
    所述退化电感子电路至少包括第二电感和第二旁路开关；其中，通过控制第二旁路开关的闭合/断开状态能够控制所述第二电感处于旁路/正常的状态。
  8. 根据权利要求7所述的双频低噪声放大器电路，其中，
    在所述第二旁路开关处于闭合状态的情况下，确认所述退化电感子电路处于第一退化电感模式；
    在所述第二旁路开关处于断开状态的情况下，确认所述退化电感子电路处于第二退化电感模式。
  9. 根据权利要求4所述的双频低噪声放大器电路，其中，所述输出匹配子电路包括扼流电容组件和输出电容组件；其中，
    所述扼流电容组件至少包括扼流电感和第三电容组，且所述扼流电感和所 述第三电容组并联；其中，所述第三电容组中至少包括有第三电容和第三连接开关，所述第三连接开关用于控制所述第三电容组是否影响所述扼流电容组件的电学参数；
    所述输出电容组件包括第四电容和第五电容组，且所述第四电容和所述第五电容组串联；其中，所述第五电容组至少包括有第五电容和第四连接开关，所述第四连接开关用于控制所述第五电容组是否影响所述输出电容组件的电学参数。
  10. 根据权利要求9所述的双频低噪声放大器电路，其中，
    在所述第三连接开关处于断开状态且所述第四连接开关处于断开状态的情况下，确认所述输出匹配子电路处于第一输出模式；
    在所述第三连接开关处于闭合状态且所述第四连接开关处于闭合状态的情况下，确认所述输出匹配子电路处于第二输出模式。
  11. 根据权利要求2所述的双频低噪声放大器电路，其中，所述双频低噪声放大器电路还包括隔直流电容，所述隔直流电容连接在所述输入匹配子电路和所述放大子电路之间。
  12. 根据权利要求1-11任一项所述的双频低噪声放大器电路，其中，所述放大子电路包括两个放大晶体管，所述两个放大晶体管通过共源共栅结构进行连接。
  13. 一种低噪声放大器，所述低噪声放大器至少包括如权利要求1-12任一项所述的双频低噪声放大器电路。
  14. 一种电子设备，所述电子设备至少包括如权利要求13所述的低噪声放大器。
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