WO2022028053A1 - Fpga加速卡的功耗加压测试方法、装置及存储介质 - Google Patents

Fpga加速卡的功耗加压测试方法、装置及存储介质 Download PDF

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WO2022028053A1
WO2022028053A1 PCT/CN2021/096272 CN2021096272W WO2022028053A1 WO 2022028053 A1 WO2022028053 A1 WO 2022028053A1 CN 2021096272 W CN2021096272 W CN 2021096272W WO 2022028053 A1 WO2022028053 A1 WO 2022028053A1
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power consumption
dynamic
fpga
test
stress test
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French (fr)
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张静东
王江为
阚宏伟
徐亚明
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

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  • the present application relates to the field of power consumption stress test, and in particular, to a power consumption stress test method, device and computer-readable storage medium of an FPGA accelerator card.
  • FPGA Field Programmable Gate Array
  • FPGA-based accelerator cards are widely used in data centers.
  • FPGA accelerator cards are mass-produced and applied to data centers, they all need to undergo various software, hardware, and system tests, such as board card signal integrity testing, functional stress testing, power integrity testing, safety compliance testing, and functional testing.
  • the power consumption and heat dissipation test is an important test item to test whether the FPGA accelerator card can meet the requirements of the entire system by its own cooling device and server cooling strategy in the server environment.
  • the power consumption and heat dissipation test is carried out in the whole machine environment according to 1.2 times the maximum power consumption of the board design.
  • the board test firmware must also support signal integrity testing, various functional stress tests, etc.
  • the traditional CPU (central processing unit, central processing unit) chip usually uses special test software running under the operating system to run the power consumption stress test, such as PTU (Power Thermal Utility, power consumption stress test tool) software. , when it is necessary to increase the power consumption test by pressurization, you only need to install and run the software under the system, start the pressurization program, and set the pressurization parameters, and then the CPU power consumption can be increased for related tests.
  • the FPGA chip is different from the traditional CPU chip. Its internal hardware logic resources are configurable. Users can design a firmware version that uses no hardware logic resources according to different business needs. The power consumption of each firmware is also different. .
  • the power consumption of FPGA will increase with the increase of hardware logic resources required for its design, such as Register (register), LUT (Look Up Table, look-up table), etc. At the same time, the power consumption of FPGA will also increase with the main increases with increasing clock frequency. Therefore, in the related art, the method of pressurizing the FPGA acceleration card to conduct the power consumption heat dissipation test is to increase the usage of hardware resources in the FPGA acceleration card and to increase the frequency of the main clock used by these hardware resources.
  • the firmware of the FPGA accelerator card power consumption pressure test can only be used for the power consumption and heat dissipation test in the whole machine environment, and cannot be used for other functional test items such as signal integrity test and power integrity test.
  • the FPGA program generated by the existing FPGA compression method because these tests need to support all the complete function items of the board and the exclusive signal test function items, and the use environment is not necessarily the cooling environment of the whole server, usually cannot It is suitable for signal integrity testing, functional stress testing, etc., even by adjusting the number of register flips that are driven by the FPGA master clock, it is not possible to directly use the firmware with power compression function. Since the FPGA has included the hardware resources that may be driven at compile time, the static power consumption generated by this part is still very high.
  • the present application provides a power consumption compression test method, device and computer-readable storage medium for an FPGA acceleration card.
  • firmware with a power consumption compression function can be directly used Power consumption stress test for FPGA accelerator card.
  • One aspect of the embodiments of the present invention provides a power consumption stress test method for an FPGA acceleration card, including:
  • the static area is the hardware logic implementation area of other functional tests of non-power consumption stress test;
  • the dynamic PR area includes a blank mode that does not occupy hardware resources and a power consumption test mode that performs power consumption stress test.
  • the blank mode is used to perform a non-power stress test in conjunction with the static region.
  • the burning of the FPGA firmware with the partial reconfiguration function to the flash memory includes:
  • the dynamic PR region working in the blank mode and the static region are jointly compiled to generate the FPGA configuration file and the blank mode configuration file of the dynamic PR region, as the FPGA firmware with a partial reconfiguration function, and the FPGA firmware is burned recording to the flash memory.
  • the dynamic PR configuration file is pre-programmed into the flash memory or programmed into the flash memory after receiving the power consumption stress test request.
  • the method further includes:
  • the reconfiguration module is configured to enable the host side to load the dynamic PR configuration file into the dynamic PR region through the PCIe based on the partial reconfiguration method.
  • the setting of the working mode of the dynamic PR region as the power consumption test mode is:
  • the working mode of the dynamic PR region is configured through the PCIe as a power consumption test mode.
  • the area pre-division module is used to divide the FPGA accelerator card into a static area and a dynamic PR area based on the partial reconfiguration method, and burn the FPGA firmware with the partial reconfiguration function to the flash memory;
  • the static area is a non-power consumption compression
  • the dynamic PR area includes a blank mode that does not occupy hardware resources and a power consumption test mode that performs power consumption stress testing, and the blank mode is used in conjunction with the static area. Power consumption pressure test;
  • a stress test configuration module configured to set the working mode of the dynamic PR region to a power consumption test mode when a power consumption stress test request is received, and at the same time load the dynamic PR configuration file programmed in the flash memory into the Dynamic PR area;
  • a power consumption stress test execution module configured to call the power consumption stress test module to execute the power consumption stress test request in the dynamic PR region.
  • the area pre-division module includes:
  • the power consumption compression hardware logic setting sub-module generates a plurality of power consumption compression test modules using different numbers of logic resources for the dynamic PR region according to the configuration instruction of the power consumption compression test module sent by the host, as the power consumption compression test module.
  • the dynamic PR region works in the hardware logic under the power consumption test mode;
  • the firmware burning submodule is used for jointly compiling the dynamic PR region working in the blank mode and the static region to generate an FPGA configuration file and a blank mode configuration file for the dynamic PR region, as the FPGA firmware with a partial reconfiguration function , and burn and solidify the FPGA firmware to the flash memory.
  • An embodiment of the present invention further provides a power consumption pressurization test device for an FPGA acceleration card, including a processor configured to realize the power consumption of the FPGA acceleration card as described in any preceding item when executing a computer program stored in a memory Steps of the pressurized test method.
  • the embodiment of the present invention further provides a computer-readable storage medium, where a power consumption stress test program of an FPGA acceleration card is stored on the computer-readable storage medium, and the power consumption stress test program of the FPGA acceleration card is When the processor executes, the steps of implementing the power consumption stress test method of the FPGA acceleration card described in any one of the preceding items.
  • the advantage of the technical solution provided by the present application is that the FPGA partial reconfiguration technology is used to divide the hardware resources in the FPGA into a static area and a dynamic PR area, and the power consumption pressure test module is fixed in the dynamic PR area for realization, which is convenient to replace the functions of different levels.
  • Power consumption compression module; FPGA static area can be compiled with different levels of power consumption compression modules to generate power consumption compression configuration files of different levels.
  • the FPGA configuration file generated by compiling the blank mode in the dynamic PR area is suitable for the test field that does not require power consumption and will not increase the static power consumption of the board.
  • the upper layer flexibly controls whether to pressurize the FPGA, avoiding using the JTAG cable to load the FPGA firmware that switches different functions.
  • the dynamic PR configuration file generated by the joint compilation of the power consumption compression module is suitable for the test field that requires power consumption compression. After curing the FPGA project into the flash memory, it is necessary to configure the dynamic PR region to the power consumption compression mode through PCIe to achieve different
  • the test field is suitable for the purpose of unified test firmware, which reduces the test time of each test field, improves the efficiency of each test item, and simplifies the development and maintenance of test firmware.
  • FIG. 3 is a schematic flowchart of another power consumption stress test method for an FPGA accelerator card provided by an embodiment of the present invention.
  • FIG. 4 is a structural diagram of a specific implementation manner of a power consumption stress test apparatus for an FPGA acceleration card provided by an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of a method for testing power consumption under pressure of an FPGA accelerator card provided by an embodiment of the present invention.
  • An embodiment of the present invention may include the following contents:
  • S201 Divide the FPGA accelerator card into a static area and a dynamic PR area in advance based on the partial reconfiguration method, and burn the FPGA firmware with the partial reconfiguration function to the flash memory.
  • the FPGA partial reconfiguration technology is used to divide the hardware resources in the FPGA into a static area and a dynamic PR area.
  • FPGA Partial Reconfiguration PR is a loading technology that can dynamically reconfigure a local area in the FPGA. Using this technology, the partial reconfiguration area can be re-downloaded without affecting the normal operation of other areas. configuration file to realize the function of switching between different services.
  • This technology is very suitable for time-division multiplexing FPGA internal hardware resources to achieve complex systems with different functions, which can effectively reduce the hardware resource overhead of system implementation.
  • the dynamic PR area includes two working modes, and the blank mode can be set as the default mode.
  • the so-called default mode refers to the blank mode by default when the dynamic PR area is not set.
  • the working mode of the dynamic PR region can be set by the instructions of the upper layer.
  • the dynamic PR area in blank mode can be used in conjunction with the static area FPGA project to compile the project version including each functional test module, and generate the configuration file of the entire FPGA and the blank mode configuration file of the dynamic PR area, which can be used in the test field that does not require power consumption. .
  • the driver software can be installed on the host side as the upper-layer application software in advance, the dynamic PR area can be reconfigured through PCIe, and the PR configuration files of different working modes can be loaded into the dynamic PR of the FPGA through PCIe by using the upper-layer application software of the HOST host side. area to satisfy different test items.
  • the working mode of the dynamic PR region can be reconfigured through PCIe based on the driver software on the host side, and different levels of power consumption compression files can be loaded according to the user's power consumption compression test requirements.
  • S203 Invoke the power consumption stress test module to execute the power consumption stress test request in the dynamic PR region.
  • the FPGA partial reconfiguration technology is used to divide the hardware resources in the FPGA into a static area and a dynamic PR area, and the power consumption pressure test module is fixed in the dynamic PR area for implementation, which is convenient for replacing different levels of Power consumption compression module; the FPGA static area can be compiled in conjunction with different levels of power consumption compression modules to generate different levels of power consumption compression configuration files.
  • the FPGA configuration file generated by compiling the blank mode in the dynamic PR area is suitable for the test field that does not require power consumption and will not increase the static power consumption of the board.
  • the dynamic PR region and the static region working in blank mode are jointly compiled to generate the FPGA configuration file and the blank mode configuration file of the dynamic PR region as the FPGA firmware with partial reconfiguration function, and the FPGA firmware is burned and solidified into the flash memory.
  • the dynamic PR configuration files can be pre-programmed and solidified into flash memory, or can be stored after receiving power consumption After the pressure test request, it is burned and solidified to the flash memory.
  • different levels of power consumption boosting modules can be generated according to requirements, for example, two levels of using about 30% of hardware logic resources in the dynamic PR region and about 80% of hardware logic resources are used.
  • the power consumption compression module of the level combined with the static area FPGA project, compiles and generates two levels of power consumption compression dynamic PR area configuration files.
  • different levels of power consumption boosting modules can be flexibly configured, corresponding to the same level of power consumption boosting programs, different boosting parameters can be configured, and the power consumption of the FPGA can be controlled more accurately.
  • the static area may include PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard), DDR (Double Data Rate, double-rate memory) driver, optical module driver and reconfiguration module ; Only the connection interface is reserved between the static area and the dynamic PR area, and no other hardware logic resources in the area are used.
  • PCIe is used as the data communication interface and command issuing interface between the host and the FPGA accelerator card.
  • the working mode of the dynamic PR region can be configured through PCIe to be the power consumption test mode; the DDR driver is used for The double-rate memory is driven, the optical module driver is used to drive each optical module in the FPGA acceleration board, and the reconfiguration module is used to make the host side load the dynamic PR configuration file into the dynamic PR area through PCIe based on the partial reconfiguration method.
  • This embodiment unifies the power consumption boosting program and the normal function item testing program, which simplifies the development and maintenance of FPGA firmware in different test fields during the development and testing phase of the FPGA board.
  • the adjustable range of FPGA power consumption measurement is further expanded. Using PR technology to treat blank mode as level 0 power consumption, it can be used as other test areas that do not require FPGA power compression.
  • the embodiment of the present invention also provides a corresponding device for the power consumption stress test method of the FPGA acceleration card, which further makes the method more practical.
  • the device can be described separately from the perspective of functional modules and the perspective of hardware.
  • the power consumption stress test apparatus for an FPGA acceleration card provided by the embodiment of the present invention will be introduced below.
  • the power consumption stress test apparatus for an FPGA accelerator card described below and the power consumption stress test method for an FPGA accelerator card described above are mutually compatible. corresponding reference.
  • the area pre-division module 401 is used to divide the FPGA accelerator card into a static area and a dynamic PR area based on the partial reconfiguration method, and burn the FPGA firmware with the partial reconfiguration function to the flash memory;
  • the static area is a non-power stress test
  • the dynamic PR area includes a blank mode that does not occupy hardware resources and a power consumption test mode that performs power consumption stress tests. The blank mode is used to perform non-power consumption stress tests in conjunction with the static area.
  • the stress test configuration module 402 is configured to set the working mode of the dynamic PR region to the power consumption test mode when a power consumption stress test request is received, and simultaneously load the dynamic PR configuration file programmed in the flash memory into the dynamic PR region.
  • the power consumption stress test execution module 403 is configured to call the power consumption stress test module to execute the power consumption stress test request in the dynamic PR region.
  • the area pre-division module 401 may include:
  • the power consumption compression hardware logic setting sub-module generates multiple power consumption compression test modules using different numbers of logic resources for the dynamic PR region according to the configuration instruction of the power consumption compression test module sent by the host, as the dynamic PR The hardware logic of the region working in the power consumption test mode;
  • the firmware burning sub-module is used to jointly compile the dynamic PR region and the static region working in blank mode to generate the FPGA configuration file and the blank mode configuration file of the dynamic PR region, as the FPGA firmware with partial reconfiguration function, and the FPGA Firmware is burned and cured to flash memory.
  • the area pre-division module 401 may further include:
  • the dynamic PR configuration file generation sub-module is used to jointly compile multiple power consumption compression test modules and static regions to generate dynamic PR configuration files of various levels of power consumption compression; wherein, the dynamic PR configuration file is pre-burned and cured To flash memory or after receiving a power consumption stress test request, it is burned and solidified to flash memory.
  • the area pre-division module 401 may further include:
  • the pressurization parameter setting sub-module is used to automatically configure the corresponding pressurization parameters for the power consumption pressurization test module of the same level according to the power consumption pressurization parameter configuration command sent by the host to control the power consumption of the FPGA accelerator card. value.
  • the static area may include PCIe, DDR driver, optical module driver, and a reconfiguration module; only a connection interface is reserved between the static area and the dynamic PR area; the reconfiguration module It is used to make the host side load the dynamic PR configuration file into the dynamic PR area through PCIe based on the partial reconfiguration method.
  • the stress test configuration module 402 may also be a module that configures the working mode of the dynamic PR region through PCIe to a power consumption test mode according to a mode adjustment instruction sent by the host.
  • each functional module of the power consumption pressurization test device of the FPGA acceleration card can be specifically implemented according to the method in the above method embodiment, and the specific implementation process can refer to the relevant description of the above method embodiment, here No longer.
  • the embodiment of the present invention can directly use firmware with a power consumption compression function to perform a power consumption compression test on the FPGA acceleration card without increasing the static power consumption of the FPGA acceleration card.
  • FIG. 4 is a structural diagram of another power consumption pressurization test device for an FPGA accelerator card provided by an embodiment of the present application, the device includes a memory for storing a computer program; The steps of the power consumption stress test method for an FPGA acceleration card mentioned in an embodiment.
  • the memory may include one or more computer-readable storage media, which may be non-transitory. Memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash storage devices. In this embodiment, the memory is at least used to store the following computer program, where, after the computer program is loaded and executed by the processor, relevant steps of the power consumption stress test method for an FPGA accelerator card disclosed in any of the foregoing embodiments can be implemented.
  • the resources stored in the memory may also include an operating system and data, etc., and the storage mode may be short-term storage or permanent storage.
  • the operating system may include Windows, Unix, Linux, and the like.
  • the data may include, but are not limited to, data corresponding to test results, and the like.
  • the power consumption stress test apparatus of the FPGA acceleration card may further include an input/output interface, a communication interface, a power supply, and a communication bus, for example, a sensor may also be included.
  • each functional module of the power consumption pressurization test device of the FPGA acceleration card can be specifically implemented according to the method in the above method embodiment, and the specific implementation process can refer to the relevant description of the above method embodiment, here No longer.
  • the embodiment of the present invention can directly use firmware with a power consumption compression function to perform a power consumption compression test on the FPGA acceleration card without increasing the static power consumption of the FPGA acceleration card.
  • the power consumption stress test method of the FPGA acceleration card in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , to execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), electrically erasable programmable ROM, registers, hard disks, programmable Various media that can store program codes, such as removable disks, CD-ROMs, magnetic disks, or optical disks.
  • an embodiment of the present invention further provides a computer-readable storage medium storing a power consumption stress test program of an FPGA acceleration card, where the power consumption stress test program of the FPGA acceleration card is executed by a processor as any of the above The steps of the power consumption stress test method for an FPGA acceleration card according to an embodiment.
  • the power consumption compression test of the FPGA acceleration card can be performed directly using the firmware with the power consumption compression function.

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Abstract

一种FPGA加速卡的功耗加压测试方法、装置及计算机可读存储介质。其中，方法包括基于部分重配置方法将FPGA加速卡的硬件资源划分为作为执行正常功能测试的硬件逻辑实现区域的静态区域、包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式的动态PR区域，并将具有部分重配置功能的FPGA固件烧录至闪存。当接收到功耗加压测试请求，设置动态PR区域的工作模式为功耗测试模式，同时将闪存中烧录的动态PR配置文件加载至动态PR区域；调用功耗加压测试模块在动态PR区域中执行功耗加压测试请求，从而在不增加FPGA加速卡的静态功耗的基础上，可直接使用具有功耗加压功能的固件对FPGA加速卡进行功耗加压测试。

Description

FPGA加速卡的功耗加压测试方法、装置及存储介质
本申请要求于2020年8月7日提交中国专利局、申请号为202010793010.0、发明名称为“FPGA加速卡的功耗加压测试方法、装置及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及功耗加压测试领域，特别是涉及一种FPGA加速卡的功耗加压测试方法、装置及计算机可读存储介质。
背景技术
随着FPGA(Field Programmable Gate Array，现场可编程与门阵列)在异构计算领域的应用日益增长，基于FPGA的加速卡被广泛应用于数据中心。FPGA加速卡在被批量生产应用于数据中心时，均需经过各种软硬件、系统等的测试，如板卡信号完整性测试、各项功能压力测试、电源完整性测试、安规测试、功耗散热测试等。其中，功耗散热测试是测试FPGA加速卡在服务器整机环境中，自身散热装置和服务器散热策略是否能满足整个系统要求的重要测试项。通常功耗散热测试在整机环境下按照板卡设计最大功耗的1.2倍进行各项测试，同时板卡测试固件还必须支持信号完整性测试、各项功能压力测试等。
传统的CPU(central processing unit，中央处理器)芯片在进行功耗加压测试时，通常利用运行在操作系统下的专用测试软件运行实现，如PTU(Power Thermal Utility，功耗压力测试工具)软件，当需要加压增加功耗测试时，只需在系统下安装运行该软件，启动加压程序，设置加压参数，即可提高CPU功耗进行相关测试。而FPGA芯片不同于传统CPU芯片，其内部硬件逻辑资源是可配置的，用户可以根据不通的业务需求，设计出使用不用硬件逻辑资源的固件版本，每种固件的功耗也都是不一样的。FPGA的功耗会随着其设计所需硬件逻辑资源如Register(寄存器)、LUT(Look Up Table，查找表)等的增加而增加的，同时，FPGA的功耗也会 随着FPGA使用的主时钟频率的增大而提高。所以相关技术通过给FPGA加速卡加压以进行功耗散热测试的方法是提高FPGA加速卡内的硬件资源使用量及提高这些硬件资源使用的主时钟频率。而FPGA加速卡功耗加压测试的固件仅能用于整机环境下的功耗散热测试，无法用于信号完整性测试、电源完整性测试等其他功能测试项。如图1所示，FPGA加速卡本身无法存储固件程序，需要外部掉电不丢失存储设备如Flash(编码型快闪记忆体)闪存芯片存储FPGA加压程序，主机通过JTAG(Joint Test Action Group，联合测试行动小组)线缆将FPGA加压固件烧录至Flash芯片中，以便在系统整机环境下进行多次长时间测试。
相关技术在进行FPGA功耗加压测试过程中，为了尽可能的提高FPGA加速卡功耗，FPGA加压程序往往会使用很多FPGA加速卡内的硬件资源如LUT、寄存器、RAM(Random Access Memory，随机存取存储器)和DSP(Digital Signal Processing，数字信号处理)等，这些硬件资源一旦被在FPGA工程设计时例化使用，就会增加FPGA的静态功耗，这也是FPGA内使用硬件资源越多，其功耗越大的原因所在。这也限制了其功耗会在一个目标等级下，尽管调整FPGA的主时钟可以略微调整FPGA的功耗，仍不能较大范围地调整FPGA板卡的功耗。如果想要调整FPGA的功耗等级，只能重新设计FPGA工程，调整硬件资源使用量，改变其功耗等级，再通过JTAG将新的程序固化到Flash芯片中。其次，采用现有的FPGA加压方法生成的FPGA程序，由于这些测试需要支持板卡所有的完整功能项、专有的信号测试功能项，而且使用环境不一定是服务器整机散热环境，通常不能适用于信号完整性测试、功能压力测试等，即使通过调整使用FPGA主时钟驱动的寄存器翻转使能数量，也不能直接使用具有功耗加压功能的固件。由于FPGA在编译时已经将可能被驱动的硬件资源包含在内，这部分产生的静态功耗仍然很高。
鉴于此，如何在不增加FPGA加速卡的静态功耗的基础上，直接使用具有功耗加压功能的固件对FPGA加速卡进行功耗加压测试，是所属领域技术人员需要解决的技术问题。
发明内容
本申请提供了一种FPGA加速卡的功耗加压测试方法、装置及计算机可读存储介质，在不增加FPGA加速卡的静态功耗的基础上，可直接使用具有功耗加压功能的固件对FPGA加速卡进行功耗加压测试。
为解决上述技术问题，本发明实施例提供以下技术方案：
本发明实施例一方面提供了一种FPGA加速卡的功耗加压测试方法，包括：
预先基于部分重配置方法将FPGA加速卡划分为静态区域和动态PR(Partial Reconfiguration，部分重配置技术)区域，并将具有部分重配置功能的FPGA固件烧录至闪存；
当接收到功耗加压测试请求，设置所述动态PR区域的工作模式为功耗测试模式，同时将所述闪存中烧录的动态PR配置文件加载至所述动态PR区域；
调用所述功耗加压测试模块在所述动态PR区域中执行所述功耗加压测试请求；
其中，所述静态区域为非功耗加压测试的其他功能测试的硬件逻辑实现区域；所述动态PR区域包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式，所述blank模式用于联合所述静态区域执行非功耗加压测试。
可选的，所述将具有部分重配置功能的FPGA固件烧录至闪存包括：
根据接收到主机端发送的功耗加压测试模块配置指令，为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块，以作为所述动态PR区域工作于所述功耗测试模式下的硬件逻辑；
将工作于所述blank模式下的动态PR区域与所述静态区域联合编译生成FPGA配置文件和动态PR区域blank模式配置文件，以作为具有部分重配置功能的FPGA固件，并将所述FPGA固件烧录固化至所述闪存。
可选的，所述为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块之后，还包括：
将多个功耗加压测试模块与所述静态区域联合编译生成多种等级功耗 加压的动态PR配置文件；
其中，所述动态PR配置文件为预先被烧录固化至所述闪存或在接收到所述功耗加压测试请求之后，被烧录固化至所述闪存。
可选的，所述为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块之后，还包括：
根据接收到主机端发送的功耗加压参数配置指令，对同一等级的功耗加压测试模块自动配置相应的加压参数，以控制所述FPGA加速卡的功耗值。
可选的，所述静态区域包括PCIe(peripheral component interconnect express，高速串行计算机扩展总线标准)、DDR(Double Data Rate，双倍速率存储器)驱动、光模块驱动和重配置模块；所述静态区域与所述动态PR区域之间只保留连接接口；
所述重配置模块用于使得主机端基于部分重配置方法通过所述PCIe将所述动态PR配置文件加载至所述动态PR区域。
可选的，所述设置所述动态PR区域的工作模式为功耗测试模式为：
根据主机端发送的模式调整指令，通过所述PCIe配置所述动态PR区域的工作模式为功耗测试模式。
本发明实施例另一方面提供了一种FPGA加速卡的功耗加压测试装置，包括：
区域预划分模块，用于基于部分重配置方法将FPGA加速卡划分为静态区域和动态PR区域，并将具有部分重配置功能的FPGA固件烧录至闪存；所述静态区域为非功耗加压测试的其他功能测试的硬件逻辑实现区域；所述动态PR区域包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式，所述blank模式用于联合所述静态区域执行非功耗加压测试；
加压测试配置模块，用于当接收到功耗加压测试请求，设置所述动态PR区域的工作模式为功耗测试模式，同时将所述闪存中烧录的动态PR配置文件加载至所述动态PR区域；
功耗加压测试执行模块，用于调用所述功耗加压测试模块在所述动态 PR区域中执行所述功耗加压测试请求。
可选的，所述区域预划分模块包括：
功耗加压硬件逻辑设置子模块，根据接收到主机端发送的功耗加压测试模块配置指令，为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块，以作为所述动态PR区域工作于所述功耗测试模式下的硬件逻辑；
固件烧录子模块，用于将工作于所述blank模式下的动态PR区域与所述静态区域联合编译生成FPGA配置文件和动态PR区域blank模式配置文件，以作为具有部分重配置功能的FPGA固件，并将所述FPGA固件烧录固化至所述闪存。
本发明实施例还提供了一种FPGA加速卡的功耗加压测试装置，包括处理器，所述处理器用于执行存储器中存储的计算机程序时实现如前任一项所述FPGA加速卡的功耗加压测试方法的步骤。
本发明实施例最后还提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有FPGA加速卡的功耗加压测试程序，所述FPGA加速卡的功耗加压测试程序被处理器执行时实现如前任一项所述FPGA加速卡的功耗加压测试方法的步骤。
本申请提供的技术方案的优点在于，利用FPGA部分重配置技术将FPGA内硬件资源划分为静态区域和动态PR区域，将功耗加压测试模块固定在动态PR区域实现，便于更换不同等级的功耗加压模块；FPGA静态区域可以联合不同等级的功耗加压模块编译，生成不同等级的功耗加压配置文件。动态PR区域使用blank模式编译生成的FPGA配置文件适用于不需要功耗加压的测试领域，不会增加板卡的静态功耗，使用者只需要烧录一次固件至闪存，以后可以通过主机端上层灵活地控制是否对FPGA进行加压，避免使用JTAG线缆加载切换不同功能的FPGA固件。使用功耗加压模块联合编译生成的动态PR配置文件适用于需要功耗加压的测试领域，将FPGA工程固化至闪存后，需要再通过PCIe配置动态PR区域为功耗加压模式，达到不同测试领域适用统一测试固件的目的，减少了各测试领域的测试时间，提高了各测试项的效率，简化了测试固件开发与维护。
此外，本发明实施例还针对FPGA加速卡的功耗加压测试方法提供了相应的实现装置及计算机可读存储介质，进一步使得所述方法更具有实用性，所述装置及计算机可读存储介质具有相应的优点。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
为了更清楚的说明本发明实施例或相关技术的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的相关技术通过JTAG方式更新FPGA配置文件方法的框架示意图；
图2为本发明实施例提供的一种FPGA加速卡的功耗加压测试方法的流程示意图；
图3为本发明实施例提供的另一种FPGA加速卡的功耗加压测试方法的流程示意图；
图4为本发明实施例提供的FPGA加速卡的功耗加压测试装置的一种具体实施方式结构图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等是用于区别不同的对象，而不是用于描述特定的顺序。 此外术语“包括”和“具有”以及他们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可包括没有列出的步骤或单元。
在介绍了本发明实施例的技术方案后，下面详细的说明本申请的各种非限制性实施方式。
首先参见图2，图2为本发明实施例提供的一种FPGA加速卡的功耗加压测试方法的流程示意图，本发明实施例可包括以下内容：
S201：预先基于部分重配置方法将FPGA加速卡划分为静态区域和动态PR区域，并将具有部分重配置功能的FPGA固件烧录至闪存。
在本步骤中，利用FPGA部分重配置技术将FPGA内的硬件资源划分为静态区域和动态PR区域。FPGA部分重配置技术(Partial Reconfiguration，PR)为一种能够动态地重新配置FPGA内的局部区域的加载技术，利用这种技术能够在不影响其他区域正常工作的条件下，重新下载部分重配置区域的配置文件，实现切换不同业务的功能。这种技术非常适用于时分复用FPGA内部硬件资源来实现不同功能的复杂系统，能够有效地降低系统实现的硬件资源开销。举例来说，可将FPGA芯片划分为A区域和B区域，A为FPGA静态区域，B为可以部分重配置的动态PR区域，B区域可以在不影响A区域模块的正常工作情况下重新加载PR配置文件1和PR配置文件2，实现切换B区域内所跑业务的功能。
本申请的静态区域为非功耗加压测试的其他功能测试如信号完整性测试、电源完整性测试等正常功能测试的硬件逻辑实现区域。动态PR区域可包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式，其作为功耗加压测试的硬件逻辑实现区域，blank模式用于联合静态区域执行非功耗加压测试。也就是说，在服务器整机环境下，当需要执行FPGA功耗加压的测试，如散热测试、系统压力测试、安规测试等，将动态PR区域重配置成不同等级的功耗加压模块并工作于功耗测试模式，以满足不同测试项的需求；在不需要FPGA功耗加压功能的其他测试项，如信号完整性测试、电源完整性测试、板卡出厂基本测试等测试领域，可使用默认工作状态blank模式的动态PR区域配置文件或者通过上层命令将动态PR 区域配置成blank模式，移除功耗加压模块，以便在非服务器整机环境下进行其他项测试，统一了FPGA加速卡测试固件，简化测试固件开发和维护。
在本步骤中，动态PR区域包括两种工作模式，可设置blank模式为默认模式，所谓的默认模式是指没有设置动态PR区域时默认其工作状态为blank模式。当然，动态PR区域的工作模式可通过上层的指令进行设置。可使用blank模式下的动态PR区域联合静态区域FPGA工程编译包含各功能测试模块的工程版本，生成整个FPGA的配置文件和动态PR区域blank模式配置文件，面向不需要功耗加压的测试领域使用。将整个FPGA的配置文件烧录至闪存Flash内固化，这样上电动态PR区域默认为blank模式，FPGA没有加压，其他各项功能正常，供不需要功耗加压的测试。将具有PR功能的初始FPGA固件烧录至Flash，以后可以通过上层灵活地控制是否对FPGA进行加压，避免使用JTAG线缆加载切换不同功能的FPGA固件。
S202：当接收到功耗加压测试请求，设置动态PR区域的工作模式为功耗测试模式，同时将闪存中烧录的动态PR配置文件加载至动态PR区域。
在本步骤中，可预先在主机端安装驱动软件作为上层应用软件，通过PCIe重新配置动态PR区域，利用HOST主机端的上层应用软件通过PCIe可将不同工作模式的PR配置文件加载至FPGA的动态PR区域中，从而满足不同的测试项。对于需要功耗加压的测试，可基于主机端的驱动软件通过PCIe重新配置动态PR区域的工作模式，根据用户功耗加压测试需求加载不同等级的功耗加压文件。
S203：调用功耗加压测试模块在动态PR区域中执行功耗加压测试请求。
本实施的功耗加压测试模块固定在动态PR区域，当需要执行功耗加压测试如散热测试，在通过S102配置好动态PR区域后，在该区域执行功耗加压测试。
在本发明实施例提供的技术方案中，利用FPGA部分重配置技术将FPGA内硬件资源划分为静态区域和动态PR区域，将功耗加压测试模块固 定在动态PR区域实现，便于更换不同等级的功耗加压模块；FPGA静态区域可以联合不同等级的功耗加压模块编译，生成不同等级的功耗加压配置文件。动态PR区域使用blank模式编译生成的FPGA配置文件适用于不需要功耗加压的测试领域，不会增加板卡的静态功耗，使用者只需要烧录一次固件至闪存，以后可以通过主机端上层灵活地控制是否对FPGA进行加压，避免使用JTAG线缆加载切换不同功能的FPGA固件。使用功耗加压模块联合编译生成的动态PR配置文件适用于需要功耗加压的测试领域，将FPGA工程固化至闪存后，需要再通过PCIe配置动态PR区域为功耗加压模式，达到不同测试领域适用统一测试固件的目的，减少了各测试领域的测试时间，提高了各测试项的效率，简化了测试固件开发与维护。
需要说明的是，本申请中各步骤之间没有严格的先后执行顺序，只要符合逻辑上的顺序，则这些步骤可以同时执行，也可按照某种预设顺序执行，图1只是一种示意方式，并不代表只能是这样的执行顺序。
上述实施例中，FPGA内部硬件资源利用FPGA部分重配置技术划分出部分重配置区域作为功耗加压模块的硬件逻辑实现区域，将PR技术引入功耗加压测试，将功耗加压模块固定在PR区域实现，便于更换不同等级的功耗加压模块；同时，在FPGA静态区来实现信号完整性测试、电源完整性测试等其他测试项的功能。作为一种可选的实施方式，为了进一步提高FPGA功耗加压测试的灵活性，基于上述实施例，本申请还可包括：
根据接收到主机端发送的功耗加压测试模块配置指令，为动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块，以作为动态PR区域工作于功耗测试模式下的硬件逻辑。在生成多个不同等级的功耗加压测试模块之后，还可根据接收到主机端发送的功耗加压参数配置指令，对同一等级的功耗加压测试模块自动配置相应的加压参数，以控制FPGA加速卡的功耗值。
将工作于blank模式下的动态PR区域与静态区域联合编译生成FPGA配置文件和动态PR区域blank模式配置文件，以作为具有部分重配置功能的FPGA固件，并将FPGA固件烧录固化至闪存。
将多个功耗加压测试模块与静态区域联合编译生成多种等级功耗加压的动态PR配置文件；动态PR配置文件可为预先被烧录固化至闪存，也可在接收到功耗加压测试请求之后，再被烧录固化至闪存。
在本实施例中，根据需求可生成不同等级的功耗加压模块，如使用动态PR区域内30％左右的硬件逻辑资源和使用80％左右的硬件逻辑资源两种等级，将这两种不同等级的功耗加压模块作为动态PR区域的硬件逻辑，联合静态区域FPGA工程，编译生成两种等级的功耗加压动态PR区域配置文件。可以通过上层驱动软件，可以灵活地配置不同等级的功耗加压模块，对应同一等级的功耗加压程序，可以配置不同的加压参数，更加精确地控制FPGA功耗大小。
作为另外一种可选的实施方式，静态区域可包括PCIe(peripheral component interconnect express，高速串行计算机扩展总线标准)、DDR(Double Data Rate，双倍速率存储器)驱动、光模块驱动和重配置模块；静态区域与动态PR区域之间只保留连接接口，不使用区域内其他任何硬件逻辑资源。PCIe用于作为主机端和FPGA加速卡的数据通信接口和指令下发接口，如根据主机端发送的模式调整指令，可通过PCIe配置动态PR区域的工作模式为功耗测试模式；DDR驱动用于驱动双倍速率存储器，光模块驱动用于驱动FPGA加速板卡中的各光模块，重配置模块用于使得主机端基于部分重配置方法通过PCIe将动态PR配置文件加载至动态PR区域。
本实施例将功耗加压程序和正常功能项测试程序统一在了一起，简化了FPGA板卡开发测试阶段不同测试领域的FPGA固件的开发维护，通过动态PR区域灵活配置FPGA功耗等级，使FPGA功耗测可调范围进一步扩大。利用PR技术将blank模式视为0级功耗，可作为不需要FPGA功耗加压的其他测试领域使用。
本发明实施例还针对FPGA加速卡的功耗加压测试方法提供了相应的装置，进一步使得所述方法更具有实用性。其中，装置可从功能模块的角 度和硬件的角度分别说明。下面对本发明实施例提供的FPGA加速卡的功耗加压测试装置进行介绍，下文描述的FPGA加速卡的功耗加压测试装置与上文描述的FPGA加速卡的功耗加压测试方法可相互对应参照。
基于功能模块的角度，参见图4，图4为本发明实施例提供的FPGA加速卡的功耗加压测试装置在一种具体实施方式下的结构图，该装置可包括：
区域预划分模块401，用于基于部分重配置方法将FPGA加速卡划分为静态区域和动态PR区域，并将具有部分重配置功能的FPGA固件烧录至闪存；静态区域为非功耗加压测试的其他功能测试的硬件逻辑实现区域；动态PR区域包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式，blank模式用于联合静态区域执行非功耗加压测试。
加压测试配置模块402，用于当接收到功耗加压测试请求，设置动态PR区域的工作模式为功耗测试模式，同时将闪存中烧录的动态PR配置文件加载至动态PR区域。
功耗加压测试执行模块403，用于调用功耗加压测试模块在动态PR区域中执行功耗加压测试请求。
可选的，在本实施例的一些实施方式中，所述区域预划分模块401可包括：
功耗加压硬件逻辑设置子模块，根据接收到主机端发送的功耗加压测试模块配置指令，为动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块，以作为动态PR区域工作于功耗测试模式下的硬件逻辑；
固件烧录子模块，用于将工作于blank模式下的动态PR区域与静态区域联合编译生成FPGA配置文件和动态PR区域blank模式配置文件，以作为具有部分重配置功能的FPGA固件，并将FPGA固件烧录固化至闪存。
在本发明实施例的一些实施方式中，所述区域预划分模块401还可包括：
动态PR配置文件生成子模块，用于将多个功耗加压测试模块与静态区域联合编译生成多种等级功耗加压的动态PR配置文件；其中，动态PR 配置文件为预先被烧录固化至闪存或在接收到功耗加压测试请求之后，被烧录固化至闪存。
在本发明实施例的其他一些实施方式中，所述区域预划分模块401还可包括：
加压参数设置子模块，用于根据接收到主机端发送的功耗加压参数配置指令，对同一等级的功耗加压测试模块自动配置相应的加压参数，以控制FPGA加速卡的功耗值。
可选的，在本实施例的另一些实施方式中，所述静态区域可包括PCIe、DDR驱动、光模块驱动和重配置模块；静态区域与动态PR区域之间只保留连接接口；重配置模块用于使得主机端基于部分重配置方法通过PCIe将动态PR配置文件加载至动态PR区域。
在本发明实施例的一些实施方式中，所述加压测试配置模块402还可为根据主机端发送的模式调整指令，通过PCIe配置动态PR区域的工作模式为功耗测试模式的模块。
本发明实施例所述FPGA加速卡的功耗加压测试装置的各功能模块的功能可根据上述方法实施例中的方法具体实现，其具体实现过程可以参照上述方法实施例的相关描述，此处不再赘述。
由上可知，本发明实施例在不增加FPGA加速卡的静态功耗的基础上，可直接使用具有功耗加压功能的固件对FPGA加速卡进行功耗加压测试。
上文中提到的FPGA加速卡的功耗加压测试装置是从功能模块的角度描述，进一步的，本申请还提供一种FPGA加速卡的功耗加压测试装置，是从硬件角度描述。图4为本申请实施例提供的另一种FPGA加速卡的功耗加压测试装置的结构图，该装置包括存储器，用于存储计算机程序；处理器，用于执行计算机程序时实现如上述任一实施例提到的FPGA加速卡的功耗加压测试方法的步骤。
存储器可以包括一个或多个计算机可读存储介质，该计算机可读存储介质可以是非暂态的。存储器还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。本实施例中， 存储器至少用于存储以下计算机程序，其中，该计算机程序被处理器加载并执行之后，能够实现前述任一实施例公开的FPGA加速卡的功耗加压测试方法的相关步骤。另外，存储器所存储的资源还可以包括操作系统和数据等，存储方式可以是短暂存储或者永久存储。其中，操作系统可以包括Windows、Unix、Linux等。数据可以包括但不限于测试结果对应的数据等。
在一些实施例中，FPGA加速卡的功耗加压测试装置还可包括有输入输出接口、通信接口、电源以及通信总线，例如还可包括传感器。
本发明实施例所述FPGA加速卡的功耗加压测试装置的各功能模块的功能可根据上述方法实施例中的方法具体实现，其具体实现过程可以参照上述方法实施例的相关描述，此处不再赘述。
由上可知，本发明实施例在不增加FPGA加速卡的静态功耗的基础上，可直接使用具有功耗加压功能的固件对FPGA加速卡进行功耗加压测试。
可以理解的是，如果上述实施例中的FPGA加速卡的功耗加压测试方法以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，执行本申请各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、磁碟或者光盘等各种可以存储程序代码的介质。
基于此，本发明实施例还提供了一种计算机可读存储介质，存储有FPGA加速卡的功耗加压测试程序，所述FPGA加速卡的功耗加压测试程序被处理器执行时如上任意一实施例所述FPGA加速卡的功耗加压测试方法的步骤。
本发明实施例所述计算机可读存储介质的各功能模块的功能可根据上述方法实施例中的方法具体实现，其具体实现过程可以参照上述方法实施 例的相关描述，此处不再赘述。
在不增加FPGA加速卡的静态功耗的基础上，可直接使用具有功耗加压功能的固件对FPGA加速卡进行功耗加压测试。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
以上对本申请所提供的一种FPGA加速卡的功耗加压测试方法、装置及计算机可读存储介质进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。

Claims (10)

  1. 一种FPGA加速卡的功耗加压测试方法，其特征在于，包括：
    预先基于部分重配置方法将FPGA加速卡划分为静态区域和动态PR区域，并将具有部分重配置功能的FPGA固件烧录至闪存；
    当接收到功耗加压测试请求，设置所述动态PR区域的工作模式为功耗测试模式，同时将所述闪存中烧录的动态PR配置文件加载至所述动态PR区域；
    调用功耗加压测试模块在所述动态PR区域中执行所述功耗加压测试请求；
    其中，所述静态区域为非功耗加压测试的其他功能测试的硬件逻辑实现区域；所述动态PR区域包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式，所述blank模式用于联合所述静态区域执行非功耗加压测试。
  2. 根据权利要求1所述的FPGA加速卡的功耗加压测试方法，其特征在于，所述将具有部分重配置功能的FPGA固件烧录至闪存包括：
    根据接收到主机端发送的功耗加压测试模块配置指令，为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块，以作为所述动态PR区域工作于所述功耗测试模式下的硬件逻辑；
    将工作于所述blank模式下的动态PR区域与所述静态区域联合编译生成FPGA配置文件和动态PR区域blank模式配置文件，以作为具有部分重配置功能的FPGA固件，并将所述FPGA固件烧录固化至所述闪存。
  3. 根据权利要求2所述的FPGA加速卡的功耗加压测试方法，其特征在于，所述为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块之后，还包括：
    将多个功耗加压测试模块与所述静态区域联合编译生成多种等级功耗加压的动态PR配置文件；
    其中，所述动态PR配置文件为预先被烧录固化至所述闪存或在接收到所述功耗加压测试请求之后，被烧录固化至所述闪存。
  4. 根据权利要求2所述的FPGA加速卡的功耗加压测试方法，其特征 在于，所述为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块之后，还包括：
    根据接收到主机端发送的功耗加压参数配置指令，对同一等级的功耗加压测试模块自动配置相应的加压参数，以控制所述FPGA加速卡的功耗值。
  5. 根据权利要求1至4任意一项所述的FPGA加速卡的功耗加压测试方法，其特征在于，所述静态区域包括PCIe、DDR驱动、光模块驱动和重配置模块；所述静态区域与所述动态PR区域之间只保留连接接口；
    所述重配置模块用于使得主机端基于部分重配置方法通过所述PCIe将所述动态PR配置文件加载至所述动态PR区域。
  6. 根据权利要求5所述的FPGA加速卡的功耗加压测试方法，其特征在于，所述设置所述动态PR区域的工作模式为功耗测试模式为：
    根据主机端发送的模式调整指令，通过所述PCIe配置所述动态PR区域的工作模式为功耗测试模式。
  7. 一种FPGA加速卡的功耗加压测试装置，其特征在于，包括：
    区域预划分模块，用于基于部分重配置方法将FPGA加速卡划分为静态区域和动态PR区域，并将具有部分重配置功能的FPGA固件烧录至闪存；所述静态区域为非功耗加压测试的其他功能测试的硬件逻辑实现区域；所述动态PR区域包括不占用硬件资源的blank模式和执行功耗加压测试的功耗测试模式，所述blank模式用于联合所述静态区域执行非功耗加压测试；
    加压测试配置模块，用于当接收到功耗加压测试请求，设置所述动态PR区域的工作模式为功耗测试模式，同时将所述闪存中烧录的动态PR配置文件加载至所述动态PR区域；
    功耗加压测试执行模块，用于调用所述功耗加压测试模块在所述动态PR区域中执行所述功耗加压测试请求。
  8. 根据权利要求7所述的FPGA加速卡的功耗加压测试装置，其特征在于，所述区域预划分模块包括：
    功耗加压硬件逻辑设置子模块，根据接收到主机端发送的功耗加压测 试模块配置指令，为所述动态PR区域生成多个使用不同数量逻辑资源的功耗加压测试模块，以作为所述动态PR区域工作于所述功耗测试模式下的硬件逻辑；
    固件烧录子模块，用于将工作于所述blank模式下的动态PR区域与所述静态区域联合编译生成FPGA配置文件和动态PR区域blank模式配置文件，以作为具有部分重配置功能的FPGA固件，并将所述FPGA固件烧录固化至所述闪存。
  9. 一种FPGA加速卡的功耗加压测试装置，其特征在于，包括处理器，所述处理器用于执行存储器中存储的计算机程序时实现如权利要求1至6任一项所述FPGA加速卡的功耗加压测试方法的步骤。
  10. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有FPGA加速卡的功耗加压测试程序，所述FPGA加速卡的功耗加压测试程序被处理器执行时实现如权利要求1至6任一项所述FPGA加速卡的功耗加压测试方法的步骤。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN111984480B (zh) * 2020-08-07 2022-07-22 苏州浪潮智能科技有限公司 Fpga加速卡的功耗加压测试方法、装置及存储介质
CN114636921A (zh) * 2022-03-01 2022-06-17 厦门智多晶科技有限公司 一种基于jtag的fpga ft通用测试方法及装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105807263A (zh) * 2016-03-28 2016-07-27 北京航空航天大学 一种fpga部分重构在雷达信号处理中的结构及其实现方法
CN104598310B (zh) * 2015-01-23 2017-08-08 武汉理工大学 基于fpga部分动态可重构技术模块划分的低功耗调度方法
US10324436B2 (en) * 2015-08-10 2019-06-18 Keysight Technologies Singapore (Sales) Pte. Ltd. System and method for programmable control instruments, test and measurement hardware configuration
US10608640B1 (en) * 2019-05-10 2020-03-31 Achronix Semiconductor Corporation On-chip network in programmable integrated circuit
CN111176919A (zh) * 2019-12-29 2020-05-19 苏州浪潮智能科技有限公司 一种fpga的测试方法、设备以及存储介质
CN111258830A (zh) * 2020-01-18 2020-06-09 苏州浪潮智能科技有限公司 一种服务器功耗对比测试系统及方法
CN111984480A (zh) * 2020-08-07 2020-11-24 苏州浪潮智能科技有限公司 Fpga加速卡的功耗加压测试方法、装置及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4491002B2 (ja) * 2007-08-31 2010-06-30 株式会社東芝 半導体集積回路装置
CN101788931B (zh) * 2010-01-29 2013-03-27 杭州电子科技大学 一种硬件实时容错的动态局部可重构系统
US20140059278A1 (en) * 2011-11-14 2014-02-27 Lsi Corporation Storage device firmware and manufacturing software
US10764129B2 (en) * 2017-04-18 2020-09-01 Amazon Technologies, Inc. Logic repository service supporting adaptable host logic
CN109739581A (zh) * 2019-01-29 2019-05-10 郑州云海信息技术有限公司 一种fpga部分重配置方法、系统、设备及计算机介质

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104598310B (zh) * 2015-01-23 2017-08-08 武汉理工大学 基于fpga部分动态可重构技术模块划分的低功耗调度方法
US10324436B2 (en) * 2015-08-10 2019-06-18 Keysight Technologies Singapore (Sales) Pte. Ltd. System and method for programmable control instruments, test and measurement hardware configuration
CN105807263A (zh) * 2016-03-28 2016-07-27 北京航空航天大学 一种fpga部分重构在雷达信号处理中的结构及其实现方法
US10608640B1 (en) * 2019-05-10 2020-03-31 Achronix Semiconductor Corporation On-chip network in programmable integrated circuit
CN111176919A (zh) * 2019-12-29 2020-05-19 苏州浪潮智能科技有限公司 一种fpga的测试方法、设备以及存储介质
CN111258830A (zh) * 2020-01-18 2020-06-09 苏州浪潮智能科技有限公司 一种服务器功耗对比测试系统及方法
CN111984480A (zh) * 2020-08-07 2020-11-24 苏州浪潮智能科技有限公司 Fpga加速卡的功耗加压测试方法、装置及存储介质

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
周盛雨 (ZHOU, SHENGYU): "《基于FPGA的动态部分重构系统实现》 (A Dynamically Partial Reconfigurable System Based on FPGA)", 《中国优秀博硕士学位论文全文数据库(博士) 信息科技辑》(CHINESE SELECTED DOCTORAL DISSERTATIONS AND MASTER’S THESES FULL-TEXT DATABASES (DOCTORAL), INFORMATION SCIENCE AND TECHNOLOGY), no. 10, 15 October 2008 (2008-10-15), ISSN: 1674-022X *

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