WO2022027170A1 - Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage - Google Patents

Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage Download PDF

Info

Publication number
WO2022027170A1
WO2022027170A1 PCT/CN2020/106548 CN2020106548W WO2022027170A1 WO 2022027170 A1 WO2022027170 A1 WO 2022027170A1 CN 2020106548 W CN2020106548 W CN 2020106548W WO 2022027170 A1 WO2022027170 A1 WO 2022027170A1
Authority
WO
WIPO (PCT)
Prior art keywords
target block
programming
erasing
preset
latency
Prior art date
Application number
PCT/CN2020/106548
Other languages
English (en)
Chinese (zh)
Inventor
李楠
伦志远
周威
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/106548 priority Critical patent/WO2022027170A1/fr
Priority to CN202080100778.3A priority patent/CN115552383A/zh
Publication of WO2022027170A1 publication Critical patent/WO2022027170A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

Definitions

  • the present application relates to the field of storage technologies, and in particular, to a flash data management method, a storage device controller, and a storage device.
  • NAND Flash is a current mainstream non-volatile storage medium, which has been widely used in smartphones, enterprise-level solid-state drives, servers, and cloud storage.
  • the current method for determining bad blocks is based on the failure behavior that has already occurred, and the data processing of the bad block after the failure behavior occurs, the risk of data loss in its storage is high.
  • the present application provides a flash data management method, a storage device controller, and a storage device, so as to reduce the risk of data loss in the flash memory medium and improve the data storage reliability of the flash memory medium.
  • an embodiment of the present application provides a flash data management method, including: acquiring intrinsic parameters of a target block in a flash memory medium during an erasing and writing operation, wherein the intrinsic parameters include an execution time of the erasing and writing operations;
  • the running state of the target block is predicted according to the intrinsic parameters and the preset intrinsic parameter threshold, and the running state includes a normal state and an abnormal state; the subsequent data management of the target block is performed according to the predicted running state.
  • the evaluation of the flash medium by obtaining the intrinsic parameters of the target block in the flash medium during the erasing and writing operations, and then predicting the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the evaluation of the flash medium
  • the health level of each block is used to perform subsequent data management on the block according to the predicted operating state of each block, thereby reducing the risk of data loss and improving the data storage reliability of the flash medium.
  • the subsequent data management of the target block according to the predicted running state may include: stopping the write operation or programming operation on the target block.
  • the write operation or programming operation to the target block is stopped, so as to avoid the failure of newly written data, so as to further reduce the risk of data loss and improve the data of the flash medium. Storage reliability.
  • the above-mentioned subsequent data management of the target block according to the predicted operation state may include: performing data migration on the stored data in the target block.
  • the data stored in the target block is data moved, so as to further reduce the risk of data loss and improve the reliability of data storage.
  • the target block may also be marked as bad if the prediction is an abnormal state.
  • the failure is predicted in advance by the intrinsic parameters of the target block during the erasing and writing operation, and the corresponding advance processing is performed, which reduces the additional operations generated after the failure occurs, further reduces the risk of data loss, and improves the flash memory.
  • the data storage reliability of the medium is not limited.
  • the erasing and writing operations include programming operations
  • the intrinsic parameters include the programming latency of the target block to perform the programming operation; if the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time limit, the predicted running state is abnormal state. .
  • the operating state of the target block is predicted by comparing the programming latency with the preset programming time range. If the predicted operating state is an abnormal state, the target is determined according to the intrinsic parameters and the preset intrinsic parameters. After the running state of the block, the target block can be marked as bad. Therefore, through the intrinsic parameters of the target block during the erasing and writing operations, the failure can be predicted in advance and the corresponding advanced processing is carried out, so as to reduce the additional operations generated after the failure occurs, further reduce the risk of data loss, and improve the data storage reliability of the flash medium. sex.
  • the programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset upper limit value of the word line programming time, the predicted operating state is an abnormal state,
  • the preset upper limit of programming time includes a preset upper limit of word line programming time, and the preset intrinsic parameter threshold includes a preset upper limit of word line programming time of each word line in the target block.
  • the intrinsic parameter further includes the number of times of erasing and writing, and the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of times of erasing and writing.
  • the erasing operation includes the erasing operation
  • the intrinsic parameter includes the erasing latency of the target block to perform the erasing operation; if the erasing latency is greater than the preset upper limit value of the erasing time, the operating state is predicted is an abnormal state.
  • the operating state of the target block is determined by comparing the erasing latency with the preset upper limit value of erasing time. If the predicted operating state is an abnormal state, the After predicting the running state of the target block based on the characteristic parameters, the target block can be marked as a bad block. Therefore, through the intrinsic parameters of the target block during the erasing and writing operations, the failure can be predicted in advance and the corresponding advanced processing is carried out, so as to reduce the additional operations generated after the failure occurs, further reduce the risk of data loss, and improve the data storage reliability of the flash medium. sex.
  • the erasing latency is greater than the preset upper limit value of the erasing time, the number of bit errors in the erasing operation is read, and if the number of bit errors is greater than the preset number of bit errors, the predicted operating state is an abnormal state .
  • an embodiment of the present application further provides a storage device controller, including: a processor and a buffer; wherein, the processor obtains, from the buffer, the intrinsic properties of a target block in a flash medium during an erasing and writing operation. parameters, the intrinsic parameters include the execution time of the erasing and writing operations; the processor predicts the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, and stores the running state in the buffer, and the running state includes the normal state and the abnormal state ; Data management of the target block by the processor according to the predicted operating state.
  • a storage device controller including: a processor and a buffer; wherein, the processor obtains, from the buffer, the intrinsic properties of a target block in a flash medium during an erasing and writing operation. parameters, the intrinsic parameters include the execution time of the erasing and writing operations; the processor predicts the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, and stores the running state in the buffer, and the running state includes the normal state and
  • the processor stops writing or programming the target block.
  • the processor is used to perform data movement on the stored data in the target block.
  • the processor marks the target block as a bad block in the buffer.
  • the erasing and writing operations include programming operations
  • the intrinsic parameters include the programming latency of the target block to perform the programming operation; if the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time limit, then the running state is determined to be an abnormal state.
  • the programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset upper limit value of the word line programming time, the predicted operating state is an abnormal state,
  • the preset upper limit of programming time includes a preset upper limit of word line programming time, and the preset intrinsic parameter threshold includes a preset upper limit of word line programming time of each word line in the target block.
  • the intrinsic parameter further includes the number of times of erasing and writing, and the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of times of erasing and writing.
  • the erasing operation includes the erasing operation
  • the intrinsic parameter includes the erasing latency of the target block to perform the erasing operation; if the erasing latency is greater than the preset upper limit value of the erasing time, the operating state is predicted is an abnormal state.
  • the erasing latency is greater than the preset upper limit value of the erasing time, the number of bit errors in the erasing operation is read, and if the number of bit errors is greater than the preset number of bit errors, the predicted operating state is an abnormal state .
  • an embodiment of the present application further provides a storage device, including: a flash memory medium and any one of the storage device controllers provided in the third aspect; wherein, the storage device controller is used to control each block in the flash memory medium Conduct data management.
  • the present application provides a flash data management method, a storage device controller, and a storage device.
  • a flash data management method By acquiring intrinsic parameters of a target block in a flash memory medium during an erasing and writing operation, and then predicting based on intrinsic parameters and preset intrinsic parameter thresholds
  • the operating status of the target block is used to evaluate the health of each block in the flash medium, and the subsequent data management of the block can be performed according to the predicted operating status of each block, thereby reducing the risk of data loss and improving the data storage reliability of the flash medium. sex.
  • FIG. 1 is a schematic diagram of a NAND Flash organizational structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a storage system architecture provided by an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a flash data management method provided in Embodiment 1 of the present application.
  • FIG. 4 is a schematic flowchart of a flash data management method provided in Embodiment 2 of the present application.
  • FIG. 5 is a schematic diagram of a programming latency test result according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a programming latency test result shown in the present application according to another embodiment
  • FIG. 7 is a schematic diagram of the voltage distribution of the S1 region shown in FIG. 6;
  • FIG. 8 is a schematic flowchart of a flash data management method provided in Embodiment 3 of the present application.
  • FIG. 9 is a schematic diagram of the test result of the number of bit errors shown in the present application according to an embodiment
  • FIG. 10 is a schematic flowchart of a flash data management method provided in Embodiment 4 of the present application.
  • FIG. 11 is a schematic structural diagram of a storage device controller according to Embodiment 5 of the present application.
  • FIG. 12 is a schematic structural diagram of a storage device provided in Embodiment 5 of the present application.
  • NAND Flash is a current mainstream non-volatile storage medium, which has been widely used in smartphones, enterprise-level solid-state drives, servers, and cloud storage. It can save data for a long time after power failure, and has the advantages of fast data transmission speed, low production cost, and large storage capacity.
  • the current mainstream NAND Flash manufacturers use a 3D multi-layer stacking structure; as the number of stacked layers becomes larger and larger, more and more memory cells (cells) are squeezed into a small space, and the mutual interference between cells/cells The leakage current increases significantly, and the reliability risk of the storage medium increases.
  • the reduction of the distance between the memory cells and the reduction of the thickness of the oxide layer make the inherent errors in the flash memory more and more serious.
  • the traditional error correction code method can no longer meet the reliability requirements of the flash memory. important subject.
  • the medium may have key read and write errors due to process defects, resulting in data loss, or the system needs to spend additional processes to recover data.
  • PE erasing and writing
  • FIG. 1 is a schematic diagram of a NAND Flash organizational structure provided by an embodiment of the present application.
  • the NAND chip 100 divides the storage unit into several flash memory slices (planes), for example: a first plane 110 and a second plane 120 .
  • planes can be further divided into different blocks (blocks), for example, the first plane 110 includes the first block 110B.
  • the block needs to be marked as a bad block, that is, a bad block, where the smallest unit of isolation failure unit is a block.
  • the block in the organizational structure of a NAND chip, the block is divided into different strings (strings), and the following strings are further divided into different word lines (Word Lines, WL for short).
  • the minimum unit of the erase operation is a block
  • the minimum unit of the programming operation is a WL.
  • the industry usually only marks the target block as a bad block when the target block in the NAND Flash is erased or written, for example, when a write failure or an erase failure occurs. Then, additional means are used to recover data lost due to write failures.
  • FIG. 2 is a schematic diagram of an architecture of a storage system provided by an embodiment of the present application.
  • the storage system provided in this embodiment mainly includes three core modules: a controller (Controller), a buffer (Cache), and a storage medium (NAND Flash), wherein the controller is the entire storage
  • the control brain of the system is responsible for the processing of read and write commands of the SSD, data distribution management, and NAND Flash management.
  • the NAND flash part may consist of 1 die or multiple dies, and is the physical carrier for the final storage of data.
  • the buffer part is used to buffer the data sent from the controller or read from the buffer.
  • the redundant array of independent hard disks Redundant Array of Independent Disks, referred to as RAID
  • RAID redundant array of independent hard disks
  • one of the dies may be used to XOR the data in the remaining dies and then write them into the RAID dies. After the media failure occurs, the lost data can be recovered by reading data from other locations on the same strip; In addition, there is also a way to write the data cache, which can be to write the data to the cache first, and release the cache after the writing to the NAND is successful.
  • the embodiment of the present application aims to predict/evaluate the state of the target block by using some intrinsic parameters during NAND erasing and writing, so as to predict the failure in advance, so as to perform corresponding advanced processing, so as to perform corresponding data on each block in the flash memory medium. management to reduce the risk of data loss.
  • the technical approach provided by the embodiments of the present application utilizes the intrinsic characteristics of the NAND Flash medium, and mainly utilizes the programming latency (T program , referred to as T PROG ), the erasing latency (T erase , referred to as T ERS ) and the number of blank page errors after erasing Detect (erased page FBC check) to judge the health status of NAND media, and predict/handle upcoming failures in advance through subsequent operations.
  • T program referred to as T PROG
  • T erase erasing latency
  • T ERS erasing latency
  • the number of blank page errors after erasing Detect erasesed page FBC check
  • FIG. 3 is a schematic flowchart of a flash data management method provided in Embodiment 1 of the present application. As shown in FIG. 3 , the flash data management method provided by this embodiment includes:
  • Step 101 Acquire intrinsic parameters of the target block in the flash memory medium during the erasing and writing operations.
  • NAND Flash media mainly includes three basic operations: read operation (Read), programming operation (Program), and erase operation (Erase).
  • Read read operation
  • Program programming operation
  • Erase erase operation
  • the NAND erase operation and programming operation time will change with the wear degree of the medium.
  • the current erase operation or programming operation may not necessarily show state failure. But it can show a big change in erasing operation or programming operation time. Therefore, the prediction of the running state of the target block can be performed by obtaining intrinsic parameters of the target block in the flash medium during the erasing and writing operations, wherein the intrinsic parameters include the operation time required to complete the erasing and writing operations.
  • Step 102 Predict the running state of the target block according to the intrinsic parameters and a preset intrinsic parameter threshold.
  • the operating state of the target block can be predicted according to the intrinsic parameters of the NAND medium, and based on the intrinsic parameters and the preset intrinsic parameter threshold, wherein the operating state includes normal state and abnormal state. Therefore, the health of the NAND medium is evaluated by monitoring the programming latency and erasing latency of NAND, so as to predict the occurrence of target block failure in advance.
  • the embodiment of the present application may be a software management solution, in which a whole set of application policies is implemented through a storage system controller.
  • the programming latency and the erasing latency can be detected by the controller to detect the execution time of the programming and erasing operations, and the number of blank page errors after erasing can be detected by the controller issuing a read operation to read the blank page data.
  • the controller can compare the operation time preset offline or the threshold for the number of blank page errors. If a failure is predicted to occur, the controller defines this block as a bad block, ignores it in subsequent operations, and no longer operates.
  • the above three sub-schemes may be combined arbitrarily for prediction, or only a single scheme may be used for prediction.
  • Step 103 Perform subsequent data management on the target block according to the predicted running state.
  • the controller may perform subsequent data management on the target block according to the predicted running state of the target block.
  • the predicted operating state of the target block is abnormal, it means that the target block has a high risk of failure. Therefore, in order to reduce the risk of data loss, the write operation or programming operation on the target block can be stopped to avoid new writing.
  • the entered data is invalid.
  • the predicted running state of the target block is abnormal, it means that the failure risk of the target block is low, and the reliability of storing data in the target block is high. Therefore, you can continue to write to the target block or programming operation.
  • data movement may also be performed on the stored data in the target block.
  • the controller can obtain the relevant identification code of each block to predict the running state of the block, and the block predicted to be in an abnormal state will be marked as a bad block.
  • the identification bit of the block is configured as a specific field for bad block identification.
  • the evaluation of the flash medium by acquiring the intrinsic parameters of the target block in the flash medium during the erasing and writing operation, and then predicting the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the evaluation of the flash medium
  • the health level of each block is used to perform subsequent data management on the block according to the predicted operating state of each block, thereby reducing the risk of data loss and improving the data storage reliability of the flash medium.
  • the target block may be marked as a bad block. Therefore, through the intrinsic parameters of the target block during the erasing and writing operations, the failure can be predicted in advance and the corresponding advanced processing is carried out, so as to reduce the additional operations generated after the failure occurs, further reduce the risk of data loss, and improve the data storage reliability of the flash medium. sex.
  • the data stored in the target block can also be moved. Therefore, before the target block fails, the data stored in the target block is moved to further reduce the risk of data loss and improve the reliability of data storage.
  • FIG. 4 is a schematic flowchart of a flash data management method provided in Embodiment 2 of the present application. As shown in FIG. 4 , the flash data management method provided by this embodiment includes:
  • Step 201 Acquire intrinsic parameters of the target block in the flash medium during the erasing and writing operations.
  • the programming operation time will change with the wear degree of the medium, especially when some weak leakage occurs, the current programming operation may not necessarily show a state failure, but it can show a large change in the programming operation time.
  • the programming latency can be obtained by the controller detecting the execution time of the programming operation.
  • the prediction of the running state of the target block can be performed by obtaining the programming latency of the target block in the flash memory medium when the programming operation is performed.
  • Step 202 Determine whether the programming latency is within a preset programming time range. If the judgment result is yes, go to step 204; if the judgement result is no, go to step 203.
  • the programming latency can also be compared with a preset programming time range, so as to predict the running state of the target block.
  • the preset programming time range may be determined according to a normal programming time range.
  • Step 203 predicting that the running state is an abnormal state.
  • the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time lower limit, it can be predicted that the operating state is an abnormal state.
  • the word line programming time of each word line in the target block can also be obtained.
  • the above programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset word line programming time upper limit, the predicted operating state is an abnormal state, and the preset programming time upper limit Values include preset word line programming time upper limit values.
  • the leakage between the word line and the word line (WL-WL), or between the word line and the channel (WL-channel) may be only a small leakage in the early stage, and the programming failure will not occur immediately, but due to the existence of Leakage will cause the programming voltage on the WL to drop, resulting in a decrease in programming efficiency and an abnormal increase in programming latency, but it does not reach the level of programming failure.
  • FIG. 5 is a schematic diagram of a programming latency test result according to an embodiment of the present application.
  • the horizontal axis is the number of erase/write cycles of the target block
  • the vertical axis is the programming latency
  • the four groups are four WLs on the same layer that share the WL metal layer but different channels.
  • the programming sequence is from From top to bottom, it is a cycle. It can be seen that with the increase of the number of erase/write cycles, the programming latency decreases slowly, but when the number of erase/write cycles is around 7500, the programming time of the first WL and the second WL suddenly increases abnormally, but there is no programming failure. A programming failure occurs when the third WL is reached, that is, the fourth WL cannot continue programming.
  • L10 is the programming latency test curve corresponding to the first WL
  • L20 is the programming latency test curve corresponding to the second WL
  • L30 is the programming latency test curve corresponding to the third WL
  • L40 is the fourth WL The corresponding programming latency test curve.
  • the running state can also be predicted to be an abnormal state.
  • the above-mentioned intrinsic parameters may also include the number of times of erasing and writing, and the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of erasing and writing.
  • the defects in the oxide layer will gradually increase after the tunnel oxide layer is subjected to repeated voltage pressure, making it easier for electrons to enter the charge trap layer through the defects.
  • the response in the programming latency is that the programming speed increases and the programming latency decreases. Speeding up the programming speed to a certain threshold will lead to an increase in the number of electrons acquired by each voltage pulse, resulting in a decrease in programming accuracy, which is reflected in particle performance as over-programming, that is, the programmed threshold voltage is higher than the preset value, and the final response is read Data errors are on the rise, even leading to UNC.
  • FIG. 6 is a schematic diagram of a programming latency test result according to another embodiment of the present application. As shown in FIG. 6 , the vertical axis is the programming latency, and the horizontal axis is the maximum number of errors per page. It can be seen from the figure that the page with an increased Fail Bit Count (FBC for short), that is, the S1 area shown in the figure, has a programming latency in a smaller range.
  • FBC Fail Bit Count
  • FIG. 7 is a schematic diagram of the voltage distribution in the S1 region shown in Figure 6.
  • an obvious over-programming problem can be found, and the increase in the number of errors caused by such over-programming is due to the rise of the voltage valley, even if the bias voltage reads It cannot be recovered.
  • the horizontal axis in FIG. 7 represents the value of the threshold voltage
  • the vertical axis represents the number of memory cells under the threshold voltage.
  • all memory cells under a word line of a three-level cell (TLC) are distributed in 8 states, except erase.
  • L1 represents the threshold voltage distribution of the page with a large number of errors in the total S1 area of Figure 6, and L2/L3 are The threshold voltage distribution of the normal error number page.
  • the decreasing trend of programming latency can be used to evaluate or predict the health state of the storage medium, and samples can be measured offline, such as the variation of programming latency with the number of PEs, and the programming latency threshold that causes over-programming problems. for online monitoring.
  • the programming latency drops to a certain threshold, the corresponding target block is processed in advance.
  • Step 204 predicting that the operating state is a normal state.
  • the operating state of the target block is predicted by comparing the programming latency with the preset programming time range. If the predicted operating state is an abnormal state, the target block is predicted according to the intrinsic parameters and the preset intrinsic parameters. After the running state of the block, the target block can be marked as bad. Therefore, the failure is predicted in advance by the intrinsic parameters of the target block during the erasing and writing operation, and the corresponding advanced processing is carried out, which reduces the extra operation after the failure occurs, further reduces the risk of data loss, and improves the data storage reliability of the flash medium. sex.
  • Step 205 Perform subsequent data management on the target block according to the predicted running state.
  • the controller may perform subsequent data management on the target block according to the predicted operating state of the target block.
  • the target block may also be marked as a bad block.
  • the target block can be marked as a bad block, the write operation or programming operation can be stopped on the target block, or the stored data in the target block can be stopped.
  • the data migration can also be any combination of the above three methods.
  • FIG. 8 is a schematic flowchart of a flash data management method provided in Embodiment 3 of the present application. As shown in FIG. 8 , the flash data management method provided by this embodiment includes:
  • Step 301 Acquire intrinsic parameters of the target block in the flash memory medium during the erasing and writing operations.
  • the current erasing operation may not necessarily show a state failure, but it can show a large amount of time in the erasing and writing operation time. Variations, where the erase-write latency can be obtained by the controller detecting the execution time of the programming operation.
  • the prediction of the running state of the target block can be performed by obtaining the erasing latency of the target block in the flash medium when the erasing operation is performed.
  • Step 302 judging whether the erasing latency is greater than the preset upper limit of erasing time. If the judgment result is yes, step 303 is executed; if the judgment result is no, step 304 is executed.
  • Step 303 predicting that the running state is an abnormal state.
  • the predicted operating state is an abnormal state.
  • the predicted operating state is an abnormal state.
  • continue to read the number of bit errors in the erasing operation If the number of bit errors is greater than the preset number of bit errors, the predicted operating state is abnormal. .
  • FIG. 9 is a schematic diagram illustrating a test result of the number of bit errors according to an embodiment of the present application.
  • the data shows that the erase operation before the programming failure did not feedback the erase failure, but the Erased FBC (the dot is the FBC value after erasing, the vertical axis is the FBC, and the horizontal axis is the number of erase cycles) read Fetch has shown abnormality, and programming failure occurs in the next programming cycle (the cross point is the FBC value after programming, where the number of errors read is very high because of programming failure).
  • Step 304 predicting that the operating state is a normal state.
  • the operating state of the target block is predicted by comparing the erasing latency with the preset upper limit value of erasing time. If the predicted operating state is an abnormal state, the After predicting the running state of the target block based on the characteristic parameters, the target block can be marked as a bad block. Therefore, the failure is predicted in advance by the intrinsic parameters of the target block during the erasing and writing operation, and the corresponding advanced processing is carried out, which reduces the extra operation after the failure occurs, further reduces the risk of data loss, and improves the data storage reliability of the flash medium. sex.
  • Step 305 Perform subsequent data management on the target block according to the predicted running state.
  • step 305 For the specific implementation of step 305, reference may be made to the specific description of step 205 in the embodiment shown in FIG. 4 , which will not be repeated here.
  • FIG. 10 is a schematic flowchart of a flash data management method of a flash memory provided by Embodiment 4 of the present application. As shown in FIG. 8 , the flash data management method provided by this embodiment includes:
  • Step 401 select the word line of the target block to start writing data.
  • Step 402 Record the programming latency after programming is completed.
  • the controller when programming the target block, the controller records the programming time and the number of erase/write cycles of each WL, and compares it with the programming latency measured offline and the preset programming time range of the number of erase/write cycles after wear. Compared.
  • Step 403 Determine whether the programming latency is within a preset programming time range. If the judgment result is yes, step 405 is executed, and if the judgment result is no, step 404 is executed.
  • the programming operation time will change with the wear degree of the medium, especially when some weak leakage occurs, the current programming operation may not necessarily show a state failure, but it can show a large change in the programming operation time.
  • the programming latency can be obtained by the controller detecting the execution time of the programming operation.
  • the programming latency can also be compared with a preset programming time range, so as to predict the running state of the target block.
  • the preset programming time range may be determined according to a normal programming time range.
  • Step 404 Determine whether the programming latency is greater than the preset programming time upper limit. If the judgment result is yes, step 410 is executed, and if the judgment result is no, step 4041 is executed.
  • the word line programming time of each word line in the target block can also be obtained.
  • the above programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset word line programming time upper limit, the predicted operating state is an abnormal state, and the preset programming time upper limit Values include preset word line programming time upper limit values.
  • Step 4041 read verification.
  • Step 4042 Determine whether the read verification is passed. If the judgment result is no, step 410 is executed, and if the judgment result is yes, step 405 is executed.
  • the running state can also be predicted to be an abnormal state.
  • the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of times of erasing and writing. When the programming latency reaches a certain threshold, the corresponding target block is processed in advance.
  • Step 405 Continue to program the next word line.
  • Step 406 perform an erasing operation on the target block, and record the erasing latency.
  • the current erasing operation may not necessarily show a state failure, but it can show a large amount of time in the erasing and writing operation time. Variations, where the erase-write latency can be obtained by the controller detecting the execution time of the programming operation.
  • the prediction of the running state of the target block can be performed by obtaining the erasing latency of the target block in the flash medium when the erasing operation is performed.
  • Step 407 Determine whether the erasing latency is greater than the preset upper limit of erasing time. If the judgment result is no, go to step 409, and if the judgement result is yes, go to step 4081.
  • Step 4081 Read the number of bit errors in the erase operation.
  • Step 4082 Determine that the number of bit errors is greater than the preset number of bit errors. If the judgment result is no, step 409 is executed, and if the judgment result is yes, step 410 is executed.
  • the predicted operating state is an abnormal state.
  • the predicted operating state is an abnormal state.
  • continue to read the number of bit errors in the erasing operation If the number of bit errors is greater than the preset number of bit errors, the predicted operating state is abnormal. .
  • the controller records the programming time and the number of erasing and writing cycles of each WL, and compares it with the relationship between the programming time and the number of wear cycles measured offline. If the programming latency is within the preset programming time safety range corresponding to the current cycle value, the WL is considered to be in a healthy state, and the next step can be continued. When it is detected that the current programming time is greater than the preset programming time safety range of the cycle value When the target block is directly identified as a bad block, the bad block is marked and the necessary data movement is performed.
  • the target block is in a risk state, and the programmed WL is immediately read and verified to determine whether FBC occurs. In the case of rising, if the FBC is found to exceed a certain threshold, it will be marked as a bad block.
  • the controller records the erasing latency, and compares the erasing latency with the relationship between the erasing time and the number of wear cycles measured offline. When the erasing latency is found When the erasure time safety interval of the current cycle value is exceeded, the controller sends a read command to read the number of errors in the blank page after erasing the specified page. If the number of bit errors is found to be greater than the preset number of bit errors, it will The target block is marked as bad.
  • Step 409 update the erasing cycle times.
  • Step 410 Mark the target block as a bad block.
  • FIG. 11 is a schematic structural diagram of a storage device controller according to Embodiment 5 of the present application.
  • the storage device controller 500 provided in this embodiment includes: a processor 501 and a buffer 502 ; wherein, the processor 501 obtains a target block in the flash medium from the buffer 502 when performing an erasing and writing operation and the intrinsic parameters include the execution time of the erase and write operations; then, the processor 501 predicts the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, and stores the running state in the buffer 502, The running state includes a normal state and an abnormal state; then, the processor 501 performs data management on the target block according to the predicted running state.
  • the processor 501 stops writing or programming the target block.
  • the processor 501 is configured to perform data movement on the stored data in the target block.
  • the processor 501 marks the target block as a bad block in the buffer 502 .
  • the erasing and writing operations include programming operations
  • the intrinsic parameters include the programming latency for the target block to perform the programming operation; if the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time limit, the predicted running state is abnormal state.
  • the programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset upper limit value of the word line programming time, the predicted operating state is an abnormal state,
  • the preset upper limit of programming time includes a preset upper limit of word line programming time, and the preset intrinsic parameter threshold includes a preset upper limit of word line programming time of each word line in the target block.
  • the intrinsic parameter further includes the number of times of erasing and writing, and the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of times of erasing and writing.
  • the erasing operation includes the erasing operation
  • the intrinsic parameter includes the erasing latency of the target block to perform the erasing operation; if the erasing latency is greater than the preset upper limit value of the erasing time, the operating state is predicted is an abnormal state.
  • the erasing latency is greater than the preset upper limit value of the erasing time, the number of bit errors in the erasing operation is read, and if the number of bit errors is greater than the preset number of bit errors, the predicted operating state is an abnormal state .
  • FIG. 12 is a schematic structural diagram of a storage device provided in Embodiment 5 of the present application.
  • the storage device provided in this embodiment includes a flash memory medium and the storage device controller shown in FIG. 11 .
  • the flash media part may be composed of one die or multiple die, and is the physical carrier for the final storage of data.
  • the storage device controller is used for data management of each block in the flash memory medium.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

Certains modes de réalisation de la présente invention concernent un procédé de gestion de données de mémoire Flash, un contrôleur de dispositif de stockage, et un dispositif de stockage. Le procédé comporte les étapes consistant à: acquérir des paramètres intrinsèques, lorsqu'un bloc cible dans un support à mémoire Flash est soumis à des opérations d'effacement et d'écriture, du bloc cible, les paramètres intrinsèques comportant un temps d'exécution des opérations d'effacement et d'écriture; prédire des états de fonctionnement du bloc cible selon les paramètres intrinsèques et un seuil prédéfini de paramètres intrinsèques, les états de fonctionnement comportant un état normal et un état anormal; et en fonction des états de fonctionnement prédits, effectuer une gestion de données subséquente sur le bloc cible. Dans le procédé selon les présents modes de réalisation, en acquérant les paramètres intrinsèques, lorsque le bloc cible dans le support à mémoire Flash est soumis aux opérations d'effacement et de programmation, du bloc cible, puis en prédisant les états de fonctionnement du bloc cible selon les paramètres intrinsèques et le seuil prédéfini de paramètres intrinsèques, le niveau d'intégrité de chaque bloc dans le support à mémoire Flash est évalué, de façon à effectuer une gestion de données subséquente sur le bloc en fonction d'un état de fonctionnement déterminé de chaque block, réduisant ainsi le risque de perte de données, et améliorant la fiabilité de stockage de données du support à mémoire Flash.
PCT/CN2020/106548 2020-08-03 2020-08-03 Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage WO2022027170A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2020/106548 WO2022027170A1 (fr) 2020-08-03 2020-08-03 Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage
CN202080100778.3A CN115552383A (zh) 2020-08-03 2020-08-03 闪存数据管理方法、存储设备控制器及存储设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/106548 WO2022027170A1 (fr) 2020-08-03 2020-08-03 Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage

Publications (1)

Publication Number Publication Date
WO2022027170A1 true WO2022027170A1 (fr) 2022-02-10

Family

ID=80119815

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/106548 WO2022027170A1 (fr) 2020-08-03 2020-08-03 Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage

Country Status (2)

Country Link
CN (1) CN115552383A (fr)
WO (1) WO2022027170A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116302633B (zh) * 2023-01-18 2024-04-09 北京得瑞领新科技有限公司 闪存存储器的逻辑单元失效管理方法、装置、介质及设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1517947A (zh) * 2003-01-28 2004-08-04 株式会社瑞萨科技 非易失性存储器
US20110191526A1 (en) * 2007-12-21 2011-08-04 Brent Haukness Flash Memory Timing Pre-Characterization
US8254172B1 (en) * 2009-09-30 2012-08-28 Western Digital Technologies, Inc. Wear leveling non-volatile semiconductor memory based on erase times and program times
CN103678150A (zh) * 2013-12-23 2014-03-26 华为技术有限公司 固态硬盘使用方法及装置
CN108052287A (zh) * 2017-12-12 2018-05-18 深圳市创维软件有限公司 一种非易失性存储器的分区数据管理方法、机顶盒及介质
US20180286485A1 (en) * 2017-03-29 2018-10-04 Toshiba Memory Corporation Memory system controlling data erase for nonvolatile memory and control method for erasing data

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1517947A (zh) * 2003-01-28 2004-08-04 株式会社瑞萨科技 非易失性存储器
US20110191526A1 (en) * 2007-12-21 2011-08-04 Brent Haukness Flash Memory Timing Pre-Characterization
US8254172B1 (en) * 2009-09-30 2012-08-28 Western Digital Technologies, Inc. Wear leveling non-volatile semiconductor memory based on erase times and program times
CN103678150A (zh) * 2013-12-23 2014-03-26 华为技术有限公司 固态硬盘使用方法及装置
US20180286485A1 (en) * 2017-03-29 2018-10-04 Toshiba Memory Corporation Memory system controlling data erase for nonvolatile memory and control method for erasing data
CN108052287A (zh) * 2017-12-12 2018-05-18 深圳市创维软件有限公司 一种非易失性存储器的分区数据管理方法、机顶盒及介质

Also Published As

Publication number Publication date
CN115552383A (zh) 2022-12-30

Similar Documents

Publication Publication Date Title
US9304856B2 (en) Implementing ECC control for enhanced endurance and data retention of flash memories
CN108052414B (zh) 一种提升ssd工作温度范围的方法及系统
KR102487553B1 (ko) 리페어 가능한 휘발성 메모리를 포함하는 스토리지 장치 및 상기 스토리지 장치의 동작 방법
CN106776109B (zh) 固态硬盘读错误检测装置及读不可纠错误原因的检测方法
US9208817B1 (en) System and method for determination and reallocation of pending sectors caused by media fatigue
US9424927B2 (en) Memory system, control system and method of predicting lifetime
US8887027B2 (en) Solid-state mass storage device and method for failure anticipation
US9349476B2 (en) Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on flash program verify
US8910002B2 (en) NAND flash-based storage device with built-in test-ahead for failure anticipation
US8464106B2 (en) Computer system with backup function and method therefor
DE102014115885B4 (de) Funktionstüchtigkeitszustand von nicht-flüchtigem Speicher
US9330783B1 (en) Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block
TWI566252B (zh) 非揮發性記憶體裝置進行耗損管理之方法
Shim et al. Exploiting process similarity of 3D flash memory for high performance SSDs
CN109918022B (zh) 一种ssd开卡坏块表继承方法
US9165688B2 (en) Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory
US11170866B2 (en) Managing block retirement for temporary operational conditions
US20210264980A1 (en) Identifying failure type in NVM programmed in SLC mode using a single programming pulse with no verification
JP2012517068A (ja) メモリ装置、メモリ管理装置、およびメモリ管理方法
WO2022027170A1 (fr) Procédé de gestion de données de mémoire flash, contrôleur de dispositif de stockage, et dispositif de stockage
US20230161482A1 (en) Memory device defect scanning
US8988799B1 (en) Magnetic disk device and control method of magnetic disk
US20070277059A1 (en) Storage device, control device, and error reporting method
US20120159280A1 (en) Method for controlling nonvolatile memory apparatus
CN116153381A (zh) 一种闪存颗粒寿命预测方法、装置、设备及可读存储介质

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20947863

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20947863

Country of ref document: EP

Kind code of ref document: A1