WO2022027170A1

WO2022027170A1 - Flash memory data management method, storage device controller, and storage device

Info

Publication number: WO2022027170A1
Application number: PCT/CN2020/106548
Authority: WO
Inventors: 李楠; 伦志远; 周威
Original assignee: 华为技术有限公司
Priority date: 2020-08-03
Filing date: 2020-08-03
Publication date: 2022-02-10
Also published as: CN115552383A

Abstract

Provided by embodiments of the present application are a flash memory data management method, a storage device controller, and a storage device. The method comprises: acquiring intrinsic parameters, when a target block in a flash memory medium is subjected to erase and write operations, of the target block, wherein the intrinsic parameters comprise an execution time of the erase and write operations; predicting running statuses of the target block according to the intrinsic parameters and a preset intrinsic parameter threshold, wherein the running statuses comprise a normal status and an abnormal status; and according to the predicted running statuses, performing subsequent data management on the target block. In the method provided in the present embodiments, by means of acquiring the intrinsic parameters, when the target block in the flash memory medium is subjected to the erase and program operations, of the target block, and then predicting the running statuses of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the health level of each block in the flash memory medium is evaluated, so as to perform subsequent data management on the block according to a determined running status of each block, thereby reducing the risk of data loss, and improving the data storage reliability of the flash memory medium.

Description

Flash data management method, storage device controller and storage device

technical field

The present application relates to the field of storage technologies, and in particular, to a flash data management method, a storage device controller, and a storage device.

Background technique

NAND Flash (NAND Flash) is a current mainstream non-volatile storage medium, which has been widely used in smartphones, enterprise-level solid-state drives, servers, and cloud storage.

When erasing or writing data to a target block in NAND Flash, the industry usually only occurs when the target block fails, for example, in the event of a write failure (Program Status Fail, PSF for short) or Erase Status Fail (ESF for short) When this occurs, the target block is marked as bad for data management of the target block.

It can be seen that the current method for determining bad blocks is based on the failure behavior that has already occurred, and the data processing of the bad block after the failure behavior occurs, the risk of data loss in its storage is high.

SUMMARY OF THE INVENTION

The present application provides a flash data management method, a storage device controller, and a storage device, so as to reduce the risk of data loss in the flash memory medium and improve the data storage reliability of the flash memory medium.

In a first aspect, an embodiment of the present application provides a flash data management method, including: acquiring intrinsic parameters of a target block in a flash memory medium during an erasing and writing operation, wherein the intrinsic parameters include an execution time of the erasing and writing operations; The running state of the target block is predicted according to the intrinsic parameters and the preset intrinsic parameter threshold, and the running state includes a normal state and an abnormal state; the subsequent data management of the target block is performed according to the predicted running state.

In this implementation manner, by obtaining the intrinsic parameters of the target block in the flash medium during the erasing and writing operations, and then predicting the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the evaluation of the flash medium The health level of each block is used to perform subsequent data management on the block according to the predicted operating state of each block, thereby reducing the risk of data loss and improving the data storage reliability of the flash medium.

In a possible design, if the prediction is an abnormal state, the subsequent data management of the target block according to the predicted running state may include: stopping the write operation or programming operation on the target block.

In this implementation manner, when the target block is determined to be in an abnormal state, the write operation or programming operation to the target block is stopped, so as to avoid the failure of newly written data, so as to further reduce the risk of data loss and improve the data of the flash medium. Storage reliability.

In a possible design, if the prediction is an abnormal state, the above-mentioned subsequent data management of the target block according to the predicted operation state may include: performing data migration on the stored data in the target block.

In this implementation manner, before the target block fails, the data stored in the target block is data moved, so as to further reduce the risk of data loss and improve the reliability of data storage.

In one possible design, the target block may also be marked as bad if the prediction is an abnormal state.

In this implementation manner, the failure is predicted in advance by the intrinsic parameters of the target block during the erasing and writing operation, and the corresponding advance processing is performed, which reduces the additional operations generated after the failure occurs, further reduces the risk of data loss, and improves the flash memory. The data storage reliability of the medium.

In a possible design, the erasing and writing operations include programming operations, and the intrinsic parameters include the programming latency of the target block to perform the programming operation; if the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time limit, the predicted running state is abnormal state. .

In this implementation, the operating state of the target block is predicted by comparing the programming latency with the preset programming time range. If the predicted operating state is an abnormal state, the target is determined according to the intrinsic parameters and the preset intrinsic parameters. After the running state of the block, the target block can be marked as bad. Therefore, through the intrinsic parameters of the target block during the erasing and writing operations, the failure can be predicted in advance and the corresponding advanced processing is carried out, so as to reduce the additional operations generated after the failure occurs, further reduce the risk of data loss, and improve the data storage reliability of the flash medium. sex.

In a possible design, the programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset upper limit value of the word line programming time, the predicted operating state is an abnormal state, The preset upper limit of programming time includes a preset upper limit of word line programming time, and the preset intrinsic parameter threshold includes a preset upper limit of word line programming time of each word line in the target block.

In a possible design, the intrinsic parameter further includes the number of times of erasing and writing, and the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of times of erasing and writing.

In a possible design, the erasing operation includes the erasing operation, and the intrinsic parameter includes the erasing latency of the target block to perform the erasing operation; if the erasing latency is greater than the preset upper limit value of the erasing time, the operating state is predicted is an abnormal state.

In this implementation manner, the operating state of the target block is determined by comparing the erasing latency with the preset upper limit value of erasing time. If the predicted operating state is an abnormal state, the After predicting the running state of the target block based on the characteristic parameters, the target block can be marked as a bad block. Therefore, through the intrinsic parameters of the target block during the erasing and writing operations, the failure can be predicted in advance and the corresponding advanced processing is carried out, so as to reduce the additional operations generated after the failure occurs, further reduce the risk of data loss, and improve the data storage reliability of the flash medium. sex.

In a possible design, if the erasing latency is greater than the preset upper limit value of the erasing time, the number of bit errors in the erasing operation is read, and if the number of bit errors is greater than the preset number of bit errors, the predicted operating state is an abnormal state .

In a second aspect, an embodiment of the present application further provides a storage device controller, including: a processor and a buffer; wherein, the processor obtains, from the buffer, the intrinsic properties of a target block in a flash medium during an erasing and writing operation. parameters, the intrinsic parameters include the execution time of the erasing and writing operations; the processor predicts the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, and stores the running state in the buffer, and the running state includes the normal state and the abnormal state ; Data management of the target block by the processor according to the predicted operating state.

In a possible design, if the running state of the target block obtained by the processor from the buffer is an abnormal state, the processor stops writing or programming the target block.

In a possible design, if the running state of the target block obtained by the processor from the buffer is an abnormal state, the processor is used to perform data movement on the stored data in the target block.

In a possible design, if the running state of the target block obtained by the processor from the buffer is abnormal, the processor marks the target block as a bad block in the buffer.

In a possible design, the erasing and writing operations include programming operations, and the intrinsic parameters include the programming latency of the target block to perform the programming operation; if the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time limit, then the running state is determined to be an abnormal state.

In a third aspect, an embodiment of the present application further provides a storage device, including: a flash memory medium and any one of the storage device controllers provided in the third aspect; wherein, the storage device controller is used to control each block in the flash memory medium Conduct data management.

The present application provides a flash data management method, a storage device controller, and a storage device. By acquiring intrinsic parameters of a target block in a flash memory medium during an erasing and writing operation, and then predicting based on intrinsic parameters and preset intrinsic parameter thresholds The operating status of the target block is used to evaluate the health of each block in the flash medium, and the subsequent data management of the block can be performed according to the predicted operating status of each block, thereby reducing the risk of data loss and improving the data storage reliability of the flash medium. sex.

Description of drawings

1 is a schematic diagram of a NAND Flash organizational structure provided by an embodiment of the present application;

2 is a schematic diagram of a storage system architecture provided by an embodiment of the present application;

3 is a schematic flowchart of a flash data management method provided in Embodiment 1 of the present application;

FIG. 4 is a schematic flowchart of a flash data management method provided in Embodiment 2 of the present application;

5 is a schematic diagram of a programming latency test result according to an embodiment of the present application;

6 is a schematic diagram of a programming latency test result shown in the present application according to another embodiment;

FIG. 7 is a schematic diagram of the voltage distribution of the S1 region shown in FIG. 6;

FIG. 8 is a schematic flowchart of a flash data management method provided in Embodiment 3 of the present application;

9 is a schematic diagram of the test result of the number of bit errors shown in the present application according to an embodiment;

FIG. 10 is a schematic flowchart of a flash data management method provided in Embodiment 4 of the present application;

11 is a schematic structural diagram of a storage device controller according to Embodiment 5 of the present application;

FIG. 12 is a schematic structural diagram of a storage device provided in Embodiment 5 of the present application.

detailed description

In the modern electronic information industry, memory has always played a very important role as a carrier for storing data in electronic equipment. At present, the memory on the market is mainly divided into: volatile memory and non-volatile memory. Among them, NAND Flash is a current mainstream non-volatile storage medium, which has been widely used in smartphones, enterprise-level solid-state drives, servers, and cloud storage. It can save data for a long time after power failure, and has the advantages of fast data transmission speed, low production cost, and large storage capacity.

The current mainstream NAND Flash manufacturers use a 3D multi-layer stacking structure; as the number of stacked layers becomes larger and larger, more and more memory cells (cells) are squeezed into a small space, and the mutual interference between cells/cells The leakage current increases significantly, and the reliability risk of the storage medium increases. The reduction of the distance between the memory cells and the reduction of the thickness of the oxide layer make the inherent errors in the flash memory more and more serious. The traditional error correction code method can no longer meet the reliability requirements of the flash memory. important subject.

Among them, before NAND Flash reaches the maximum erasing and writing (PE) life specification, the medium may have key read and write errors due to process defects, resulting in data loss, or the system needs to spend additional processes to recover data. In addition, in the early application of new-generation media, due to incomplete optimization of production/testing/parameter adjustment, the greater the probability of early media failure, the greater the risk of data loss.

FIG. 1 is a schematic diagram of a NAND Flash organizational structure provided by an embodiment of the present application. As shown in FIG. 1 , after removing some peripheral control units, the NAND chip 100 divides the storage unit into several flash memory slices (planes), for example: a first plane 110 and a second plane 120 . Each plane can be further divided into different blocks (blocks), for example, the first plane 110 includes the first block 110B. In the process of use, if programming/erase/read failure occurs, the block needs to be marked as a bad block, that is, a bad block, where the smallest unit of isolation failure unit is a block. Continuing to refer to FIG. 1 , in the organizational structure of a NAND chip, the block is divided into different strings (strings), and the following strings are further divided into different word lines (Word Lines, WL for short). Among them, the minimum unit of the erase operation is a block, and the minimum unit of the programming operation is a WL.

The industry usually only marks the target block as a bad block when the target block in the NAND Flash is erased or written, for example, when a write failure or an erase failure occurs. Then, additional means are used to recover data lost due to write failures.

FIG. 2 is a schematic diagram of an architecture of a storage system provided by an embodiment of the present application. As shown in FIG. 2 , the storage system provided in this embodiment mainly includes three core modules: a controller (Controller), a buffer (Cache), and a storage medium (NAND Flash), wherein the controller is the entire storage The control brain of the system is responsible for the processing of read and write commands of the SSD, data distribution management, and NAND Flash management. The NAND flash part may consist of 1 die or multiple dies, and is the physical carrier for the final storage of data. The buffer part is used to buffer the data sent from the controller or read from the buffer. In the SSD storage system, the redundant array of independent hard disks (Redundant Array of Independent Disks, referred to as RAID) die will be added to protect data.

Continuing to refer to Figure 2, one of the dies may be used to XOR the data in the remaining dies and then write them into the RAID dies. After the media failure occurs, the lost data can be recovered by reading data from other locations on the same strip; In addition, there is also a way to write the data cache, which can be to write the data to the cache first, and release the cache after the writing to the NAND is successful.

When programming fails to mark bad blocks, such as using RAID and other technologies to restore, in the context of longer RAID stripes, the amount of data that needs to be read and the processing time increase, and if high-reliability cache is used, the medium will be damaged. Increased costs. In addition, some blocks that are successfully erased do not mean that the block is still a good block, and some word lines to the substrate leakage/short circuit (WL-Channel leak/short) will not feedback erase failure (Erase fail), only serious Invalidation will cause the erase to fail. These slight leakages will cause the erased state to tail, so that after the next programming, the erased state (Erase state) and the programming state (the programming state is divided into A/B/C/D/E/F/G, 7 states) intersect Overlap results in Uncorrected Code word (UNC), and this type of erased state trailing will not cause programming failure, nor can it be perceived from the programming state. Therefore, even if high reliability is adopted, when writing to NAND storage, data loss may still occur in the way of releasing the cache after successful programming.

However, the embodiment of the present application aims to predict/evaluate the state of the target block by using some intrinsic parameters during NAND erasing and writing, so as to predict the failure in advance, so as to perform corresponding advanced processing, so as to perform corresponding data on each block in the flash memory medium. management to reduce the risk of data loss.

The technical approach provided by the embodiments of the present application utilizes the intrinsic characteristics of the NAND Flash medium, and mainly utilizes the programming latency (T _program , referred to as T _PROG ), the erasing latency (T _erase , referred to as T _ERS ) and the number of blank page errors after erasing Detect (erased page FBC check) to judge the health status of NAND media, and predict/handle upcoming failures in advance through subsequent operations.

FIG. 3 is a schematic flowchart of a flash data management method provided in Embodiment 1 of the present application. As shown in FIG. 3 , the flash data management method provided by this embodiment includes:

Step 101: Acquire intrinsic parameters of the target block in the flash memory medium during the erasing and writing operations.

Among them, NAND Flash media mainly includes three basic operations: read operation (Read), programming operation (Program), and erase operation (Erase). In addition to the stable Read time, the NAND erase operation and programming operation time will change with the wear degree of the medium. Especially when some weak leakage occurs, the current erase operation or programming operation may not necessarily show state failure. But it can show a big change in erasing operation or programming operation time. Therefore, the prediction of the running state of the target block can be performed by obtaining intrinsic parameters of the target block in the flash medium during the erasing and writing operations, wherein the intrinsic parameters include the operation time required to complete the erasing and writing operations.

Step 102: Predict the running state of the target block according to the intrinsic parameters and a preset intrinsic parameter threshold.

After acquiring the intrinsic parameters of the target block during the erasing and writing operation, the operating state of the target block can be predicted according to the intrinsic parameters of the NAND medium, and based on the intrinsic parameters and the preset intrinsic parameter threshold, wherein the operating state includes normal state and abnormal state. Therefore, the health of the NAND medium is evaluated by monitoring the programming latency and erasing latency of NAND, so as to predict the occurrence of target block failure in advance.

The embodiment of the present application may be a software management solution, in which a whole set of application policies is implemented through a storage system controller. Referring to FIG. 2, the programming latency and the erasing latency can be detected by the controller to detect the execution time of the programming and erasing operations, and the number of blank page errors after erasing can be detected by the controller issuing a read operation to read the blank page data. . Furthermore, the controller can compare the operation time preset offline or the threshold for the number of blank page errors. If a failure is predicted to occur, the controller defines this block as a bad block, ignores it in subsequent operations, and no longer operates.

For the comparison of intrinsic parameters and preset intrinsic parameter thresholds, the following three sub-schemes can be included, namely:

1. Pre-predict the programming operation failure by programming the latency prediction;

2. Predicted programming problems through programming latency;

3. Predict failure by erasing latency and FBC check after erasing.

In actual operation, the above three sub-schemes may be combined arbitrarily for prediction, or only a single scheme may be used for prediction.

Step 103: Perform subsequent data management on the target block according to the predicted running state.

After predicting the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the controller may perform subsequent data management on the target block according to the predicted running state of the target block.

Among them, if the predicted operating state of the target block is abnormal, it means that the target block has a high risk of failure. Therefore, in order to reduce the risk of data loss, the write operation or programming operation on the target block can be stopped to avoid new writing. The entered data is invalid. However, if the predicted running state of the target block is abnormal, it means that the failure risk of the target block is low, and the reliability of storing data in the target block is high. Therefore, you can continue to write to the target block or programming operation.

In addition, when the predicted running state of the target block is an abnormal state, in order to further ensure the risk of loss of data already existing in the target block, data movement may also be performed on the stored data in the target block.

In the process of erasing and writing data, the controller can obtain the relevant identification code of each block to predict the running state of the block, and the block predicted to be in an abnormal state will be marked as a bad block. The identification bit of the block is configured as a specific field for bad block identification.

In this embodiment, by acquiring the intrinsic parameters of the target block in the flash medium during the erasing and writing operation, and then predicting the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the evaluation of the flash medium The health level of each block is used to perform subsequent data management on the block according to the predicted operating state of each block, thereby reducing the risk of data loss and improving the data storage reliability of the flash medium.

Based on the above embodiment, if the predicted operating state is an abnormal state, after predicting the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameters, the target block may be marked as a bad block. Therefore, through the intrinsic parameters of the target block during the erasing and writing operations, the failure can be predicted in advance and the corresponding advanced processing is carried out, so as to reduce the additional operations generated after the failure occurs, further reduce the risk of data loss, and improve the data storage reliability of the flash medium. sex.

In addition, after the target block is marked as a bad block, the data stored in the target block can also be moved. Therefore, before the target block fails, the data stored in the target block is moved to further reduce the risk of data loss and improve the reliability of data storage.

FIG. 4 is a schematic flowchart of a flash data management method provided in Embodiment 2 of the present application. As shown in FIG. 4 , the flash data management method provided by this embodiment includes:

Step 201: Acquire intrinsic parameters of the target block in the flash medium during the erasing and writing operations.

Since the programming operation time will change with the wear degree of the medium, especially when some weak leakage occurs, the current programming operation may not necessarily show a state failure, but it can show a large change in the programming operation time. Among them, the programming latency can be obtained by the controller detecting the execution time of the programming operation.

Therefore, in this step, the prediction of the running state of the target block can be performed by obtaining the programming latency of the target block in the flash memory medium when the programming operation is performed.

Step 202: Determine whether the programming latency is within a preset programming time range. If the judgment result is yes, go to step 204; if the judgement result is no, go to step 203.

In this step, after the programming latency is acquired, the programming latency can also be compared with a preset programming time range, so as to predict the running state of the target block. The preset programming time range may be determined according to a normal programming time range.

Step 203 , predicting that the running state is an abnormal state.

If the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time lower limit, it can be predicted that the operating state is an abnormal state.

Wherein, when the latency period is greater than the preset programming time upper limit value, the word line programming time of each word line in the target block can also be obtained. The above programming latency includes the word line programming time of each word line in the target block. If there is at least one word line programming time greater than the preset word line programming time upper limit, the predicted operating state is an abnormal state, and the preset programming time upper limit Values include preset word line programming time upper limit values.

Specifically, the leakage between the word line and the word line (WL-WL), or between the word line and the channel (WL-channel) may be only a small leakage in the early stage, and the programming failure will not occur immediately, but due to the existence of Leakage will cause the programming voltage on the WL to drop, resulting in a decrease in programming efficiency and an abnormal increase in programming latency, but it does not reach the level of programming failure.

FIG. 5 is a schematic diagram of a programming latency test result according to an embodiment of the present application. As shown in Figure 5, the horizontal axis is the number of erase/write cycles of the target block, the vertical axis is the programming latency, and the four groups are four WLs on the same layer that share the WL metal layer but different channels. The programming sequence is from From top to bottom, it is a cycle. It can be seen that with the increase of the number of erase/write cycles, the programming latency decreases slowly, but when the number of erase/write cycles is around 7500, the programming time of the first WL and the second WL suddenly increases abnormally, but there is no programming failure. A programming failure occurs when the third WL is reached, that is, the fourth WL cannot continue programming. 5, L10 is the programming latency test curve corresponding to the first WL, L20 is the programming latency test curve corresponding to the second WL, L30 is the programming latency test curve corresponding to the third WL, and L40 is the fourth WL The corresponding programming latency test curve.

In addition, in the specific experiment, for the cases where the programming operation fails in the test, all the programming time exceptions of the previous WL occurred before the occurrence. Therefore, an abnormal increase in this type of programming latency is an obvious abnormal signal, and therefore, can be used to detect the occurrence of programming failure in advance.

And when the programming latency is less than the preset programming time lower limit value, the running state can also be predicted to be an abnormal state. Wherein, the above-mentioned intrinsic parameters may also include the number of times of erasing and writing, and the upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of erasing and writing.

Specifically, with the increase of the wear times of the flash memory medium, the defects in the oxide layer will gradually increase after the tunnel oxide layer is subjected to repeated voltage pressure, making it easier for electrons to enter the charge trap layer through the defects. The response in the programming latency is that the programming speed increases and the programming latency decreases. Speeding up the programming speed to a certain threshold will lead to an increase in the number of electrons acquired by each voltage pulse, resulting in a decrease in programming accuracy, which is reflected in particle performance as over-programming, that is, the programmed threshold voltage is higher than the preset value, and the final response is read Data errors are on the rise, even leading to UNC.

Through testing, it is found that the flash memory medium with over-programmed phenomenon has a much shorter programming latency than other normal mediums. FIG. 6 is a schematic diagram of a programming latency test result according to another embodiment of the present application. As shown in FIG. 6 , the vertical axis is the programming latency, and the horizontal axis is the maximum number of errors per page. It can be seen from the figure that the page with an increased Fail Bit Count (FBC for short), that is, the S1 area shown in the figure, has a programming latency in a smaller range.

The threshold voltage distributions of these larger pages of FBCs can be analyzed for the S1 region in Figure 6. Figure 7 is a schematic diagram of the voltage distribution in the S1 region shown in Figure 6. As shown in Figure 7, an obvious over-programming problem can be found, and the increase in the number of errors caused by such over-programming is due to the rise of the voltage valley, even if the bias voltage reads It cannot be recovered. Among them, the horizontal axis in FIG. 7 represents the value of the threshold voltage, and the vertical axis represents the number of memory cells under the threshold voltage. Generally, all memory cells under a word line of a three-level cell (TLC) are distributed in 8 states, except erase. Outside the state, as shown in Figure 7, from left to right are A/B/C/D/E/F/G states, L1 represents the threshold voltage distribution of the page with a large number of errors in the total S1 area of Figure 6, and L2/L3 are The threshold voltage distribution of the normal error number page.

Therefore, the decreasing trend of programming latency can be used to evaluate or predict the health state of the storage medium, and samples can be measured offline, such as the variation of programming latency with the number of PEs, and the programming latency threshold that causes over-programming problems. for online monitoring. When the programming latency drops to a certain threshold, the corresponding target block is processed in advance.

Step 204, predicting that the operating state is a normal state.

In this embodiment, the operating state of the target block is predicted by comparing the programming latency with the preset programming time range. If the predicted operating state is an abnormal state, the target block is predicted according to the intrinsic parameters and the preset intrinsic parameters. After the running state of the block, the target block can be marked as bad. Therefore, the failure is predicted in advance by the intrinsic parameters of the target block during the erasing and writing operation, and the corresponding advanced processing is carried out, which reduces the extra operation after the failure occurs, further reduces the risk of data loss, and improves the data storage reliability of the flash medium. sex.

Step 205: Perform subsequent data management on the target block according to the predicted running state.

After determining the operating state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, the controller may perform subsequent data management on the target block according to the predicted operating state of the target block.

Among them, if the predicted operating state of the target block is abnormal, it means that the target block has a high risk of failure. Therefore, in order to reduce the risk of data loss, the write operation or programming operation on the target block can be stopped to avoid new writing. The entered data is invalid. However, if the predicted running state of the target block is abnormal, it means that the failure risk of the target block is low, and the reliability of storing data in the target block is high. Therefore, you can continue to write to the target block or programming operation. Moreover, in order to identify the target block subsequently, the target block may also be marked as a bad block.

It is worth noting that if the running state of the target block is predicted to be abnormal, the target block can be marked as a bad block, the write operation or programming operation can be stopped on the target block, or the stored data in the target block can be stopped. The data migration can also be any combination of the above three methods.

FIG. 8 is a schematic flowchart of a flash data management method provided in Embodiment 3 of the present application. As shown in FIG. 8 , the flash data management method provided by this embodiment includes:

Step 301: Acquire intrinsic parameters of the target block in the flash memory medium during the erasing and writing operations.

Since the erasing operation time will change with the degree of wear of the medium, especially when some weak leakage occurs, the current erasing operation may not necessarily show a state failure, but it can show a large amount of time in the erasing and writing operation time. Variations, where the erase-write latency can be obtained by the controller detecting the execution time of the programming operation.

Therefore, in this step, the prediction of the running state of the target block can be performed by obtaining the erasing latency of the target block in the flash medium when the erasing operation is performed.

Step 302, judging whether the erasing latency is greater than the preset upper limit of erasing time. If the judgment result is yes, step 303 is executed; if the judgment result is no, step 304 is executed.

Step 303 , predicting that the running state is an abnormal state.

If the erasing latency is greater than the preset upper limit of erasing time, the predicted operating state is an abnormal state. Optionally, after it is determined that the erasing latency is greater than the preset upper limit of erasing time, continue to read the number of bit errors in the erasing operation. If the number of bit errors is greater than the preset number of bit errors, the predicted operating state is abnormal. .

Specifically, due to the high potential difference generated during erasing, many tunnel oxide breakdowns occur during erasing cycles. The leakage of WL-Channel will cause the erase voltage to drop, resulting in an abnormal increase in the erase latency, and the leakage of WL will cause the erased state tail. Since a single WL erased state tail is likely not to feedback the erasure failure, in the follow-up During programming, the Erase state and the programming A state overlap, resulting in unrecoverable data, or programming failure directly in the next programming cycle.

FIG. 9 is a schematic diagram illustrating a test result of the number of bit errors according to an embodiment of the present application. As shown in Figure 9, the data shows that the erase operation before the programming failure did not feedback the erase failure, but the Erased FBC (the dot is the FBC value after erasing, the vertical axis is the FBC, and the horizontal axis is the number of erase cycles) read Fetch has shown abnormality, and programming failure occurs in the next programming cycle (the cross point is the FBC value after programming, where the number of errors read is very high because of programming failure). Therefore, firstly, by judging the change of the erasing time, if the erasing time is abnormally long, read the FBC number in the erasing state, monitor the tailing of the erasing state caused by slight leakage, and predict the failure in advance.

Step 304, predicting that the operating state is a normal state.

In this embodiment, the operating state of the target block is predicted by comparing the erasing latency with the preset upper limit value of erasing time. If the predicted operating state is an abnormal state, the After predicting the running state of the target block based on the characteristic parameters, the target block can be marked as a bad block. Therefore, the failure is predicted in advance by the intrinsic parameters of the target block during the erasing and writing operation, and the corresponding advanced processing is carried out, which reduces the extra operation after the failure occurs, further reduces the risk of data loss, and improves the data storage reliability of the flash medium. sex.

Step 305: Perform subsequent data management on the target block according to the predicted running state.

For the specific implementation of step 305, reference may be made to the specific description of step 205 in the embodiment shown in FIG. 4 , which will not be repeated here.

FIG. 10 is a schematic flowchart of a flash data management method of a flash memory provided by Embodiment 4 of the present application. As shown in FIG. 8 , the flash data management method provided by this embodiment includes:

Step 401 , select the word line of the target block to start writing data.

Step 402: Record the programming latency after programming is completed.

During the programming operation, when programming the target block, the controller records the programming time and the number of erase/write cycles of each WL, and compares it with the programming latency measured offline and the preset programming time range of the number of erase/write cycles after wear. Compared.

Step 403: Determine whether the programming latency is within a preset programming time range. If the judgment result is yes, step 405 is executed, and if the judgment result is no, step 404 is executed.

Step 404: Determine whether the programming latency is greater than the preset programming time upper limit. If the judgment result is yes, step 410 is executed, and if the judgment result is no, step 4041 is executed.

Step 4041, read verification.

Step 4042: Determine whether the read verification is passed. If the judgment result is no, step 410 is executed, and if the judgment result is yes, step 405 is executed.

And when the programming latency is less than the preset programming time lower limit value, the running state can also be predicted to be an abnormal state. The upper limit of the preset programming time and the lower limit of the preset programming time are determined according to the normal programming time corresponding to each number of times of erasing and writing. When the programming latency reaches a certain threshold, the corresponding target block is processed in advance.

Step 405: Continue to program the next word line.

Step 406 , perform an erasing operation on the target block, and record the erasing latency.

Step 407: Determine whether the erasing latency is greater than the preset upper limit of erasing time. If the judgment result is no, go to step 409, and if the judgement result is yes, go to step 4081.

Step 4081: Read the number of bit errors in the erase operation.

Step 4082: Determine that the number of bit errors is greater than the preset number of bit errors. If the judgment result is no, step 409 is executed, and if the judgment result is yes, step 410 is executed.

During the programming operation, when the target starts to perform the programming operation, the controller records the programming time and the number of erasing and writing cycles of each WL, and compares it with the relationship between the programming time and the number of wear cycles measured offline. If the programming latency is within the preset programming time safety range corresponding to the current cycle value, the WL is considered to be in a healthy state, and the next step can be continued. When it is detected that the current programming time is greater than the preset programming time safety range of the cycle value When the target block is directly identified as a bad block, the bad block is marked and the necessary data movement is performed. When it is detected that the current programming time is less than the preset programming time safety range of the cycle value, it is considered that the target block is in a risk state, and the programmed WL is immediately read and verified to determine whether FBC occurs. In the case of rising, if the FBC is found to exceed a certain threshold, it will be marked as a bad block.

During the erasing operation, when the target block starts to be erased, the controller records the erasing latency, and compares the erasing latency with the relationship between the erasing time and the number of wear cycles measured offline. When the erasing latency is found When the erasure time safety interval of the current cycle value is exceeded, the controller sends a read command to read the number of errors in the blank page after erasing the specified page. If the number of bit errors is found to be greater than the preset number of bit errors, it will The target block is marked as bad.

Step 409 , update the erasing cycle times.

Step 410: Mark the target block as a bad block.

FIG. 11 is a schematic structural diagram of a storage device controller according to Embodiment 5 of the present application. As shown in FIG. 11 , the storage device controller 500 provided in this embodiment includes: a processor 501 and a buffer 502 ; wherein, the processor 501 obtains a target block in the flash medium from the buffer 502 when performing an erasing and writing operation and the intrinsic parameters include the execution time of the erase and write operations; then, the processor 501 predicts the running state of the target block according to the intrinsic parameters and the preset intrinsic parameter threshold, and stores the running state in the buffer 502, The running state includes a normal state and an abnormal state; then, the processor 501 performs data management on the target block according to the predicted running state.

In a possible design, if the running state of the target block acquired by the processor 501 from the buffer 502 is an abnormal state, the processor 501 stops writing or programming the target block.

In a possible design, if the running state of the target block acquired by the processor 501 from the buffer 502 is an abnormal state, the processor 501 is configured to perform data movement on the stored data in the target block.

In a possible design, if the running state of the target block obtained by the processor 501 from the buffer 502 is an abnormal state, the processor 501 marks the target block as a bad block in the buffer 502 .

In a possible design, the erasing and writing operations include programming operations, and the intrinsic parameters include the programming latency for the target block to perform the programming operation; if the programming latency is greater than the preset programming time upper limit, or the programming latency is less than the preset programming time limit, the predicted running state is abnormal state.

FIG. 12 is a schematic structural diagram of a storage device provided in Embodiment 5 of the present application. As shown in FIG. 12 , the storage device provided in this embodiment includes a flash memory medium and the storage device controller shown in FIG. 11 . The flash media part may be composed of one die or multiple die, and is the physical carrier for the final storage of data. The storage device controller is used for data management of each block in the flash memory medium.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

A method for managing flash memory data, comprising:

Acquiring intrinsic parameters of the target block in the flash medium during the erasing and writing operations, wherein the intrinsic parameters include the execution time of the erasing and writing operations;

Predict the operating state of the target block according to the intrinsic parameter and a preset intrinsic parameter threshold, where the operating state includes a normal state and an abnormal state;

Data management of the target block according to the predicted operating state.
The method according to claim 1, wherein if the prediction is the abnormal state, the data management performed on the target block according to the predicted operating state comprises:

Stop writing or programming to the target block.
The method according to claim 1 or 2, wherein if the prediction is the abnormal state, the subsequent data management of the target block according to the operating state includes:

Data movement is performed on the stored data in the target block.
The method according to claim 2 or 3, wherein the performing subsequent data management on the target block according to the running state further comprises:

Mark the target block as bad.
The method according to any one of claims 1-4, wherein the erasing and writing operations include programming operations, and the intrinsic parameters include a programming latency for the target block to perform the programming operations;

If the programming latency is greater than the preset programming time upper limit value, or the programming latency is less than the preset programming time lower limit value, the operating state is predicted to be the abnormal state.
The method according to claim 5, wherein the programming latency includes a word line programming time of each word line in the target block, and if there is at least one word line programming time greater than a preset word line programming time limit, the operating state is predicted to be the abnormal state, the preset upper limit of programming time includes the upper limit of the preset word line programming time, and the preset intrinsic parameter threshold includes the target block The preset upper limit value of word line programming time for each word line in .
The method according to claim 5, wherein the intrinsic parameter further includes the number of times of erasing and writing, and the upper limit value of the preset programming time and the lower limit of the preset programming time are based on the lower limit of each number of erasing and writing times. The corresponding normal programming time is determined.
The method according to any one of claims 1-4, wherein the erasing operation includes an erasing operation, and the intrinsic parameter includes an erasing latency for the target block to perform the erasing operation ;

If the erasing latency period is greater than a preset upper limit value of erasing time, it is predicted that the operating state is the abnormal state.
The method according to claim 8, wherein if the erasing latency is greater than a preset upper limit of erasing time, the number of bit errors in the erasing operation is read, and if the number of bit errors is greater than a preset number of errors The number of bit errors is predicted, the operating state is predicted to be the abnormal state.
A storage device controller, comprising: a processor and a buffer;

The processor acquires, from the buffer, an intrinsic parameter of the target block in the flash medium during an erasing and writing operation, wherein the intrinsic parameter includes an execution time of the erasing and writing operation;

The processor determines an operating state of the target block according to the intrinsic parameter and a preset intrinsic parameter threshold, and stores the operating state in the buffer, where the operating state includes a normal state and an abnormal state;

Data management of the target block by the processor according to the predicted operating state.
The storage device controller according to claim 10, wherein if the running state of the target block obtained by the processor from the buffer is the abnormal state, the processor Stop writing or programming to the target block.
The storage device controller according to claim 10 or 11, wherein if the running state of the target block acquired by the processor from the buffer is the abnormal state, the The processor is configured to perform data movement on the stored data in the target block.
The storage device controller according to claim 11 or 12, wherein if the running state of the target block acquired by the processor from the buffer is the abnormal state, the The processor marks the target block as a bad block in the buffer.
The storage device controller according to any one of claims 10-13, wherein the erasing operation includes a programming operation, and the intrinsic parameter includes a programming latency for the target block to perform the programming operation ;

If the programming latency is greater than the preset programming time upper limit value, or the programming latency is less than the preset programming time lower limit value, the operating state is predicted to be the abnormal state.
The storage device controller of claim 14, wherein the programming latency includes a word line programming time of each word line in the target block, and if there is at least one word line programming time greater than a preset word line programming time upper limit value, the operating state is predicted to be the abnormal state, the preset programming time upper limit value includes the preset word line programming time upper limit value, and the preset intrinsic parameter threshold includes all The preset upper limit value of the word line programming time for each word line in the target block.
The storage device controller according to claim 14, wherein the intrinsic parameter further comprises the number of times of erasing and writing, the upper limit value of the preset programming time and the lower limit value of the preset programming time according to each erasing and writing time The normal programming time corresponding to the number of times is determined.
The storage device controller according to any one of claims 10-13, wherein the erasing operation includes an erasing operation, and the intrinsic parameter includes the target block performing the erasing operation. erasure latency;

If the erasing latency period is greater than a preset upper limit value of erasing time, it is predicted that the operating state is the abnormal state.
The storage device controller according to claim 17, wherein if the erasing latency is greater than a preset upper limit of erasing time, the number of bit errors in the erasing operation is read, and if the number of bit errors is If it is greater than the preset number of bit errors, the running state is predicted to be the abnormal state.
A storage device, comprising: a flash memory medium and the storage device controller according to any one of claims 10-18; wherein, the storage device controller is configured to process each block in the flash memory medium Conduct data management.