WO2022022431A1 - System-in-package structure and manufacturing method therefor, and electronic device - Google Patents

System-in-package structure and manufacturing method therefor, and electronic device Download PDF

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Publication number
WO2022022431A1
WO2022022431A1 PCT/CN2021/108316 CN2021108316W WO2022022431A1 WO 2022022431 A1 WO2022022431 A1 WO 2022022431A1 CN 2021108316 W CN2021108316 W CN 2021108316W WO 2022022431 A1 WO2022022431 A1 WO 2022022431A1
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WO
WIPO (PCT)
Prior art keywords
conductive
package structure
substrate
template
pillars
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PCT/CN2021/108316
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French (fr)
Chinese (zh)
Inventor
马会财
佘勇
肖甜
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华为技术有限公司
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Publication of WO2022022431A1 publication Critical patent/WO2022022431A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Definitions

  • the present application relates to the technical field of semiconductor packaging, and in particular, to a system-in-package structure, a manufacturing method thereof, and an electronic device.
  • a certain switching scheme is required to lead the signal of the substrate to the outside of the module for communication.
  • Existing methods for exporting the signals of the substrate to the outside of the module for communication include: arranging solder balls on both sides of a frame board (FB), where one solder ball is connected to the laminated circuit in the substrate, and the other is connected to the laminated circuit in the substrate.
  • Solder balls are interconnected with external circuits; alternatively, balls are mounted on the substrate, and interconnections with external circuits are achieved through the ball-mounting part; or, copper posts are electroplated on the substrate, and the terminals are exposed on the copper posts to connect with external circuits. Realize interconnection; or, use laser or mechanical processing to generate copper column array to realize interconnection with external circuits.
  • these existing methods still have the problems of complicated process, low efficiency or high cost, which need to be further improved.
  • the purpose of the present application is to provide a system-level packaging structure, a manufacturing method thereof, and an electronic device, which have simple process flow, high efficiency, reliability, low cost, and easy popularization and application.
  • a method for fabricating a system-in-package structure comprising the following steps: providing a template, wherein the template is provided with a through hole; filling the through hole with a conductive material; providing a substrate, the The substrate is provided with a pad; the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad.
  • the manufacturing method of the system-level package structure uses a template with through holes, that is, a template method, to sinter and fabricate a conductive column, and electrically connect one end of the conductive column to a pad on the substrate, so that the pad on the substrate is
  • a template with through holes that is, a template method
  • the formation of conductive pillars has the characteristics of simple process, high efficiency, reliability and low cost, which can alleviate the complex process, low efficiency, high cost or difficult application of the existing system-level packaging structure manufacturing method to the conductive pillars. The space between them is small and other scenes.
  • a system-in-package structure comprising:
  • a substrate the substrate is provided with a pad; a conductive column, one end of the conductive column is electrically connected to the pad, and the other end of the conductive column is used for electrical connection with an external circuit; wherein, the conductive column is connected to the conductive material
  • the conductive material is formed by sintering, and the conductive material is filled in the through holes of the template, and the through holes of the template are arranged corresponding to the pads.
  • the system-in-package structure and the fabrication method of the system-in-package structure are based on the same application concept, and therefore at least have the same characteristics as the fabrication method of the system-in-package structure.
  • the system-in-package structure obtained by the method for fabricating the system-in-package structure has the effects of reliable performance and low cost, which will not be described in detail here.
  • an electronic device including the system-in-package structure or the system-in-package structure fabricated by the foregoing fabrication method.
  • the electronic device, the foregoing system-in-package structure and its fabrication method are based on the same application concept, and therefore at least have the same All the features and advantages described in the system-in-package structure and its fabrication method will not be described in detail here.
  • a template with a through hole is used in the packaging process, a conductive material is filled in the through hole, and the conductive material is sintered to form a conductive column.
  • One end of the substrate is electrically connected to the pad of the substrate, so that a conductive column can be formed on the substrate to lead out the signal of the substrate.
  • It uses a conductive material to form conductive pillars on the substrate through a template method to lead out signals from the substrate, which can alleviate the problems of long time and low efficiency of the existing copper plating on the substrate, and can alleviate the existing through-molded vias (TMV).
  • TMV through-molded vias
  • the method cannot achieve high aspect ratio, small-pitch conductive column arrays and the high cost of lasers, which can alleviate the problem of easy delamination of the interface existing in the existing transfer board (FB) method. It is an efficient, low-cost, high-reliability method A method for fabricating a double-sided system-in-package structure of a conductive column array with high aspect ratio and small pitch can be realized.
  • the electronic device including the system-in-package structure of the present application has at least the same advantages as the above-mentioned system-in-package structure and the manufacturing method thereof, and details are not described herein again.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an exemplary embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a method for manufacturing a system-in-package structure provided by an exemplary embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a substrate provided by an exemplary embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a substrate provided with a conductive column array according to an exemplary embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a template provided by an exemplary embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a template provided by another exemplary embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a template provided by another exemplary embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a method for fabricating a system-in-package structure provided by another exemplary embodiment of the present application.
  • FIG. 9 is a schematic flowchart of a method for manufacturing a system-level packaging structure provided in Embodiment 1 of the present application.
  • FIG. 10 is a schematic diagram of a system-in-package structure provided by an embodiment of the present application.
  • Fig. 11 is a schematic diagram of the system-in-package structure provided by Comparative Example 1; in Fig. 11(a), the conductive pillars in the system-in-package structure are boss structures, and in Fig. 11(b), the conductive pillars in the system-in-package structure It is a drum-shaped structure;
  • FIG. 12 is a schematic diagram of a system-in-package structure provided by Comparative Example 2;
  • FIG. 13 is a schematic flowchart of a method for fabricating a system-level packaging structure provided in Embodiment 2 of the present application;
  • FIG. 14 is a schematic flowchart of a method for manufacturing a system-level packaging structure provided in Embodiment 3 of the present application;
  • FIG. 15 is a schematic diagram of a system-in-package structure according to Embodiment 4 of the present application.
  • SiP system-in-package
  • module system integrated chips such as central processing units, storage, communication, power management and charging of electronic products.
  • SiP is developing from single-sided to double-sided, and double-sided SiP needs to export the signal of the substrate to the outside of the module for communication through some switching scheme.
  • the signals of the double-sided SiP are led out from the main substrate to the bottom surface of the module through a transfer board, molded through holes, copper pillars or solder balls, or conductive structural components in the double-sided SiP.
  • the methods of extracting the signal of the substrate to the outside of the module for communication mainly include the following:
  • the copper column array is generated in advance by laser or mechanical processing.
  • One end of the copper column array is fixed on the frame, and then the other end of the copper column array is welded to the substrate, and then plastic-sealed, and the frame part is removed by flat grinding the plastic sealing layer.
  • One end of the column array, and a ball is placed on this terminal to achieve interconnection with external circuits.
  • SMT surface mount technology
  • the technical solutions of the embodiments of the present application provide a system-in-package, a method for manufacturing the same, and an electronic device, so as to alleviate the process complexity of the existing method for fabricating a system-in-package structure , low efficiency, high cost or difficult to apply to metal pillars such as small spacing between copper pillars and other scenarios, to provide a fast, efficient, suitable for high aspect ratio, small spacing metal pillars lead out
  • I A method for fabricating a system-in-package structure of the /O scheme.
  • system-in-package and its manufacturing method of the present application and the electronic device including the system-in-package structure of the present application are further described in detail below with reference to the accompanying drawings.
  • the system-level packaging structure can be applied to electronic devices.
  • electronic devices may include, but are not limited to, mobile phones, tablet computers, laptop computers, in-vehicle computers, display screen devices (such as TVs), wearable devices such as wearable watches, smart bracelets, smart glasses, head-mounted displays, etc.
  • display screen devices such as TVs
  • wearable devices such as wearable watches, smart bracelets, smart glasses, head-mounted displays, etc.
  • AR Augmented Reality
  • VR Virtual Reality
  • PDA Personal Digital Assistant
  • the electronic device of the present application is not limited to the above-mentioned devices, but may include newly developed electronic devices.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the electronic device may be a mobile phone, a wearable device, a computer, a vehicle-mounted computer, or the like.
  • the system-in-package structure provided by the embodiments of the present application can be used for radio frequency antenna modules, power management modules, charging modules, and integrated packaging modules such as mobile phones, wearable devices, computers, and car computers.
  • the embodiment of the present application specifically describes the electronic device by taking a mobile phone as the above-mentioned electronic device as an example.
  • a mobile phone as the above-mentioned electronic device
  • the principles of the present application may be implemented in any suitably arranged electronic device.
  • descriptions of well-known functions and constructions may be omitted for clarity and conciseness.
  • the present application provides an electronic device in some embodiments, the electronic device includes a casing 1 , a system-in-package structure 2 and a battery 3 disposed in the casing 1 .
  • One or more system-in-package structures 2 may be provided within the housing 1 of the electronic device.
  • the system-in-package structure 2 may be a double-sided system-in-package structure.
  • the system-in-package structure 2 can be applied to module system integrated chips such as central processing unit, storage, communication, power management, display module and charging of electronic equipment.
  • the specific structure and fabrication method of the double-sided system-in-package structure 2 will be described in detail below with reference to FIGS. 2 to 15 , and will not be described in detail here.
  • the double-sided package is reused substrate area, enabling higher levels of integration while achieving more reliable interconnects.
  • the embodiments of the present application do not limit the specific position of the double-sided system-in-package structure 2 in the electronic device or the connection with other devices, and it may have various setting forms.
  • the double-sided system-in-package structure 2 can be disposed above the battery 3, or can also be disposed below the battery 3, or can also be disposed adjacent to other devices.
  • the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device.
  • the electronic device may include more or less components than shown, or combine some components, or separate some components, or arrange different components.
  • the electronic device may also include devices such as a camera.
  • the electronic device includes a display screen, the casing and the display screen can be fixedly connected, and the casing and the display screen can form a sealed space to accommodate devices such as a system-in-package structure, a battery, and the like.
  • the display screen may be a display device such as an organic light-emitting diode display (Organic Light-Emitting Diode, OLED), a liquid crystal display (Liquid Crystal Display, LCD), etc., but is not limited to this, and other methods may also be used.
  • the display screen may include a display and a touch device, the display is used for outputting display content to the user, and the touch device is used for receiving touch events input by the user on the display screen.
  • the structure and material of the display screen are not limited.
  • an electronic device may include several devices arranged inside the device, which is not particularly limited in this application. Those skilled in the art can determine the position or location of each device according to actual needs Adjust the specific structure, etc.
  • system-in-package structure and the fabrication method thereof especially the double-sided system-in-package structure and the fabrication method thereof, will be further described below.
  • an embodiment of the present application provides a method for fabricating a system-in-package structure, which includes the following steps:
  • a substrate is provided, and the substrate is provided with pads;
  • the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad.
  • the system-in-package structure is a double-sided system-in-package structure, that is, double-sided SiP.
  • the conductive pillars can be used to transmit electrical signals, that is, the electrical and signal interconnection between the double-sided SiP and the outside world can be realized through the conductive pillars.
  • a template with a through hole is used in the packaging process, a conductive material is filled in the through hole, and the conductive material is sintered to form a conductive column.
  • One end of the column is electrically connected to the pad of the substrate, so that a conductive column can be formed on the substrate to lead out the signal of the substrate. Therefore, in the method for fabricating the system-in-package structure, conductive pillars are formed on the substrate by sintering conductive materials such as metal paste or powder through a template method, so as to lead out signals from the substrate.
  • the process parameters of the template method for sintering conductive pillars can be compatible with the SMT process, which can alleviate the problems of long time and low efficiency of the existing copper plating on the substrate, and can relieve the existing TMV method that cannot realize the conductive pillars with high aspect ratio and small spacing.
  • the problem of high cost of arrays and lasers can alleviate the problem of easy delamination of the interface existing in the existing transfer plate (FB) method. Double-sided SiP fabrication method of pillar array.
  • the substrate 4 includes a first surface 401 and a second surface 402 arranged oppositely; one or more electronic components 5 are mounted on the first surface 401 of the substrate 4 , One or more electronic components 5 are mounted on the second surface 402 of the substrate 4 ; pads 6 are provided on the first surface 401 and/or the second surface 402 of the substrate 4 . That is, the electronic components 5 may be mounted on both the first surface 401 and the second surface 402 of the substrate 4 , the pads 6 may be provided on the first surface 401 of the substrate 4 , or the second surface of the substrate 4 402 may be provided with pads 6 , or both the first surface 401 and the second surface 402 of the substrate 4 may be provided with pads 6 .
  • the pad 6 can be used for electrical connection with one end of the conductive post.
  • the substrate 4 includes a first surface 401 and a second surface 402, and the first surface 401 and the second surface 402 are disposed opposite to each other.
  • the first surface 401 may be the upper surface (front) of the substrate 4, and the second surface 402 may be the lower surface (back) of the substrate 4; or, the first surface 401 may be the lower surface (back) of the substrate 1,
  • the second surface 402 may be the upper surface (front surface) of the substrate 1 .
  • the following mainly takes the first surface 401 as the upper surface (front side) of the substrate 4 and the second surface 402 as the lower surface (back side) of the substrate 4 as an example.
  • the upper surface is the upper surface of the component
  • the lower surface is the downward surface of the component.
  • the front side and the back side of the substrate are only relative concepts, and the embodiments of the present application do not limit the specific positions of the front side and the back side of the substrate.
  • the setting positions of the above-mentioned pads 6 may have various manners.
  • a pad 6 is provided on the back of the substrate 4 , and correspondingly, a conductive material is sintered on the back pad 6 of the substrate 4 by a template method.
  • Conductive pillars 9 are formed.
  • pads 6 may be provided on both the front and the back of the substrate 4.
  • the conductive material is sintered on the front of the substrate 4 by a template method.
  • Conductive pillars 9 are formed on both the pad 6 and the backside pad 6 .
  • one or more of the electronic components 5 may be active and/or passive components.
  • passive components may include inductors, capacitors, resistors, filters, antennas, and the like.
  • the electronic component 5 may be a bare chip or a chip package, and the bare chip or chip package may be an analog integrated circuit chip, a digital integrated circuit chip, and may include operational amplifiers, multipliers, integrated voltage regulators, timers , signal generators, data selectors, codecs, flip-flops, counters, registers, memories, programmable logic, etc.
  • the electronic element 5 may also be an optical element, a communication element, various types of sensors, and the like.
  • the substrate 4 is an important part of the packaging system.
  • the substrate 4 may provide mechanical support and electrical interconnection.
  • Electronic components such as resistors, capacitors, inductors, processors, bare chips, packaged logic components, memories, or other secondary packaged devices may be integrated on the above-mentioned substrate 4 .
  • the substrate can also embed passive components such as resistors, capacitors, inductors, filters, etc., to improve the packaging efficiency of the system.
  • the electronic components may be mounted on the front and back of the substrate through various interconnection techniques of the electronic components and the substrate.
  • electronic components can be mounted on the surface of the SiP substrate by techniques such as SMT, wire bonding, automatic tape bonding, flip-chip bonding, press-fit flip-chip interconnection, etc.
  • the connection method is not limited to the above list. out technology.
  • Those skilled in the art can select an appropriate interconnection technology to mount specific electronic components and/or components on the surface of the SiP substrate according to actual needs, which is not limited in this application. Therefore, for the sake of simplicity and clarity, detailed descriptions of interconnection techniques for electronic components and substrates are omitted herein.
  • the provided substrate 4 is a substrate 4 with one or more electronic components 5 arranged on the front and back, and with pads 6 arranged on the front and/or back.
  • the above-mentioned substrate 4 is provided with a plurality of pads 6, and the plurality of pads 6 form a pad array;
  • the above-mentioned template 7 is provided with a plurality of through holes 8,
  • a plurality of through holes 8 form a through hole array;
  • the through hole array is arranged corresponding to the pad array, so that all the The formed conductive column array is electrically connected to the pad array correspondingly.
  • the backside of the substrate 4 may be provided with a pad array, or both the front and the backside of the substrate 4 may be provided with a pad array.
  • the above-mentioned plurality of pads 6 are arranged at intervals, correspondingly, the above-mentioned plurality of through holes 8 are also arranged at intervals, and correspondingly, the above-mentioned plurality of conductive pillars 9 are also arranged at intervals.
  • the arrangement or position, shape structure, size, etc. of the plurality of through holes 8 are set corresponding to the pad array on the substrate, so that each conductive column 9 in the formed conductive column array can Correspondingly connected to each pad 6 in the pad array.
  • the pads 6 are isolated from each other.
  • the so-called phase isolation means that there is a certain distance between two adjacent pads 6 and they are not in contact.
  • the conductive pillars 9 are also isolated from each other, that is, there is a certain distance between two adjacent conductive pillars 9 and are not in contact, so that there is no signal transmission between adjacent conductive pillars 9 . Therefore, it is possible to avoid a good isolation effect between the lead terminals, avoid a short circuit phenomenon caused by contact, and ensure that each device can work stably.
  • the template 7 may be made of a material that can withstand a certain high temperature and can be reused. In this way, the template can be maintained to have certain mechanical properties or performance during the sintering process, and can be reused many times, thereby reducing the cost.
  • the specific material type of the template 7 can be various types, for example, the template 7 can be made of silicone resin, ceramics, stainless steel and other materials, and the prepared template 7 can withstand a certain high temperature, for example, can withstand a high temperature of about 250°C , and can be reused.
  • the materials of the template 7 are not limited to the ones listed above, and other materials can also be selected, which are not limited in the embodiments of the present application.
  • the through-hole array and the template 7 may be integrally formed, or the template 7 may be fabricated first, and then holes are formed on the template to form the through-hole array.
  • the embodiments of the present application do not limit the specific manner of forming the through-hole array.
  • the through-hole array is formed by using any one of mechanical perforation, photolithography, and the like.
  • the through-hole arrays on the template 7 are in one-to-one correspondence with the pad arrays on the substrate 4 , and the opening size, spacing, and position of the through-holes 8 need to be based on the actual substrate 4 .
  • the arrangement, size, etc. of the pad array are set.
  • the opening size of the through hole 8 is in the range of 10 ⁇ m-1 mm, further can be 50 ⁇ m-1 mm, further can be 100 ⁇ m-0.9 mm, and further can be 200 ⁇ m-0.8 mm, typical but non-limiting, for example, can be 10 ⁇ m, 20 ⁇ m, 40 ⁇ m, 50 ⁇ m, 80 ⁇ m, 100 ⁇ m, 150 ⁇ m, 200 ⁇ m, 300 ⁇ m, 400 ⁇ m, 500 ⁇ m, 600 ⁇ m, 700 ⁇ m, 800 ⁇ m, 900 ⁇ m, 1 mm, and any value in the range of any two of these point values.
  • the distance between two adjacent through holes 8 ranges from 10 ⁇ m to 1 mm, further can be 50 ⁇ m-1 mm, further can be 100 ⁇ m-0.9 mm, and further can be 500 ⁇ m-0.8 mm, typical but non-limiting For example, it can be 10 ⁇ m, 20 ⁇ m, 40 ⁇ m, 50 ⁇ m, 80 ⁇ m, 100 ⁇ m, 150 ⁇ m, 200 ⁇ m, 300 ⁇ m, 400 ⁇ m, 500 ⁇ m, 600 ⁇ m, 700 ⁇ m, 800 ⁇ m, 900 ⁇ m, 1 mm and any two of these point values. any value of .
  • the opening size of the above-mentioned through hole 8 is determined or adapted according to the cross-sectional shape of the through hole.
  • the cross-sectional shape of the through hole 8 can be a circle, a square, an ellipse, a polygon or other regular/irregular shapes, etc.
  • the cross-sectional shape of the formed conductive column 9 can be a circle, a square, an ellipse, Polygons or other regular/irregular shapes, etc.
  • the opening size of the through-hole 8 can be expressed as the diameter of the through-hole (circle diameter); when the cross-sectional shape of the through-hole 8 is oval, the above-mentioned through-hole 8
  • the opening size of the ellipse can be expressed as the long diameter (long diameter) of the ellipse, that is, the distance between the longest two points in the ellipse; when the cross-sectional shape of the through hole 8 is a square, the opening size of the through hole 8 can be expressed as It is the side length of a square, etc., which will not be listed here.
  • the diameter of the through hole 8 and the distance between two adjacent through holes 8 are set according to the pad array on the substrate 4 to be packaged. Within the range of the distance between them, it can meet practical application requirements, has strong adaptability, and can make a certain distance between adjacent conductive pillars 9, which can avoid short-circuit phenomenon caused by contact and ensure that each device can work stably. It can also alleviate the problem that the existing system-in-package method cannot realize the conductive pillar array with high aspect ratio and small pitch.
  • the embodiments of the present application do not limit the specific shape and structure of the through hole 8 and the conductive column, which may be a circle, a square, an ellipse, a polygon, etc., or other
  • the shape of the conductive column which is not described in detail here, can realize the electrical and signal interconnection between the substrate and the outside. Any shape of the conductive column falls within the protection scope of the present application.
  • the thickness of the template 7 can be determined according to the thickness of the bottom surface of the actual double-sided SiP product.
  • the thickness of the template 7 is in the range of 10 ⁇ m-1 mm, further may be 50 ⁇ m-1 mm, further may be 100 ⁇ m-0.9 mm, further may be 500 ⁇ m-0.8 mm, typical but non-limiting, for example, may be 10 ⁇ m, 20 ⁇ m, 40 ⁇ m, 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, 80 ⁇ m, 100 ⁇ m, 150 ⁇ m, 200 ⁇ m, 300 ⁇ m, 400 ⁇ m, 500 ⁇ m, 600 ⁇ m, 700 ⁇ m, 800 ⁇ m, 900 ⁇ m, 1mm and any two of these point values in the range any value.
  • the thickness of the template 7 refers to the thickness of the template in the vertical direction, which can be understood as the height of the template.
  • the thickness (height) of the above-mentioned template 7 may be the height (depth of the through hole) of the through hole 8 .
  • “aspect ratio” refers to the ratio between the depth of the through hole and the opening size of the through hole, eg, the diameter of the through hole.
  • the diameter of the above-mentioned through holes 8 is compatible with the diameter of the formed conductive pillars 9 , and the spacing between the above-mentioned two adjacent through-holes 8 corresponds to the spacing between the formed two adjacent conductive pillars 9 .
  • the height of the through hole 8 and the height of the formed conductive pillar 9 may be compatible, or, in actual operation, according to the condition of the filled conductive material or the operation error, etc., the formed conductive pillar 9 There may also be a slight difference between the height and the height diameter of the through hole 8 .
  • the specific dimensions of the formed conductive pillars 9 will not be described in detail here, and reference may be made to the foregoing description on the dimensions of the through holes.
  • the upper and lower dimensions of the through holes 8 may be the same or different.
  • the through hole 8 may be a through hole structure with the same size of each part.
  • the through hole 8 may be a stepped hole, and the stepped hole includes an upper part of the hole structure and a lower part of the hole structure, wherein the diameter of the upper part of the hole structure is larger than that of the lower part of the hole structure, or the diameter of the upper part of the hole structure is smaller than that of the lower part of the hole structure The diameter of the pore structure.
  • the through hole 8 may be a hole structure whose diameter decreases sequentially from top to bottom, or a hole structure whose diameter increases sequentially from top to bottom.
  • the specific shape and structure of the through hole 8 is not limited, and it may also have other structure and shape structure, which will not be described in detail here.
  • the shape and structure of each through hole 8 in the through hole array may be the same or different.
  • the through hole array may be composed of circular through holes, or may also be composed of circular through holes and oval through holes.
  • the specific form of the through-hole array can also have various types according to the pad array on the substrate.
  • the array of vias can be single-row, multi-row, or random.
  • the through-hole arrays may be arranged in two rows on the top and bottom of the substrate, and one column on the left and right, respectively, and form an annular structure of through-hole arrays.
  • the through hole arrays may be arranged in a row on the upper and lower sides of the substrate, and arranged in a column on the left and right, respectively, and form a ring-shaped through hole array.
  • the through-hole array may be a through-hole array in which the upper, middle, and lower portions of the substrate are arranged in one row, and the left, middle, and right are arranged in a column, and the template is divided into four parts.
  • the specific form of the through-hole array is not limited to the several structural forms listed above.
  • the specific form of the through-hole array can also adopt other structural forms.
  • the number of conductive pillars and pads included in the system-in-package structure may be more than one hundred, so the number and arrangement shown in the accompanying drawings are for illustration only, and do not limit the present application.
  • the conductive material is filled in the above-mentioned through-hole array, and after sintering, a conductive column array can be formed on the pad array of the substrate.
  • the conductive material may be a metal material and/or a non-metal material
  • the formed conductive column may be a metal column, a non-metal column or a composite column.
  • the conductive material includes one or more of metal materials, carbon materials, or polymer materials. That is, the conductive material may be a metal material, a non-metal material, or a mixed material of a metal material and a non-metal material, wherein the non-metal material may be a carbon material, a polymer material, or the like. Further, the carbon material may be graphite, graphene, carbon nanotube (CNT), carbon fiber and other carbon materials.
  • CNT carbon nanotube
  • the form of the conductive material includes powder or paste.
  • the conductive material may be metal powder or a paste containing metal powder.
  • the conductive material may be copper powder, silver powder, aluminum powder, solder paste such as SAC305 solder paste, nano-copper paste, nano-silver paste, and the like.
  • solder paste such as SAC305 solder paste
  • nano-copper paste nano-silver paste
  • the use of these conductive materials has a wide range of sources, strong practicability, easy sintering into conductive columns, and high conductivity, which can meet the required requirements for conduction and signal transmission.
  • the conductive material can be a carbon material such as graphite, graphene or carbon nanotubes, or a mixed material of carbonaceous materials such as graphite, graphene or carbon nanotubes and metal materials such as copper powder, silver powder, etc., or It is a mixed material of polymer material and metal material, etc.
  • the conductive pillars are metal pillars, non-metallic pillars, or composite pillars composed of metal materials and non-metallic materials.
  • the metal pillars may be solder pillars, copper pillars, silver pillars, etc., or may also be carbon material pillars, or may also be composite pillars formed by compounding carbon materials and metal materials. Therefore, the metal pillars help to realize the electrical and signal interconnection between the double-sided SiP structure and the outside world.
  • the material of the pad can also be of various types, for example, the material of the pad includes copper, aluminum or tungsten, and the surface of the pad can be sprayed with tin, immersion silver or immersion gold, etc. This embodiment of the present application also does not make any special restrictions on this.
  • the specific sintering process parameters for sintering the conductive material to form the conductive pillars can be the same as the reflow soldering process parameters of the backside electronic components of the double-sided SiP structure.
  • the sintering process conditions also need to be adjusted according to the type of the specific conductive material.
  • the sintering temperature is 100°C-280°C, further can be 150°C-280°C, further can be 160°C-260°C, further can be 180°C-240°C, typical but not limited For example, it can be 100°C, 120°C, 150°C, 160°C, 180°C, 190°C, 200°C, 220°C, 240°C, 250°C, 260°C, 280°C and any two of these point values. Any value in the range that constitutes.
  • the above-mentioned conductive material can use the existing common lead-free solder. Therefore, in this sintering operation, the metal powder or metal paste in the through-hole array of the template can be sintered under the lead-free solder reflow temperature curve, and then the through-hole array can be sintered. The metal powder or metal paste is cured and sintered. The sintering temperature of the above-mentioned metal powder or paste is compatible with the temperature of the common lead-free solder reflow process. Therefore, the specific operation method or operation conditions of this sintering step will not be described in detail, which can be adjusted by those skilled in the art according to the actual situation. .
  • filling the conductive material in the through hole includes: firstly disposing the template on the transfer carrier, and then filling the conductive material in the through hole.
  • the through holes on the template are through holes passing through the template. Therefore, in order to facilitate the filling of the conductive material into the through holes, the template needs to be fixed on the transfer carrier before filling. Then, the conductive material is filled in the through hole, so as to use the transfer carrier plate to play a certain role of supporting and ensuring the amount of the conductive material filled in the through hole.
  • the template filled with conductive material and the transfer carrier can be transferred to the substrate together, so that the upper surface of the template (the surface on the side away from the transfer carrier) is inverted and in contact with the substrate, and the template is placed on the substrate.
  • the through hole array is aligned with the pad array on the substrate.
  • the transfer carrier located on the lower surface of the template (the surface close to the side of the transfer carrier) can be removed, and then sintered.
  • the operation sequence of removing the transfer carrier plate can be adjusted, which can be adapted according to the operation sequence of the specific packaging method.
  • the conductive material may be sintered first, and then the template of the conductive column and the transfer carrier may be transferred to the substrate together, so that the upper surface of the template is inverted and contacted with the substrate, and the template is placed on the substrate.
  • the through-hole array is aligned with the pad array on the substrate, and after the alignment is completed, the transfer carrier and the template are removed in turn.
  • the conductive material may be filled in the through holes by means of printing. During the printing process, it may need to be repeated several times according to the size of the through hole, such as diameter and height, to ensure that the through hole is filled or filled with a certain amount of metal powder or paste, and then the upper surface of the template can be cleaned to ensure that there is no metal powder. or paste residue.
  • the conductive material may also be filled in the through hole in other manners, which will not be described in detail here.
  • the method for fabricating the system-in-package structure further includes: assembling the tape
  • the substrate with the conductive posts is plastic-sealed to form a plastic-sealing layer; the part of the plastic-sealing layer corresponding to the conductive posts is removed to expose the conductive posts.
  • the plastic encapsulation layer and the substrate are firmly combined, which ensures the reliability of the encapsulation.
  • a plastic sealing process can be performed on the double-sided SiP to form a plastic sealing layer.
  • the balls are implanted to form interconnections, and then the subsequent process steps are completed for the double-sided SiP, and finally a double-sided SiP structure is obtained.
  • the conductive pillar array In order to realize the interconnection between the double-sided SiP structure and the outside world, the conductive pillar array needs to be exposed outside the plastic package.
  • the conductive pillar array may be exposed by flat grinding the plastic encapsulation layer, thinning process, and the like.
  • the above-mentioned forming process of the plastic sealing layer may be an injection molding process, a transfer molding process or a screen printing process, etc. Of course, it may also be other forming processes, which are not limited in the embodiments of the present application.
  • the method further includes: planting balls on the conductive posts. That is, solder balls are formed on the conductive pillars by means of ball mounting, and the solder balls may be located on the top of the conductive pillars, and may also be located on the tops and sidewalls of the conductive pillars.
  • the ball-mounting step may not be performed, that is, the other end of the metal column is directly connected to the external circuit to realize the double-sided SiP structure and the outside world. electrical and signal interconnection.
  • the manufacturing method of the system-in-package structure includes the following steps:
  • Silicone resin, ceramics, stainless steel and other materials are used to make a template that can withstand high temperature of 250°C and can be reused.
  • the template is provided with an array of through holes corresponding to the array of pads on the backside of the double-sided SiP substrate.
  • the opening size and spacing of the through holes can be set according to the pad array of the actual product.
  • the opening size of the through holes can be any size in the range of 10 ⁇ m-1mm, and the spacing between two adjacent through holes can be Any size in the range of 10 ⁇ m-1mm.
  • the shape of the through hole can be a square hole, a circular hole, an oval hole and other holes of any shape.
  • the upper and lower dimensions of the through hole may be the same or different, for example, the upper surface dimension of the through hole is larger than the lower surface dimension, or the lower surface dimension of the through hole is larger than the upper surface dimension and the like.
  • the thickness of the template (through hole depth) can be determined according to the thickness of the actual double-sided SiP product.
  • the thickness of the template can be any size in the range of 10 ⁇ m to 1 mm.
  • the template can be pre-fixed on the transfer carrier plate with tape, and then the metal powder or paste containing metal powder can be filled into the through hole array of the template by printing.
  • the sintering temperature of the metal powder or paste is the same as that of common
  • the lead-free solder reflow process temperature is compatible.
  • the metal powder or metal paste in the template through hole can be sintered.
  • the sintering process parameters are the same as the reflow soldering process parameters of the double-sided SiP backside device.
  • the sintering temperature can be 100°C- In the range of 280°C, after the sintering step is completed, the conductive material in the through hole has been cured and sintered.
  • the sintering process step can be before, after or at the same time as the double-sided SiP backside device surface mount.
  • the template After sintering, the template can be removed and demolded to form a conductive column array, that is, one end of the conductive column is electrically connected to the pad. Then, a plastic sealing process can be performed on the back of the double-sided SiP. After plastic sealing, the conductive column array is leaked through the flat grinding plastic sealing layer, and the ball is planted on the other end of the conductive column to form an interconnection, and then the subsequent process steps are completed for the double-sided SiP. Double-sided SiP structure.
  • the manufacturing method of the system-level packaging structure of the embodiment of the present application is simple to operate, easy to implement, efficient, reliable, low in cost, and easy to realize large-scale production.
  • the method can solve the problem that some existing methods such as TMV method cannot realize conductive column arrays with high aspect ratio and small spacing, and can solve the problems of long time and low efficiency of the existing copper electroplating method.
  • each operation step may be performed in sequence, or may not be performed in sequence.
  • the embodiments of the present application do not limit the sequence of steps for preparing the system-in-package structure, which may be adjusted according to the actual production process.
  • the template filled with conductive material can be transferred to the substrate of double-sided SiP (referred to as transfer), and then sintered, and then the template can be removed (referred to as demolding); or, it can be transferred first, and then demolded , and then sintering; alternatively, sintering can be performed first, then transfer, and then demolding.
  • FIG. 9 shows a schematic flowchart of the manufacturing method of the system-in-package structure provided in Embodiment 1, as shown in FIG. 9 .
  • Template making a silicon resin material is used to make a template that can withstand a high temperature of 250°C and can be reused.
  • the template is provided with a through-hole array corresponding to the pad array on the backside of the double-sided SiP substrate.
  • the through-hole array can be up and down.
  • the through-hole arrays are respectively arranged in two rows and left and right are arranged in one column.
  • the thickness of the prepared template may be 0.15mm or 0.3mm, the diameter of the through holes on the template may be 0.2mm, and the distance between two adjacent through holes may be 0.4mm.
  • the conductive material in the template through hole can be sintered under the lead-free solder reflow temperature curve.
  • the sintering temperature can be in the range of 150°C-280°C, and the sintering step is completed.
  • the conductive material in the rear via has been cured and sintered.
  • the template after sintering, the template can be removed to perform demolding, and a conductive column array is formed on the pad array of the substrate.
  • the diameter of each conductive column in the formed conductive column array is 0.2 mm, and the height is 0.15 mm or 0.285 mm.
  • the double-sided SiP can be plastic-sealed to form a plastic-sealing layer.
  • the conductive column array is leaked out through the flat-grinding plastic-sealing layer. structure.
  • Example 1 of the present application The double-sided system-in-package structure prepared in Example 1 of the present application is shown in FIG. 10 .
  • the double-sided system-in-package structure is prepared.
  • the double-sided system-in-package structure prepared in Comparative Example 1 is shown in FIG. 11 .
  • the conductive pillars 9 in the double-sided system-in-package structure 2 are boss structures
  • the conductive pillars 9 in the double-sided system-in-package structure 2 are drum-shaped structures.
  • electroplating conductive pillar method such as electroplating metal pillar method, or SMT metal pillar method
  • the preparation of the double-sided system level packaging structure is carried out.
  • the double-sided system-in-package structure prepared in Comparative Example 2 is shown in FIG. 12 .
  • the conductive pillars 9 in the double-sided system-in-package structure 2 are cylindrical structures.
  • the method for fabricating the system-level packaging structure provided in Embodiment 1 of the present application includes post-processing such as S100 template fabrication, S200 filling, S300 transfer, S400 sintering, S500 demoulding, and S600 plastic sealing.
  • post-processing such as S100 template fabrication, S200 filling, S300 transfer, S400 sintering, S500 demoulding, and S600 plastic sealing.
  • Example 1 a double-sided system-level package structure fabricated by sintering nano-copper paste or solder paste by a template method is shown in FIG. 10 below.
  • the morphology of the conductive column 9 sintered under the reflow temperature of lead-free solder is 90° in verticality, the conductive column 9 can be a regular cylindrical shape, and the internal structure of the conductive column 9 is not dense, that is, the inner structure of the conductive column 9 is not dense.
  • the tissue density will generally be less than 100%, eg the density is 60%-95% or 70%-90%.
  • the conductive 9-pillars are generally in the shape of bosses with inconsistent upper and lower openings or in the shape of a double-sided system-in-package structure 2.
  • Drum-shaped structure in this way, when the distance between adjacent conductive columns 9 is small, it is easy to connect the two conductive columns, which easily leads to the occurrence of short circuit and affects the transmission of signals. As shown in FIG.
  • the double-sided system-in-package structure 2 prepared by the existing electroplating conductive pillar or SMT conductive pillar method can produce a cylindrical conductive pillar 9 , but the obtained conductive pillar 9
  • the internal structure is dense, and generally the density of the conductive column 9 is 100%, which will increase the cost, and the operation time is long and the efficiency is low.
  • the method for fabricating the system-level packaging structure directly fabricates the conductive column array on the double-sided SiP substrate by the template method, with few process steps, and the conductive column forming process is compatible with the reflow process.
  • the conductive column array is stable and reliable, has low cost and high efficiency, and is suitable for the preparation of conductive column arrays with high aspect ratio and small spacing. Therefore, it is possible to alleviate the high cost of laser drilling in the existing TMV solution and the inability to realize the preparation of conductive column arrays with high aspect ratio and small spacing, or can alleviate the problems of the existing metal column electroplating process taking a long time and high cost .
  • FIG. 13 shows a schematic flowchart of the manufacturing method of the system-in-package structure provided in Embodiment 2, as shown in FIG. 13 .
  • Template making a silicon resin material is used to make a template that can withstand a high temperature of 250°C and can be reused.
  • the template is provided with a through-hole array corresponding to the pad array on the backside of the double-sided SiP substrate.
  • the through-hole array can be up and down.
  • the through-hole arrays are respectively arranged in two rows and left and right are arranged in one column.
  • the thickness of the prepared template may be 0.4 mm or 0.5 mm, the diameter of the through holes on the template may be 0.3 mm, and the distance between two adjacent through holes may be 0.2 mm.
  • the conductive material in the template through hole can be sintered under the lead-free solder reflow temperature curve.
  • the sintering temperature can be in the range of 150°C-280°C.
  • the conductive material in the through hole can be sintered The material has been cured and sintered.
  • each conductive column has a diameter of 0.3 mm and a height of 0.4 mm or 0.5 mm.
  • the double-sided SiP can be plastic-sealed to form a plastic-sealing layer.
  • the conductive column array is leaked out through the flat-grinding plastic-sealing layer. structure.
  • the method for fabricating a system-level package structure provided in Embodiment 2 of the present application includes post-processing such as S100 template fabrication, S200 filling, S300 sintering, S400 transfer, S500 demoulding, and S600 plastic sealing.
  • post-processing such as S100 template fabrication, S200 filling, S300 sintering, S400 transfer, S500 demoulding, and S600 plastic sealing.
  • the main difference between Example 2 and Example 1 is that, in the manufacturing process, Example 2 first sinters the conductive column array, and then transfers the template with the conductive column array to the substrate; The template filled with conductive material is transferred to the substrate, and then sintered to produce the array of conductive pillars.
  • Example 2 The double-sided system-in-package structure prepared in Example 2 can also be shown in FIG. 10 . Compared with Comparative Example 1 and Comparative Example 2, Example 2 can also achieve the same or similar effects as Example 1, which will not be repeated here.
  • FIG. 14 shows a schematic flowchart of the manufacturing method of the system-in-package structure provided in Embodiment 3, as shown in FIG. 14 .
  • Template production use stainless steel and other materials to make a template that can withstand high temperature of 250 ° C and can be reused.
  • the template is provided with a through-hole array corresponding to the pad array on the back of the double-sided SiP substrate.
  • the through-hole array can be up and down.
  • the through-hole arrays are arranged in two or three rows respectively, and in the form of one or two columns on the left and right.
  • the thickness of the prepared template may be 0.6 mm, the diameter of the through holes on the template may be 0.4 mm, and the distance between two adjacent through holes may be 0.15 mm.
  • S200 Filling: pre-fix the prepared template on the transfer carrier, and then fill the solder paste or nano-silver paste or nano-copper paste into the through-hole array of the template by printing, so that the through-holes can be filled. Then clean the upper surface of the template.
  • demoulding after the transfer, the template can be removed, that is, demoulding.
  • each conductive column has a diameter of 0.4 mm and a height of 0.6 mm.
  • the double-sided SiP can be plastic-sealed to form a plastic-sealing layer.
  • the conductive column array is leaked out through the flat-grinding plastic-sealing layer, and then the double-sided SiP structure is finally obtained through subsequent operation steps. .
  • the method for fabricating a system-level package structure provided in Embodiment 3 of the present application includes S100 template fabrication, S200 filling, S300 transfer, S400 demoulding, S500 sintering, S600 plastic sealing and other post-processing.
  • the main difference between Example 3 and Example 1 is that, in the manufacturing process, Example 3 first transfers the template filled with conductive material to the substrate, and then demolds it, that is, pre-sets the conductive column array on the substrate, and then Conducting sintering to fabricate a conductive column array; while in Example 1, a template filled with conductive materials was first transferred to a substrate, then sintered to fabricate a conductive column array, and then demolded.
  • Example 3 can also achieve the same or similar effects as Example 1, which will not be repeated here.
  • the manufacturing process of the method for manufacturing a system-level packaging structure provided in this Embodiment 4 may be the manufacturing process provided by any of the foregoing Embodiments 1-3, and the difference is:
  • Example 4 both the upper surface (front side) and the lower surface (back side) of the substrate are provided with pad arrays, a conductive column array is formed on the pad array on the upper surface of the substrate, and a pad array is formed on the lower surface pad array of the substrate There are arrays of conductive pillars.
  • solder balls are formed on the conductive pillars, and the solder balls can be formed on the conductive pillars by a ball-mounting process. The electrical and signal interconnection between the double-sided system-in-package structure and the outside world or other package structures can be realized through solder balls.
  • the double-sided system-in-package structure prepared in Example 4 of the present application is shown in FIG. 15 .
  • the double-sided system-in-package structure may be a first package body 11 , the first package body 11 and the second package body 12 are stacked in a vertical direction, the upper surface of the first package body 11 and the lower surface of the second package body 12
  • one or more electronic components 5 may be provided on both the upper surface and the lower surface of the first package body 11
  • one or more electronic components 5 may be provided on the second package body 12 .
  • a conductive pillar array is formed on the pad array on the upper surface of the substrate of the first package body 11 , and solder balls 10 are formed on the conductive pillars 9 in the conductive pillar array.
  • the solder balls 10 are located on the upper surface of the first package body 11 and the second Between the lower surfaces of the two packages 12, and the two ends of the solder balls 10 are respectively connected to the conductive pillars 9 and the lower surfaces of the second package 12, thus, through the arrangement of the conductive pillar array and the solder balls 10, the Signal transmission between the first package body 11 and the second package body 12 .
  • a conductive column array is formed on the pad array on the lower surface of the substrate 4 in the first package body 11 , and solder balls 10 are formed on the conductive column 9 in the conductive column array.
  • first,” “second,” and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Words like “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

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Abstract

The present application relates to the technical field of semiconductor encapsulation, and in particular to a system-in-package structure and a manufacturing method therefor, and an electronic device. The manufacturing method for a system-in-package structure in the present application comprises the following steps: providing a template, the template being provided with a through hole; filling the through hole with a conductive material; providing a substrate, the substrate being provided with a pad; and the sintered conductive material forming a conductive column, one end of which is electrically connected to the pad. The manufacturing method in the present application has a simple process flow, is efficient, is reliable, has a low cost, and is easily popularized and applied. The present application can alleviate the problems of a high cost, a low efficiency and a complicated operation existing in an existing encapsulation method.

Description

系统级封装结构及其制作方法和电子设备System-in-package structure, method for making the same, and electronic device
本申请要求于2020年07月30日提交中国专利局,申请号为202010750420.7、申请名称为“系统级封装结构及其制作方法和电子设备”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application with the application number of 202010750420.7 and the application title of "System Level Package Structure and its Fabrication Method and Electronic Equipment", which was submitted to the China Patent Office on July 30, 2020, the entire contents of which are incorporated by reference in this application.
技术领域technical field
本申请涉及半导体封装技术领域,尤其涉及一种系统级封装结构及其制作方法和电子设备。The present application relates to the technical field of semiconductor packaging, and in particular, to a system-in-package structure, a manufacturing method thereof, and an electronic device.
背景技术Background technique
近年来,随着集成电路技术的不断演进与发展,集成功能越来越多,电子产品越来越向小型化、智能化、高性能以及高可靠性发展。而集成电路封装不仅影响着集成电路、电子模块甚至整机的性能,而且还制约着整个电子系统的小型化、低成本化和可靠性。其中,系统级封装(System In a Package,SiP)技术使电子元件的集成度越来越高,其可将大量的电子器件,如多个具有不同功能的有源电子元件与可选无源器件组装到一起,实现一定功能的单个标准封装件,形成一个系统或子系统。系统级封装模块具有微型体积、低耗电等特点,可广泛应用于无线通信模块、便携式通讯产品等领域中。In recent years, with the continuous evolution and development of integrated circuit technology, there are more and more integrated functions, and electronic products are increasingly developing towards miniaturization, intelligence, high performance and high reliability. The integrated circuit packaging not only affects the performance of integrated circuits, electronic modules and even the whole machine, but also restricts the miniaturization, cost reduction and reliability of the entire electronic system. Among them, System In a Package (SiP) technology makes the integration of electronic components higher and higher, which can combine a large number of electronic devices, such as multiple active electronic components with different functions and optional passive components A single standard package that is assembled together to perform a certain function to form a system or subsystem. The system-in-package module has the characteristics of miniature size and low power consumption, and can be widely used in wireless communication modules, portable communication products and other fields.
现有的系统级封装模块中,例如双面系统级封装模块,需要通过某种转接方案将基板的信号引出到模组外进行通信。现有的将基板的信号引出到模组外进行通信的方式包括:通过在转接板(Frame board,FB)的双面设置焊球,其中一个焊球连接到基板内叠层电路,另一个焊球与外部电路实现互连;或者,在基板上植球,通过该植球部分与外部电路实现互连;或者,在基板上电镀铜柱,通过在该铜柱露出端子植球与外部电路实现互连;或者,用激光或机械加工的方式生成铜柱阵列等方式与外部电路实现互连。然而,现有的这些方法还存在工艺复杂、效率低或成本高等问题,有待于进一步改进。In an existing system-in-package module, such as a double-sided system-in-package module, a certain switching scheme is required to lead the signal of the substrate to the outside of the module for communication. Existing methods for exporting the signals of the substrate to the outside of the module for communication include: arranging solder balls on both sides of a frame board (FB), where one solder ball is connected to the laminated circuit in the substrate, and the other is connected to the laminated circuit in the substrate. Solder balls are interconnected with external circuits; alternatively, balls are mounted on the substrate, and interconnections with external circuits are achieved through the ball-mounting part; or, copper posts are electroplated on the substrate, and the terminals are exposed on the copper posts to connect with external circuits. Realize interconnection; or, use laser or mechanical processing to generate copper column array to realize interconnection with external circuits. However, these existing methods still have the problems of complicated process, low efficiency or high cost, which need to be further improved.
申请内容Application content
本申请的目的在于提供一种系统级封装结构及其制作方法和电子设备,工艺流程简单,高效、可靠,成本较低,易于进行推广应用。The purpose of the present application is to provide a system-level packaging structure, a manufacturing method thereof, and an electronic device, which have simple process flow, high efficiency, reliability, low cost, and easy popularization and application.
根据本申请的第一方面,提供一种系统级封装结构的制作方法,包括以下步骤:提供模板,所述模板开设有通孔;将导电材料填充于所述通孔内;提供基板,所述基板设置有焊盘;经烧结的所述导电材料形成导电柱,所述导电柱的一端与所述焊盘电连接。According to a first aspect of the present application, a method for fabricating a system-in-package structure is provided, comprising the following steps: providing a template, wherein the template is provided with a through hole; filling the through hole with a conductive material; providing a substrate, the The substrate is provided with a pad; the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad.
该系统级封装结构的制作方法,通过使用带有通孔的模板,即使用模板法,烧结制作导电柱,并使导电柱的一端与基板上的焊盘电连接,从而在基板的焊盘上形成导电柱,具有工艺简单,高效、可靠,成本较低等特点,能够缓解现有的系统级封装结构的制作方法存在的工艺复杂、效率较低、成本较高或较难应用于导电柱之间的间距 较小等场景的问题。The manufacturing method of the system-level package structure uses a template with through holes, that is, a template method, to sinter and fabricate a conductive column, and electrically connect one end of the conductive column to a pad on the substrate, so that the pad on the substrate is The formation of conductive pillars has the characteristics of simple process, high efficiency, reliability and low cost, which can alleviate the complex process, low efficiency, high cost or difficult application of the existing system-level packaging structure manufacturing method to the conductive pillars. The space between them is small and other scenes.
根据本申请的第二方面,提供一种系统级封装结构,包括:According to a second aspect of the present application, a system-in-package structure is provided, comprising:
基板,所述基板设置有焊盘;导电柱,所述导电柱的一端与焊盘电连接,所述导电柱的另一端用于与外部电路电连接;其中,所述导电柱经由对导电材料烧结而形成,所述导电材料填充于模板的通孔内,所述模板的所述通孔与所述焊盘相对应布置。a substrate, the substrate is provided with a pad; a conductive column, one end of the conductive column is electrically connected to the pad, and the other end of the conductive column is used for electrical connection with an external circuit; wherein, the conductive column is connected to the conductive material The conductive material is formed by sintering, and the conductive material is filled in the through holes of the template, and the through holes of the template are arranged corresponding to the pads.
如前述第一方面关于系统级封装结构的制作方法的阐述,该系统级封装结构与前述系统级封装结构的制作方法是基于同一申请构思的,因而至少具有与前述系统级封装结构的制作方法所描述的所有特征和优势,通过该系统级封装结构的制作方法所得到的系统级封装结构具有性能可靠、成本低的效果,在此不再详细描述。As described in the foregoing first aspect regarding the fabrication method of the system-in-package structure, the system-in-package structure and the fabrication method of the system-in-package structure are based on the same application concept, and therefore at least have the same characteristics as the fabrication method of the system-in-package structure. For all the features and advantages described, the system-in-package structure obtained by the method for fabricating the system-in-package structure has the effects of reliable performance and low cost, which will not be described in detail here.
根据本申请的第三方面,提供一种电子设备,包括由前述的制作方法制作而成的系统级封装结构或前述系统级封装结构。According to a third aspect of the present application, an electronic device is provided, including the system-in-package structure or the system-in-package structure fabricated by the foregoing fabrication method.
如前述第一方面关于系统级封装结构的制作方法和第二方面关于系统级封装结构的阐述,该电子设备与前述系统级封装结构及其制作方法是基于同一申请构思的,因而至少具有与前述系统级封装结构及其制作方法所描述的所有特征和优势,在此不再详细描述。As described in the foregoing first aspect regarding the system-in-package structure and the second aspect regarding the system-in-package structure, the electronic device, the foregoing system-in-package structure and its fabrication method are based on the same application concept, and therefore at least have the same All the features and advantages described in the system-in-package structure and its fabrication method will not be described in detail here.
本申请提供的技术方案可以达到以下有益效果:The technical solution provided by this application can achieve the following beneficial effects:
本申请提供的系统级封装结构及其制作方法,在封装过程中使用了带有通孔的模板,将导电材料填充在该通孔内,对该导电材料进行烧结以形成导电柱,该导电柱的一端电连接在基板的焊盘上,进而可以在基板上形成导电柱,将基板信号引出。其通过模板法使用导电材料在基板上形成导电柱,用以将基板信号引出,能够缓解现有的基板电镀铜柱时间长、效率低的问题,能够缓解现有的模塑通孔(TMV)法无法实现高深宽比、小间距的导电柱阵列和激光成本高的问题,能够缓解现有的转接板(FB)法存在的界面容易分层问题,是一种高效、低成本、高可靠性,能够实现高深宽比、小间距的导电柱阵列的双面系统级封装结构制作方法。In the system-in-package structure and its manufacturing method provided by the present application, a template with a through hole is used in the packaging process, a conductive material is filled in the through hole, and the conductive material is sintered to form a conductive column. One end of the substrate is electrically connected to the pad of the substrate, so that a conductive column can be formed on the substrate to lead out the signal of the substrate. It uses a conductive material to form conductive pillars on the substrate through a template method to lead out signals from the substrate, which can alleviate the problems of long time and low efficiency of the existing copper plating on the substrate, and can alleviate the existing through-molded vias (TMV). The method cannot achieve high aspect ratio, small-pitch conductive column arrays and the high cost of lasers, which can alleviate the problem of easy delamination of the interface existing in the existing transfer board (FB) method. It is an efficient, low-cost, high-reliability method A method for fabricating a double-sided system-in-package structure of a conductive column array with high aspect ratio and small pitch can be realized.
因此,包含本申请系统级封装结构的电子设备,至少具有与上述系统级封装结构及其制作方法相同的优势,在此不再赘述。Therefore, the electronic device including the system-in-package structure of the present application has at least the same advantages as the above-mentioned system-in-package structure and the manufacturing method thereof, and details are not described herein again.
应当理解的是,以上的一般描述和后文的细节描述仅是示例性的,并不能限制本申请。It is to be understood that the foregoing general description and the following detailed description are exemplary only and do not limit the application.
附图说明Description of drawings
为了更清楚地说明本申请实施例的技术方案,下面将对本申请实施例中所需要使用的附图作简单地介绍,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings that need to be used in the embodiments of the present application. For those of ordinary skill in the art, without creative work, the Additional drawings can be obtained from these drawings.
图1为本申请示例性的一种实施方式提供的电子设备结构示意图;FIG. 1 is a schematic structural diagram of an electronic device provided by an exemplary embodiment of the present application;
图2为本申请示例性的一种实施方式提供的系统级封装结构的制作方法流程示意图;FIG. 2 is a schematic flowchart of a method for manufacturing a system-in-package structure provided by an exemplary embodiment of the present application;
图3为本申请示例性的一种实施方式提供的基板结构示意图;FIG. 3 is a schematic structural diagram of a substrate provided by an exemplary embodiment of the present application;
图4为本申请示例性的一种实施方式提供的设置有导电柱阵列的基板结构示意图;FIG. 4 is a schematic structural diagram of a substrate provided with a conductive column array according to an exemplary embodiment of the present application;
图5为本申请示例性的一种实施方式提供的模板结构示意图;FIG. 5 is a schematic structural diagram of a template provided by an exemplary embodiment of the present application;
图6为本申请示例性的另一种实施方式提供的模板结构示意图;FIG. 6 is a schematic structural diagram of a template provided by another exemplary embodiment of the present application;
图7为本申请示例性的另一种实施方式提供的模板结构示意图;FIG. 7 is a schematic structural diagram of a template provided by another exemplary embodiment of the present application;
图8为本申请示例性的另一种实施方式提供的系统级封装结构的制作方法流程示意图;FIG. 8 is a schematic flowchart of a method for fabricating a system-in-package structure provided by another exemplary embodiment of the present application;
图9为本申请实施例1提供的系统级封装结构的制作方法流程示意图;9 is a schematic flowchart of a method for manufacturing a system-level packaging structure provided in Embodiment 1 of the present application;
图10为本申请实施例提供的系统级封装结构的示意图;FIG. 10 is a schematic diagram of a system-in-package structure provided by an embodiment of the present application;
图11为对比例1提供的系统级封装结构的示意图;图11(a)中,系统级封装结构中的导电柱为凸台结构,图11(b)中,系统级封装结构中的导电柱为鼓形结构;Fig. 11 is a schematic diagram of the system-in-package structure provided by Comparative Example 1; in Fig. 11(a), the conductive pillars in the system-in-package structure are boss structures, and in Fig. 11(b), the conductive pillars in the system-in-package structure It is a drum-shaped structure;
图12为对比例2提供的系统级封装结构的示意图;12 is a schematic diagram of a system-in-package structure provided by Comparative Example 2;
图13为本申请实施例2提供的系统级封装结构的制作方法流程示意图;13 is a schematic flowchart of a method for fabricating a system-level packaging structure provided in Embodiment 2 of the present application;
图14为本申请实施例3提供的系统级封装结构的制作方法流程示意图;14 is a schematic flowchart of a method for manufacturing a system-level packaging structure provided in Embodiment 3 of the present application;
图15为本申请实施例4提供的系统级封装结构的示意图。FIG. 15 is a schematic diagram of a system-in-package structure according to Embodiment 4 of the present application.
其中,附图标记说明如下:Among them, the reference numerals are described as follows:
1-壳体;2-系统级封装结构;3-电池;4-基板;401-第一表面;402-第二表面;5-电子元件;6-焊盘;7-模板;8-通孔;9-导电柱;10-焊球;11-第一封装体;12-第二封装体。1-housing; 2-system-in-package structure; 3-battery; 4-substrate; 401-first surface; 402-second surface; 5-electronic component; 6-pad; 7-template; 8-through hole ; 9-conductive column; 10-solder ball; 11-first package body; 12-second package body.
此处的附图被并入说明书中并构成本说明书的一部分,示出了符合本申请的实施例,并与说明书一起用于解释本申请的原理。The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.
具体实施方式detailed description
为了更好的理解本申请的技术方案,下面结合附图对本申请实施例进行详细描述。应当理解,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments.
除非另有定义或说明,本文中所用的专业与科学术语与本领域熟练人员所熟悉的意义相同。Unless otherwise defined or indicated, professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art.
为了提高电子产品性能,集成电路(Integrated circuit,IC)器件的集成度和印刷电路板(PCB)上器件和电路的集成度不断提高,其中,系统级封装(SiP)是一种器件高密度集成封装的趋势,可广泛应用于电子产品的中央处理器、存储、通信、电源管理和充电等模块系统集成芯片。目前,SiP正在从单面向双面发展,双面SiP需通过某种转接方案将基板的信号引出到模组外进行通信。例如,现有技术通过双面SiP中的转接板、模塑穿孔、铜柱或焊球或者导电结构件转接方案将双面SiP的信号从主基板引出到模组的底面。具体地,现有技术中,将基板的信号引出到模组外进行通信的方式主要包括以下几种:In order to improve the performance of electronic products, the integration degree of integrated circuit (IC) devices and the integration degree of devices and circuits on printed circuit boards (PCB) are constantly improving. Among them, system-in-package (SiP) is a high-density integration of devices. The trend of packaging can be widely used in module system integrated chips such as central processing units, storage, communication, power management and charging of electronic products. At present, SiP is developing from single-sided to double-sided, and double-sided SiP needs to export the signal of the substrate to the outside of the module for communication through some switching scheme. For example, in the prior art, the signals of the double-sided SiP are led out from the main substrate to the bottom surface of the module through a transfer board, molded through holes, copper pillars or solder balls, or conductive structural components in the double-sided SiP. Specifically, in the prior art, the methods of extracting the signal of the substrate to the outside of the module for communication mainly include the following:
a)在转接板的两侧表面设置焊球,通过将转接板的一侧面的焊球焊接在基板上,信号通过该焊球到传递基板内叠层电路,然后,通过转接板的另一侧面的焊球实现与外部电路(其他或相邻模组)互连。但是,该方案存在的不足之处在于,转接板方案占用面积较大,工艺复杂,转接板与主板之间在后续回流过程中会由 于局部变形不匹配发生环氧树脂塑封料(Epoxy molding compound,EMC)/基板界面分层,此外,还存在焊料连锡风险高的问题。a) Set solder balls on both sides of the adapter board, by soldering the solder balls on one side of the adapter board to the substrate, the signal passes through the solder balls to the multilayer circuit in the transmission substrate, and then passes through the solder balls of the adapter board. Solder balls on the other side enable interconnection with external circuits (other or adjacent modules). However, the shortcomings of this scheme are that the adapter board scheme occupies a large area and the process is complicated. In the subsequent reflow process between the adapter board and the main board, due to the mismatch of local deformation, epoxy molding compound will occur. compound, EMC)/substrate interface delamination, in addition, there is a high risk of solder bonding.
b)首先在基板上植球,然后塑封,通过平磨塑封层漏出植球部分实现与外部电路互连。但是,该方案存在的不足之处在于,在基板背面先植焊球方案,无法满足I/O(输入/输出)端子数量多、间距小的需求。b) First, mount balls on the substrate, and then plastic-encapsulate, and realize interconnection with external circuits by flat grinding the plastic-encapsulation layer to leak out the ball-mounting part. However, the disadvantage of this solution is that the solder balls are first implanted on the back of the substrate, which cannot meet the requirements of a large number of I/O (input/output) terminals and a small spacing.
c)在基板上电镀铜柱,然后塑封,通过平磨塑封层漏出铜柱部分,在铜柱漏出端子植球实现与外部电路互连。但是,该方案存在的不足之处在于,在基板上电镀铜柱的方案,电镀铜柱的时间随铜柱高度增加而增加,当铜柱高度超过200μm,电镀时间大于3小时,效率较低,成本较高,此外,该方案很难实现较厚的模组互连。c) Electroplating copper pillars on the substrate, and then plastic sealing, the copper pillars are leaked out by flat grinding the plastic sealing layer, and the leakage terminals are planted on the copper pillars to achieve interconnection with external circuits. However, the shortcoming of this scheme is that in the scheme of electroplating copper pillars on the substrate, the time of electroplating copper pillars increases with the height of copper pillars. When the height of copper pillars exceeds 200 μm, the plating time is longer than 3 hours, and the efficiency is low. The cost is high, and in addition, it is difficult to achieve thicker module interconnection with this solution.
d)预先用激光或者机械加工的方式生成铜柱阵列,铜柱阵列一端固定在框架上,然后将铜柱阵列的另一端焊接在基板上,然后塑封,通过平磨塑封层去掉框架部分漏出铜柱阵列的一端,并在这一端子上植球实现与外部电路互连。但是,该方案存在的不足之处在于,在基板上表面贴装(Surface mounting technique,SMT)铜柱方案中,首先要用机械加工或激光加工方式制作带框架的铜柱,当铜柱阵列间距减小、数量增加的情况下,机械和激光加工难度大,制作时间长,效率低,成本较高。d) The copper column array is generated in advance by laser or mechanical processing. One end of the copper column array is fixed on the frame, and then the other end of the copper column array is welded to the substrate, and then plastic-sealed, and the frame part is removed by flat grinding the plastic sealing layer. One end of the column array, and a ball is placed on this terminal to achieve interconnection with external circuits. However, the disadvantage of this solution is that in the surface mount technology (SMT) copper column solution on the substrate, the copper column with frame must be fabricated by machining or laser processing first. When the copper column array spacing is In the case of reducing and increasing the number, mechanical and laser processing is difficult, the production time is long, the efficiency is low, and the cost is high.
e)首先对双面SiP进行塑封,然后在SiP背面用激光方法形成孔阵列,即模塑通孔(Through molding via,TMV),在通孔内填充焊球实现互连引出端子(I/O端子)。但是,该方案存在的不足之处在于,TMV方案无法实现厚度较大、(铜柱阵列)间距较小的应用,且成本较高;此外,TMV方案用激光在塑封层上打孔,效率低,成本高。e) First, plastic-encapsulate the double-sided SiP, and then use a laser method to form a hole array on the back of the SiP, that is, through molding via (TMV), and fill the through hole with solder balls to achieve interconnection lead-out terminals (I/O terminal). However, the disadvantage of this scheme is that the TMV scheme cannot achieve applications with large thickness and small spacing (copper column array), and the cost is high; in addition, the TMV scheme uses lasers to punch holes in the plastic sealing layer, which is inefficient. ,high cost.
鉴于此,为了克服现有技术的不完善,本申请实施例的技术方案提供一种系统级封装及其制作方法和电子设备,以期能够缓解现有的系统级封装结构的制作方法存在的工艺复杂、效率较低、成本较高或较难应用于金属柱如铜柱之间的间距较小等场景的问题,提供一种可快速、高效、适用于高深宽比、小间距的金属柱引出I/O方案的系统级封装结构的制作方法。In view of this, in order to overcome the imperfection of the prior art, the technical solutions of the embodiments of the present application provide a system-in-package, a method for manufacturing the same, and an electronic device, so as to alleviate the process complexity of the existing method for fabricating a system-in-package structure , low efficiency, high cost or difficult to apply to metal pillars such as small spacing between copper pillars and other scenarios, to provide a fast, efficient, suitable for high aspect ratio, small spacing metal pillars lead out I A method for fabricating a system-in-package structure of the /O scheme.
在一种具体实施例中,下面通过具体的实施例并结合附图对本申请的系统级封装及其制作方法和包含该系统级封装结构的电子设备做进一步的详细描述。In a specific embodiment, the system-in-package and its manufacturing method of the present application and the electronic device including the system-in-package structure of the present application are further described in detail below with reference to the accompanying drawings.
为了方便理解本申请实施例提供的系统级封装结构及其制作方法,下面首先说明一下其应用场景,该系统级封装结构可以应用于电子设备。具体地,电子设备可以包括但不限于手机、平板电脑、笔记本电脑、车载电脑、显示屏设备(如电视)、可穿戴设备如穿戴手表、智能手环、智能眼镜、头戴式显示器等,还有增强现实(Augmented Reality,AR)设备、虚拟现实(Virtual Reality,VR)设备、个人数字助理(Personal Digital Assistant,PDA)、智能家居产品等。另外,本申请的电子设备不限于上述设备,而是可以包括新开发的电子设备。本申请实施例对于上述电子设备的具体形式不作特殊限制。In order to facilitate understanding of the system-level packaging structure and the manufacturing method thereof provided by the embodiments of the present application, an application scenario thereof is first described below. The system-level packaging structure can be applied to electronic devices. Specifically, electronic devices may include, but are not limited to, mobile phones, tablet computers, laptop computers, in-vehicle computers, display screen devices (such as TVs), wearable devices such as wearable watches, smart bracelets, smart glasses, head-mounted displays, etc. There are Augmented Reality (AR) devices, Virtual Reality (VR) devices, Personal Digital Assistant (PDA), smart home products, etc. In addition, the electronic device of the present application is not limited to the above-mentioned devices, but may include newly developed electronic devices. The embodiments of the present application do not specifically limit the specific form of the above electronic device.
作为示例而非限定,在本申请实施例中,该电子设备可以为手机、可穿戴设 备、电脑、车载电脑等。本申请实施例提供的系统级封装结构可以用于手机、可穿戴设备、电脑、车载电脑等射频天线模块、电源管理模块、充电模块小型化和一体式封装模块等。As an example and not a limitation, in this embodiment of the present application, the electronic device may be a mobile phone, a wearable device, a computer, a vehicle-mounted computer, or the like. The system-in-package structure provided by the embodiments of the present application can be used for radio frequency antenna modules, power management modules, charging modules, and integrated packaging modules such as mobile phones, wearable devices, computers, and car computers.
为了方便描述,本申请实施例以手机为上述电子设备为例对所述电子设备做具体阐述。然而,本领域技术人员将理解,本申请的原理可以在任何适当布置的电子设备中实现。此外,为了清楚和简洁,可以省略对公知功能和结构的描述。For the convenience of description, the embodiment of the present application specifically describes the electronic device by taking a mobile phone as the above-mentioned electronic device as an example. Those skilled in the art will understand, however, that the principles of the present application may be implemented in any suitably arranged electronic device. Also, descriptions of well-known functions and constructions may be omitted for clarity and conciseness.
具体地,请参考附图1所示,本申请在一些实施例中提供一种电子设备,该电子设备包括壳体1和设置于壳体1内的系统级封装结构2和电池3。在该电子设备的壳体1内可以设置一个或多个系统级封装结构2。其中,系统级封装结构2可以为双面系统级封装结构。该系统级封装结构2可以应用于电子设备品的中央处理器、存储、通信、电源管理、显示模组和充电等模块系统集成芯片。该双面系统级封装结构2的具体结构及制作方法将在下文结合图2-图15进行详细描述,在此暂不详述。Specifically, referring to FIG. 1 , the present application provides an electronic device in some embodiments, the electronic device includes a casing 1 , a system-in-package structure 2 and a battery 3 disposed in the casing 1 . One or more system-in-package structures 2 may be provided within the housing 1 of the electronic device. The system-in-package structure 2 may be a double-sided system-in-package structure. The system-in-package structure 2 can be applied to module system integrated chips such as central processing unit, storage, communication, power management, display module and charging of electronic equipment. The specific structure and fabrication method of the double-sided system-in-package structure 2 will be described in detail below with reference to FIGS. 2 to 15 , and will not be described in detail here.
为了进一步提高系统级封装芯片的集成度,通过在封装基板的双面安装一个或多个电子元件(电子元器件),其中电子元件包括有源元件和/或无源元件,双面重复利用封装基板面积,实现更高的集成度,同时获得更加可靠的互连。In order to further improve the integration of the system-in-package chip, by mounting one or more electronic components (electronic components) on both sides of the package substrate, wherein the electronic components include active components and/or passive components, the double-sided package is reused substrate area, enabling higher levels of integration while achieving more reliable interconnects.
需要指出的是,本申请实施例对于双面系统级封装结构2在电子设备中的具体位置或与其他器件的连接等不作限定,其可以是具有多种设置形式的。示例性的,双面系统级封装结构2可以设置于电池3的上方,或者也可以设置于电池3的下方,或者也可以与其他的器件相邻设置。It should be pointed out that the embodiments of the present application do not limit the specific position of the double-sided system-in-package structure 2 in the electronic device or the connection with other devices, and it may have various setting forms. Exemplarily, the double-sided system-in-package structure 2 can be disposed above the battery 3, or can also be disposed below the battery 3, or can also be disposed adjacent to other devices.
还需说明的是,本申请实施例示意的结构并不构成对电子设备的具体限定。在本申请另一些实施例中,电子设备可以包括比图示更多或更少的部件,或者组合某些部件,或者拆分某些部件,或者不同的部件布置。例如电子设备还可以包括摄像头等器件。It should also be noted that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or less components than shown, or combine some components, or separate some components, or arrange different components. For example, the electronic device may also include devices such as a camera.
在一些实施例中,该电子设备包括显示屏,壳体和显示屏可以固定连接,壳体和显示屏可以形成密封空间,以容纳系统级封装结构、电池等器件。In some embodiments, the electronic device includes a display screen, the casing and the display screen can be fixedly connected, and the casing and the display screen can form a sealed space to accommodate devices such as a system-in-package structure, a battery, and the like.
具体地,显示屏可以为有机发光二极管显示器(OrganicLight-Emitting Diode,OLED)、液晶显示器(Liquid Crystal Display,LCD)等显示器件,但并不限于此,还可以采用其它方式。应当理解的是,显示屏可以包括显示器和触控器件,显示器用于向用户输出显示内容,触控器件用于接收用户在显示屏上输入的触摸事件。本申请实施例中,对显示屏的结构和材质不作限定。Specifically, the display screen may be a display device such as an organic light-emitting diode display (Organic Light-Emitting Diode, OLED), a liquid crystal display (Liquid Crystal Display, LCD), etc., but is not limited to this, and other methods may also be used. It should be understood that the display screen may include a display and a touch device, the display is used for outputting display content to the user, and the touch device is used for receiving touch events input by the user on the display screen. In the embodiments of the present application, the structure and material of the display screen are not limited.
本领域技术人员理解,为了向用户提供所需的功能,电子设备可包括布置在设备内部的若干器件,本申请对此也不作特殊限制,本领域技术人员可以根据实际需求对各器件的位置或具体结构等进行调整。Those skilled in the art understand that, in order to provide users with required functions, an electronic device may include several devices arranged inside the device, which is not particularly limited in this application. Those skilled in the art can determine the position or location of each device according to actual needs Adjust the specific structure, etc.
下面将对系统级封装结构及其制作方法,尤其是双面系统级封装结构及其制作方法进行进一步的说明。The system-in-package structure and the fabrication method thereof, especially the double-sided system-in-package structure and the fabrication method thereof, will be further described below.
请参阅图2所示,本申请的实施例提供一种系统级封装结构的制作方法,其包括以下步骤:Referring to FIG. 2 , an embodiment of the present application provides a method for fabricating a system-in-package structure, which includes the following steps:
提供模板,模板开设有通孔;Provide template with through holes;
将导电材料填充于所述通孔内;filling the conductive material in the through hole;
提供基板,基板设置有焊盘;A substrate is provided, and the substrate is provided with pads;
经烧结的导电材料形成导电柱,导电柱的一端与焊盘电连接。The sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad.
其中,系统级封装结构为双面系统级封装结构,即双面SiP。导电柱可以用于传递电信号,也就是,通过该导电柱可以实现双面SiP与外界的电、信号互连。The system-in-package structure is a double-sided system-in-package structure, that is, double-sided SiP. The conductive pillars can be used to transmit electrical signals, that is, the electrical and signal interconnection between the double-sided SiP and the outside world can be realized through the conductive pillars.
本申请实施例提供的系统级封装结构的制作方法,在封装过程中使用了带有通孔的模板,将导电材料填充在该通孔内,对该导电材料进行烧结以形成导电柱,该导电柱的一端电连接在基板的焊盘上,进而可以在基板上形成导电柱,将基板信号引出。由此,该系统级封装结构的制作方法,通过模板法使用导电材料比如金属膏体或粉末烧结在基板上形成导电柱,用以将基板信号引出。该模板法烧结制作导电柱工艺参数可以与SMT工艺兼容,能够缓解现有的基板电镀铜柱时间长、效率低的问题,能够缓解现有的TMV法无法实现高深宽比、小间距的导电柱阵列和激光成本高的问题,能够缓解现有的转接板(FB)法存在的界面容易分层问题,是一种高效、低成本、高可靠性,能够实现高深宽比、小间距的导电柱阵列的双面SiP制作方法。In the method for fabricating a system-in-package structure provided by the embodiments of the present application, a template with a through hole is used in the packaging process, a conductive material is filled in the through hole, and the conductive material is sintered to form a conductive column. One end of the column is electrically connected to the pad of the substrate, so that a conductive column can be formed on the substrate to lead out the signal of the substrate. Therefore, in the method for fabricating the system-in-package structure, conductive pillars are formed on the substrate by sintering conductive materials such as metal paste or powder through a template method, so as to lead out signals from the substrate. The process parameters of the template method for sintering conductive pillars can be compatible with the SMT process, which can alleviate the problems of long time and low efficiency of the existing copper plating on the substrate, and can relieve the existing TMV method that cannot realize the conductive pillars with high aspect ratio and small spacing. The problem of high cost of arrays and lasers can alleviate the problem of easy delamination of the interface existing in the existing transfer plate (FB) method. Double-sided SiP fabrication method of pillar array.
具体地,如图3所示,在一些实施例中,基板4包括相对设置的第一表面401和第二表面402;在基板4的第一表面401安装有一个或多个电子元件5,在基板4的第二表面402安装有一个或多个电子元件5;在基板4的第一表面401和/或第二表面402设置有焊盘6。也就是,在该基板4的第一表面401和第二表面402均可以安装有电子元件5,在该基板4的第一表面401可以设置有焊盘6,或在该基板4的第二表面402可以设置有焊盘6,或在该基板4的第一表面401和第二表面402均可以设置有焊盘6。该焊盘6可以用于与导电柱的一端电连接。Specifically, as shown in FIG. 3 , in some embodiments, the substrate 4 includes a first surface 401 and a second surface 402 arranged oppositely; one or more electronic components 5 are mounted on the first surface 401 of the substrate 4 , One or more electronic components 5 are mounted on the second surface 402 of the substrate 4 ; pads 6 are provided on the first surface 401 and/or the second surface 402 of the substrate 4 . That is, the electronic components 5 may be mounted on both the first surface 401 and the second surface 402 of the substrate 4 , the pads 6 may be provided on the first surface 401 of the substrate 4 , or the second surface of the substrate 4 402 may be provided with pads 6 , or both the first surface 401 and the second surface 402 of the substrate 4 may be provided with pads 6 . The pad 6 can be used for electrical connection with one end of the conductive post.
应理解,该基板4包括第一表面401和第二表面402,且第一表面401和第二表面402相对设置。其中,第一表面401可以为基板4的上表面(正面),第二表面402可以为基板4的下表面(背面);或者,第一表面401可以为基板1的下表面(背面),第二表面402可以为基板1的上表面(正面)。示例性的,为了方便描述几个部件的相对位置关系,下面主要以第一表面401为基板4的上表面(正面),第二表面402为基板4的下表面(背面)为例对该双面SiP及其制作方法做具体阐述。参照图3所示,其中,上表面为部件上朝向上方的表面,下表面为部件上朝向下方的表面。然而,本领域技术人员将理解,基板的正面和背面仅为相对的概念,本申请实施例不限制基板的正面和背面的具体位置。It should be understood that the substrate 4 includes a first surface 401 and a second surface 402, and the first surface 401 and the second surface 402 are disposed opposite to each other. Wherein, the first surface 401 may be the upper surface (front) of the substrate 4, and the second surface 402 may be the lower surface (back) of the substrate 4; or, the first surface 401 may be the lower surface (back) of the substrate 1, The second surface 402 may be the upper surface (front surface) of the substrate 1 . Exemplarily, for the convenience of describing the relative positional relationship of several components, the following mainly takes the first surface 401 as the upper surface (front side) of the substrate 4 and the second surface 402 as the lower surface (back side) of the substrate 4 as an example. The surface SiP and its manufacturing method are described in detail. Referring to FIG. 3 , the upper surface is the upper surface of the component, and the lower surface is the downward surface of the component. However, those skilled in the art will understand that the front side and the back side of the substrate are only relative concepts, and the embodiments of the present application do not limit the specific positions of the front side and the back side of the substrate.
为适应不同的应用场景或满足不同的需求,上述焊盘6的设置位置是可以具有多种方式的。可选的,如图3和图4所示,在一些实施例中,在该基板4的背面设置有焊盘6,相应的,通过模板法使用导电材料烧结在基板4的背面焊盘6上形成导电柱9。在另一实施例中,当系统级封装结构包括多层结构时,在该基板4的正面和背面均可以设置有焊盘6,相应的,通过模板法使用导电材料烧结在基板4的正面焊盘6和背面焊盘6上均形成导电柱9。In order to adapt to different application scenarios or meet different requirements, the setting positions of the above-mentioned pads 6 may have various manners. Optionally, as shown in FIG. 3 and FIG. 4 , in some embodiments, a pad 6 is provided on the back of the substrate 4 , and correspondingly, a conductive material is sintered on the back pad 6 of the substrate 4 by a template method. Conductive pillars 9 are formed. In another embodiment, when the system-in-package structure includes a multi-layer structure, pads 6 may be provided on both the front and the back of the substrate 4. Correspondingly, the conductive material is sintered on the front of the substrate 4 by a template method. Conductive pillars 9 are formed on both the pad 6 and the backside pad 6 .
需要指出的是,本申请实施例对于上述设置在基板正面、背面的一个或多个 电子元件5的具体类型不作限定。例如,一个或多个电子元件5可以为有源元件和/或无源元件。示例性的,无源元件可以包括电感、电容、电阻、滤波器、天线等。示例性的,电子元件5可以是裸芯片或芯片封装件,该裸芯片或芯片封装件可以是模拟集成电路芯片、数字集成电路芯片,可包括运算放大器、乘法器、集成稳压器、定时器、信号发生器、数据选择器、编码译码器、触发器、计数器、寄存器、存储器、可编程逻辑等。电子元件5还可以是光学元件、通信元件、各类传感器等。It should be noted that the embodiments of the present application do not limit the specific types of the above-mentioned one or more electronic components 5 disposed on the front side and the back side of the substrate. For example, one or more of the electronic components 5 may be active and/or passive components. Exemplarily, passive components may include inductors, capacitors, resistors, filters, antennas, and the like. Exemplarily, the electronic component 5 may be a bare chip or a chip package, and the bare chip or chip package may be an analog integrated circuit chip, a digital integrated circuit chip, and may include operational amplifiers, multipliers, integrated voltage regulators, timers , signal generators, data selectors, codecs, flip-flops, counters, registers, memories, programmable logic, etc. The electronic element 5 may also be an optical element, a communication element, various types of sensors, and the like.
基板4是封装系统的重要组成部分。例如,基板4可提供机械支撑和电互连。上述基板4上可以集成有电阻、电容、电感、处理器、裸芯片、封装过的逻辑部件、存储器或其他二次封装的器件等电子元件。此外,基板还可以埋置电阻、电容、电感、滤波器等无源元件,以提高系统的封装效率。The substrate 4 is an important part of the packaging system. For example, the substrate 4 may provide mechanical support and electrical interconnection. Electronic components such as resistors, capacitors, inductors, processors, bare chips, packaged logic components, memories, or other secondary packaged devices may be integrated on the above-mentioned substrate 4 . In addition, the substrate can also embed passive components such as resistors, capacitors, inductors, filters, etc., to improve the packaging efficiency of the system.
在本申请的实施例中,可通过各种电子元件和基板的互连技术将电子元件安装在基板的正面和背面。例如,可通过SMT、引线键合、载带自动键合、倒装芯片键合、压接倒装互连等技术将电子元件安装在SiP基板的表面上,此外,该连接方式不限于以上列出的技术。本领域的技术人员可根据实际需要,选择适当的互连技术将具体电子元件和或组件安装在SiP基板的表面上,本申请对此不作限定。因此,为了简化和清楚起见,本文省略电子元件和基板的互连技术的详细描述。In the embodiments of the present application, the electronic components may be mounted on the front and back of the substrate through various interconnection techniques of the electronic components and the substrate. For example, electronic components can be mounted on the surface of the SiP substrate by techniques such as SMT, wire bonding, automatic tape bonding, flip-chip bonding, press-fit flip-chip interconnection, etc. In addition, the connection method is not limited to the above list. out technology. Those skilled in the art can select an appropriate interconnection technology to mount specific electronic components and/or components on the surface of the SiP substrate according to actual needs, which is not limited in this application. Therefore, for the sake of simplicity and clarity, detailed descriptions of interconnection techniques for electronic components and substrates are omitted herein.
可以理解,本申请实施例中,所提供的基板4,是正面和背面设置有一个或多个电子元件5,正面和/或背面设置有焊盘6的基板4。It can be understood that, in the embodiment of the present application, the provided substrate 4 is a substrate 4 with one or more electronic components 5 arranged on the front and back, and with pads 6 arranged on the front and/or back.
具体地,在一些实施例中,如图3至图5所示,上述基板4设置有多个焊盘6,多个焊盘6形成焊盘阵列;上述模板7设置有多个通孔8,多个通孔8形成通孔阵列;通过多个通孔8的设置能够形成多个导电柱9,多个导电柱9形成导电柱阵列;通孔阵列与焊盘阵列相对应配置,以使所形成的导电柱阵列与焊盘阵列相对应电连接。其中,基板4的背面可以设置有焊盘阵列,或者在基板4的正面和背面均可以设置有焊盘阵列。Specifically, in some embodiments, as shown in FIGS. 3 to 5 , the above-mentioned substrate 4 is provided with a plurality of pads 6, and the plurality of pads 6 form a pad array; the above-mentioned template 7 is provided with a plurality of through holes 8, A plurality of through holes 8 form a through hole array; through the arrangement of the plurality of through holes 8, a plurality of conductive pillars 9 can be formed, and the plurality of conductive pillars 9 form a conductive pillar array; the through hole array is arranged corresponding to the pad array, so that all the The formed conductive column array is electrically connected to the pad array correspondingly. Wherein, the backside of the substrate 4 may be provided with a pad array, or both the front and the backside of the substrate 4 may be provided with a pad array.
应理解,上述多个焊盘6是间隔设置的,相应的,上述多个通孔8也是间隔设置的,相应的,上述多个导电柱9也是间隔设置的。并且,多个通孔8的排列方式或位置、形状结构、尺寸等是与基板上的焊盘阵列相对应设置的,以使所形成的导电柱阵列中的每一导电柱9能以对一对应连接到焊盘阵列中的每一焊盘6。在具体设置时,各焊盘6之间是相隔离的,所谓的相隔离就是相邻两个焊盘6之间具有一定的间距、是不接触的,相应的,连接在各焊盘6上的导电柱9也是相隔离的,即相邻两个导电柱9之间具有一定的间距、是不接触的,以使相邻的导电柱9之间没有信号传输。从而能避免各引出端子之间具有良好的隔离效果,能避免因接触导致的短路现象,保证各器件能够稳定的工作。It should be understood that the above-mentioned plurality of pads 6 are arranged at intervals, correspondingly, the above-mentioned plurality of through holes 8 are also arranged at intervals, and correspondingly, the above-mentioned plurality of conductive pillars 9 are also arranged at intervals. In addition, the arrangement or position, shape structure, size, etc. of the plurality of through holes 8 are set corresponding to the pad array on the substrate, so that each conductive column 9 in the formed conductive column array can Correspondingly connected to each pad 6 in the pad array. In the specific setting, the pads 6 are isolated from each other. The so-called phase isolation means that there is a certain distance between two adjacent pads 6 and they are not in contact. Correspondingly, they are connected to each pad 6 The conductive pillars 9 are also isolated from each other, that is, there is a certain distance between two adjacent conductive pillars 9 and are not in contact, so that there is no signal transmission between adjacent conductive pillars 9 . Therefore, it is possible to avoid a good isolation effect between the lead terminals, avoid a short circuit phenomenon caused by contact, and ensure that each device can work stably.
具体地,在一些实施例中,模板7可以是由能够耐一定的高温、能重复利用的材质制作而成。这样,能在烧结过程中保持模板具有一定的机械性能或使用性能,而且能够多次重复使用,可降低成本。模板7的具体材料类型可以是多种类型的,示例性的,模板7可由硅树脂、陶瓷、不锈钢等材料制作而成,制成的模板7可耐一定的高温例如可耐250℃左右的高温,且能够重复利用。此外,模板7的材料并 不限于以上所列举的几种,还可以选用其他的材料,本申请实施例对此不作限定。Specifically, in some embodiments, the template 7 may be made of a material that can withstand a certain high temperature and can be reused. In this way, the template can be maintained to have certain mechanical properties or performance during the sintering process, and can be reused many times, thereby reducing the cost. The specific material type of the template 7 can be various types, for example, the template 7 can be made of silicone resin, ceramics, stainless steel and other materials, and the prepared template 7 can withstand a certain high temperature, for example, can withstand a high temperature of about 250°C , and can be reused. In addition, the materials of the template 7 are not limited to the ones listed above, and other materials can also be selected, which are not limited in the embodiments of the present application.
在制作上述模板7时,可以利用各种成型或开孔方式,依据基板4上的焊盘阵列,形成带有通孔阵列的模板7。本申请实施例中,可以使通孔阵列与模板7一体成型,或者也可以先制作模板7,而后在该模板上进行开孔,以形成通孔阵列。本申请实施例对于形成通孔阵列的具体方式不作限定,示例性的,通孔阵列是采用机械穿孔、光刻工艺等中的任何一种形成的。When making the above-mentioned template 7 , various forming or drilling methods can be used to form the template 7 with an array of through holes according to the pad array on the substrate 4 . In the embodiment of the present application, the through-hole array and the template 7 may be integrally formed, or the template 7 may be fabricated first, and then holes are formed on the template to form the through-hole array. The embodiments of the present application do not limit the specific manner of forming the through-hole array. Exemplarily, the through-hole array is formed by using any one of mechanical perforation, photolithography, and the like.
具体地,在一些实施例中,上述模板7上的通孔阵列是与基板4上的焊盘阵列一一对应的,通孔8的开孔尺寸、间距、位置等,需要根据实际基板4上的焊盘阵列的排列方式、尺寸等而设定。Specifically, in some embodiments, the through-hole arrays on the template 7 are in one-to-one correspondence with the pad arrays on the substrate 4 , and the opening size, spacing, and position of the through-holes 8 need to be based on the actual substrate 4 . The arrangement, size, etc. of the pad array are set.
在具体设置时,通孔8的开口尺寸范围为10μm-1mm,进一步可以为50μm-1mm,进一步可以为100μm-0.9mm,进一步可以为200μm-0.8mm,典型但非限制性的,例如可以为10μm、20μm、40μm、50μm、80μm、100μm、150μm、200μm、300μm、400μm、500μm、600μm、700μm、800μm、900μm、1mm以及这些点值中的任意两个所构成的范围中的任意值。In the specific setting, the opening size of the through hole 8 is in the range of 10 μm-1 mm, further can be 50 μm-1 mm, further can be 100 μm-0.9 mm, and further can be 200 μm-0.8 mm, typical but non-limiting, for example, can be 10 μm, 20 μm, 40 μm, 50 μm, 80 μm, 100 μm, 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1 mm, and any value in the range of any two of these point values.
在具体设置时,相邻两个通孔8之间的间距范围为10μm-1mm,进一步可以为50μm-1mm,进一步可以为100μm-0.9mm,进一步可以为500μm-0.8mm,典型但非限制性的,例如可以为10μm、20μm、40μm、50μm、80μm、100μm、150μm、200μm、300μm、400μm、500μm、600μm、700μm、800μm、900μm、1mm以及这些点值中的任意两个所构成的范围中的任意值。In the specific setting, the distance between two adjacent through holes 8 ranges from 10 μm to 1 mm, further can be 50 μm-1 mm, further can be 100 μm-0.9 mm, and further can be 500 μm-0.8 mm, typical but non-limiting For example, it can be 10 μm, 20 μm, 40 μm, 50 μm, 80 μm, 100 μm, 150 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1 mm and any two of these point values. any value of .
需要说明的是,上述通孔8的开口尺寸,是根据通孔的横截面形状而确定或相适应的。例如,通孔8的截面形状可以是圆形、方形、椭圆形、多边形或其他规则/不规则形状等,相应的,所形成的导电柱9的截面形状可以是圆形、方形、椭圆形、多边形或其他规则/不规则形状等。当通孔8的截面形状为圆形时,上述通孔8的开口尺寸可以表示为该通孔的直径(圆形的直径);当通孔8的截面形状为椭圆形时,上述通孔8的开口尺寸可以表示为该椭圆形的长直径(长径),即该椭圆形中最长的两点间距离;当通孔8的截面形状为正方形时,上述通孔8的开口尺寸可以表示为正方形的边长等等,在此不再一一列举。It should be noted that, the opening size of the above-mentioned through hole 8 is determined or adapted according to the cross-sectional shape of the through hole. For example, the cross-sectional shape of the through hole 8 can be a circle, a square, an ellipse, a polygon or other regular/irregular shapes, etc. Correspondingly, the cross-sectional shape of the formed conductive column 9 can be a circle, a square, an ellipse, Polygons or other regular/irregular shapes, etc. When the cross-sectional shape of the through-hole 8 is circular, the opening size of the through-hole 8 can be expressed as the diameter of the through-hole (circle diameter); when the cross-sectional shape of the through-hole 8 is oval, the above-mentioned through-hole 8 The opening size of the ellipse can be expressed as the long diameter (long diameter) of the ellipse, that is, the distance between the longest two points in the ellipse; when the cross-sectional shape of the through hole 8 is a square, the opening size of the through hole 8 can be expressed as It is the side length of a square, etc., which will not be listed here.
上述通孔8的直径、相邻两个通孔8之间的间距是依据所需封装的基板4上的焊盘阵列设置的,在上述通孔8的直径、相邻两个通孔8之间的间距范围内,能够满足实际应用需求,适应性强,而且能够使相邻导电柱9之间具有一定的间距,能避免因接触导致的短路现象,保证各器件能够稳定的工作。还可以缓解现有的系统级封装方法无法实现高深宽比、小间距的导电柱阵列的问题。The diameter of the through hole 8 and the distance between two adjacent through holes 8 are set according to the pad array on the substrate 4 to be packaged. Within the range of the distance between them, it can meet practical application requirements, has strong adaptability, and can make a certain distance between adjacent conductive pillars 9, which can avoid short-circuit phenomenon caused by contact and ensure that each device can work stably. It can also alleviate the problem that the existing system-in-package method cannot realize the conductive pillar array with high aspect ratio and small pitch.
需要说明的是,如图5、图6所示,本申请实施例对于通孔8、导电柱的具体形状结构不作限定,其可以是圆形、方形、椭圆形、多边形等,还可以是其他的形状,在此不再一一详细描述,能够实现基板与外部的电、信号互连的任何形状结构的导电柱均落入本申请的保护范围。It should be noted that, as shown in FIG. 5 and FIG. 6 , the embodiments of the present application do not limit the specific shape and structure of the through hole 8 and the conductive column, which may be a circle, a square, an ellipse, a polygon, etc., or other The shape of the conductive column, which is not described in detail here, can realize the electrical and signal interconnection between the substrate and the outside. Any shape of the conductive column falls within the protection scope of the present application.
上述模板7的厚度可以根据实际双面SiP产品底面厚度而定。例如,在具体设置时,模板7的厚度范围为10μm-1mm,进一步可以为50μm-1mm,进一步可以为 100μm-0.9mm,进一步可以为500μm-0.8mm,典型但非限制性的,例如可以为10μm、20μm、40μm、50μm、60μm、70μm、80μm、100μm、150μm、200μm、300μm、400μm、500μm、600μm、700μm、800μm、900μm、1mm以及这些点值中的任意两个所构成的范围中的任意值。该模板7的厚度是指模板在竖直方向上的厚度,可以理解为模板的高度。The thickness of the template 7 can be determined according to the thickness of the bottom surface of the actual double-sided SiP product. For example, in specific settings, the thickness of the template 7 is in the range of 10 μm-1 mm, further may be 50 μm-1 mm, further may be 100 μm-0.9 mm, further may be 500 μm-0.8 mm, typical but non-limiting, for example, may be 10μm, 20μm, 40μm, 50μm, 60μm, 70μm, 80μm, 100μm, 150μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1mm and any two of these point values in the range any value. The thickness of the template 7 refers to the thickness of the template in the vertical direction, which can be understood as the height of the template.
应理解,上述模板7的厚度(高度)可以为通孔8的高度(通孔的深度)。本文中,“深宽比”是指通孔的深度与通孔的开口尺寸例如通孔的直径之间的比例。It should be understood that the thickness (height) of the above-mentioned template 7 may be the height (depth of the through hole) of the through hole 8 . Herein, "aspect ratio" refers to the ratio between the depth of the through hole and the opening size of the through hole, eg, the diameter of the through hole.
上述通孔8的直径与所形成的导电柱9的直径是相适应的,上述相邻两通孔8之间的间距与所形成的相邻两导电柱9之间的间距是相对应的。此外,通孔8的高度与所形成的导电柱9的高度与可以是相适应的,或者,在实际操作中,根据所填充的导电材料的情况或操作误差等,所形成的导电柱9的高度与通孔8的高度直径也可具有略微的差异。对于所形成的导电柱9的具体尺寸在此不再详细描述,可参照前述关于通孔的尺寸的描述。The diameter of the above-mentioned through holes 8 is compatible with the diameter of the formed conductive pillars 9 , and the spacing between the above-mentioned two adjacent through-holes 8 corresponds to the spacing between the formed two adjacent conductive pillars 9 . In addition, the height of the through hole 8 and the height of the formed conductive pillar 9 may be compatible, or, in actual operation, according to the condition of the filled conductive material or the operation error, etc., the formed conductive pillar 9 There may also be a slight difference between the height and the height diameter of the through hole 8 . The specific dimensions of the formed conductive pillars 9 will not be described in detail here, and reference may be made to the foregoing description on the dimensions of the through holes.
在具体设置时,通孔8的上下尺寸是可以相同的,也可以是不同的。例如,通孔8可以为各部分尺寸均相同的通孔结构。或者,通孔8可以为阶梯孔,该阶梯孔包括上部分孔结构和下部分孔结构,其中,上部分孔结构的直径大于下部分孔结构的直径,或上部分孔结构的直径小于下部分孔结构的直径。或者,通孔8可以为自上而下直径依次减少的孔结构,或为自上而下直径依次增大的孔结构。当然,在其他实施例中,通孔8的具体形状结构并不限于,其还可以具有其他的结构形状结构,在此不再详细描述。此外,通孔阵列中的各个通孔8的形状结构可以是相同的,也可以是不同的。例如,该通孔阵列可由圆形通孔组成,或者也可以由圆形通孔和椭圆形通孔组成。In specific settings, the upper and lower dimensions of the through holes 8 may be the same or different. For example, the through hole 8 may be a through hole structure with the same size of each part. Alternatively, the through hole 8 may be a stepped hole, and the stepped hole includes an upper part of the hole structure and a lower part of the hole structure, wherein the diameter of the upper part of the hole structure is larger than that of the lower part of the hole structure, or the diameter of the upper part of the hole structure is smaller than that of the lower part of the hole structure The diameter of the pore structure. Alternatively, the through hole 8 may be a hole structure whose diameter decreases sequentially from top to bottom, or a hole structure whose diameter increases sequentially from top to bottom. Of course, in other embodiments, the specific shape and structure of the through hole 8 is not limited, and it may also have other structure and shape structure, which will not be described in detail here. In addition, the shape and structure of each through hole 8 in the through hole array may be the same or different. For example, the through hole array may be composed of circular through holes, or may also be composed of circular through holes and oval through holes.
在具体设置时,依据基板上的焊盘阵列,该通孔阵列的具体形式也是可以具有多种类型的。例如,通孔阵列可以是单排、多排,或随机排列。如图5所示,在一些实施例中,通孔阵列可以是在基板的上下分别设置为两行、左右分别设置为一列,并围构形成环形结构的通孔阵列。In the specific setting, the specific form of the through-hole array can also have various types according to the pad array on the substrate. For example, the array of vias can be single-row, multi-row, or random. As shown in FIG. 5 , in some embodiments, the through-hole arrays may be arranged in two rows on the top and bottom of the substrate, and one column on the left and right, respectively, and form an annular structure of through-hole arrays.
如图6所示,在另一些实施例中,通孔阵列可以是在基板的上下分别设置为一行、左右分别设置为一列,并围构形成环形结构的通孔阵列。As shown in FIG. 6 , in other embodiments, the through hole arrays may be arranged in a row on the upper and lower sides of the substrate, and arranged in a column on the left and right, respectively, and form a ring-shaped through hole array.
如图7所示,在另一些实施例中,通孔阵列可以是在基板的上中下分别设置为一行、左中右分别设置为一列,并将模板划分为四部分的通孔阵列。As shown in FIG. 7 , in other embodiments, the through-hole array may be a through-hole array in which the upper, middle, and lower portions of the substrate are arranged in one row, and the left, middle, and right are arranged in a column, and the template is divided into four parts.
需要说明的是,通孔阵列的具体形式并不限于上述列举的几种结构形式,在满足封装基板或系统级封装结构需要的情况下,通孔阵列的具体形式还可以采用其他结构形式,本申请对此不作特殊限制。比如在一些实际情况中,系统级封装结构所包括的导电柱、焊盘数量可能大于一百个,因此附图所示的数量、排列方式仅供举例说明,并非限制本申请。It should be noted that the specific form of the through-hole array is not limited to the several structural forms listed above. In the case of meeting the needs of the packaging substrate or the system-level packaging structure, the specific form of the through-hole array can also adopt other structural forms. There is no special restriction on the application. For example, in some practical situations, the number of conductive pillars and pads included in the system-in-package structure may be more than one hundred, so the number and arrangement shown in the accompanying drawings are for illustration only, and do not limit the present application.
本申请实施例中,在上述通孔阵列内填充导电材料,经烧结后,可在基板的焊盘阵列上形成导电柱阵列。其中,导电材料可为金属材料和/或非金属材料,所形成的导电柱可以为金属柱、非金属柱或复合柱。In the embodiment of the present application, the conductive material is filled in the above-mentioned through-hole array, and after sintering, a conductive column array can be formed on the pad array of the substrate. Wherein, the conductive material may be a metal material and/or a non-metal material, and the formed conductive column may be a metal column, a non-metal column or a composite column.
具体地,在一些实施例中,导电材料包括金属材料、碳素材料或高分子材料中的一种或多种。也就是,该导电材料可以为金属材料,也可以为非金属材料,也可以为金属材料和非金属材料的混合材料,其中的非金属材料可以为碳素材料、高分子材料等。进一步,碳素材料可以为石墨、石墨烯、碳纳米管(CNT)、碳纤维等碳素材料。Specifically, in some embodiments, the conductive material includes one or more of metal materials, carbon materials, or polymer materials. That is, the conductive material may be a metal material, a non-metal material, or a mixed material of a metal material and a non-metal material, wherein the non-metal material may be a carbon material, a polymer material, or the like. Further, the carbon material may be graphite, graphene, carbon nanotube (CNT), carbon fiber and other carbon materials.
该导电材料的形态包括粉末或膏体。The form of the conductive material includes powder or paste.
进一步,该导电材料可以是金属粉末或含有金属粉末的膏体。Further, the conductive material may be metal powder or a paste containing metal powder.
可选的,该导电材料可以为铜粉、银粉、铝粉、焊锡膏例如SAC305焊锡膏、纳米铜膏、纳米银膏等。采用这几种导电材料,具有来源广泛,实用性强,容易烧结成导电柱,导电率较高,能够满足所需的导电、信号传输等需求。Optionally, the conductive material may be copper powder, silver powder, aluminum powder, solder paste such as SAC305 solder paste, nano-copper paste, nano-silver paste, and the like. The use of these conductive materials has a wide range of sources, strong practicability, easy sintering into conductive columns, and high conductivity, which can meet the required requirements for conduction and signal transmission.
可选的,该导电材料可以为碳素材料如石墨、石墨烯或碳纳米管,或者为碳素材料如石墨、石墨烯或碳纳米管与金属材料如铜粉、银粉等的混合材料,或者为高分子材料与金属材料的混合材料等。Optionally, the conductive material can be a carbon material such as graphite, graphene or carbon nanotubes, or a mixed material of carbonaceous materials such as graphite, graphene or carbon nanotubes and metal materials such as copper powder, silver powder, etc., or It is a mixed material of polymer material and metal material, etc.
具体地,在一些实施例中,导电柱为金属柱、非金属柱或由金属材料和非金属材料复合而成的复合柱。进一步,金属柱可以是焊锡柱、铜柱、银柱等,或者也可以为碳素材料柱,或者也可以为由碳素材料和金属材料复合而成的复合柱等。由此,通过该金属柱有助于实现双面SiP结构与外界的电、信号互连。Specifically, in some embodiments, the conductive pillars are metal pillars, non-metallic pillars, or composite pillars composed of metal materials and non-metallic materials. Further, the metal pillars may be solder pillars, copper pillars, silver pillars, etc., or may also be carbon material pillars, or may also be composite pillars formed by compounding carbon materials and metal materials. Therefore, the metal pillars help to realize the electrical and signal interconnection between the double-sided SiP structure and the outside world.
应理解,上述示例性的列出几种导电材料或导电柱的具体类型,然而,导电材料或导电柱的具体类型并不限于上述列举的几种,在满足双面SiP结构与外界的电、信号互连需要的情况下,导电材料或导电柱的具体类型的具体类型还可以采用其他形式,本申请实施例对此不作特殊限制。It should be understood that several specific types of conductive materials or conductive pillars are exemplarily listed above. However, the specific types of conductive materials or conductive pillars are not limited to the ones listed above. When required for signal interconnection, the specific type of the conductive material or the specific type of the conductive column may also adopt other forms, which are not particularly limited in this embodiment of the present application.
具体地,在一些实施例中,焊盘的材料也可以是具有多种类型的,例如,焊盘的材料包括铜、铝或钨,焊盘的表面可以喷锡、浸银或浸金等,本申请实施例对此也不作特殊限制。Specifically, in some embodiments, the material of the pad can also be of various types, for example, the material of the pad includes copper, aluminum or tungsten, and the surface of the pad can be sprayed with tin, immersion silver or immersion gold, etc. This embodiment of the present application also does not make any special restrictions on this.
将导电材料烧结以形成导电柱的具体烧结工艺参数,可以与双面SiP结构的背面电子元件的回流焊接工艺参数相同,此外,烧结工艺条件也需要根据具体的导电材料的类型进行调节。具体地,在一些实施例中,烧结的温度为100℃-280℃,进一步可以为150℃-280℃,进一步可以为160℃-260℃,进一步可以为180℃-240℃,典型但非限制的,例如可以为100℃、120℃、150℃、160℃、180℃、190℃、200℃、220℃、240℃、250℃、260℃、280℃以及这些点值中的任意两个所构成的范围中的任意值。The specific sintering process parameters for sintering the conductive material to form the conductive pillars can be the same as the reflow soldering process parameters of the backside electronic components of the double-sided SiP structure. In addition, the sintering process conditions also need to be adjusted according to the type of the specific conductive material. Specifically, in some embodiments, the sintering temperature is 100°C-280°C, further can be 150°C-280°C, further can be 160°C-260°C, further can be 180°C-240°C, typical but not limited For example, it can be 100°C, 120°C, 150°C, 160°C, 180°C, 190°C, 200°C, 220°C, 240°C, 250°C, 260°C, 280°C and any two of these point values. Any value in the range that constitutes.
上述导电材料可以采用现有的常用无铅焊料,因而,该烧结操作,可以在无铅焊料回流温度曲线下进行模板的通孔阵列内金属粉末或金属膏体的烧结,进而使通孔阵列内的金属粉末或金属膏体完成固化烧结。上述金属粉末或膏体的烧结温度与常用无铅焊料回流工艺温度兼容,因而,对于该烧结步骤的具体操作方法或操作条件不再详细描述,其均是本领域技术人员根据实际情况可以调控的。The above-mentioned conductive material can use the existing common lead-free solder. Therefore, in this sintering operation, the metal powder or metal paste in the through-hole array of the template can be sintered under the lead-free solder reflow temperature curve, and then the through-hole array can be sintered. The metal powder or metal paste is cured and sintered. The sintering temperature of the above-mentioned metal powder or paste is compatible with the temperature of the common lead-free solder reflow process. Therefore, the specific operation method or operation conditions of this sintering step will not be described in detail, which can be adjusted by those skilled in the art according to the actual situation. .
具体地,在一些实施例中,如图8所示,将导电材料填充于通孔内包括:先将模板设置于转移载板上,而后再将导电材料填充于通孔内。Specifically, in some embodiments, as shown in FIG. 8 , filling the conductive material in the through hole includes: firstly disposing the template on the transfer carrier, and then filling the conductive material in the through hole.
该模板上的通孔为贯穿模板的贯穿孔,因而,为了便于将导电材料填充于通孔内,需要在填充前先将模板固定到转移载板上,例如可以用胶带将模板预固定在转移载板上,而后将导电材料填充于通孔内,以利用转移载板起到一定的支撑和确保通孔内所填充的导电材料的量的作用。The through holes on the template are through holes passing through the template. Therefore, in order to facilitate the filling of the conductive material into the through holes, the template needs to be fixed on the transfer carrier before filling. Then, the conductive material is filled in the through hole, so as to use the transfer carrier plate to play a certain role of supporting and ensuring the amount of the conductive material filled in the through hole.
此外,在填充完毕后,可以将填充有导电材料的模板和转移载板一同转移到基板上,使模板的上表面(背离转移载板一侧的表面)倒转并与基板接触,并将模板上的通孔阵列与基板上的焊盘阵列进行对位,完成对位后可以将位于模板的下表面(靠近转移载板一侧的表面)的转移载板去除,然后进行烧结。In addition, after filling, the template filled with conductive material and the transfer carrier can be transferred to the substrate together, so that the upper surface of the template (the surface on the side away from the transfer carrier) is inverted and in contact with the substrate, and the template is placed on the substrate. The through hole array is aligned with the pad array on the substrate. After the alignment is completed, the transfer carrier located on the lower surface of the template (the surface close to the side of the transfer carrier) can be removed, and then sintered.
需要说明的是,该去除转移载板的操作顺序是可以调整的,其可以依据具体地封装方法的操作顺序而适应的调整。示例性的,在填充完毕后,还可以先对导电材料进行烧结,而后可以将导电柱的模板和转移载板一同转移到基板上,使模板的上表面倒转并与基板接触,并将模板上的通孔阵列与基板上的焊盘阵列进行对位,完成对位后再依次去除转移载板和模板。It should be noted that the operation sequence of removing the transfer carrier plate can be adjusted, which can be adapted according to the operation sequence of the specific packaging method. Exemplarily, after the filling is completed, the conductive material may be sintered first, and then the template of the conductive column and the transfer carrier may be transferred to the substrate together, so that the upper surface of the template is inverted and contacted with the substrate, and the template is placed on the substrate. The through-hole array is aligned with the pad array on the substrate, and after the alignment is completed, the transfer carrier and the template are removed in turn.
将导电材料填充于通孔内的具体实现方式也是可以具有多种方式的。例如,在一些实施例中,请继续参阅图8所示,可以采用印刷的方式,将导电材料填充于通孔内。印刷过程中,根据通孔的尺寸如直径和高度可能需要重复几次,保证通孔内填满或者填充一定量的金属粉末或膏体,然后可以将模板上表面清洗干净,以确保无金属粉末或膏体残留。此外,在其他实施例中,还可以采用其他的方式将导电材料填充于通孔内,在此不再详细描述。The specific implementation manner of filling the conductive material in the through hole can also have various manners. For example, in some embodiments, please continue to refer to FIG. 8 , the conductive material may be filled in the through holes by means of printing. During the printing process, it may need to be repeated several times according to the size of the through hole, such as diameter and height, to ensure that the through hole is filled or filled with a certain amount of metal powder or paste, and then the upper surface of the template can be cleaned to ensure that there is no metal powder. or paste residue. In addition, in other embodiments, the conductive material may also be filled in the through hole in other manners, which will not be described in detail here.
具体地,在一些实施例中,请继续参阅图8所示,在经烧结的导电材料形成导电柱,导电柱的一端与焊盘电连接之后,系统级封装结构的制作方法还包括:对带有导电柱的基板进行塑封,形成塑封层;将与导电柱相对应的部分塑封层去除,使导电柱露出。该塑封层与基板的结合牢靠,保证了封装的可靠性。Specifically, in some embodiments, please continue to refer to FIG. 8 , after the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad, the method for fabricating the system-in-package structure further includes: assembling the tape The substrate with the conductive posts is plastic-sealed to form a plastic-sealing layer; the part of the plastic-sealing layer corresponding to the conductive posts is removed to expose the conductive posts. The plastic encapsulation layer and the substrate are firmly combined, which ensures the reliability of the encapsulation.
可以理解,该方法中,经过烧结,在基板的焊盘阵列上形成导电柱阵列之后,本领域技术人员可以根据实际需求,采用适宜的塑封工艺技术和设备,完成上述塑封过程,以及可以采用适宜的方式使导电柱露出,本申请实施例对此不作限定。示例性的,在基板的焊盘阵列上形成导电柱阵列之后,可以对双面SiP进行塑封工艺,形成塑封层,塑封后通过平磨塑封层漏出导电柱阵列,然后可以在导电柱的端子上植球形成互连,然后对双面SiP完成后续的工序步骤,最终得到双面SiP结构。It can be understood that in this method, after sintering to form a conductive column array on the pad array of the substrate, those skilled in the art can use suitable plastic packaging technology and equipment to complete the above plastic packaging process according to actual needs. The conductive pillars are exposed in the manner of , which is not limited in this embodiment of the present application. Exemplarily, after the conductive column array is formed on the pad array of the substrate, a plastic sealing process can be performed on the double-sided SiP to form a plastic sealing layer. The balls are implanted to form interconnections, and then the subsequent process steps are completed for the double-sided SiP, and finally a double-sided SiP structure is obtained.
为了实现双面SiP结构与外界的互连,导电柱阵列需要露在塑封的外部。例如可以通过平磨塑封层、减薄工艺等使导电柱阵列露出。示例性的,上述塑封层的形成工艺可以为注塑工艺、转塑工艺或丝网印刷工艺等,当然,还可以为其他的形成工艺本申请实施例对此不作限定。In order to realize the interconnection between the double-sided SiP structure and the outside world, the conductive pillar array needs to be exposed outside the plastic package. For example, the conductive pillar array may be exposed by flat grinding the plastic encapsulation layer, thinning process, and the like. Exemplarily, the above-mentioned forming process of the plastic sealing layer may be an injection molding process, a transfer molding process or a screen printing process, etc. Of course, it may also be other forming processes, which are not limited in the embodiments of the present application.
可选的,在一些实施例中,请继续参阅图8所示,在将与导电柱相对应的部分塑封层去除,使导电柱露出之后,方法还包括:在导电柱上植球。也就是,通过植球的方式,在导电柱上形成焊球,该焊球可以位于导电柱的顶部,还可以位于导电柱的顶部和侧壁。此外,在其他实施例中,为适应不同的应用场景或满足不同的需求,也可以不进行植球步骤,即直接利用金属柱的另一端与外部电路进行 互连,实现双面SiP结构与外界的电、信号互连。Optionally, in some embodiments, please continue to refer to FIG. 8 , after removing part of the plastic encapsulation layer corresponding to the conductive posts to expose the conductive posts, the method further includes: planting balls on the conductive posts. That is, solder balls are formed on the conductive pillars by means of ball mounting, and the solder balls may be located on the top of the conductive pillars, and may also be located on the tops and sidewalls of the conductive pillars. In addition, in other embodiments, in order to adapt to different application scenarios or meet different requirements, the ball-mounting step may not be performed, that is, the other end of the metal column is directly connected to the external circuit to realize the double-sided SiP structure and the outside world. electrical and signal interconnection.
在一个具体地实施方案中,该系统级封装结构的制作方法,包括以下步骤:In a specific embodiment, the manufacturing method of the system-in-package structure includes the following steps:
使用硅树脂、陶瓷、不锈钢等材料制作可耐250℃高温且重复利用的模板,模板上设置有与双面SiP的基板背面焊盘阵列一一对应的通孔阵列。其中,通孔的开孔尺寸和间距等可以根据实际产品的焊盘阵列而设定,例如,通孔的开口尺寸可以为10μm-1mm范围的任意尺寸,相邻两通孔之间的间距可以为10μm-1mm范围的任意尺寸。通孔的形状可以为方孔、圆孔、椭圆孔等任何形状的孔。通孔的上下的尺寸可以相同或者不同,例如,通孔的上表面尺寸大于下表面尺寸,或者通孔的下表面尺寸大于上表面尺寸等。所制作的模板厚度(通孔深度)可以根据实际双面SiP产品厚度而定,例如模板厚度可以为10μm-1mm范围的任意尺寸。Silicone resin, ceramics, stainless steel and other materials are used to make a template that can withstand high temperature of 250°C and can be reused. The template is provided with an array of through holes corresponding to the array of pads on the backside of the double-sided SiP substrate. Among them, the opening size and spacing of the through holes can be set according to the pad array of the actual product. For example, the opening size of the through holes can be any size in the range of 10μm-1mm, and the spacing between two adjacent through holes can be Any size in the range of 10μm-1mm. The shape of the through hole can be a square hole, a circular hole, an oval hole and other holes of any shape. The upper and lower dimensions of the through hole may be the same or different, for example, the upper surface dimension of the through hole is larger than the lower surface dimension, or the lower surface dimension of the through hole is larger than the upper surface dimension and the like. The thickness of the template (through hole depth) can be determined according to the thickness of the actual double-sided SiP product. For example, the thickness of the template can be any size in the range of 10 μm to 1 mm.
然后,可以将模板用胶带预固定在转移载板上,再将金属粉末或含有金属粉末的膏体通过印刷的方式填充到模板的通孔阵列内,该金属粉末或膏体的烧结温度与常用无铅焊料回流工艺温度兼容,印刷过程中,根据通孔的直径和深度可能需要重复几次,以保证通孔孔内填满或者填充一定量的金属粉末的膏体,而后再将模板上表面(背离转移载板一侧的表面)清洗干净,以确保无金属粉末或膏体残留。Then, the template can be pre-fixed on the transfer carrier plate with tape, and then the metal powder or paste containing metal powder can be filled into the through hole array of the template by printing. The sintering temperature of the metal powder or paste is the same as that of common The lead-free solder reflow process temperature is compatible. During the printing process, it may be necessary to repeat several times according to the diameter and depth of the through hole to ensure that the through hole is filled or filled with a certain amount of metal powder paste, and then the upper surface of the template is (Surface on the side facing away from the transfer carrier) is cleaned to ensure that no metal powder or paste remains.
在填充完毕后,将模板和转移载板一同拿起,并将填充好导电材料的模板的上表面安装在双面SiP的基板上,并使模板的通孔阵列与基板上的焊盘阵列对位,完成对位后去掉转移载板。After filling, pick up the template and the transfer carrier together, mount the upper surface of the template filled with conductive material on the double-sided SiP substrate, and align the through-hole array of the template with the pad array on the substrate position, remove the transfer carrier after the alignment is completed.
对位放置好并去除转移载板之后,可以进行模板通孔内金属粉末或金属膏体的烧结,烧结工艺参数与双面SiP背面器件的回流焊接工艺参数相同,例如烧结温度可以在100℃-280℃范围,该烧结步骤完成后通孔内的导电材料已完成固化烧结。烧结工艺步骤可以在双面SiP背面器件表贴之前、之后或同时。After the alignment is placed and the transfer carrier is removed, the metal powder or metal paste in the template through hole can be sintered. The sintering process parameters are the same as the reflow soldering process parameters of the double-sided SiP backside device. For example, the sintering temperature can be 100℃- In the range of 280°C, after the sintering step is completed, the conductive material in the through hole has been cured and sintered. The sintering process step can be before, after or at the same time as the double-sided SiP backside device surface mount.
在烧结之后,可以将模板取下来即进行脱模,形成导电柱阵列,即使得导电柱的一端与焊盘电连接。然后,可以对双面SiP背面进行塑封工艺,塑封后通过平磨塑封层漏出导电柱阵列,在导电柱的另一端上植球形成互连,然后对双面SiP完成后续的工序步骤,最终得到双面SiP结构。After sintering, the template can be removed and demolded to form a conductive column array, that is, one end of the conductive column is electrically connected to the pad. Then, a plastic sealing process can be performed on the back of the double-sided SiP. After plastic sealing, the conductive column array is leaked through the flat grinding plastic sealing layer, and the ball is planted on the other end of the conductive column to form an interconnection, and then the subsequent process steps are completed for the double-sided SiP. Double-sided SiP structure.
从以上可知,本申请实施例的系统级封装结构的制作方法操作简单,易于实施,高效、可靠,成本低,易于实现大规模生产。并且,该方法能够解决现有的某些方法如TMV法无法实现高深宽比、小间距的导电柱阵列的问题,能够解决现有的电镀铜柱法的时间长、效率低等问题。It can be seen from the above that the manufacturing method of the system-level packaging structure of the embodiment of the present application is simple to operate, easy to implement, efficient, reliable, low in cost, and easy to realize large-scale production. In addition, the method can solve the problem that some existing methods such as TMV method cannot realize conductive column arrays with high aspect ratio and small spacing, and can solve the problems of long time and low efficiency of the existing copper electroplating method.
需要说明的是,本申请中,除非另有说明,各个操作步骤可以顺序进行,也可以不按照顺序进行。本申请实施例对于制备系统级封装结构的步骤顺序不作限定,可以根据实际生产工艺进行调整。例如,可以先将填充好导电材料的模板的转移到双面SiP的基板上(简称转移),而后进行烧结,再去除模板(简称脱模);或者,也可以先进行转移,再进行脱模,而后再进行烧结;或者,也可以先进行烧结,再进行转移,而后再进行脱模。It should be noted that, in the present application, unless otherwise specified, each operation step may be performed in sequence, or may not be performed in sequence. The embodiments of the present application do not limit the sequence of steps for preparing the system-in-package structure, which may be adjusted according to the actual production process. For example, the template filled with conductive material can be transferred to the substrate of double-sided SiP (referred to as transfer), and then sintered, and then the template can be removed (referred to as demolding); or, it can be transferred first, and then demolded , and then sintering; alternatively, sintering can be performed first, then transfer, and then demolding.
下面结合附图对几种不同的系统级封装结构的具体制作方法进行详细的说明。 以下以具体实施例说明本申请的效果和制作方法中各操作步骤的顺序不同,但本申请的保护范围不受以下实施例的限制。The specific fabrication methods of several different system-level packaging structures will be described in detail below with reference to the accompanying drawings. The effects of the present application and the order of the operation steps in the production method are described below with specific examples, but the protection scope of the present application is not limited by the following examples.
实施例1Example 1
图9显示了实施例1提供的系统级封装结构的制作方法流程示意图,如图9所示。FIG. 9 shows a schematic flowchart of the manufacturing method of the system-in-package structure provided in Embodiment 1, as shown in FIG. 9 .
S100、模板制作:使用硅树脂材料制作可耐250℃高温且重复利用的模板,模板上设置有与双面SiP的基板背面焊盘阵列一一对应的通孔阵列,该通孔阵列可以为上下分别设置为两行、左右分别设置为一列形式的通孔阵列。所制作的模板厚度可以为0.15mm或0.3mm,模板上通孔的直径可以为0.2mm,相邻两通孔之间的间距可以为0.4mm。S100. Template making: a silicon resin material is used to make a template that can withstand a high temperature of 250°C and can be reused. The template is provided with a through-hole array corresponding to the pad array on the backside of the double-sided SiP substrate. The through-hole array can be up and down. The through-hole arrays are respectively arranged in two rows and left and right are arranged in one column. The thickness of the prepared template may be 0.15mm or 0.3mm, the diameter of the through holes on the template may be 0.2mm, and the distance between two adjacent through holes may be 0.4mm.
S200、填充:将所制得的模板预固定在转移载板上,再将SAC305焊锡膏或纳米铜膏通过印刷的方式填充到模板的通孔阵列内,可以将通孔填满,再将模板上表面清洗干净。S200, filling: pre-fix the prepared template on the transfer carrier board, and then fill the SAC305 solder paste or nano-copper paste into the through-hole array of the template by printing to fill the through-holes, and then the template Clean the top surface.
S300、转移:在填充完毕后,将模板和转移载板一同取出,并将填充好导电材料的模板的上表面转移到双面SiP的基板上,并使模板的通孔阵列与基板上的焊盘阵列对位,完成对位后去掉转移载板。S300, transfer: after filling, take out the template and the transfer carrier together, transfer the upper surface of the template filled with conductive material to the double-sided SiP substrate, and make the through-hole array of the template and the solder on the substrate Align the disk array, and remove the transfer carrier after the alignment is complete.
S400、烧结:对位放置好并去除转移载板之后,可以在无铅焊料回流温度曲线下进行模板通孔内导电材料的烧结,例如烧结温度可以在150℃-280℃范围,该烧结步骤完成后通孔内的导电材料已完成固化烧结。S400, sintering: after the alignment is placed and the transfer carrier is removed, the conductive material in the template through hole can be sintered under the lead-free solder reflow temperature curve. For example, the sintering temperature can be in the range of 150°C-280°C, and the sintering step is completed. The conductive material in the rear via has been cured and sintered.
S500、脱模:在烧结之后,可以将模板取下来即进行脱模,在基板的焊盘阵列上形成导电柱阵列。所形成的导电柱阵列中各导电柱的直径为0.2mm,高度为0.15mm或0.285mm。S500, demoulding: after sintering, the template can be removed to perform demolding, and a conductive column array is formed on the pad array of the substrate. The diameter of each conductive column in the formed conductive column array is 0.2 mm, and the height is 0.15 mm or 0.285 mm.
S600、塑封等后处理:在脱模之后,可以对双面SiP进行塑封工艺,形成塑封层,塑封后通过平磨塑封层漏出导电柱阵列,然后经过后续的操作工序步骤,最终得到双面SiP结构。S600, plastic sealing and other post-processing: After demolding, the double-sided SiP can be plastic-sealed to form a plastic-sealing layer. After plastic-sealing, the conductive column array is leaked out through the flat-grinding plastic-sealing layer. structure.
本申请实施例1制得的双面系统级封装结构如图10所示。The double-sided system-in-package structure prepared in Example 1 of the present application is shown in FIG. 10 .
对比例1Comparative Example 1
利用现有的任意一种TMV法,进行双面系统级封装结构的制备。Using any existing TMV method, the double-sided system-in-package structure is prepared.
对比例1制得的双面系统级封装结构如图11所示。图11(a)中,双面系统级封装结构2中的导电柱9为凸台结构,图11(b)中,双面系统级封装结构2中的导电柱9为鼓形结构。The double-sided system-in-package structure prepared in Comparative Example 1 is shown in FIG. 11 . In FIG. 11( a ), the conductive pillars 9 in the double-sided system-in-package structure 2 are boss structures, and in FIG. 11( b ), the conductive pillars 9 in the double-sided system-in-package structure 2 are drum-shaped structures.
对比例2Comparative Example 2
利用现有的任意一种电镀导电柱法如电镀金属柱法,或者SMT金属柱法,进行双面系统级封装结构的制备。Using any of the existing electroplating conductive pillar methods, such as electroplating metal pillar method, or SMT metal pillar method, the preparation of the double-sided system level packaging structure is carried out.
对比例2制得的双面系统级封装结构如图12所示。图12中,双面系统级封装结构2中的导电柱9为圆柱形结构。The double-sided system-in-package structure prepared in Comparative Example 2 is shown in FIG. 12 . In FIG. 12 , the conductive pillars 9 in the double-sided system-in-package structure 2 are cylindrical structures.
本申请实施例1提供的系统级封装结构的制作方法,包括S100模板制作、S200填充、S300转移、S400烧结、S500脱模、S600塑封等后处理。该实施例1通过模板法,对纳米铜膏或焊锡膏进行烧结制作的双面系统级封装结构如下图10所示。在 无铅焊料回流温度条件下烧结的导电柱9的形貌为垂直度为90°,该导电柱9可以为规整的圆柱状,该导电柱9的内部组织不致密,即导电柱9的内部组织致密度一般会小于100%,例如该致密度为60%-95%或70%-90%。The method for fabricating the system-level packaging structure provided in Embodiment 1 of the present application includes post-processing such as S100 template fabrication, S200 filling, S300 transfer, S400 sintering, S500 demoulding, and S600 plastic sealing. In Example 1, a double-sided system-level package structure fabricated by sintering nano-copper paste or solder paste by a template method is shown in FIG. 10 below. The morphology of the conductive column 9 sintered under the reflow temperature of lead-free solder is 90° in verticality, the conductive column 9 can be a regular cylindrical shape, and the internal structure of the conductive column 9 is not dense, that is, the inner structure of the conductive column 9 is not dense. The tissue density will generally be less than 100%, eg the density is 60%-95% or 70%-90%.
如图11(a)和图11(b)所示,对比例1利用现有的TMV法制得的双面系统级封装结构2,其中的导电9柱一般呈上下开口不一致的凸台状或呈鼓形结构,这样,在相邻导电柱9之间的间距较小的情况下,容易使两导电柱相连,容易导致短路现象的发生,影响信号的传输。如图12所示,对比例2利用现有的电镀导电柱或SMT导电柱法制得的双面系统级封装结构2,可以制得呈圆柱状的导电柱9,但是其所得到的导电柱9内部组织结构致密,一般该导电柱9的致密度为100%,会增加成本,而且操作时间长,效率低。As shown in Fig. 11(a) and Fig. 11(b), in Comparative Example 1, the double-sided system-in-package structure 2 prepared by the existing TMV method, the conductive 9-pillars are generally in the shape of bosses with inconsistent upper and lower openings or in the shape of a double-sided system-in-package structure 2. Drum-shaped structure, in this way, when the distance between adjacent conductive columns 9 is small, it is easy to connect the two conductive columns, which easily leads to the occurrence of short circuit and affects the transmission of signals. As shown in FIG. 12 , in Comparative Example 2, the double-sided system-in-package structure 2 prepared by the existing electroplating conductive pillar or SMT conductive pillar method can produce a cylindrical conductive pillar 9 , but the obtained conductive pillar 9 The internal structure is dense, and generally the density of the conductive column 9 is 100%, which will increase the cost, and the operation time is long and the efficiency is low.
由此可知,本申请实施例提供的系统级封装结构的制作方法,通过模板法在双面SiP基板上直接制作导电柱阵列,工艺步骤少,导电柱成型工艺与回流工艺兼容,所制得的导电柱阵列稳定、可靠,成本低,效率高,适于高深宽比、小间距的导电柱阵列的制备。从而,能够缓解现有的TMV方案的激光打孔高成本且无法能实现高深宽比、小间距的导电柱阵列的制备问题,或能够缓解现有的金属柱电镀工艺耗时长、成本高的问题。It can be seen from this that the method for fabricating the system-level packaging structure provided by the embodiment of the present application directly fabricates the conductive column array on the double-sided SiP substrate by the template method, with few process steps, and the conductive column forming process is compatible with the reflow process. The conductive column array is stable and reliable, has low cost and high efficiency, and is suitable for the preparation of conductive column arrays with high aspect ratio and small spacing. Therefore, it is possible to alleviate the high cost of laser drilling in the existing TMV solution and the inability to realize the preparation of conductive column arrays with high aspect ratio and small spacing, or can alleviate the problems of the existing metal column electroplating process taking a long time and high cost .
实施例2Example 2
图13显示了实施例2提供的系统级封装结构的制作方法流程示意图,如图13所示。FIG. 13 shows a schematic flowchart of the manufacturing method of the system-in-package structure provided in Embodiment 2, as shown in FIG. 13 .
S100、模板制作:使用硅树脂材料制作可耐250℃高温且重复利用的模板,模板上设置有与双面SiP的基板背面焊盘阵列一一对应的通孔阵列,该通孔阵列可以为上下分别设置为两行、左右分别设置为一列形式的通孔阵列。所制作的模板厚度可以为0.4mm或0.5mm,模板上通孔的直径可以为0.3mm,相邻两通孔之间的间距可以为0.2mm。S100. Template making: a silicon resin material is used to make a template that can withstand a high temperature of 250°C and can be reused. The template is provided with a through-hole array corresponding to the pad array on the backside of the double-sided SiP substrate. The through-hole array can be up and down. The through-hole arrays are respectively arranged in two rows and left and right are arranged in one column. The thickness of the prepared template may be 0.4 mm or 0.5 mm, the diameter of the through holes on the template may be 0.3 mm, and the distance between two adjacent through holes may be 0.2 mm.
S200、填充:将所制得的模板预固定在转移载板上,再将纳米银膏或纳米铜膏通过印刷的方式填充到模板的通孔阵列内,可以将通孔填满,再将模板上表面清洗干净。S200, filling: pre-fix the prepared template on the transfer carrier, and then fill the nano-silver paste or nano-copper paste into the through-hole array of the template by printing, the through-holes can be filled, and then the template is filled Clean the top surface.
S300、烧结:在填充完毕后,可以在无铅焊料回流温度曲线下进行模板通孔内导电材料的烧结,例如烧结温度可以在150℃-280℃范围,该烧结步骤完成后通孔内的导电材料已完成固化烧结。S300. Sintering: After filling, the conductive material in the template through hole can be sintered under the lead-free solder reflow temperature curve. For example, the sintering temperature can be in the range of 150℃-280℃. After the sintering step is completed, the conductive material in the through hole can be sintered The material has been cured and sintered.
S400、转移:在烧结之后,将带有导电柱阵列的模板转移到双面SiP的基板上,并使模板的通孔阵列与基板上的焊盘阵列对位,使得所形成的导电柱阵列中的每一导电柱与焊盘阵列中的每一焊盘对应地电连接。S400, transfer: after sintering, transfer the template with the conductive column array to the double-sided SiP substrate, and align the through hole array of the template with the pad array on the substrate, so that the formed conductive column array Each of the conductive pillars is correspondingly electrically connected to each pad in the pad array.
S500、脱模:在转移之后,可以将模板取下来,即进行脱模。在基板的焊盘阵列上所形成的导电柱阵列中各导电柱的直径为0.3mm,高度为0.4mm或0.5mm。S500, demoulding: after the transfer, the template can be removed, that is, demoulding. In the conductive column array formed on the pad array of the substrate, each conductive column has a diameter of 0.3 mm and a height of 0.4 mm or 0.5 mm.
S600、塑封等后处理:在脱模之后,可以对双面SiP进行塑封工艺,形成塑封层,塑封后通过平磨塑封层漏出导电柱阵列,然后经过后续的操作工序步骤,最终得到双面SiP结构。S600, plastic sealing and other post-processing: After demolding, the double-sided SiP can be plastic-sealed to form a plastic-sealing layer. After plastic-sealing, the conductive column array is leaked out through the flat-grinding plastic-sealing layer. structure.
本申请实施例2提供的系统级封装结构的制作方法,包括S100模板制作、S200填充、S300烧结、S400转移、S500脱模、S600塑封等后处理。实施例2与实施例1的主要区别在于,在制作过程中,实施例2先进行烧结制作导电柱阵列,而后再将带有该导电柱阵列的模板转移到基板上;而实施例1先将填充有导电材料的模板转移到基板上,而后再进行烧结制作导电柱阵列。The method for fabricating a system-level package structure provided in Embodiment 2 of the present application includes post-processing such as S100 template fabrication, S200 filling, S300 sintering, S400 transfer, S500 demoulding, and S600 plastic sealing. The main difference between Example 2 and Example 1 is that, in the manufacturing process, Example 2 first sinters the conductive column array, and then transfers the template with the conductive column array to the substrate; The template filled with conductive material is transferred to the substrate, and then sintered to produce the array of conductive pillars.
实施例2所制得的双面系统级封装结构也可以如图10所示。相比于对比例1和对比例2,实施例2也能达到与实施例1相同或类似的效果,在此不再赘述。The double-sided system-in-package structure prepared in Example 2 can also be shown in FIG. 10 . Compared with Comparative Example 1 and Comparative Example 2, Example 2 can also achieve the same or similar effects as Example 1, which will not be repeated here.
实施例3Example 3
图14显示了实施例3提供的系统级封装结构的制作方法流程示意图,如图14所示。FIG. 14 shows a schematic flowchart of the manufacturing method of the system-in-package structure provided in Embodiment 3, as shown in FIG. 14 .
S100、模板制作:使用不锈钢等材料制作可耐250℃高温且重复利用的模板,模板上设置有与双面SiP的基板背面焊盘阵列一一对应的通孔阵列,该通孔阵列可以为上下分别设置为两行或三行、左右分别设置为一列或两列形式的通孔阵列。所制作的模板厚度可以为0.6mm,模板上通孔的直径可以为0.4mm,相邻两通孔之间的间距可以为0.15mm。S100. Template production: use stainless steel and other materials to make a template that can withstand high temperature of 250 ° C and can be reused. The template is provided with a through-hole array corresponding to the pad array on the back of the double-sided SiP substrate. The through-hole array can be up and down. The through-hole arrays are arranged in two or three rows respectively, and in the form of one or two columns on the left and right. The thickness of the prepared template may be 0.6 mm, the diameter of the through holes on the template may be 0.4 mm, and the distance between two adjacent through holes may be 0.15 mm.
S200、填充:将所制得的模板预固定在转移载板上,再将焊锡膏或纳米银膏或纳米铜膏通过印刷的方式填充到模板的通孔阵列内,可以将通孔填满,再将模板上表面清洗干净。S200. Filling: pre-fix the prepared template on the transfer carrier, and then fill the solder paste or nano-silver paste or nano-copper paste into the through-hole array of the template by printing, so that the through-holes can be filled. Then clean the upper surface of the template.
S300、转移:在填充完毕后,将填充有导电材料的模板转移到双面SiP的基板上,并使模板的通孔阵列与基板上的焊盘阵列对位,在对位放置好之后可以去除转移载板。S300, transfer: after filling, transfer the template filled with conductive material to the double-sided SiP substrate, and align the through-hole array of the template with the pad array on the substrate, which can be removed after the alignment is placed Transfer the carrier plate.
S400、脱模:在转移之后,可以将模板取下来,即进行脱模。S400, demoulding: after the transfer, the template can be removed, that is, demoulding.
S500、烧结:在脱模之后,可以在无铅焊料回流温度曲线下进行导电材料的烧结,例如烧结温度可以在150℃-280℃范围,该烧结步骤完成后导电材料已完成固化烧结。在基板的焊盘阵列上形成的导电柱阵列,各导电柱的直径为0.4mm,高度为0.6mm。S500, sintering: after demolding, the conductive material can be sintered under the lead-free solder reflow temperature curve, for example, the sintering temperature can be in the range of 150°C-280°C, and the conductive material has been cured and sintered after the sintering step is completed. In the conductive column array formed on the pad array of the substrate, each conductive column has a diameter of 0.4 mm and a height of 0.6 mm.
S600、塑封等后处理:在烧结之后,可以对双面SiP进行塑封工艺,形成塑封层,塑封后通过平磨塑封层漏出导电柱阵列,然后经过后续的操作工序步骤,最终得到双面SiP结构。S600, plastic sealing and other post-processing: After sintering, the double-sided SiP can be plastic-sealed to form a plastic-sealing layer. After plastic-sealing, the conductive column array is leaked out through the flat-grinding plastic-sealing layer, and then the double-sided SiP structure is finally obtained through subsequent operation steps. .
本申请实施例3提供的系统级封装结构的制作方法,包括S100模板制作、S200填充、S300转移、S400脱模、S500烧结、S600塑封等后处理。实施例3与实施例1的主要区别在于,在制作过程中,实施例3先将填充有导电材料的模板转移到基板上,然后进行脱模,即在基板上预置导电柱阵列,然后再进行烧结制作导电柱阵列;而实施例1先将填充有导电材料的模板转移到基板上,再进行烧结制作导电柱阵列,而后再进行脱模。The method for fabricating a system-level package structure provided in Embodiment 3 of the present application includes S100 template fabrication, S200 filling, S300 transfer, S400 demoulding, S500 sintering, S600 plastic sealing and other post-processing. The main difference between Example 3 and Example 1 is that, in the manufacturing process, Example 3 first transfers the template filled with conductive material to the substrate, and then demolds it, that is, pre-sets the conductive column array on the substrate, and then Conducting sintering to fabricate a conductive column array; while in Example 1, a template filled with conductive materials was first transferred to a substrate, then sintered to fabricate a conductive column array, and then demolded.
相比于对比例1和对比例2,实施例3也能达到与实施例1相同或类似的效果,在此不再赘述。Compared with Comparative Example 1 and Comparative Example 2, Example 3 can also achieve the same or similar effects as Example 1, which will not be repeated here.
实施例4Example 4
本实施例4提供的系统级封装结构的制作方法的制作流程,可以为上述实施例1-3中任一实施例所提供的制作流程,区别在于:The manufacturing process of the method for manufacturing a system-level packaging structure provided in this Embodiment 4 may be the manufacturing process provided by any of the foregoing Embodiments 1-3, and the difference is:
实施例4中的基板的上表面(正面)和下表面(背面)均设置有焊盘阵列,在基板的上表面焊盘阵列上形成有导电柱阵列,在基板的下表面焊盘阵列上形成有导电柱阵列。并且,在导电柱上形成有焊球,可以采用植球工艺在导电柱上形成焊球。通过焊球可以实现双面系统级封装结构与外界或其余封装结构的电、信号互连。In Example 4, both the upper surface (front side) and the lower surface (back side) of the substrate are provided with pad arrays, a conductive column array is formed on the pad array on the upper surface of the substrate, and a pad array is formed on the lower surface pad array of the substrate There are arrays of conductive pillars. In addition, solder balls are formed on the conductive pillars, and the solder balls can be formed on the conductive pillars by a ball-mounting process. The electrical and signal interconnection between the double-sided system-in-package structure and the outside world or other package structures can be realized through solder balls.
本申请实施例4制得的双面系统级封装结构如图15所示。其中,双面系统级封装结构可以为第一封装体11,第一封装体11与第二封装体12沿竖直方向层叠,第一封装体11的上表面与第二封装体12的下表面相对,第一封装体11的上表面和下表面均可以设置有一个或多个电子元件5,第二封装体12可以设置有一个或多个电子元件5。该第一封装体11的基板上表面焊盘阵列上形成有导电柱阵列,导电柱阵列中的导电柱9上形成有焊球10,该焊球10位于第一封装体11的上表面与第二封装体12的下表面之间,且焊球10的两端分别与导电柱9和第二封装体12的下表面连接,由此,通过该导电柱阵列和焊球10的设置,实现了第一封装体11与第二封装体12之间的信号传输。The double-sided system-in-package structure prepared in Example 4 of the present application is shown in FIG. 15 . The double-sided system-in-package structure may be a first package body 11 , the first package body 11 and the second package body 12 are stacked in a vertical direction, the upper surface of the first package body 11 and the lower surface of the second package body 12 In contrast, one or more electronic components 5 may be provided on both the upper surface and the lower surface of the first package body 11 , and one or more electronic components 5 may be provided on the second package body 12 . A conductive pillar array is formed on the pad array on the upper surface of the substrate of the first package body 11 , and solder balls 10 are formed on the conductive pillars 9 in the conductive pillar array. The solder balls 10 are located on the upper surface of the first package body 11 and the second Between the lower surfaces of the two packages 12, and the two ends of the solder balls 10 are respectively connected to the conductive pillars 9 and the lower surfaces of the second package 12, thus, through the arrangement of the conductive pillar array and the solder balls 10, the Signal transmission between the first package body 11 and the second package body 12 .
此外,该第一封装体11中的基板4下表面焊盘阵列上形成有导电柱阵列,导电柱阵列中的导电柱9上形成有焊球10,通过该导电柱阵列和焊球10的设置,也可以实现第一封装体11与其他封装体之间的信号传输。In addition, a conductive column array is formed on the pad array on the lower surface of the substrate 4 in the first package body 11 , and solder balls 10 are formed on the conductive column 9 in the conductive column array. Through the arrangement of the conductive column array and the solder balls 10 , the signal transmission between the first package 11 and other packages can also be realized.
需要说明的是,本文中使用的术语“和/或”或者“/”仅仅是一种描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B这三种情况。It should be noted that the term "and/or" or "/" used in this document is only an association relationship to describe associated objects, indicating that there can be three kinds of relationships, for example, A and/or B, which can mean that: exist independently A, there are both A and B, and there are three cases of B alone.
本申请中使用的“第一”“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。As used in this application, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
在本申请的描述中,需要理解的是,术语“上”、“下”等指示的方位或位置关系,仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。还需要理解的是,当诸如层、基体之类的元件被称作位于另一个元件“上”或者“下”时,其不仅能够直接连接在另一个元件“上”或者“下”,也可以通过中间元件间接连接在另一个元件“上”或者“下”。In the description of this application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is only used to represent the relative positional relationship. When the absolute position of the object to be described changes, the relative position Relationships may also change accordingly. It will also be understood that when an element such as a layer or a substrate is referred to as being "on" or "under" another element, it can not only be directly connected "on" or "under" the other element, but also Indirectly connected "on" or "under" another element through intervening elements.
需要指出的是,本专利申请文件的一部分包含受著作权保护的内容。除了对专利局的专利文件或记录的专利文档内容制作副本以外,著作权人保留著作权。It should be noted that a part of this patent application file contains content protected by copyright. Except for making copies of the patent files of the Patent Office or the contents of the recorded patent files, the copyright owner reserves the right to copyright.

Claims (24)

  1. 一种系统级封装结构的制作方法,其特征在于,包括以下步骤:A method for manufacturing a system-level packaging structure, comprising the following steps:
    提供模板,所述模板开设有通孔;A template is provided, and the template is provided with through holes;
    将导电材料填充于所述通孔内;filling the conductive material in the through hole;
    提供基板,所述基板设置有焊盘;providing a substrate, the substrate is provided with pads;
    经烧结的所述导电材料形成导电柱,所述导电柱的一端与所述焊盘电连接。The sintered conductive material forms a conductive pillar, and one end of the conductive pillar is electrically connected to the pad.
  2. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,经烧结的所述导电材料形成导电柱,所述导电柱的一端与所述焊盘电连接包括:The method for fabricating a system-in-package structure according to claim 1, wherein the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad comprising:
    将填充有所述导电材料的所述模板转移到所述基板上,使所述通孔与所述焊盘相对应;transferring the template filled with the conductive material onto the substrate so that the through holes correspond to the pads;
    然后进行烧结,使所述导电材料形成所述导电柱,所述导电柱的一端与所述焊盘电连接;and then sintering, so that the conductive material forms the conductive column, and one end of the conductive column is electrically connected to the pad;
    去除所述模板。Remove the template.
  3. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,经烧结的所述导电材料形成导电柱,所述导电柱的一端与所述焊盘电连接包括:The method for fabricating a system-in-package structure according to claim 1, wherein the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad comprising:
    将填充有所述导电材料的所述模板进行烧结,使所述导电材料形成所述导电柱;sintering the template filled with the conductive material, so that the conductive material forms the conductive pillar;
    将带有所述导电柱的所述模板转移到所述基板上,使所述通孔与所述焊盘相对应,并使所述导电柱的一端与所述焊盘电连接;transferring the template with the conductive pillars to the substrate, so that the through holes correspond to the pads, and one end of the conductive pillars is electrically connected to the pads;
    去除所述模板。Remove the template.
  4. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,经烧结的所述导电材料形成导电柱,所述导电柱的一端与所述焊盘电连接包括:The method for fabricating a system-in-package structure according to claim 1, wherein the sintered conductive material forms a conductive column, and one end of the conductive column is electrically connected to the pad comprising:
    将填充有所述导电材料的所述模板转移到所述基板上,使所述通孔与所述焊盘相对应;transferring the template filled with the conductive material onto the substrate so that the through holes correspond to the pads;
    去除所述模板;remove the template;
    然后进行烧结,使所述导电材料形成所述导电柱,所述导电柱的一端与所述焊盘电连接。Then, sintering is performed so that the conductive material forms the conductive pillar, and one end of the conductive pillar is electrically connected to the pad.
  5. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,将导电材料填充于所述通孔内包括:The method for fabricating a system-in-package structure according to claim 1, wherein filling the conductive material in the through hole comprises:
    先将所述模板设置于转移载板上,而后再将所述导电材料填充于所述通孔内。The template is set on the transfer carrier first, and then the conductive material is filled in the through holes.
  6. 根据权利要求5所述的系统级封装结构的制作方法,其特征在于,采用印刷的方式,将所述导电材料填充于所述通孔内。The method for fabricating a system-in-package structure according to claim 5, wherein the conductive material is filled in the through hole by means of printing.
  7. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述焊盘包括多个焊盘,所述多个焊盘形成焊盘阵列,所述通孔包括多个通孔,所述多个通孔形成通孔阵列,所述导电柱包括多个导电柱,所述多个导电柱形成导电柱阵列;The method for fabricating a system-in-package structure according to claim 1, wherein the pad comprises a plurality of pads, the plurality of pads form a pad array, and the through hole comprises a plurality of through holes, The plurality of through holes form a through hole array, the conductive pillars include a plurality of conductive pillars, and the plurality of conductive pillars form a conductive pillar array;
    所述通孔阵列与所述焊盘阵列相对应配置,以使所形成的所述导电柱阵列与所述焊盘阵列相对应电连接。The through hole array is configured corresponding to the pad array, so that the formed conductive pillar array is electrically connected to the pad array correspondingly.
  8. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述基板包括相对设置的第一表面和第二表面;The method for fabricating a system-in-package structure according to claim 1, wherein the substrate comprises a first surface and a second surface disposed opposite to each other;
    在所述基板的所述第一表面安装有一个或多个电子元件,在所述基板的所述第二表面安装有一个或多个电子元件;One or more electronic components are mounted on the first surface of the substrate, and one or more electronic components are mounted on the second surface of the substrate;
    在所述基板的所述第一表面和/或所述第二表面设置有所述焊盘。The pads are provided on the first surface and/or the second surface of the substrate.
  9. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述导电柱包括金属柱、非金属柱或由金属材料和非金属材料复合而成的复合柱。The method for fabricating a system-in-package structure according to claim 1, wherein the conductive pillars comprise metal pillars, non-metallic pillars, or composite pillars composed of metal materials and non-metallic materials.
  10. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述导电材料包括金属材料、碳素材料或高分子材料中的一种或多种;The method for fabricating a system-in-package structure according to claim 1, wherein the conductive material comprises one or more of a metal material, a carbon material or a polymer material;
    所述导电材料的形态包括粉末或膏体。The form of the conductive material includes powder or paste.
  11. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述通孔的开口尺寸范围为10μm-1mm;The method for fabricating a system-in-package structure according to claim 1, wherein the size of the opening of the through hole ranges from 10 μm to 1 mm;
    所述通孔包括多个通孔,相邻两个所述通孔之间的间距范围为10μm-1mm。The through holes include a plurality of through holes, and the distance between two adjacent through holes ranges from 10 μm to 1 mm.
  12. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述模板的厚度范围为10μm-1mm。The method for fabricating a system-in-package structure according to claim 1, wherein the thickness of the template ranges from 10 μm to 1 mm.
  13. 根据权利要求1所述的系统级封装结构的制作方法,其特征在于,所述烧结的温度为100℃-280℃。The method for fabricating a system-in-package structure according to claim 1, wherein the sintering temperature is 100°C-280°C.
  14. 根据权利要求1-13任一项所述的系统级封装结构的制作方法,其特征在于,在所述经烧结的所述导电材料形成导电柱,所述导电柱的一端与所述焊盘电连接之后,所述方法还包括:对带有所述导电柱的所述基板进行塑封,形成塑封层;The method for fabricating a system-in-package structure according to any one of claims 1-13, wherein a conductive column is formed on the sintered conductive material, and one end of the conductive column is electrically connected to the pad. After the connection, the method further includes: plastic-sealing the substrate with the conductive posts to form a plastic-sealing layer;
    将与所述导电柱相对应的部分所述塑封层去除,使所述导电柱露出。Parts of the plastic encapsulation layer corresponding to the conductive pillars are removed to expose the conductive pillars.
  15. 根据权利要求14所述的系统级封装结构的制作方法,其特征在于,在所述将与所述导电柱相对应的部分所述塑封层去除,使所述导电柱露出之后,所述方法还包括:在所述导电柱上植球。The method for fabricating a system-in-package structure according to claim 14, wherein after removing the part of the plastic encapsulation layer corresponding to the conductive pillars to expose the conductive pillars, the method further comprises: Including: planting balls on the conductive posts.
  16. 一种系统级封装结构,其特征在于,包括:A system-in-package structure, comprising:
    基板,所述基板设置有焊盘;a substrate, the substrate is provided with a pad;
    导电柱,所述导电柱的一端与焊盘电连接,所述导电柱的另一端用于与外部电路电连接;a conductive column, one end of the conductive column is electrically connected to the pad, and the other end of the conductive column is used for electrical connection with an external circuit;
    其中,所述导电柱经由对导电材料烧结而形成,所述导电材料填充于模板的通孔内,所述模板的所述通孔与所述焊盘相对应布置。Wherein, the conductive pillars are formed by sintering a conductive material, and the conductive material is filled in the through holes of the template, and the through holes of the template are arranged corresponding to the pads.
  17. 根据权利要求16所述的系统级封装结构,其特征在于,所述基板包括相对设置的第一表面和第二表面;The system-in-package structure of claim 16, wherein the substrate comprises a first surface and a second surface disposed opposite to each other;
    所述第一表面安装有一个或多个电子元件,所述第二表面安装有一个或多个电子元件;one or more electronic components are mounted on the first surface, and one or more electronic components are mounted on the second surface;
    所述第一表面和/或所述第二表面设置有所述焊盘。The first surface and/or the second surface are provided with the pads.
  18. 根据权利要求16所述的系统级封装结构,其特征在于,所述焊盘包括多个焊盘,所述多个焊盘形成焊盘阵列,所述导电柱包括多个导电柱,所述多个导电柱形成导电柱阵列;The system-in-package structure of claim 16, wherein the pads comprise a plurality of pads, the plurality of pads form an array of pads, the conductive pillars comprise a plurality of conductive pillars, the plurality of bonding pads a conductive column array is formed;
    所述导电柱阵列与所述焊盘阵列相对应电连接。The conductive column array is electrically connected to the pad array correspondingly.
  19. 根据权利要求16所述的系统级封装结构,其特征在于,所述导电柱包括金属柱、非金属柱或由金属材料和非金属材料复合而成的复合柱。The system-in-package structure according to claim 16, wherein the conductive pillars comprise metal pillars, non-metallic pillars or composite pillars composed of metal materials and non-metallic materials.
  20. 根据权利要求16所述的系统级封装结构,其特征在于,所述导电柱的直径范围为10μm-1mm;The system-in-package structure according to claim 16, wherein the diameter of the conductive pillars ranges from 10 μm to 1 mm;
    所述导电柱包括多个导电柱,相邻两个所述导电柱之间的间距范围为10μm-1mm。The conductive pillars include a plurality of conductive pillars, and the distance between two adjacent conductive pillars ranges from 10 μm to 1 mm.
  21. 根据权利要求16所述的系统级封装结构,其特征在于,所述导电柱的高度范围为10μm-1mm。The system-in-package structure according to claim 16, wherein the height of the conductive pillars ranges from 10 μm to 1 mm.
  22. 根据权利要求16-21任一项所述的系统级封装结构,其特征在于,所述系统级封装结构还包括包封在所述基板外部的塑封层,所述导电柱露在所述塑封层的外部。The system-in-package structure according to any one of claims 16-21, wherein the system-in-package structure further comprises a plastic sealing layer encapsulated outside the substrate, and the conductive pillars are exposed on the plastic sealing layer the exterior.
  23. 根据权利要求16-21任一项所述的系统级封装结构,其特征在于,所述系统级封装结构还包括设置在所述导电柱上的焊球。The system-in-package structure according to any one of claims 16-21, wherein the system-in-package structure further comprises solder balls disposed on the conductive pillars.
  24. 一种电子设备,其特征在于,包括由权利要求1-15任一项所述的制作方法制作而成的系统级封装结构或权利要求16-23任一项所述的系统级封装结构。An electronic device, characterized in that it comprises a system-in-package structure fabricated by the fabrication method according to any one of claims 1-15 or the system-in-package structure according to any one of claims 16-23.
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CN111279473A (en) * 2017-11-02 2020-06-12 国际商业机器公司 High aspect ratio solder bumps with stud bumps and injection molded solder and method of making flip chip connected to solder bumps

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