WO2022022311A1 - 产生伪随机序列的方法和装置、电子设备、存储介质 - Google Patents

产生伪随机序列的方法和装置、电子设备、存储介质 Download PDF

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WO2022022311A1
WO2022022311A1 PCT/CN2021/107084 CN2021107084W WO2022022311A1 WO 2022022311 A1 WO2022022311 A1 WO 2022022311A1 CN 2021107084 W CN2021107084 W CN 2021107084W WO 2022022311 A1 WO2022022311 A1 WO 2022022311A1
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sequence
bit value
bit
equal
pseudo
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PCT/CN2021/107084
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French (fr)
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蔡婉婕
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中兴通讯股份有限公司
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Priority to US18/018,601 priority Critical patent/US20230325151A1/en
Priority to EP21850613.7A priority patent/EP4187369A1/en
Publication of WO2022022311A1 publication Critical patent/WO2022022311A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/586—Pseudo-random number generators using an integer algorithm, e.g. using linear congruential method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

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  • the embodiments of the present application relate to the field of communications, and in particular, to a method and apparatus for generating a pseudo-random sequence, an electronic device, and a computer-readable storage medium.
  • Pseudo-random sequence (Pseudo-random Sequence) is widely used in channel estimation, signal scrambling and frequency hopping in communication systems because of its good randomness and correlation function close to white noise, and can be pre-determined and repeatable. Turn and so on.
  • the 3rd Generation Partnership Project 3rd Generation Partnership Project
  • LTE Long Term Evolution
  • NR New Radio
  • the 3rd Generation Partnership Project 3rd Generation Partnership Project
  • LTE Long Term Evolution
  • NR New Radio
  • Embodiments of the present application provide a method and apparatus for generating a pseudorandom sequence, an electronic device, and a computer-readable storage medium.
  • an embodiment of the present application provides a method for generating a pseudorandom sequence, comprising: performing AND operation and XOR operation on M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence ; wherein, M is an integer greater than or equal to 1, and A is an integer greater than or equal to 0; the mth bit value of the pseudo-random sequence is determined according to the (A+m)th bit value of the first sequence.
  • an embodiment of the present application provides an electronic device, including: at least one processor; and a memory, where at least one program is stored, and when the at least one program is executed by the at least one processor, the at least one processor implements any of the above A method for generating pseudorandom sequences.
  • embodiments of the present application provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, any of the foregoing methods for generating a pseudo-random sequence is implemented.
  • an embodiment of the present application provides an apparatus for generating a pseudorandom sequence, including: a calculation module configured to calculate M bit values of the first sequence according to the initial value of the first sequence; wherein M is greater than or equal to 1 The integer of ; the logic operation module is used to perform AND operation and XOR operation on the M bit values to obtain the (A+m)th bit value of the first sequence; wherein, A is an integer greater than or equal to 0; the determination module, for determining the mth bit value of the pseudorandom sequence according to the (A+m)th bit value of the first sequence.
  • the (A+m)th bit value of the first sequence can be obtained by performing simple AND operation and XOR operation on the M bit values of the first sequence, and then The m-th bit value of the pseudo-random sequence is obtained. Since the AND operation and the XOR operation are both simple logical operations, the operation speed is improved, the storage space and processor resources are saved, and the performance of the device is improved.
  • FIG. 1 is a flowchart of a method for generating a pseudorandom sequence provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of performing AND operation and XOR operation in an embodiment of the present application
  • FIG. 3 is a block diagram of an apparatus for generating a pseudo-random sequence provided by another embodiment of the present application.
  • the pseudo-random sequence used by 3GPP LTE or the new standard (NR, New Radio) is a 31-bit (bit) Gold sequence, and the polynomial used to generate the 31-bit Gold sequence is shown in formula (1) to formula (3):
  • x 1 (n+31) [x 1 (n+3)+x 1 (n)]mod 2 (2)
  • x 2 (n+31) [x 2 (n+3)+x 2 (n+2)+x 2 (n+1)+x 2 (n)]mod 2 (3)
  • the first is to input the initial values of x 1 and x 2 , and calculate all sequences iteratively according to the polynomial iteration relations (1) to (3), which can be implemented in software or hardware, occupying device resources (including memory resources and processor resources) ) is less, but the calculation speed is low, which is not conducive to the scene generated by real-time calculation.
  • the second is to obtain the initial state sequence V 0 according to the initial values of x 1 and x 2 , and deduce the one-step state transition matrix M from the current state sequence to the next state sequence according to the iterative formula.
  • the next state sequence can pass through the current state sequence. Multiply by M to obtain, and so on, to generate all sequences as follows:
  • the advantage of the second method is that it takes advantage of the parallel processing computing power of multiple computing units, and can calculate 32-bit at the same time.
  • the disadvantage is that it needs to perform the calculation of the k-th power of M, which requires a lot of accumulation and product calculation, which wastes a lot of storage. Space and processor resources that affect device performance.
  • FIG. 1 is a flowchart of a method for generating a pseudo-random sequence provided by an embodiment of the present application.
  • an embodiment of the present application provides a method for generating a pseudo-random sequence, including:
  • Step 100 perform AND operation and XOR operation on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence; wherein, M is an integer greater than or equal to 1, and A is greater than or equal to An integer of 0.
  • M is less than or equal to the bit width of the processor.
  • the performance is optimal. For example, when the bit width of the processor is 32, M can take any one of 4, 8, 16, and 32, but when M takes 32, the performance is optimal. And so on in other cases.
  • the M bit values include: the jth bit value to the (j+M-1)th bit value; wherein, j is an integer greater than or equal to 0.
  • the M bit values include the 0th bit value to the (M-1)th bit value, or the 1st bit value to the Mth bit value. This embodiment of the present application does not limit which M bit values are the M bit values.
  • the first sequence may be an x 2 sequence. If the pseudo-random sequence to be generated is another sequence, the first sequence may also be another sequence, and the specific form of the first sequence is not limited in this embodiment of the present application.
  • performing AND operation and XOR operation on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence includes:
  • the i-th bit value in the M bit values is ANDed with k (mi) to obtain the corresponding i-th intermediate bit value; wherein, i is an integer greater than or equal to 1 and less than or equal to M, and k (mi ) is the proportional coefficient corresponding to the i-th bit value and m; m is an integer greater than or equal to 0; the M intermediate bit values are XORed to obtain the (A+m)-th bit value of the first sequence.
  • the value of k (mi) is determined according to the original scale coefficient of x 2 (i) obtained by dividing x 2 (A+m), when dividing x 2 (A+m) When the original scale coefficient of x 2 (i) obtained is an even number, k (mi) takes the value of 0; when the original scale coefficient of x 2 (i) obtained by splitting x 2 (A+m) is an odd number, k (mi) takes the value 1.
  • FIG. 2 shows a schematic diagram of the AND operation and the XOR operation by taking M as 32 as an example.
  • input 32 bit values perform bitwise AND operation on the 32 bit values and 32 k values to obtain 32 intermediate bit values, and perform XOR operation on the 32 intermediate bit values to obtain the (A+m ) bit value.
  • the pseudo-random sequence is a Gold sequence
  • A may take a value of Nc, that is, 1600. If the pseudo-random sequence is another sequence, A can also take other values, and the specific value is determined according to the actual situation, as long as the value of A satisfies the calculation of the first bit value of the pseudo-random sequence.
  • Nc x 2
  • the method before performing AND operation on the i-th bit value among the M bit values and k (mi) to obtain the corresponding i-th intermediate bit value, the method further includes: according to i, m and k The first correspondence between ( mi ), determines k (mi) .
  • the first correspondence may be implemented in multiple representation forms, for example, in the form of a two-dimensional table, or in the form of a two-dimensional array, or in the form of a two-dimensional matrix. If it is in the form of a two-dimensional table, the row of the table can be i, and the column can be m; or, the row of the table can be m, and the column can be i; each cell is the value corresponding to k (mi) . Other cases are analogous, and will not be repeated here.
  • the AND operation and the XOR operation may be performed in a serial manner, or may be performed in a parallel manner.
  • the operation unit of the processor is fully utilized in a parallel manner, which achieves the effect of generating pseudo-random sequences quickly and in real time, saves storage space, and improves the generation efficiency of pseudo-random sequences.
  • 4 arithmetic units through the analysis of the time sequence, according to the optimal segmentation of 4, it is possible to calculate the result of 4 bits in 1 clock cycle, that is to say, for the first sequence, 4
  • the AND operation of the bit values of the M bits can be performed simultaneously, thereby improving the operation speed.
  • performing the AND operation and the XOR operation in a parallel manner may specifically include: performing the AND operation and the XOR operation corresponding to m corresponding to the same segment in parallel; wherein each segment includes N bits value, N is an integer greater than or equal to 2; the segment is the segment obtained by dividing the pseudo-random sequence.
  • the pseudo-random sequence is divided to obtain at least one segment, each segment includes N bit values of the pseudo-random sequence, and the calculation process of the N bit values belonging to the same segment is performed in parallel, and each bit value is performed in parallel.
  • the calculation process includes AND operation, XOR operation, and step 102 .
  • N is less than or equal to the maximum number of parallelisms supported by the processor.
  • the Gold sequence is used as an example for description here, it is not excluded that the generation process of other pseudo-random sequences may also adopt the manner of the embodiments of the present application.
  • x 2 (n+31) [x 2 (n+3)+x 2 (n+2)+x 2 (n+1)+x 2 (n)]mod 2
  • x 2 (1570+31) can be calculated, namely:
  • x 2 (1601) ⁇ [x 2 (1545)]mod 2+[x 2 (1543)]mod 2+[x 2 (1541)]mod 2+[x 2 (1539)]mod 2 ⁇ mod 2;
  • N C 1600, k (mi) ⁇ [0,1], and x 2 (i) ⁇ [0,1].
  • ⁇ represents the exclusive OR operation, that is to say, to obtain the (A+m)th bit value of the first sequence, it is necessary to perform a bitwise AND operation on the bit values of M bits, and then perform a bitwise AND operation on the result of the M-bit AND operation.
  • the XOR operation of M bits can obtain the (A+m)th bit value of the first sequence, and then obtain the output of 1 bit value of the pseudo-random sequence.
  • Step 101 Determine the mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence.
  • the determination of N bit values belonging to the same segment in the pseudorandom sequence is performed in parallel.
  • the method before performing AND operation and XOR operation on the M bit values of the first sequence to obtain the (A+m)th bit value of the first sequence, the method further includes:
  • the M bit values of the first sequence are calculated according to the initial values of the first sequence.
  • the 0th bit value to the 30th bit value are calculated according to the initial value c init , that is, the initial value of the first sequence. Specifically, according to the formula Calculation;
  • the method before determining the mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence, the method further includes: according to a preset i and the second sequence The second correspondence between the i bit values is to obtain the (A+m)th bit value of the second sequence; wherein, i is an integer greater than or equal to 1 and less than or equal to M;
  • determining the mth bit value of the pseudorandom sequence according to the (A+m)th bit value of the first sequence includes: according to the (A+m)th bit value of the first sequence and the ((A+m)th bit value of the second sequence A+m) bit values determine the m-th bit value of the pseudorandom sequence.
  • the second sequence may be an x 1 sequence.
  • the second corresponding relationship may be implemented in various representation forms, for example, in the form of a one-dimensional table, or in the form of a one-dimensional array, or in the form of a one-dimensional matrix. If it is in the form of a one-dimensional table, the row or column of the table can be i; the cell corresponding to each row or column is the i-th bit value of the second sequence. Other cases are analogous, and will not be repeated here.
  • M bit values of the first sequence are first calculated, and then the M bit values are subjected to simple AND operation and XOR operation to obtain the (A+)th value of the first sequence.
  • m) bit values and then the m-th bit value of the pseudo-random sequence is obtained, since the AND operation and the XOR operation are both simple logical operations, while improving the operation speed, the storage space and processor resources are saved, thereby Improved device performance.
  • the method for generating a pseudo-random sequence provided by the embodiments of the present application may be implemented by software or by hardware, for example, by using an AND gate and an XOR gate.
  • an electronic device including:
  • a memory where at least one program is stored, and when the at least one program is executed by at least one processor, the at least one processor implements any one of the foregoing methods for generating a pseudorandom sequence.
  • the processor is a device with data processing capability, which includes but is not limited to a central processing unit (CPU), etc.
  • the memory is a device with data storage capability, which includes but is not limited to random access memory (RAM, more specifically such as SDRAM) , DDR, etc.), read-only memory (ROM), charged erasable programmable read-only memory (EEPROM), flash memory (FLASH).
  • RAM random access memory
  • ROM read-only memory
  • EEPROM charged erasable programmable read-only memory
  • FLASH flash memory
  • the processor and memory are interconnected by a bus, which in turn is connected to other components of the computing device.
  • embodiments of the present application provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, any of the foregoing methods for generating a pseudo-random sequence is implemented.
  • FIG. 3 is a block diagram of an apparatus for generating a pseudo-random sequence provided by another embodiment of the present application.
  • FIG. 3 another embodiment of the present application provides an apparatus for generating a pseudo-random sequence, including:
  • a calculation module 301 configured to calculate M bit values of the first sequence according to the initial value of the first sequence; wherein, M is an integer greater than or equal to 1;
  • the logical operation module 302 is used to perform AND operation and XOR operation on the M bit values to obtain the (A+m)th bit value of the first sequence; wherein, A is an integer greater than or equal to 0;
  • the determining module 303 is configured to determine the mth bit value of the pseudo-random sequence according to the (A+m)th bit value of the first sequence.
  • the logic operation module 302 is specifically used to:
  • the i-th bit value in the M bit values is ANDed with k (mi) to obtain the corresponding i-th intermediate bit value; wherein, i is an integer greater than or equal to 1 and less than or equal to M, and k (mi ) is the proportional coefficient corresponding to the i-th bit value and m; m is an integer greater than or equal to 0; the M intermediate bit values are XORed to obtain the (A+m)-th bit value of the first sequence.
  • the logic operation module 302 is also used to:
  • the AND operation and the XOR operation corresponding to m corresponding to the same segment are performed in parallel, and the determination of the bit values belonging to the same segment in the pseudo-random sequence is performed in parallel; wherein each segment includes N bit values, where N is an integer greater than or equal to 2; the segment is a segment obtained by dividing the pseudo-random sequence.
  • N is less than or equal to the maximum number of parallelisms supported by the processor.
  • M is less than or equal to the bit width of the processor.
  • the M bit values include: the jth bit value to the (j+M-1)th bit value; wherein, j is an integer greater than or equal to 0.
  • it further includes: an obtaining module 304, configured to obtain the (A+mth) of the second sequence according to the preset second correspondence between i and the ith bit value of the second sequence ) bit values; wherein, i is an integer greater than or equal to 1 and less than or equal to M;
  • the determining module 303 is specifically configured to: determine the mth bit value of the pseudorandom sequence according to the (A+m)th bit value of the first sequence and the (A+m)th bit value of the second sequence.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage, or available with Any other medium that stores the desired information and can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

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Abstract

一种产生伪随机序列的方法和装置、电子设备、计算机可读存储介质，产生伪随机序列的方法包括：将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值；其中，M为大于或等于1的整数，A为大于或等于0的整数（100）；根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值（101）。

Description

产生伪随机序列的方法和装置、电子设备、存储介质
交叉引用
本申请基于申请号为“202010765593.6”、申请日为2020年07月31日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此以引入方式并入本申请。
技术领域
本申请实施例涉及通信领域，特别涉及产生伪随机序列的方法和装置、电子设备、计算机可读存储介质。
背景技术
伪随机序列(Pseudo-random Sequence)因具有良好的随机性和接近于白噪声的相关功能，并且可以预先确定和具有可重复性，被广泛应用在通信系统中信道估计、信号加扰和频率跳转等方面。
第三代合作伙伴计划(3GPP，3rd Generation Partnership Project)长期演进(LTE，Long Term Evolution)或新制式(NR，New Radio)标准采用Gold序列作为伪随机序列，目前Gold序列生成时内存占用量或执行时间会随着序列长度的增加而增加，从而影响设备的性能。
发明内容
本申请实施例提供一种产生伪随机序列的方法和装置、电子设备、计算机可读存储介质。
第一方面，本申请实施例提供一种产生伪随机序列的方法，包括：将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值；其中，M为大于或等于1的整数，A为大于或等于0的整数；根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
第二方面，本申请实施例提供一种电子设备，包括：至少一个处理器；存储器，存储器上存储有至少一个程序，当至少一个程序被至少一个处理器执行，使得至少一个处理器实现上述任意一种产生伪随机序列的方法。
第三方面，本申请实施例提供一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述任意一种产生伪随机序列的方法。
第四方面，本申请实施例提供一种产生伪随机序列的装置，包括：计算模块，用于根据第一序列的初始值计算第一序列的M个比特值；其中，M为大于 或等于1的整数；逻辑运算模块，用于将M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值；其中，A为大于或等于0的整数；确定模块，用于根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
本申请实施例提供的产生伪随机序列的方法，先将第一序列的M个比特值进行简单的与运算和异或运算即可得到第一序列的第(A+m)个比特值，继而得到伪随机序列的第m个比特值，由于与运算和异或运算均为简单的逻辑运算，在提高了运算速度的同时，节约了存储空间和处理器资源，从而提高了设备的性能。
附图说明
图1为本申请一个实施例提供的产生伪随机序列的方法的流程图；
图2为本申请实施例进行与运算和异或运算的示意图；
图3为本申请另一个实施例提供的产生伪随机序列的装置的组成框图。
具体实施方式
为使本领域的技术人员更好地理解本申请的技术方案，下面结合附图对本申请提供的产生伪随机序列的方法和装置、电子设备、计算机可读存储介质进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本申请透彻和完整，并将使本领域技术人员充分理解本申请的范围。
在不冲突的情况下，本申请各实施例及实施例中的各特征可相互组合。
如本文所使用的，术语“和/或”包括至少一个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本申请。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加至少一个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本申请的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
3GPP LTE或新制式(NR，New Radio)采用的伪随机序列为31-比特(bit)Gold序列，用于生成31-bit Gold序列的多项式如公式(1)到公式(3)：
c(n)＝[x 1(n+N C)+x 2(n+N C)]mod 2   (1)
x 1(n+31)＝[x 1(n+3)+x 1(n)]mod 2   (2)
x 2(n+31)＝[x 2(n+3)+x 2(n+2)+x 2(n+1)+x 2(n)]mod 2   (3)
其中，N C＝1600。
根据多项式迭代关系(1)到(3)，序列c(n)是根据x 1(n+N C)和x 2(n+N C)计算得到的，将x 1初始化为：x 1(0)＝1，x 1(n)＝0；n＝1,2,3...30；x 2的初始化值根据c init计算获得，即
Figure PCTCN2021107084-appb-000001
那么就可以得到x 1(n+N C)序列和x 2(n+N C)序列，从而获得最终的c(n)序列。
目前产生伪随机序列的方法有以下两种：
第一种，输入x 1和x 2的初始值，根据多项式迭代关系(1)到(3)，逐次迭代计算所有序列，可以使用软件或硬件实现，占用设备资源(包括内存资源和处理器资源)较少，但是计算速度较低，不利于实时计算生成的场景。
第二种，根据x 1和x 2的初始值得到初始状态序列V 0，根据迭代公式推导出从当前状态序列到下一个状态序列的一步状态转移矩阵M，下一状态序列可以通过当前状态序列乘以M获得，以此类推，生成所有序列，如下所示：
Figure PCTCN2021107084-appb-000002
第二种方法的优点是利用了多运算单元的并行处理计算能力，可以同时计算32-bit，缺点是需要进行M的k次幂的计算，需要进行大量的累加和乘积计算，浪费大量的存储空间和处理器资源，影响了设备性能。
图1为本申请一个实施例提供的产生伪随机序列的方法的流程图。
第一方面，参照图1，本申请一个实施例提供一种产生伪随机序列的方法，包括：
步骤100、将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值；其中，M为大于或等于1的整数，A为大于或等于0的整数。
在一些示例性实施例中，M小于或等于处理器的位宽。当M的取值等于处理器的位宽时，性能最优。例如，当处理器的位宽为32时，M可以取4、8、16、32中的任意一个，但是当M取32时性能最优。其他情况以此类推。
在一些示例性实施例中，M个比特值包括：第j个比特值到第(j+M-1)个比特值；其中，j为大于或等于0的整数。例如，M个比特值包括第0个比特值到第(M-1)个比特值，或者第1个比特值到第M个比特值。本申请实施例对M个比特值具体是哪M个比特值不作限定。
在一些示例性实施例中，如果需要生成的伪随机序列为Gold序列，那么第 一序列可以是x 2序列。如果需要生成的伪随机序列为其他序列，第一序列也可以是其他序列，本申请实施例对第一序列的具体形式不做限定。
在一些示例性实施例中，将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值包括：
将M个比特值中的第i个比特值和k (m.i)进行与运算得到相应的第i个中间比特值；其中，i为大于或等于1，且小于或等于M的整数，k (m.i)为第i个比特值和m对应的比例系数；m为大于或等于0的整数；将M个中间比特值进行异或运算得到第一序列的第(A+m)个比特值。
在一些示例性实施例中，k (m.i)的取值根据将x 2(A+m)拆分得到的x 2(i)的原始比例系数确定，当将x 2(A+m)拆分得到的x 2(i)的原始比例系数为偶数时，k (m.i)取值为0；当将x 2(A+m)拆分得到的x 2(i)的原始比例系数为奇数时，k (m.i)取值为1。
图2以M为32为例给出了与运算和异或运算的示意图。如图2所示，输入32个比特值，将32个比特值与32个k值按位进行与运算得到32个中间比特值，将32个中间比特值进行异或运算得到第(A+m)个比特值。
在一些示例性实施例中，如果伪随机序列为Gold序列，则A可以取值为Nc，即1600。如果伪随机序列为其他序列，则A也可以取值为其他的值，具体的取值根据实际情况来确定，只要A的取值满足计算伪随机序列的第1个比特值的计算就可以。对于Gold序列，由于Gold序列的第1个比特值是根据x 2(Nc)来计算得到的，因此，A取值为Nc是最为高效的计算方式，当然，A也可以不取值为Nc，但是需要做进一步的迭代计算才能得到Gold序列的第1个比特值。
在一些示例性实施例中，将M个比特值中的第i个比特值和k (m.i)进行与运算得到相应的第i个中间比特值之前，该方法还包括：根据i、m和k (m.i)之间的第一对应关系，确定k (m.i)。
在一些示例性实施例中，第一对应关系可以采用多种表现形式来实现，例如，可以采用二维表格的形式，或者采用二维数组的形式，或者采用二维矩阵的形式。如果采用二维表格的形式，表格的行可以是i，列可以是m；或者，表格的行可以是m，列可以是i；每一个单元格为k (m.i)对应的取值。其他情况以此类推，这里不再赘述。
在一些示例性实施例中，进行与运算和异或运算可以采用串行的方式进行，也可以采用并行的方式进行。其中，采用并行的方式充分的利用了处理器的运算单元，达到了快速实时生成伪随机序列的效果，节省了存储空间，提高了伪随机序列的生成效率。例如，在4个运算单元的情况下，通过时序的分析，按照4分段最优，可以做到1个时钟周期计算出4个比特的结果，也就是说，对于第一序列来说，4个M比特的比特值的与运算可以同时进行，从而提高了运算速度。
在一些示例性实施例中，采用并行方式进行与运算和异或运算具体可以包括：同一个分段对应的m对应的与运算和异或运算并行进行；其中，每一个分 段包括N个比特值，N为大于或等于2的整数；分段为对伪随机序列进行划分得到的分段。
也就是说，将伪随机序列进行划分得到至少一个分段，每一个分段包括伪随机序列的N个比特值，属于同一个分段的N个比特值的计算过程并行进行，每一个比特值的计算过程包括与运算、异或运算，以及步骤102。
在一些示例性实施例中，N小于或等于处理器支持的最大并行数。
下面以Gold序列为例说明为什么将M个特征进行与运算和异或运算就能得到第一序列的第(A+m)个比特值。这里虽然以Gold序列为例进行说明，但是不排除其他的伪随机序列的生成过程也可以采用本申请实施例的方式。
根据x 2序列的递推公式x 2(n+31)＝[x 2(n+3)+x 2(n+2)+x 2(n+1)+x 2(n)]mod 2，可以计算x 2(1570+31)，即：
Figure PCTCN2021107084-appb-000003
由于mod2运算反映了结果的奇偶性，因此可以将所有的比特位相加后再求一次mod2运算，则有
Figure PCTCN2021107084-appb-000004
上式也可以等价于对k i×x 2(i)先求mod2运算后再相加，最后再进行一次mod2运算，因此，上式可以重写为：
Figure PCTCN2021107084-appb-000005
对于[k i×x 2(n)]mod 2，由于[k i×x 2(n)]mod 2＝(k imod 2)×[x 2(n)mod 2]，如果k i(即原始比例系数)为偶数，那么[k i×x 2(n)]mod 2＝0；如果k i为奇数，那么[k i×x 2(n)]mod 2＝x 2(n)mod 2；因此，上式可以简化为：
x 2(1601)＝{[x 2(1545)]mod 2+[x 2(1543)]mod 2+[x 2(1541)]mod 2+[x 2(1539)]mod 2}mod 2；
然后，可以将x 2(1545)、x 2(1543)、x 2(1541)、x 2(1539)继续拆分，最终将x 2(1601)拆分为x 2(n)的组合，n∈[0，M-1]，即可得到：
Figure PCTCN2021107084-appb-000006
其中，N C＝1600，k (m.i)∈[0,1]，x 2(i)∈[0,1]。
其中，y (m，i)＝k (m，i)*x 2(i)可以通过(M-1)比特的按位与运算实现，即y (m，i)＝k (m，i)*x 2(i)等价于y (m，i)＝k (m，i)&x 2(i)，标记为y (m.i)，由于[x 2(i)+x 2(i+1)]mod 2等价于x 2(i)^x 2(i+1)，从而x 2(N C+m)又可以通过的异或运算实现，即得到：
Figure PCTCN2021107084-appb-000007
其中，^表示异或运算，也就是说，获得第一序列的第(A+m)个比特值需要先将M比特的比特值按位进行与运算，再将M比特的与运算的结果进行M比特的异或运算，就可以得到第一序列的第(A+m)个比特值，进而得到伪随机序列的1个比特值的输出。
步骤101、根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
在一些示例性实施例中，伪随机序列中属于同一个分段的N个比特值的确定并行进行。
在一些示例性实施例中，将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值之前，该方法还包括：
根据第一序列的初始值计算第一序列的M个比特值。
下面以伪随机序列为Gold序列为例说明M个比特值的计算过程。
首先，根据初始值c init计算第0个比特值到第30个比特值，也就是第一序列的初始值。具体的，按照公式
Figure PCTCN2021107084-appb-000008
进行计算；
其次，如果M个比特值中存在在第一序列中的位置大于30的比特值，则按照递推公式x 2(n+31)＝[x 2(n+3)+x 2(n+2)+x 2(n+1)+x 2(n)]mod 2计算在第一序列中的位置大于30的比特值。
在一些示例性实施例中，根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值之前，该方法还包括：根据预先设置的i和第二序列的第i个比特值之间的第二对应关系，获取第二序列的第(A+m)个比特值；其中，i为大于或等于1，且小于或等于M的整数；
相应的，根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值包括：根据第一序列的第(A+m)个比特值和第二序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
在一些示例性实施例中，如果伪随机序列为Gold序列，则第二序列可以是x 1序列。x 1序列的各个比特值可以预先根据递推公式x 1(n+31)＝[x 1(n+3)+x 1(n)]mod 2计算获得，并存储起来，在需要获取第二序列的某一个比特值时，直接调用即可。
在一些示例性实施例中，第二对应关系可以采用多种表现形式来实现，例如，可以采用一维表格的形式，或者采用一维数组的形式，或者采用一维矩阵的形式。如果采用一维表格的形式，表格的行或列可以是i；每一行或列对应的单元格为第二序列的第i个比特值。其他情况以此类推，这里不再赘述。
在一些示例性实施例中，如果伪随机序列为Gold序列，则伪随机序列的第m个比特值根据递推公式c(n)＝[x 1(n+N C)+x 2(n+N C)]mod 2计算获得。
本申请实施例提供的产生伪随机序列的方法，先计算第一序列的M个比特 值，再将M个比特值进行简单的与运算和异或运算即可得到第一序列的第(A+m)个比特值，继而得到伪随机序列的第m个比特值，由于与运算和异或运算均为简单的逻辑运算，在提高了运算速度的同时，节约了存储空间和处理器资源，从而提高了设备的性能。
需要说明的是，本申请实施例提供的产生伪随机序列的方法可以采用软件实现，也可以采用硬件实现，例如，采用与门和异或门来实现。
第二方面，本申请实施例提供一种电子设备，包括：
至少一个处理器；
存储器，存储器上存储有至少一个程序，当至少一个程序被至少一个处理器执行，使得至少一个处理器实现上述任意一种产生伪随机序列的方法。
其中，处理器为具有数据处理能力的器件，其包括但不限于中央处理器(CPU)等；存储器为具有数据存储能力的器件，其包括但不限于随机存取存储器(RAM，更具体如SDRAM、DDR等)、只读存储器(ROM)、带电可擦可编程只读存储器(EEPROM)、闪存(FLASH)。
在一些实施例中，处理器、存储器通过总线相互连接，进而与计算设备的其它组件连接。
第三方面，本申请实施例提供一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述任意一种产生伪随机序列的方法。
图3为本申请另一个实施例提供的产生伪随机序列的装置的组成框图。
第四方面，参照图3，本申请另一个实施例提供一种产生伪随机序列的装置，包括：
计算模块301，用于根据第一序列的初始值计算第一序列的M个比特值；其中，M为大于或等于1的整数；
逻辑运算模块302，用于将M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值；其中，A为大于或等于0的整数；
确定模块303，用于根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
在一些示例性实施例中，逻辑运算模块302具体用于：
将M个比特值中的第i个比特值和k (m.i)进行与运算得到相应的第i个中间比特值；其中，i为大于或等于1，且小于或等于M的整数，k (m.i)为第i个比特值和m对应的比例系数；m为大于或等于0的整数；将M个中间比特值进行异或运算得到第一序列的第(A+m)个比特值。
在一些示例性实施例中，逻辑运算模块302还用于：
根据i、m和k (m.i)之间的第一对应关系，确定k (m.i)。
在一些示例性实施例中，同一个分段对应的m对应的与运算和异或运算并行进行，伪随机序列中属于同一个分段的比特值的确定并行进行；其中，每一个分段包括N个比特值，N为大于或等于2的整数；分段为对伪随机序列进行划分得到的分段。
在一些示例性实施例中，N小于或等于处理器支持的最大并行数。
在一些示例性实施例中，M小于或等于处理器的位宽。
在一些示例性实施例中，M个比特值包括：第j个比特值到第(j+M-1)个比特值；其中，j为大于或等于0的整数。
在一些示例性实施例中，还包括：获取模块304，用于根据预先设置的i和第二序列的第i个比特值之间的第二对应关系，获取第二序列的第(A+m)个比特值；其中，i为大于或等于1，且小于或等于M的整数；
相应的，确定模块303具体用于：根据第一序列的第(A+m)个比特值和第二序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
上述产生伪随机序列的装置的具体实现过程与前述实施例产生伪随机序列的方法的具体实现过程相同，这里不再赘述。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其它数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其它存储器技术、CD-ROM、数字多功能盘(DVD)或其它光盘存储、磁盒、磁带、磁盘存储或其它磁存储器、或者可以用于存储期望的信息并且可以被计算机访问的任何其它的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其它传输机制之类的调制数据信号中的其它数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本申请的范围的情况下，可进行各种形式和细节上的改变。

Claims (12)

  1. 一种产生伪随机序列的方法，包括：
    将第一序列的M个比特值进行与运算和异或运算得到所述第一序列的第(A+m)个比特值；其中，所述M为大于或等于1的整数，所述A为大于或等于0的整数；
    根据所述第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
  2. 根据权利要求1所述的方法，其中，所述将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值包括：
    将M个所述比特值中的第i个比特值和k (m.i)进行与运算得到相应的第i个中间比特值；其中，所述i为大于或等于1，且小于或等于M的整数，所述k (m.i)为所述第i个比特值和m对应的比例系数；其中，m为大于或等于0的整数；
    将M个所述中间比特值进行异或运算得到所述第一序列的第(A+m)个比特值。
  3. 根据权利要求2所述的方法，所述将M个比特值中的第i个比特值和k (m.i)进行与运算得到相应的第i个中间比特值之前，该方法还包括：
    根据i、m和k (m.i)之间的第一对应关系，确定k (m.i)。
  4. 根据权利要求1至3中任一项所述的方法，其中，同一个分段对应的m对应的与运算和异或运算并行进行，所述伪随机序列中属于同一个分段的比特值的确定并行进行；其中，每一个所述分段包括所述伪随机序列的N个比特值，N为大于或等于2的整数；所述分段为对所述伪随机序列进行划分得到的分段。
  5. 根据权利要求4所述的方法，其中，所述N小于或等于处理器支持的最大并行数。
  6. 根据权利要求1至5中任一项所述的方法，其中，所述M小于或等于处理器的位宽。
  7. 根据权利要求1至6中任一项所述的方法，其中，M个所述比特值包括：第j个比特值到第(j+M-1)个比特值；其中，j为大于或等于0的整数。
  8. 根据权利要求1至7中任一项所述的方法，所述将第一序列的M个比特值进行与运算和异或运算得到第一序列的第(A+m)个比特值之前，该方法还包括：
    根据所述第一序列的初始值计算所述第一序列的M个比特值。
  9. 根据权利要求1至7中任一项所述的方法，所述根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值之前，该方法还包括：根据预先设置的i和第二序列的第i个比特值之间的第二对应关系，获取所述第二序列的第(A+m)个比特值；其中，所述i为大于或等于1，且小于或等于M的整数；
    相应的，所述根据第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值包括：根据所述第一序列的第(A+m)个比特值和所述第二序列的第(A+m)个比特值确定所述伪随机序列的第m个比特值。
  10. 一种电子设备，包括：
    至少一个处理器；
    存储器，所述存储器上存储有至少一个程序，当所述至少一个程序被所述至少一个处理器执行，使得所述至少一个处理器实现根据权利要求1至9中任意一项所述的产生伪随机序列的方法。
  11. 一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现根据权利要求1至9中任意一项所述的产生伪随机序列的方法。
  12. 一种产生伪随机序列的装置，包括：
    计算模块，用于根据第一序列的初始值计算第一序列的M个比特值；其中，M为大于或等于1的整数；
    逻辑运算模块，用于将所述M个比特值进行与运算和异或运算得到所述第一序列的第(A+m)个比特值；其中，A为大于或等于0的整数；
    确定模块，用于根据所述第一序列的第(A+m)个比特值确定伪随机序列的第m个比特值。
PCT/CN2021/107084 2020-07-31 2021-07-19 产生伪随机序列的方法和装置、电子设备、存储介质 WO2022022311A1 (zh)

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CN102025389A (zh) * 2009-09-09 2011-04-20 中兴通讯股份有限公司 一种伪随机序列的生成方法及装置
CN102405602A (zh) * 2011-07-18 2012-04-04 华为技术有限公司 用于生成伪随机序列数据的数据序列的生成方法及设备
CN102891726A (zh) * 2012-09-10 2013-01-23 华为技术有限公司 一种产生Gold序列的方法及芯片
CN103873181A (zh) * 2014-04-04 2014-06-18 中国科学院自动化研究所 一种lte系统中伪随机序列并行生成方法
CN108023661A (zh) * 2016-10-31 2018-05-11 深圳市中兴微电子技术有限公司 一种获取伪随机序列的方法和装置

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CN102405602A (zh) * 2011-07-18 2012-04-04 华为技术有限公司 用于生成伪随机序列数据的数据序列的生成方法及设备
CN102891726A (zh) * 2012-09-10 2013-01-23 华为技术有限公司 一种产生Gold序列的方法及芯片
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