WO2022017353A1 - 物理上行控制信道资源重叠的处理方法及装置 - Google Patents

物理上行控制信道资源重叠的处理方法及装置 Download PDF

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Publication number
WO2022017353A1
WO2022017353A1 PCT/CN2021/107267 CN2021107267W WO2022017353A1 WO 2022017353 A1 WO2022017353 A1 WO 2022017353A1 CN 2021107267 W CN2021107267 W CN 2021107267W WO 2022017353 A1 WO2022017353 A1 WO 2022017353A1
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priority
pucch
low
harq
ack
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PCT/CN2021/107267
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English (en)
French (fr)
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李娜
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维沃移动通信有限公司
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Publication of WO2022017353A1 publication Critical patent/WO2022017353A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/1607—Details of the supervisory signal
    • H04L1/1671—Details of the supervisory signal the supervisory signal being transmitted together with control information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1854—Scheduling and prioritising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1829—Arrangements specially adapted for the receiver end
    • H04L1/1861—Physical mapping arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0053—Allocation of signaling, i.e. of overhead other than pilot signals
    • H04L5/0055—Physical resource allocation for ACK/NACK
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation

Definitions

  • the present application belongs to the field of communication technologies, and in particular relates to a method and device for processing overlapping physical uplink control channel resources.
  • PUCCH Physical Uplink Control Channel
  • UCI Uplink Control Information
  • the purpose of the embodiments of the present application is to provide a method and apparatus for processing physical uplink control channel resource overlap, so as to solve the problem of how to ensure the performance of low-priority services.
  • a method for processing PUCCH resource overlap including:
  • the terminal multiplexes the at least two PUCCH transmissions;
  • the at least two PUCCHs include: a high-priority PUCCH and a low-priority PUCCH.
  • an apparatus for processing PUCCH resource overlap is provided, applied to a terminal, including:
  • a processing module configured to multiplex the at least two PUCCH transmissions when the at least two PUCCH transmission resources overlap
  • the at least two PUCCHs include: a high-priority PUCCH and a low-priority PUCCH.
  • the processing module is further configured to: multiplex the at least two PUCCH transmissions according to the first information;
  • the first information includes at least one of the following:
  • the type of uplink control information carried by the PUCCH is the type of uplink control information carried by the PUCCH.
  • the at least two PUCCHs include at least one of the following:
  • PUCCH carrying CSI PUCCH carrying HARQ-ACK and PUCCH carrying SR
  • the PUCCH carrying HARQ-ACK includes: a PUCCH carrying a high-priority HARQ-ACK and/or a PUCCH carrying a low-priority HARQ-ACK;
  • the PUCCHs carrying SRs include: M PUCCHs carrying high-priority SRs and/or N PUCCHs carrying low-priority SRs;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and M PUCCHs carrying a high-priority SR;
  • the processing module is further configured to: multiplex the PUCCH bearing the high-priority HARQ-ACK with the PUCCH bearing the low-priority HARQ-ACK to obtain the first PUCCH;
  • the first PUCCH overlaps with M' PUCCHs carrying high-priority SRs, the first PUCCH is multiplexed with the M' high-priority SR-carrying PUCCHs, where M' and M equal or unequal;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and N' PUCCHs carrying a low-priority SR;
  • the processing module is further configured to: multiplex the PUCCH bearing the high-priority HARQ-ACK with the PUCCH bearing the low-priority HARQ-ACK to obtain the first PUCCH;
  • the first PUCCH overlaps the N' PUCCHs carrying low-priority SRs, multiplexing the first PUCCH with the N' PUCCHs carrying low-priority SRs, wherein the N' is equal or not equal to N;
  • the at least two PUCCHs include: PUCCHs that carry high-priority HARQ-ACKs, PUCCHs that carry low-priority HARQ-ACKs, M PUCCHs that carry high-priority SRs, and N PUCCHs that carry low-priority SRs;
  • the processing module is further configured to: multiplex the PUCCH carrying the high-priority HARQ-ACK with the PUCCH carrying the low-priority HARQ-ACK to obtain a first PUCCH;
  • the first PUCCH overlaps with M' PUCCHs carrying high-priority SRs and N' PUCCHs carrying low-priority SRs, then combine the first PUCCH with M' PUCCHs and N's carrying high-priority SRs ' PUCCHs carrying low-priority SRs are multiplexed, wherein N' and N are equal or unequal, and M' and M are equal or unequal.
  • the first PUCCH is determined by the number of bits of the high-priority HARQ-ACK and the number of bits of the low-priority HARQ-ACK.
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and M PUCCHs carrying a high-priority SR;
  • the processing module is further configured to: multiplex the high-priority HARQ-ACK, the low-priority HARQ-ACK, and M high-priority SRs on the second PUCCH;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and N PUCCHs carrying a low-priority SR;
  • the processing module is further configured to: multiplex the high-priority HARQ-ACK, the low-priority HARQ-ACK, and the N low-priority SRs on the second PUCCH;
  • the at least two PUCCHs include: PUCCHs that carry high-priority HARQ-ACKs, PUCCHs that carry low-priority HARQ-ACKs, M PUCCHs that carry high-priority SRs, and N PUCCHs that carry low-priority SRs;
  • the processing module is further configured to: multiplex the high-priority HARQ-ACK, the low-priority HARQ-ACK, the M high-priority SRs and the N low-priority SRs on the second PUCCH .
  • the second PUCCH is based on the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, the number of bits of the M high-priority SRs, the N It is determined by one or more combinations of the number of bits of the low-priority SR.
  • the second PUCCH is determined according to the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, and the number of bits of the M high-priority SRs;
  • the number of bits of the M high-priority SRs is: log 2 (1+M);
  • the second PUCCH is determined according to the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, and the number of bits of the N low-priority SRs;
  • the number of bits of the N low-priority SRs is: log 2 (1+N);
  • the second PUCCH is based on the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, the bits of the M high-priority SRs and the N low-priority SRs number determined;
  • the number of bits of the M high-priority SRs and the N low-priority SRs is: the sum of log 2 (1+M) and log 2 (1+N), or log 2 (1+M+ N).
  • the at least two PUCCHs include: PUCCHs carrying CSI, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further configured to: multiplex the M high-priority SRs and N low-priority SRs on the PUCCH carrying the CSI.
  • the at least two PUCCHs include: PUCCHs that carry CSI, and M PUCCHs that carry high-priority SRs;
  • the processing module is further configured to: place the M high-priority SRs on the PUCCH carrying the CSI.
  • processing module is further used to:
  • M represents the high priority SR of log 2 (1 + M) bits
  • N denotes a low-priority SR log 2 (1 + N) bits multiplexed on PUCCH CSI of the carrier
  • the log 2 (1+M) bits representing M high-priority SRs are multiplexed on the CSI-carrying PUCCH.
  • bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI; or , the bit positions of the M high-priority SRs are located before the bit positions of the CSI.
  • the at least two PUCCHs include: PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the format is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • processing module is further used to:
  • M represents the high priority SR of log 2 (1 + M) bits
  • N denotes a low-priority SR log 2 (1 + N) bits multiplexed in the high priority bearer the HARQ-ACK on PUCCH;
  • the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs are multiplexed on the PUCCH carrying the high-priority HARQ-ACK.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located before the bit positions representing the N low-priority SRs. .
  • the at least two PUCCHs include: PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • processing module 501 is further configured to:
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • processing module is further used to:
  • M represents the high priority SR of log 2 (1 + M) bits
  • N denotes a low-priority SR log 2 (1 + N) bit multiplexing on low priority of the bearer of the HARQ-ACK PUCCH ;
  • the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs are multiplexed on the PUCCH carrying the low-priority HARQ-ACK.
  • bit positions of the M high-priority SRs are located before the bit positions of the low-priority HARQ-ACKs, and the bit positions of the low-priority HARQ-ACKs are located before the N low-priority SRs. before the bit position.
  • the at least two PUCCHs include: PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs PUCCH;
  • the processing module is further used to:
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the third PUCCH is determined based on the number of bits of the M high-priority SRs, the number of bits of the N low-priority SRs, the number of bits of the high-priority HARQ-ACK, and the number of bits of the low-priority HARQ-ACK of.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located before the bit positions of the low-priority HARQ-ACK, The bit positions of the low-priority HARQ-ACK are located before the bit positions of the N low-priority SRs.
  • bit position of the high-priority HARQ-ACK is located before the bit position of the low-priority HARQ-ACK, and the bit position of the low-priority HARQ-ACK is located between the M high-priority SRs.
  • bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs.
  • the at least two PUCCHs include: a PUCCH carrying CSI, a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, M PUCCHs carrying a high-priority SR, and N bearers PUCCH of low priority SR;
  • the processing module is further used to:
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the Four PUCCH is based on the number of bits of the M high-priority SRs, the number of bits of the N low-priority SRs, the number of bits of the high-priority HARQ-ACK, the bits of the low-priority HARQ-ACK. The number of bits and the number of CSI bits are determined.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located in the low-priority HARQ-ACK.
  • bit positions of the low-priority HARQ-ACK are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI.
  • the bit position of the high-priority HARQ-ACK is located before the bit position of the low-priority HARQ-ACK, and the bit position of the low-priority HARQ-ACK is located between the M high-priority SRs.
  • the bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI.
  • the at least two PUCCHs include: PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the log 2 (1+M+N) bits of the priority SR are multiplexed with the high-priority HARQ-ACK on the fifth PUCCH, where the high-priority HARQ-ACK includes the physical downlink sharing with PDCCH scheduling Feedback of channel PDSCH;
  • the at least two PUCCHs include: PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the log 2 (1+M+N) bits of the priority SR are multiplexed with the low-priority HARQ-ACK on the fifth PUCCH, and the low-priority HARQ-ACK contains feedback on the PDSCH scheduled by the PDCCH;
  • the at least two PUCCHs include: PUCCHs that carry high-priority HARQ-ACKs, PUCCHs that carry low-priority HARQ-ACKs, M PUCCHs that carry high-priority SRs, and N PUCCHs that carry low-priority SRs;
  • the processing module is further used to:
  • the high priority HARQ-ACK and the low priority HARQ-ACK HARQ-ACK contains feedback on PDSCH scheduled with PDCCH.
  • the at least two PUCCHs include: PUCCHs carrying high-priority or low-priority HARQ-ACKs, and M PUCCHs carrying high-priority SRs;
  • the processing module is further used to:
  • the format of the PUCCH of the high-level or low-priority HARQ-ACK is PUCCH format 0;
  • the at least two PUCCHs include: PUCCHs carrying HARQ-ACK with high priority or low priority, and N PUCCHs carrying SRs with low priority;
  • the processing module is further used to:
  • the format of the PUCCH of the high-level or low-priority HARQ-ACK is PUCCH format 0;
  • the at least two PUCCHs include: PUCCHs carrying high-priority or low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the third SR is a positive SR of any one of the M high-priority SRs and N low-priority SRs
  • the format of the PUCCH carrying the high-priority or low-priority HARQ-ACK is PUCCH format 0.
  • the high-priority SR and the low-priority SR are multiplexed on the PUCCH carrying the high-priority or low-priority HARQ-ACK.
  • the priority SR adopts different cyclic shifts.
  • the at least two PUCCHs include: a PUCCH bearing a low-priority HARQ-ACK, and M PUCCHs bearing a high-priority SR;
  • the processing module is further configured to: multiplex the low-priority HARQ-ACK on the PUCCH bearing the positive SR;
  • the format of the PUCCH bearing the low-priority HARQ-ACK is PUCCH format 1
  • the format of the PUCCH bearing the positive SR is PUCCH format 1
  • the positive SR is any one of M high-priority SRs ;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, and N PUCCHs carrying a low-priority SR;
  • the processing module is further configured to: multiplex the high-priority HARQ-ACK on the PUCCH bearing the positive SR;
  • the format of the PUCCH bearing the high-priority HARQ-ACK is PUCCH format 1
  • the format of the PUCCH bearing the positive SR is PUCCH format 1
  • the positive SR is any one of N low-priority SRs .
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the log 2 (1+M+N) bits of the priority SR are multiplexed on the seventh PUCCH with the bits of the high-priority HARQ-ACK, where the high-priority HARQ-ACK contains feedback on the PDSCH scheduled by the PDCCH ;
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1;
  • the at least two PUCCHs PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1;
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the log 2 (1+M+N) bits of the level SR are multiplexed with the high-priority HARQ-ACK on the sixth PUCCH, wherein the high-priority HARQ-ACK does not include the feedback, and the terminal is configured with an SPS HARQ-ACK feedback PUCCH list;
  • the at least two PUCCHs PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the terminal is configured with an SPS HARQ-ACK feedback PUCCH list;
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module is further used to:
  • the first-level HARQ-ACK does not include feedback on PDSCH scheduled with PDCCH, and the terminal is configured with the SPS HARQ-ACK feedback PUCCH list.
  • the fifth PUCCH, the sixth PUCCH or the seventh PUCCH is determined according to any one of the following:
  • the number of log 2 (1+M) bits representing M high-priority SRs, the number of log 2 (1+N) bits representing N low-priority SRs, and the number of bits of the high-priority HARQ-ACK are determined by , or, the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs, and the number of bits of the high-priority HARQ-ACK are determined;
  • M represents a high-priority SR of log 2 (1 + M) bit number
  • N represents the low-priority SR log 2 (1 + N) bits
  • the low priority bits determine the HARQ-ACK , or, the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs, and the number of bits of the low-priority HARQ-ACK are determined;
  • the number of bits of the low-priority HARQ-ACK is determined, or, it represents the number of log 2 (1+M+N) bits of M high-priority SRs and N low-priority SRs, the high-priority HARQ-ACK The number of bits and the number of bits of the low-priority HARQ-ACK are determined.
  • a terminal including: a processor, a memory, and a program stored on the memory and executable on the processor, the program being executed by the processor as described in the first aspect steps of the method described.
  • a readable storage medium is provided, and a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the method according to the first aspect are implemented.
  • a program product is provided, the program product is stored in a non-volatile storage medium, the program product is executed by at least one processor to implement the steps of the method according to the first aspect.
  • a chip in a sixth aspect, includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement the method according to the first aspect .
  • a terminal is provided, the terminal being configured to perform the method of the first aspect.
  • the performance of low-priority services can be ensured, and the reliability of the communication system can be improved.
  • FIG. 1 is a block diagram of a wireless communication system to which an embodiment of the present application can be applied;
  • FIG. 2 is a flowchart of a processing method for PUCCH overlap according to an embodiment of the present application
  • Figures 3a-3d are schematic diagrams illustrating the overlap between the PUCCH carrying HARQ-ACK and the PUCCH carrying SR
  • 4a-4d are schematic diagrams of overlapping PUCCH carrying CSI or HARQ-ACK and PUCCH carrying SR;
  • FIG. 5 is a schematic diagram of an apparatus for processing physical uplink control channel resource overlap according to an embodiment of the present application
  • FIG. 6 is a schematic diagram of a terminal according to an embodiment of the present application.
  • 5G fifth generation
  • the main scenarios of 5G include Enhanced Mobile Broadband (eMBB), Ultra-Reliable and Low Latency Communications (URLLC), Massive Machine Type Communication (mMTC), these scenarios High reliability, low latency, large bandwidth, and wide coverage are required for the system.
  • eMBB Enhanced Mobile Broadband
  • URLLC Ultra-Reliable and Low Latency Communications
  • mMTC Massive Machine Type Communication
  • High reliability, low latency, large bandwidth, and wide coverage are required for the system.
  • different services may be supported.
  • the UE supports URLLC low-latency and high-reliability services, and supports large-capacity and high-speed eMBB services.
  • New Radio New Radio
  • NR New Radio
  • the time-domain overlap of transmission resources may occur.
  • the single-carrier characteristics of the UE will be destroyed, and the difference in transmit power will cause the deterioration of the channel estimation performance. This situation is usually regarded as a conflict, and a corresponding conflict resolution solution needs to be designed, merging and discarding some information.
  • a UE When a UE supports different services at the same time, such as URLLC and eMBB, since different services have different delay or reliability requirements, in order to ensure the transmission of high-priority services, the UE will distinguish the priorities corresponding to different channels/signals , such as high priority or low priority, channels or signals of different priorities may overlap in time domain resources, and the UE will discard/cancel low priority channels/signals.
  • NR R15 There is no distinction between different service types or priorities in NR R15.
  • the UE When different channel time domain resources overlap, the UE will multiplex or discard them according to predefined rules.
  • the PUCCH of request acknowledgement, HARQ-ACK) and the PUCCH carrying periodic channel state information (Channel State Information, CSI) overlap the UE multiplexes HARQ-ACK and CSI on one PUCCH, and the PUCCH is based on HARQ-ACK Determined by the PUCCH indication (PUCCH resource indicator, PRI) corresponding to the total payload of CSI and HARQ-ACK;
  • PUCCH resource indicator PUCCH resource indicator
  • NR R15 defines the time requirements that should be met when PUCCH and PUCCH, or PUCCH and PUSCH are multiplexed.
  • a UE may support different services at the same time, and different services correspond to different service requirements, such as delay, reliability and so on. Therefore, a mechanism for marking the PUCCH/PUSCH channel priority is introduced, and specifically, two levels of physical layer priorities are introduced, that is, high priority and low priority. For example, SR, Configured Grant (CG) PUSCH, Semi-Persistent Scheduling (SPS) Physical downlink Shared channel (PDSCH) and the priority of the released HARQ-ACK It is configured by Radio Resource Control (RRC) signaling.
  • CG Configured Grant
  • SPS Semi-Persistent Scheduling
  • PDSCH Physical downlink Shared channel
  • RRC Radio Resource Control
  • Periodic CSI For periodic channel state information (periodic CSI, P-CSI) or semi-periodic channel state information (semi-periodic CSI, SP-CSI) on PUCCH Treated as low priority.
  • dynamically scheduled (DG) PUSCH For HARQ-ACK of dynamically scheduled PDSCH, dynamically scheduled (DG) PUSCH, PUSCH carrying aperiodic CSI (Aperiodic CSI, A-CSI)/semi-persistent CSI (semi-persistent CSI, SP-CSI) are corresponding to The scheduling downlink control information (Downlink Control Information, DCI) indication.
  • DCI Downlink Control Information
  • the priority of the PUCCH is determined by the HARQ-ACK/SR/CSI it carries.
  • the time domain resources of different channels overlap, if they are of the same priority, they will be processed according to the multiplexing rules defined by NR R15. If they are of different priorities, the UE will discard the low-priority channel and transmit the high-priority channel. If there are both the same priority and different priorities, the UE will first process according to the multiplexing rules defined by NR R15, and then process channels with different priorities. At the same time, when the UE processes different priorities, it discards the low priority channels, and it also takes a certain processing time to transmit the high priority channels.
  • the R16 protocol defines the discard/cancel time requirements when the UE processes different priority channels.
  • first, second, etc. in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specified order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in sequences other than those illustrated or described herein, and "first”, “second” distinguishes Usually it is a class, and the number of objects is not limited.
  • the first object may be one or multiple.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the associated objects are in an "or” relationship.
  • LTE Long Term Evolution
  • LTE-Advanced LTE-Advanced
  • LTE-A Long Term Evolution-Advanced
  • CDMA Code Division Multiple Access
  • TDMA Time Division Multiple Access
  • FDMA Frequency Division Multiple Access
  • OFDMA Orthogonal Frequency Division Multiple Access
  • SC-FDMA Single-carrier Frequency-Division Multiple Access
  • system and “network” in the embodiments of the present application are often used interchangeably, and the described technology can be used not only for the above-mentioned systems and radio technologies, but also for other systems and radio technologies.
  • NR New Radio
  • the following description describes a New Radio (NR) system for example purposes, and NR terminology is used in most of the description below, although these techniques are also applicable to applications other than NR system applications, such as 6th generation ( 6 th Generation, 6G) communication system.
  • 6th generation 6 th Generation, 6G
  • FIG. 1 shows a block diagram of a wireless communication system to which the embodiments of the present application can be applied.
  • the wireless communication system includes a terminal 11 and a network-side device 12 .
  • the terminal 11 may also be called a terminal device or a user terminal (User Equipment, UE), and the terminal 11 may be a mobile phone, a tablet computer (Tablet Personal Computer), a laptop computer (Laptop Computer) or a notebook computer, a personal digital computer Assistant (Personal Digital Assistant, PDA), handheld computer, netbook, ultra-mobile personal computer (ultra-mobile personal computer, UMPC), mobile Internet device (Mobile Internet Device, MID), wearable device (Wearable Device) or vehicle-mounted device (vehicle UE, VUE), pedestrian terminal (pedestrian UE, PUE) and other terminal-side devices, wearable devices include: bracelets, headphones, glasses, etc.
  • the network side device 12 may be a base station or a core network, wherein the base station may be referred to as a Node B, an evolved Node B, an access point, a Base Transceiver Station (BTS), a radio base station, a radio transceiver, a basic service Set (Basic Service Set, BSS), Extended Service Set (Extended Service Set, ESS), Node B, Evolved Node B (evolved Node B, eNB), Home Node B, Home Evolved Node B, Wireless Local Area Network (wireless local area network) area network, WLAN) access point, wireless fidelity (WiFi) node, Transmitting Receiving Point (TRP) or some other appropriate term in the field, as long as the same technical effect is achieved, all
  • the base station described above is not limited to the specified technical vocabulary. It should be noted that, in the embodiments of this application, only the base station in the NR system
  • an embodiment of the present application provides a method for processing PUCCH overlap, where the execution subject of the method may be a terminal, and the specific steps include: step 201.
  • Step 201 In the case of overlapping at least two PUCCH transmission resources, multiplex at least two PUCCH transmissions;
  • At least two PUCCHs include: high-priority PUCCHs and low-priority PUCCHs, that is, at least two PUCCHs include: PUCCHs with different priorities.
  • the above at least two PUCCHs include: PUCCHs with different priorities, including:
  • the number of PUCCHs with overlapping resources is two, and the priorities of the two PUCCHs are different.
  • UCI1 and UCI2 can be multiplexed on one PUCCH for transmission , for example, multiplexed for transmission on PUCCH1.
  • PUCCH1 and UCI2 may be the same, or may also be different.
  • the number of PUCCHs with overlapping resources is greater than two (eg, three PUCCHs, four PUCCHs, etc.), at least two PUCCHs have different priorities.
  • At least two PUCCHs include: PUCCH1 carrying UCI1, PUCCH2 carrying UCI2, and PUCCH3 carrying UCI3.
  • PUCCH1, PUCCH2, and PUCCH3 overlap in the time domain, and UCI1 has a higher priority than UCI2, or UCI1 has a higher priority
  • UCI1, UCI2 and UCI3 can be multiplexed on one PUCCH for transmission, for example, multiplexed on PUCCH1.
  • the types of at least two of the above UCI1, UCI2 and UCI3 are different.
  • UCI1 and UCI2 are HARQ-ACK
  • UCI3 is SR.
  • the at least two PUCCHs include: PUCCH1 carrying UCI1, PUCCH2 carrying UCI2, PUCCH3 carrying UCI3, and PUCCH4 carrying UCI4.
  • PUCCH1, PUCCH2, PUCCH3, and PUCCH4 overlap in the time domain, and UCI1 has a higher priority than UCI2.
  • UCI1, UCI2, UCI3 and UCI4 can be multiplexed on one PUCCH for transmission, for example, multiplexed on PUCCH1.
  • the types of at least two of the above UCI1, UCI2, UCI3 and UCI4 are different.
  • UCI1 and UCI2 are HARQ-ACK
  • UCI3 and UCI4 are SR.
  • the above-mentioned multiplexing of at least two PUCCH transmissions refers to multiplexing UCIs borne by PUCCHs of at least two priorities on one PUCCH for transmission. payload) to determine the multiplexed PUCCH to avoid discarding the UCI borne by the low-priority PUCCH, thereby ensuring low-priority service performance.
  • the priority of the PUCCH can be determined by the UCI carried by the PUCCH. For example, the priority of UCI1 is high, the priority of the PUCCH carrying the UCI1 is high, and the priority of UCI2 is low. Then the priority of the PUCCH carrying the UCI2 is low priority. It can be understood that the types of the above UCI1 and UCI2 may be the same, or may also be different.
  • the priority of a PUCCH carrying a high-priority HARQ-ACK (hereinafter referred to as HP HARQ-ACK) is high priority
  • the priority of a PUCCH bearing a low-priority HARQ-ACK (hereinafter referred to as LP HARQ-ACK) level is low priority.
  • the priority of HARQ-ACK is related to the HARQ-ACK codebook (codebook) identifier
  • the first HARQ-ACK codebook is associated with a low-priority PUCCH
  • the second HARQ-ACK codebook is associated with a high-priority PUCCH , that is, the HARQ-ACK priority corresponding to the first HARQ-ACK codebook is low priority
  • the HARQ-ACK priority corresponding to the second HARQ-ACK codebook is high priority.
  • the priority of a PUCCH carrying a high-priority SR (which may be referred to as HP SR) is high priority
  • the priority of a PUCCH carrying a low-priority SR (which may be referred to as LP SR) is low priority.
  • the priority of the SR may be provided to the UE through parameters in the scheduling request resource configuration (SchedulingRequestResourceConfig), such as phy-PriorityIndex-r16. If the priority index of the SR is not provided for the UE, the priority is low priority.
  • SchedulingRequestResourceConfig the scheduling request resource configuration
  • the priority of the PUCCH or UCI may be represented by a priority index, for example, a priority index of 0 indicates a low priority, a priority index of 1 indicates a high priority, or, for example, a priority index of 0 indicates a high priority High priority, a priority index of 1 means low priority.
  • the terminal may multiplex at least two PUCCH transmissions according to the first information; where the first information may include at least one of:
  • PUCCH carries the type of UCI, such as HARQ-ACK, CSI, SR (positive SR (positive SR), negative SR (negative SR)), etc.
  • the priority of the PUCCH for example, the priority of the PUCCH includes a high priority and a low priority, and the priority of the PUCCH can be determined by the priority of the UCI (such as HARQ-ACK, CSI, SR) carried by it, for example, PUCCH1 carrying high-priority HARQ-ACK and PUCCH2 carrying low-priority HARQ-ACK, it can be understood that the priority of PUCCH1 is high priority, and the priority of PUCCH2 is low priority;
  • the priority of the PUCCH1 is high priority
  • the priority of PUCCH2 is low priority
  • PUCCH format for example, PUCCH format 0, PUCCH format 1, PUCCH format 2, PUCCH format 3, and PUCCH format 4.
  • the at least two PUCCHs include at least one of the following:
  • the above-mentioned CSI is CSI with low priority, such as P-CSI or SP-CSI carried on PUCCH.
  • the PUCCH carrying HARQ-ACK includes: a PUCCH carrying a high-priority HARQ-ACK and/or a PUCCH carrying a low-priority HARQ-ACK;
  • the PUCCHs carrying SRs include: M PUCCHs carrying high-priority SRs and/or N PUCCHs carrying low-priority SRs;
  • the type of UCI carried by the PUCCH, the priority of the PUCCH, and/or the format of the PUCCH are used to determine the multiplexing mode of at least two PUCCH transmissions, and then the at least two PUCCH transmissions are performed according to the determined multiplexing mode.
  • Multiplexing avoids that when at least two PUCCH transmission resources overlap, low-priority UCIs will be discarded, resulting in the problem of increasing the delay of the UCI transmission.
  • At least two PUCCHs can include the following four cases:
  • the PUCCH1 and PUCCH2 overlap in the time domain.
  • Case (2) PUCCH1 carrying high-priority HARQ-ACK, PUCCH2 carrying low-priority HARQ-ACK, and M PUCCH resources 3 carrying high-priority SR;
  • the PUCCH1, PUCCH2 and PUCCH3 overlap in the time domain.
  • Case (3) PUCCH1 carrying high-priority HARQ-ACK, PUCCH2 carrying low-priority HARQ-ACK, and N PUCCH4 carrying low-priority SR;
  • the PUCCH1, PUCCH2 and PUCCH4 overlap in the time domain.
  • Case (4) PUCCH1 carrying high priority HARQ-ACK, PUCCH2 carrying low priority HARQ-ACK, M PUCCH3 carrying high priority SR and N PUCCH3 carrying low priority SR.
  • the PUCCH1, PUCCH2, PUCCH3 and PUCCH4 overlap in the time domain.
  • the M PUCCHs carrying high-priority SRs or the N PUCCHs carrying low-priority SRs refer to the PUCCHs of each SR in the time slot determined by a set of scheduling request resource identifiers (scheduleRequestResourceId), and the M PUCCHs carrying high-priority SRs
  • the PUCCH of the priority SR or the N PUCCHs carrying the low-priority SR correspond to M SR configurations or N SR configurations, respectively, where the SR transmission timing may be the same as the transmission of the PUCCH carrying the HARQ-ACK information in the time slot or the same time.
  • the transmission of the PUCCH carrying the CSI report in the slot overlaps.
  • the M SR PUCCH or N SR PUCCH resources may or may not overlap.
  • the UE multiplexes high-priority HARQ-ACK and low-priority HARQ-ACK on PUCCH1 for transmission.
  • the PUCCH1 is determined according to the number of bits of the high-priority HARQ-ACK and the number of bits of the low-priority HARQ-ACK.
  • the UE preferentially handles the conflict between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK. For example, the UE determines that the multiplexed PUCCH is PUCCH1 according to the number of HP HARQ-ACK and LP HARQ-ACK bits. If the multiplexed PUCCH1 and the PUCCH carrying the HP SR, the UE reprocesses the conflict between the PUCCH1 and the PUCCH carrying the HP SR, for example, according to the existing HARQ-ACK and SR conflict processing principles, or according to Mode 2.
  • the UE multiplexes the high-priority HARQ-ACK, the low-priority HARQ-ACK, and M high-priority SRs on the second PUCCH.
  • the second PUCCH is determined according to the number of bits of high-priority HARQ-ACK, the number of bits of low-priority HARQ-ACK, and the number of bits of M high-priority SRs. Further, the second PUCCH is determined according to the number of bits of high-priority HARQ-ACK.
  • the priority HARQ-ACK, the low priority HARQ-ACK, and the log 2 (1+M) number of bits representing M high priority SRs are determined.
  • the UE preferentially handles the conflict between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK. For example, the UE determines that the multiplexed PUCCH is PUCCH1 according to the number of HP HARQ-ACK and LP HARQ-ACK bits. If the multiplexed PUCCH1 and the PUCCH carrying the LP SR, the UE reprocesses the conflict between the PUCCH1 and the PUCCH carrying the LP SR, for example, according to the existing HARQ-ACK and SR conflict processing principles, or according to Mode 2.
  • the UE multiplexes the high-priority HARQ-ACK, the low-priority HARQ-ACK, and the N low-priority SRs on the second PUCCH.
  • the second PUCCH is determined according to the number of bits of high-priority HARQ-ACK, the number of bits of low-priority HARQ-ACK, and the number of bits of N low-priority SRs.
  • the number of bits of the priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, and the number of log 2 (1+N) bits representing N low-priority SRs are determined.
  • the ways of multiplexing PUCCH transmission with different priorities include: way 1 and way 2.
  • the UE preferentially handles the conflict between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK. For example, the UE determines that the multiplexed PUCCH is PUCCH1 according to the number of HP HARQ-ACK and LP HARQ-ACK bits. If the multiplexed PUCCH1 collides with the PUCCH carrying the HP SR and the PUCCH carrying the LRSR, the UE re-processes the conflict between the PUCCH1 and the PUCCH carrying the HP SR and the PUCCH carrying the LRSR, for example, according to the conflict between the existing HARQ-ACK and SR Processing according to the principle of processing, or processing according to method 2.
  • Mode 1 includes:
  • the UE multiplexes the PUCCH carrying the high-priority HARQ-ACK with the PUCCH carrying the low-priority HARQ-ACK to obtain the first PUCCH; if the first PUCCH overlaps with M' PUCCHs carrying the high-priority SR, then Multiplexing the first PUCCH with M' PUCCH transmissions carrying high-priority SRs; wherein, the first PUCCH is determined by the number of bits of the high-priority HARQ-ACK and the number of bits of the low-priority HARQ-ACK , where M' is equal or unequal to M.
  • the HARQ-ACK and LP HARQ-ACK overlap with M SRs before multiplexing, and the first PUCCH after multiplexing does not necessarily overlap with M SRs, but may overlap with M' SRs, where M' may overlap. Not equal to M, because the time domain resource of the first PUCCH may be different from the time domain resource of the PUCCH of the HP/LP.
  • the UE multiplexes the PUCCH carrying the high-priority HARQ-ACK with the PUCCH carrying the low-priority HARQ-ACK to obtain the first PUCCH; if the first PUCCH and N' PUCCHs carrying the low-priority SR Overlapping, the first PUCCH is multiplexed with the N' SR configuration PUCCHs carrying low priority, where N' and N are equal or unequal;
  • the UE multiplexes the PUCCH carrying the high-priority HARQ-ACK with the PUCCH carrying the low-priority HARQ-ACK to obtain the first PUCCH; if the first PUCCH is combined with M' PUCCHs carrying the high-priority SR and N' PUCCHs carrying low-priority SRs overlap, the first PUCCH is multiplexed with M' PUCCHs carrying high-priority SRs and N' PUCCHs carrying low-priority SRs, where the N' Equal or unequal to N, the M' is equal or unequal to M.
  • the UE multiplexes HP HARQ-ACK, LP HARQ-ACK and HP SR and/or LRSR on one PUCCH, for example, the UE determines according to the number of bits of HP HARQ-ACK, LP HARQ-ACK, and HP SR and/or LRSR The multiplexed PUCCH.
  • mode 2 includes:
  • UE multiplexes high-priority HARQ-ACK, low-priority HARQ-ACK, and M high-priority SRs on the second PUCCH;
  • the second PUCCH is determined according to the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, and the number of bits of the M high-priority SRs, where the number of bits of the M high-priority SRs is is: log 2 (1+M);
  • the HP HARQ-ACK, LP HARQ-ACK and HP SR are multiplexed on one PUCCH, for example, the UE multiplexes the HP HARQ-ACK, LP HARQ-ACK and M HP SRs on the second PUCCH, or the UE
  • the multiplexed PUCCH is determined according to the multiplexed HP HARQ-ACK, the LP HARQ-ACK and the number of bits of the M HP SRs, where the number of bits of the M HP SRs is log 2 (1+M).
  • the second PUCCH is determined according to the number of bits of high-priority HARQ-ACK, the number of bits of low-priority HARQ-ACK, and the number of bits of N low-priority SRs; wherein, the number of bits of N low-priority SRs is: log 2 (1+N).
  • the HP HARQ-ACK, LP HARQ-ACK and N LP SRs are multiplexed on one PUCCH, for example, the UE multiplexes HP HARQ-ACK, LP HARQ-ACK and N LP SRs on the second PUCCH, Or the UE determines the multiplexed PUCCH according to the multiplexed HP HARQ-ACK, LP HARQ-ACK and the number of bits of the N LP SRs, and the number of bits of the N LP SRs is log 2 (1+N) bits.
  • the UE multiplexes the high-priority HARQ-ACK, the low-priority HARQ-ACK, and the M high-priority SRs and N low-priority SRs on the second PUCCH.
  • the second PUCCH is determined according to the number of bits of high-priority HARQ-ACK, the number of bits of low-priority HARQ-ACK, the number of bits of M high-priority SRs and N low-priority SRs;
  • the number of bits of the M high-priority SRs and the N low-priority SRs is: the sum of log 2 (1+M) and log 2 (1+N), or log 2 (1+M+N).
  • the HP HARQ-ACK, LP HARQ-ACK, HP SR and LP SR are multiplexed on one PUCCH, for example, the UE multiplexes HP HARQ-ACK, LP HARQ-ACK, HP SR and LP SR on the second PUCCH or the UE determines the multiplexed PUCCH according to the bits of the multiplexed HP HARQ-ACK, LP HARQ-ACK, M HP SRs and N LP SRs, and the bits of the M HP SRs and N LP SRs are : log 2 (1 + M) and log 2 (1 + N) sum (where log 2 (1 + M) and log 2 (1 + N) bits correspond to the M SR and N SR), or log 2 (1+M+N).
  • Scenario 2 Includes example 1 and example 2.
  • Example 1 introduces the multiplexing method that the UE can use when the CSI or HARQ-ACK PUCCH formats PUCCH2/3/4 and the UE supports multiplexing between PUCCHs with different priorities.
  • Example 2 describes: when the format of the PUCCH carrying the HARQ-ACK with high priority or low priority is PUCCH format 0/1, and the UE supports multiplexing between PUCCHs with different priorities, the UE can use the complex format. use method.
  • At least two PUCCHs can include the following ten situations:
  • the PUCCH1, PUCCH2 and PUCCH3 overlap in the time domain.
  • the format of the PUCCH carrying the HARQ-ACK with high priority is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • the PUCCH1, PUCCH2 and PUCCH3 overlap in the time domain.
  • Case (3) PUCCH1 carrying low-priority HARQ-ACKs, M PUCCH2s carrying high-priority SRs, and N PUCCH3s carrying low-priority SRs;
  • the PUCCH1, PUCCH2 and PUCCH3 overlap in the time domain.
  • the PUCCH1, PUCCH2, PUCCH3 and PUCCH4 overlap in the time domain.
  • the PUCCH1, PUCCH2, PUCCH3, PUCCH4 and PUCCH5 overlap in the time domain.
  • Case (6) PUCCH resources carrying CSI, PUCCH resources carrying high-priority HARQ-ACK, M PUCCH resources carrying high-priority SRs, and N PUCCH resources carrying low-priority SRs;
  • Case (7) PUCCH resources that carry CSI, PUCCH resources that carry low-priority HARQ-ACK, M PUCCH resources that carry high-priority SRs, and N PUCCH resources that carry low-priority SRs;
  • the PUCCH1 and PUCCH2 overlap in the time domain.
  • the PUCCH1 and PUCCH2 overlap in the time domain.
  • the UE places M high-priority SRs on the PUCCH carrying the CSI.
  • log 2 (1+M) bits representing M high-priority SRs are multiplexed on the PUCCH carrying the CSI.
  • Example 1 In scenario 2, if the format of CSI or HARQ-ACK PUCCH is PUCCH2/3/4, if the UE supports multiplexing between PUCCHs with different priorities, the UE can combine the above cases (1) to (7) In the case of overlapping PUCCHs, the following multiplexing method is adopted.
  • the UE multiplexes M high-priority SRs and N low-priority SRs on the PUCCH carrying CSI.
  • bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI, that is, the PUCCH carries
  • the bit order of UCI can be: HP SR ⁇ LP SR ⁇ CSI.
  • the UE multiplexes the M high-priority SRs and N low-priority SRs on the PUCCH carrying the high-priority HARQ-ACK.
  • log 2 (1+M) bits representing M high-priority SRs and log 2 (1+N) bits representing N low-priority SRs are multiplexed on the HARQ-ACK carrying the high-priority SRs.
  • the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs are multiplexed on the PUCCH carrying the high-priority HARQ-ACK.
  • bit position of the high-priority HARQ-ACK is located before the bit position of the high-priority SR
  • the bit position of the high-priority SR is located before the bit position of the low-priority SR, that is, the bit order of the UCI carried by the PUCCH can be : HP HARQ-ACK ⁇ HP SR ⁇ LP SR.
  • the UE multiplexes the M high-priority SRs and N low-priority SRs on the PUCCH carrying the low-priority HARQ-ACK;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • the UE multiplexes log 2 (1+M) bits representing M high-priority SRs and log 2 (1+N) bits representing N low-priority SRs on PUCCH carrying low-priority HARQ-ACK
  • bit positions of the M high-priority SRs are located before the bit positions of the low-priority HARQ-ACKs, and the bit positions of the low-priority HARQ-ACKs are located before the N low-priority SRs.
  • bit position that is, the bit order of the UCI carried by the PUCCH may be: HP SR ⁇ LP HARQ-ACK ⁇ LP SR.
  • the modes of PUCCH transmission multiplexing include mode 1, mode 2 and mode 3.
  • Mode 1 The UE multiplexes M high-priority SRs, N low-priority SRs, and the low-priority HARQ-ACK on the PUCCH carrying the high-priority HARQ-ACK;
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 (1 + N) bits, the low priority the HARQ-ACK bits multiplexed in the bearer On the PUCCH of the high-priority HARQ-ACK; alternatively, the UE will indicate log 2 (1+M+N) bits of M high-priority SRs and N low-priority SRs, and the low-priority HARQ-ACK bits, multiplexed on the PUCCH carrying the high-priority HARQ-ACK.
  • Mode 2 The UE multiplexes the M high-priority SRs, the N low-priority SRs, and the high-priority HARQ-ACK on the PUCCH carrying the low-priority HARQ-ACK;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • the UE For example, the UE indicating (1 + N) bits, the high priority number of bits of the HARQ-ACK M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 multiplexed in the bearer On the PUCCH of the low-priority HARQ-ACK; or, the UE will indicate log 2 (1+M+N) bits of M high-priority SRs and N low-priority SRs, and high-priority HARQ-ACK bits are multiplexed on the PUCCH carrying the low-priority HARQ-ACK.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located in the low-priority HARQ-ACK.
  • bit position of the low-priority HARQ-ACK is located before the bit positions of the N low-priority SRs, that is, the bit order of the UCI carried by the PUCCH may be: HP HARQ-ACK ⁇ HP SR ⁇ LP HARQ -ACK ⁇ LPSR.
  • bit position of the high-priority HARQ-ACK is located before the bit position of the low-priority HARQ-ACK, and the bit position of the low-priority HARQ-ACK is located in the bit positions of the M high-priority SRs Previously, the bit positions of the M high-priority SRs were located before the bit positions of the N low-priority SRs.
  • the third PUCCH is determined based on the number of bits of the M high-priority SRs, the number of bits of the N low-priority SRs, the number of bits of the high-priority HARQ-ACK, and the number of bits of the low-priority HARQ-ACK of
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 (1 + N) bits, the high priority HARQ-ACK bits of low priority HARQ -ACK bits are multiplexed on the third PUCCH; alternatively, the UE will represent the log 2 (1+M+N) bits of the high-priority HARQ-ACK bits of the M high-priority SRs and the N low-priority SRs, The low priority HARQ-ACK bits are multiplexed on the third PUCCH.
  • the ways of PUCCH multiplexing include way 1, way 2 and way 3.
  • Mode 1 The UE multiplexes the M high-priority SRs, the N low-priority SRs, the low-priority HARQ-ACK, and the CSI on the HARQ-ACK bearing the high-priority on PUCCH;
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 (1 + N) bits, the low priority the HARQ-ACK bits, bit multiplexing of CSI Used on the PUCCH carrying the high-priority HARQ-ACK; alternatively, the UE shall represent log 2 (1+M+N) bits of M high-priority SRs and N low-priority SRs, low-priority HARQ - ACK bits and CSI bits are multiplexed on the PUCCH carrying the high-priority HARQ-ACK.
  • Mode 2 The UE multiplexes the M high-priority SRs, the N low-priority SRs, the high-priority HARQ-ACK, and the CSI on the PUCCH carrying the low-priority HARQ-ACK ;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 (1 + N) bits, the high priority the HARQ-ACK bits, bit multiplexing of CSI Used on the PUCCH carrying the low-priority HARQ-ACK; alternatively, the UE shall represent log 2 (1+M+N) bits of M high-priority SRs and N low-priority SRs, high-priority HARQ - ACK bits and CSI bits are multiplexed on the PUCCH carrying the low-priority HARQ-ACK.
  • Manner 3 The UE multiplexes the M high-priority SRs, the N low-priority SRs, the high-priority HARQ-ACK and the low-priority HARQ-ACK on the PUCCH carrying CSI.
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 (1 + N) bits, the high priority HARQ-ACK bits of low priority HARQ -
  • the bits of the ACK are multiplexed on the PUCCH carrying the CSI; alternatively, the UE will represent the log 2 (1+M+N) bits of the M high-priority SRs and N low-priority SRs, high-priority HARQ-ACK , bits of high-priority HARQ-ACK, and bits of low-priority HARQ-ACK are multiplexed on the PUCCH carrying CSI.
  • the Four PUCCH is based on the number of bits of the M high-priority SRs, the number of bits of the N low-priority SRs, the number of bits of the high-priority HARQ-ACK, the bits of the low-priority HARQ-ACK. The number of bits and the number of CSI bits are determined.
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, N low-priority SR of log 2 (1 + N) bits, the high priority HARQ-ACK bits of low priority HARQ -The bits of the ACK and the bits of the CSI are multiplexed on the fourth PUCCH; or, the UE will represent the log 2 (1+M+N) bits of the M high-priority SRs and the N low-priority SRs, the high The bits of the priority HARQ-ACK, the bits of the high priority HARQ-ACK, the bits of the low priority HARQ-ACK, and the bits of the CSI are multiplexed in the fourth PUCCH.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located in the low-priority HARQ-ACK.
  • bit position of the low-priority HARQ-ACK is located before the bit position of the N low-priority SRs, and the bit position of the N low-priority SRs is located before the bit position of the CSI, that is,
  • the bit order of the UCI carried by the PUCCH may be: HP HARQ-ACK ⁇ HP SR ⁇ LP HARQ-ACK ⁇ LP SR ⁇ CSI.
  • bit position of the high-priority HARQ-ACK is located before the bit position of the low-priority HARQ-ACK, and the bit position of the low-priority HARQ-ACK is located in the bit positions of the M high-priority SRs Before, the bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI.
  • Example 1 of Scenario 2 if the high-priority or low-priority HARQ-ACK contains feedback on PDSCH scheduled with PDCCH, the UE may combine the PUCCH overlap in the above case (2), case (3), and case (4) , use the following multiplexing method:
  • Mode 1 If a high priority HARQ-ACK feedback comprising the PDCCH scheduling the PDSCH, and then indicates (1 + M) log 2 M bits high priority SR, and N number of low priority log 2 SR (1+N) bits, or log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs, multiplexed with the high-priority HARQ-ACK in the fifth PUCCH;
  • the fifth PUCCH is based on: M represents a high priority SR number of log 2 (1 + M) bits indicates (1 + N) of the N bits of low priority log SR 2, and the high
  • the number of bits of the priority HARQ-ACK is determined (that is, the PUCCH determined in multiple PUCCH sets configured by the RRC based on the above-mentioned number of bits), or, log 2 ( 1+M+N) the number of bits, and the number of bits of the high-priority HARQ-ACK.
  • Embodiment 2 If low priority HARQ-ACK feedback comprising the PDCCH scheduling the PDSCH, and then indicates (1 + M) log 2 M bits high priority SR, and N number of low priority log 2 SR (1+N) bits, or log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs, multiplexed with the low-priority HARQ-ACK the fifth PUCCH;
  • the fifth PUCCH is based: that (1 + M) bit number M of the high-priority SR log 2, represents a (1 + N) of the N bits of low priority SR log 2, and the low
  • the number of bits of the priority HARQ-ACK is determined, or, the log 2 (1+M+N) bits representing the M high-priority SRs and the N low-priority SRs, and the number of bits of the low-priority HARQ-ACK number of bits
  • Mode 3 If the high-priority HARQ-ACK and low-priority HARQ-ACK contain feedback on PDSCH scheduled by PDCCH, then log 2 (1+M) bits representing M high-priority SRs, and N The log 2 (1+N) number of bits of low priority SRs , or, will represent the log 2 (1+M+N) number of bits of M high priority SRs and N low priority SRs, with the high priority
  • the high-level HARQ-ACK and the low-priority HARQ-ACK are multiplexed in the fifth PUCCH.
  • the fifth PUCCH is based: that (1 + M) bit number M of the high-priority SR log 2, represents a (1 + N) of the N bits of low priority SR log 2, the high priority It is determined by the number of bits of the high-level HARQ-ACK and the number of bits of the low-priority HARQ-ACK, or, the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs , the number of bits of the high-priority HARQ-ACK and the number of bits of the low-priority HARQ-ACK are determined.
  • Example 2 If the format of the PUCCH carrying high-priority or low-priority HARQ-ACK is PUCCH format 0/1, and if the UE supports multiplexing between PUCCHs with different priorities, the UE can combine the PUCCH overlapping in the above case. In this case, the following multiplexing method is used.
  • Mode 1 includes (1) to (5):
  • the at least two PUCCHs include: PUCCHs carrying high-priority or low-priority HARQ-ACKs, and M PUCCHs carrying high-priority SRs;
  • the UE multiplexes the first SR on the PUCCH carrying the high-priority or low-priority HARQ-ACK, where the first SR is any one of the M high-priority SRs (positive SR),
  • the format of the PUCCH carrying high-priority or low-priority HARQ-ACK is PUCCH format 0;
  • the at least two PUCCHs include: PUCCHs carrying HARQ-ACKs of high priority or low priority, and N PUCCHs carrying SRs of low priority;
  • the UE multiplexes the second SR on the PUCCH carrying the high-priority or low-priority HARQ-ACK, where the second SR is any positive SR among N low-priority SRs, carrying high-priority SRs.
  • the format of the PUCCH of the priority or low priority HARQ-ACK is PUCCH format 0;
  • the at least two PUCCHs include: PUCCHs carrying high-priority or low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the third SR is any one of the M high-priority SRs and the N low-priority SRs
  • the format of the PUCCH carrying the high-priority or low-priority HARQ-ACK is PUCCH format 0.
  • the UE will replay the positive SR. Used for transmission on HP/LP HARQ-ACK PUCCH.
  • the high-priority SR and the low-priority SR use different Cyclic Shift (CS).
  • the UE preferentially transmits the high-priority SR.
  • the at least two PUCCHs include: a PUCCH carrying a low-priority HARQ-ACK, and M PUCCHs carrying a high-priority SR;
  • the UE multiplexes the low-priority HARQ-ACK on the PUCCH carrying the positive SR;
  • the format of the PUCCH bearing the low-priority HARQ-ACK is PUCCH format 1
  • the format of the PUCCH bearing the positive SR is PUCCH format 1
  • the positive SR is any one of M high-priority SRs .
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, and N PUCCHs carrying a low-priority SR;
  • the UE multiplexes the high-priority HARQ-ACK on the PUCCH carrying the positive SR;
  • the format of the PUCCH bearing the high-priority HARQ-ACK is PUCCH format 1
  • the format of the PUCCH bearing the positive SR is PUCCH format 1
  • the positive SR is any one of N low-priority SRs
  • the bearing HP/LP HARQ-ACK PUCCH is PUCCH format 1
  • the SR of any HP/LP PUCCH format 1 is positive SR
  • the HP SR without PUCCH format 0 is positve
  • the UE transmits the positive SR, cancels the HARQ-ACK PUCCH transmission, otherwise The UE transmits the HARQ-ACK PUCCH and does not transmit the SR.
  • Mode 2 includes: (1) to (6)
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, and N low priority SR of log 2 (1 + N) bits, or, representing the M high priority SR and N low
  • the log 2 (1+M+N) bits of the priority SR are multiplexed with the bits of the high-priority HARQ-ACK on the seventh PUCCH, wherein the high-priority HARQ-ACK contains the Feedback wherein, the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1.
  • the at least two PUCCHs PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, and N low priority SR of log 2 (1 + N) bits, or, representing the M high priority SR and N low
  • the log 2 (1+M+N) bits of the priority SR are multiplexed on the seventh PUCCH with the bits of the low priority HARQ-ACK, where the low priority HARQ-ACK contains feedback on the PDSCH scheduled by the PDCCH
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1.
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the UE indicating that the M high priority SR of log 2 (1 + M) bits, and N low priority SR of log 2 (1 + N) bits, or, representing the M high priority SR and N low log 2 (1+M+N) bits of the priority SR, multiplexed with the high-priority HARQ-ACK and low-priority HARQ-ACK bits on the seventh PUCCH, where the high-priority HARQ-ACK and The low-priority HARQ-ACK includes feedback on the PDSCH scheduled by the PDCCH, wherein the format of the PUCCH carrying the high-priority HARQ-ACK low-priority HARQ-ACKs is PUCCH format 0 or PUCCH format 1.
  • the above-mentioned seventh PUCCH is determined based on the number of bits of the multiplexed HARQ-ACK and SR, and the specific manner of determining the seventh PUCCH may refer to the manner of determining the fifth PUCCH.
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the M high priority SR of log 2 (1 + M) bits, and N low priority SR of log 2 (1 + N) bits, or, representing the M high priority SR and N The log 2 (1+M+N) bits of the low-priority SR are multiplexed with the high-priority HARQ-ACK on the sixth PUCCH; wherein the high-priority HARQ-ACK does not include the feedback, and the terminal is configured with an SPS HARQ-ACK feedback PUCCH list; wherein, the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1;
  • the at least two PUCCHs PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the log 2 (1+M+N) bits of the low-priority SR are multiplexed with the low-priority HARQ-ACK on the sixth PUCCH, where the low-priority HARQ-ACK does not include the PDSCH scheduled with the PDCCH feedback, and the terminal is configured with SPS HARQ-ACK feedback PUCCH list;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1;
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the UE shall represent log 2 (1+M) bits of M high priority SRs and log 2 (1+N) bits of N low priority SRs, or, shall represent M high priority SRs and
  • the log 2 (1+M+N) bits of the N low-priority SRs are multiplexed with the high-priority HARQ-ACK and the low-priority HARQ-ACK on the sixth PUCCH, where the high-priority HARQ - Neither ACK nor low-priority HARQ-ACK contains feedback on PDSCH scheduled with PDCCH, and the terminal is configured with an SPS HARQ-ACK feedback PUCCH list;
  • the format of the PUCCH carrying the high-priority HARQ-ACK and the low-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1.
  • the above-mentioned sixth PUCCH is determined based on the number of bits of the multiplexed HARQ-ACK and SR, and the specific manner of determining the sixth PUCCH may refer to the manner of determining the fifth PUCCH.
  • the transmission of CSI, HP SR and LP SR can be ensured, which improves the effectiveness of the communication system.
  • the formats of the PUCCH carrying LP HARQ-ACK and the PUCCH carrying HP HARQ-ACK are both PUCCH format 1 (referred to as PF1), that is, LP HARQ-ACK PF1 and HP HARQ-ACK PF1 in the figure
  • PUCCH format 1 referred to as PF1
  • PF0 the format of the PUCCH carrying the HP SR
  • the three PUCCHs shown in the figure overlap each other in the time domain. If the UE first handles the overlap between PUCCHs of the same priority, that is, the PUCCH carrying HP HARQ-ACK and the PUCCH carrying HP SR, the current According to the conflict handling rules of HARQ-ACK and SR, the UE will only transmit HP HARQ-ACK, but not HP SR. The overlap between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK is then handled. At this time, even if multiplexing between PUCCHs with different priorities is supported, the HP SR is discarded in the first step, thus affecting the transmission of the HP SR.
  • the format of the PUCCH carrying LP HARQ-ACK is PUCCH format 1, that is, the LP HARQ-ACK PF1 in the figure
  • the format of the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP SR are PUCCH format 0 , namely HP HARQ-ACK PF0 and LP SR PF0 in the figure.
  • the three PUCCH time domain resources shown in the figure overlap each other. If the UE first handles the overlap between PUCCHs of the same priority, that is, the PUCCH carrying LP HARQ-ACK and the PUCCH carrying LP SR, the existing HARQ-ACK will be processed according to the existing HARQ-ACK. According to the conflict handling rules of SR, the UE will only transmit LP HARQ-ACK, but not LP SR. The overlap between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK is then handled. At this time, even if multiplexing between uplink transmissions with different priorities is supported, the LP SR is discarded in the first step, which will affect the transmission of the LP SR.
  • the format of PUCCH carrying LP HARQ-ACK is PUCCH format 1
  • the format of PUCCH carrying HP HARQ-ACK is PUCCH format 1, that is, LP HARQ-ACK PF1 in the figure, HP HARQ-ACK PF1
  • the formats of the PUCCH carrying HP SR and the PUCCH carrying LP SR are both PUCCH format 0, namely HP SR PF0 and LP SR PF0 in the figure.
  • the four PUCCH time domain resources shown in the figure overlap each other. If the UE processes the overlap between PUCCHs of the same priority first, then according to the existing HARQ-ACK and SR conflict handling rules, the UE will only transmit HP HARQ-ACK and LP HARQ-ACK without transmitting HP SR and LP SR. The overlap between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK is then handled. At this time, even if multiplexing between upstream transmissions with different priorities is supported, LP SR and HP SR are discarded in the first step, thus affecting the transmission of LP SR and HP SR.
  • the format of PUCCH carrying LP HARQ-ACK is PUCCH format 1
  • the format of PUCCH carrying HP HARQ-ACK is PUCCH format 0, that is, LP HARQ-ACK PF1 in the figure, HP HARQ-ACK PF0
  • the format of the PUCCH carrying the LP SR is PUCCH format 0, that is, the LP SR PF0 in the figure.
  • the three PUCCH time-domain resources shown in the figure overlap each other. If the UE handles the overlap between PUCCHs with the same priority first, then according to the existing HARQ-ACK and SR conflict handling rules, the UE will only transmit LP HARQ-ACK , without transmitting the LP SR. The overlap between the PUCCH carrying HP HARQ-ACK and the PUCCH carrying LP HARQ-ACK is then handled. At this time, even if multiplexing between uplink transmissions with different priorities is supported, the LP SR is discarded in the first step, which will affect the transmission of the LP SR.
  • PUCCH conflict handling methods In order to prevent the UE from discarding the HP SR or LP SR and only transmit the HP HARQ-ACK and LP HARQ-ACK, the following PUCCH conflict handling methods can be defined:
  • M and N are positive integers.
  • Mode 1 The UE preferentially handles the conflict between the PUCCH carrying the HP HARQ-ACK and the PUCCH carrying the LP HARQ-ACK.
  • the used PUCCH is PUCCH1.
  • the UE will then process the conflict between the two PUCCHs, for example, according to the existing conflict handling principle between HARQ-ACK PUCCH and SR PUCCH, or according to the method of Mode 2 deal with.
  • UE multiplexes HP HARQ-ACK, LP HARQ-ACK and M HP SRs on one PUCCH for example, UE multiplexes HP HARQ-ACK, LP HARQ-ACK and the number of bits representing M HP SRs Determine the multiplexed PUCCH.
  • the number of bits of HP SR is: log 2 (1+M) number of bits.
  • the number of bits of the LP SR is: log 2 (1+N) number of bits.
  • the UE multiplexes HP HARQ-ACK, LP HARQ-ACK, M HP SRs and N LP SRs on one PUCCH, for example, according to the number of bits of the multiplexed HP HARQ-ACK, the LP HARQ-ACK
  • the number of bits, the number of bits representing the M HP SRs, and the number of bits representing the N LP SRs determine the multiplexed PUCCH.
  • the number of bits of M HP SRs and the number of bits representing N LP SRs are: log 2 (1+N+M) bits, or, log 2 (1+M)+log 2 (1+N) number of bits.
  • a CSI/HARQ-ACK PUCCH overlaps with two SR PUCCHs, where the SR includes HP SR and LP SR.
  • the HARQ-ACK PUCCH may be the HP HARQ-ACK PUCCH or the LP HARQ-ACK PUCCH.
  • the CSI/HARQ-ACK PUCCH is PUCCH format 2/3/4, that is, the CSI PUCCH PF2/3/4 and the HARQ-ACK PUCCH PF2/3/4 shown in the figures.
  • the UE when the PUCCH carrying CSI, or the PUCCH carrying LP HARQ-ACK in the format of PUCCH format 2/3/4 overlaps with N PUCCHs carrying LP SR, regardless of whether the LP SR is a positive SR (positive SR) Or negative SR (negative SR), the UE multiplexes log 2 (1+N) bits representing N LP SR states on the PUCCH carrying CSI, or multiplexing them on the PUCCH carrying LP HARQ-ACK for transmission.
  • the UE will Cancel lower priority CSI or LP HARQ-ACK transmissions. Therefore, it will have a greater impact on the transmission of CSI or LP HARQ-ACK with lower priority.
  • Mode 1 log UE representing the M HP the SR state log 2 (1 + M) bits ( 'bit), and N LP SR state 2 (1 + N) bit multiplexed in a PUCCH carrying CSI or bearer HP /LP HARQ-ACK is transmitted on the PUCCH.
  • the bit sequence of the UCI carried by it may be HP SR ⁇ LP SR ⁇ CSI.
  • the bit sequence of the UCI carried by it may be HP HARQ-ACK ⁇ HP SR ⁇ LP SR.
  • the bit sequence of the UCI carried by it can be HP SR ⁇ LP HARQ-ACK ⁇ LP SR or LP HARQ-ACK ⁇ HP SR ⁇ LP SR
  • the bit order of UCI carried on the multiplexed PUCCH may be: HP HARQ- ACK ⁇ HP SR ⁇ LP HARQ-ACK ⁇ LP SR( ⁇ CSI) or HP HARQ-ACK ⁇ LP HARQ-ACK ⁇ HP SR ⁇ LP SR( ⁇ CSI).
  • Mode 2 The UE multiplexes log 2 (1+M) bits representing M LP SR states, and log 2 (1+N) bits representing N LP SR states and HARQ-ACK on one PUCCH for transmission.
  • the PUCCH Determined based on the number of bits of the multiplexed HARQ-ACK and SR.
  • the format of the PUCCH carrying HARQ-ACK is PUCCH format 0/1.
  • the PUCCH carrying HARQ-ACK and N When the PUCCHs carrying the LP SR overlap, the UE multiplexes N LP SRs onto the PUCCH carrying the HARQ-ACK for transmission. If the LP SR is a negative SR, the cyclic shift (Cyclic Shift) used in transmission is the same as the HARQ-only transmission.
  • -Same for ACK if any LP SR is a positive SR, the UE transmits LP SR and HARQ-ACK using different cyclic shifts (the same as when only HARQ-ACK is transmitted).
  • the UE When the PUCCH of the HARQ-ACK with the format of PUCCH format 1 overlaps with N PUCCHs carrying the LP SR, if the LP SR carried by any PUCCH with the format of PUCCH format 1 is a positive SR, the UE multiplexes the HARQ-ACK to It is transmitted on the PUCCH carrying the SR. If the format of the PUCCH carrying the positive SR is PUCCH format 0, the UE only transmits the HARQ-ACK and discards the SR. If the priorities are different, the UE discards the PUCCH with low priority and only transmits the uplink transmission with high priority.
  • the UE can use the following multiplexing methods:
  • the UE multiplexes the positive SR in the Transmission on PUCCH carrying HARQ-ACK;
  • the UE may use different CSs when transmitting the HP SR and the LP SR on the PUCCH bearing the HARQ-ACK.
  • the UE transmits the HP SR first.
  • the format of the PUCCH carrying HARQ-ACK (HP HARQ-ACK and/or LP HARQ-ACK) is PUCCH format 1
  • the HP SR and/or LP SR carried by the PUCCH whose format is PUCCH format 1 is positive SR
  • the UE multiplexes the HARQ-ACK on the PUCCH carrying the positive SR for transmission;
  • the UE If the HP SR carried by the PUCCH whose format is PUCCH format 0 is positive SR, and the conflicting PUCCH carries the LP HARQ-ACK, the UE transmits the positive SR and cancels the LP HARQ-ACK transmission, otherwise the UE transmits the LP HARQ-ACK PUCCH, and does not Transmit positive SR.
  • the UE shall represent log 2 (1+M) bits of M LP SR states, and log 2 (1+N) bits representing N LP SR states and HARQ-
  • the ACK is multiplexed and transmitted on one PUCCH, which is determined based on the number of bits of the multiplexed HARQ-ACK and SR.
  • the UE will represent the log 2 (1+M) bits of M LP SR states, and represent N LP SRs
  • the log 2 (1+N) bits of the state and the HARQ-ACK are multiplexed for transmission on one PUCCH, and the PUCCH is determined based on the number of bits of the multiplexed HARQ-ACK and SR; otherwise, mode 1 may be used.
  • an embodiment of the present application provides an apparatus for processing PUCCH resource overlap, which is applied to a terminal, and the apparatus 500 includes:
  • a processing module 501 configured to multiplex the at least two PUCCH transmissions when the at least two PUCCH transmission resources overlap;
  • the at least two PUCCHs include: a high-priority PUCCH and a low-priority PUCCH.
  • the processing module 501 is further configured to: multiplex the at least two PUCCH transmissions according to the first information;
  • the first information includes at least one of the following:
  • PUCCH bears the type of uplink control information
  • the at least two PUCCHs include at least one of the following:
  • the PUCCH carrying HARQ-ACK includes: a PUCCH carrying a high-priority HARQ-ACK and/or a PUCCH carrying a low-priority HARQ-ACK;
  • the PUCCHs carrying SRs include: M PUCCHs carrying high-priority SRs and/or N PUCCHs carrying low-priority SRs;
  • the at least two PUCCHs include: a PUCCH bearing a high-priority HARQ-ACK, a PUCCH bearing a low-priority HARQ-ACK, and M PUCCHs bearing a high-priority SR;
  • the processing module 501 is further configured to: multiplex the PUCCH bearing the high-priority HARQ-ACK with the PUCCH bearing the low-priority HARQ-ACK to obtain the first PUCCH;
  • the first PUCCH overlaps with M' PUCCHs carrying high-priority SRs, the first PUCCH is multiplexed with the M' high-priority SR-carrying PUCCHs, where M' and M equal or unequal;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and N' PUCCHs carrying a low-priority SR;
  • the processing module 501 is further configured to: multiplex the PUCCH bearing the high-priority HARQ-ACK with the PUCCH bearing the low-priority HARQ-ACK to obtain the first PUCCH;
  • the first PUCCH overlaps the N' PUCCHs carrying low-priority SRs, multiplexing the first PUCCH with the N' PUCCHs carrying low-priority SRs, wherein the N' is equal or not equal to N;
  • the at least two PUCCHs include: PUCCHs that carry high-priority HARQ-ACKs, PUCCHs that carry low-priority HARQ-ACKs, M PUCCHs that carry high-priority SRs, and N PUCCHs that carry low-priority SRs;
  • the processing module 501 is further configured to: multiplex the PUCCH bearing the high-priority HARQ-ACK with the PUCCH bearing the low-priority HARQ-ACK to obtain a first PUCCH;
  • the first PUCCH overlaps with M' PUCCHs carrying high-priority SRs and N' PUCCHs carrying low-priority SRs, then combine the first PUCCH with M' PUCCHs and N's carrying high-priority SRs ' PUCCHs carrying low-priority SRs are multiplexed, wherein N' and N are equal or unequal, and M' and M are equal or unequal.
  • the first PUCCH is determined by the number of bits of the high-priority HARQ-ACK and the number of bits of the low-priority HARQ-ACK.
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and M PUCCHs carrying a high-priority SR;
  • the processing module 501 is further configured to: multiplex the high-priority HARQ-ACK, the low-priority HARQ-ACK, and M high-priority SRs on the second PUCCH;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, and N PUCCHs carrying a low-priority SR;
  • the processing module 501 is further configured to: multiplex the high-priority HARQ-ACK, the low-priority HARQ-ACK, and the N low-priority SRs on the second PUCCH;
  • the at least two PUCCHs include: PUCCHs that carry high-priority HARQ-ACKs, PUCCHs that carry low-priority HARQ-ACKs, M PUCCHs that carry high-priority SRs, and N PUCCHs that carry low-priority SRs;
  • the processing module 501 is further configured to: multiplex the high-priority HARQ-ACK, the low-priority HARQ-ACK, the M high-priority SRs and the N low-priority SRs on the second PUCCH superior.
  • the second PUCCH is based on the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, the number of bits of the M high-priority SRs, the N It is determined by one or more combinations of the number of bits of the low-priority SR.
  • the second PUCCH is determined according to the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, and the number of bits of the M high-priority SRs;
  • the number of bits of the M high-priority SRs is: log 2 (1+M);
  • the second PUCCH is determined according to the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, and the number of bits of the N low-priority SRs;
  • the number of bits of the N low-priority SRs is: log 2 (1+N);
  • the second PUCCH is based on the number of bits of the high-priority HARQ-ACK, the number of bits of the low-priority HARQ-ACK, the bits of the M high-priority SRs and the N low-priority SRs number determined;
  • the number of bits of the M high-priority SRs and the N low-priority SRs is: the sum of log 2 (1+M) and log 2 (1+N), or log 2 (1+M+ N).
  • the at least two PUCCHs include: PUCCHs carrying CSI, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further configured to: multiplex the M high-priority SRs and N low-priority SRs on the PUCCH carrying the CSI.
  • the at least two PUCCHs include: PUCCHs carrying CSI, and M PUCCHs carrying high-priority SRs;
  • the processing module 501 is further configured to: place the M high-priority SRs on the PUCCH carrying the CSI.
  • processing module 501 is further configured to:
  • M represents the high priority SR of log 2 (1 + M) bits
  • N denotes a low-priority SR log 2 (1 + N) bits multiplexed on PUCCH CSI of the carrier
  • the log 2 (1+M) bits representing M high-priority SRs are multiplexed on the CSI-carrying PUCCH.
  • bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI; or , the bit positions of the M high-priority SRs are located before the bit positions of the CSI.
  • the at least two PUCCHs include: PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the format is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • processing module 501 is further configured to:
  • M represents the high priority SR of log 2 (1 + M) bits
  • N denotes a low-priority SR log 2 (1 + N) bits multiplexed in the high priority bearer the HARQ-ACK on PUCCH;
  • the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs are multiplexed on the PUCCH carrying the high-priority HARQ-ACK.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located before the bit positions representing the N low-priority SRs. .
  • the at least two PUCCHs include: PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • processing module 501 is further configured to:
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4.
  • processing module 501 is further configured to:
  • M represents the high priority SR of log 2 (1 + M) bits
  • N denotes a low-priority SR log 2 (1 + N) bit multiplexing on low priority of the bearer of the HARQ-ACK PUCCH ;
  • the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs are multiplexed on the PUCCH carrying the low-priority HARQ-ACK.
  • bit positions of the M high-priority SRs are located before the bit positions of the low-priority HARQ-ACKs, and the bit positions of the low-priority HARQ-ACKs are located before the N low-priority SRs. before the bit position.
  • the at least two PUCCHs include: PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs PUCCH;
  • the processing module 501 is further used for:
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the third PUCCH is determined based on the number of bits of the M high-priority SRs, the number of bits of the N low-priority SRs, the number of bits of the high-priority HARQ-ACK, and the number of bits of the low-priority HARQ-ACK of.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located before the bit positions of the low-priority HARQ-ACK, The bit positions of the low-priority HARQ-ACK are located before the bit positions of the N low-priority SRs.
  • bit position of the high-priority HARQ-ACK is located before the bit position of the low-priority HARQ-ACK, and the bit position of the low-priority HARQ-ACK is located between the M high-priority SRs.
  • bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs.
  • the at least two PUCCHs include: a PUCCH carrying CSI, a PUCCH carrying a high-priority HARQ-ACK, a PUCCH carrying a low-priority HARQ-ACK, M PUCCHs carrying a high-priority SR, and N bearers PUCCH of low priority SR;
  • the processing module 501 is further used for:
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 2, PUCCH format 3 or PUCCH format 4;
  • the Four PUCCH is based on the number of bits of the M high-priority SRs, the number of bits of the N low-priority SRs, the number of bits of the high-priority HARQ-ACK, the bits of the low-priority HARQ-ACK. The number of bits and the number of CSI bits are determined.
  • bit positions of the high-priority HARQ-ACK are located before the bit positions of the M high-priority SRs, and the bit positions of the M high-priority SRs are located in the low-priority HARQ-ACK.
  • bit positions of the low-priority HARQ-ACK are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI.
  • the bit position of the high-priority HARQ-ACK is located before the bit position of the low-priority HARQ-ACK, and the bit position of the low-priority HARQ-ACK is located between the M high-priority SRs.
  • the bit positions of the M high-priority SRs are located before the bit positions of the N low-priority SRs, and the bit positions of the N low-priority SRs are located before the bit positions of the CSI.
  • the at least two PUCCHs include: PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the log 2 (1+M+N) bits of the priority SR are multiplexed with the high-priority HARQ-ACK on the fifth PUCCH, where the high-priority HARQ-ACK includes the physical downlink sharing with PDCCH scheduling Feedback of channel PDSCH;
  • the at least two PUCCHs include: PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the log 2 (1+M+N) bits of the priority SR are multiplexed with the low-priority HARQ-ACK on the fifth PUCCH, and the low-priority HARQ-ACK contains feedback on the PDSCH scheduled by the PDCCH;
  • the at least two PUCCHs include: PUCCHs that carry high-priority HARQ-ACKs, PUCCHs that carry low-priority HARQ-ACKs, M PUCCHs that carry high-priority SRs, and N PUCCHs that carry low-priority SRs;
  • the processing module 501 is further used for:
  • the high priority HARQ-ACK and the low priority HARQ-ACK HARQ-ACK contains feedback on PDSCH scheduled with PDCCH.
  • the at least two PUCCHs include: PUCCHs carrying high-priority or low-priority HARQ-ACKs, and M PUCCHs carrying high-priority SRs;
  • the processing module 501 is further used for:
  • the format of the PUCCH of the high-level or low-priority HARQ-ACK is PUCCH format 0;
  • the at least two PUCCHs include: PUCCHs carrying HARQ-ACK with high priority or low priority, and N PUCCHs carrying SRs with low priority;
  • the processing module 501 is further used for:
  • the format of the PUCCH of the high-level or low-priority HARQ-ACK is PUCCH format 0;
  • the at least two PUCCHs include: PUCCHs carrying high-priority or low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the third SR is a positive SR of any one of the M high-priority SRs and N low-priority SRs
  • the format of the PUCCH carrying the high-priority or low-priority HARQ-ACK is PUCCH format 0.
  • the high-priority SR and the low-priority SR are multiplexed on the PUCCH carrying the high-priority or low-priority HARQ-ACK.
  • the priority SR adopts different cyclic shifts.
  • the at least two PUCCHs include: a PUCCH bearing a low-priority HARQ-ACK, and M PUCCHs bearing a high-priority SR;
  • the processing module 501 is further configured to: multiplex the low-priority HARQ-ACK on the PUCCH bearing the positive SR;
  • the format of the PUCCH bearing the low-priority HARQ-ACK is PUCCH format 1
  • the format of the PUCCH bearing the positive SR is PUCCH format 1
  • the positive SR is any one of M high-priority SRs ;
  • the at least two PUCCHs include: a PUCCH carrying a high-priority HARQ-ACK, and N PUCCHs carrying a low-priority SR;
  • the processing module 501 is further configured to: multiplex the high-priority HARQ-ACK on the PUCCH bearing the positive SR;
  • the format of the PUCCH bearing the high-priority HARQ-ACK is PUCCH format 1
  • the format of the PUCCH bearing the positive SR is PUCCH format 1
  • the positive SR is any one of N low-priority SRs .
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the log 2 (1+M+N) bits of the priority SR are multiplexed on the seventh PUCCH with the bits of the high-priority HARQ-ACK, where the high-priority HARQ-ACK contains feedback on the PDSCH scheduled by the PDCCH ;
  • the format of the PUCCH carrying the high-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1;
  • the at least two PUCCHs PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the format of the PUCCH carrying the low-priority HARQ-ACK is PUCCH format 0 or PUCCH format 1;
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the log 2 (1+M+N) bits of the level SR are multiplexed with the high-priority HARQ-ACK on the sixth PUCCH, wherein the high-priority HARQ-ACK does not include the feedback, and the terminal is configured with an SPS HARQ-ACK feedback PUCCH list;
  • the at least two PUCCHs PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the terminal is configured with an SPS HARQ-ACK feedback PUCCH list;
  • the at least two PUCCHs PUCCHs carrying high-priority HARQ-ACKs, PUCCHs carrying low-priority HARQ-ACKs, M PUCCHs carrying high-priority SRs, and N PUCCHs carrying low-priority SRs;
  • the processing module 501 is further used for:
  • the first-level HARQ-ACK does not include feedback on PDSCH scheduled with PDCCH, and the terminal is configured with the SPS HARQ-ACK feedback PUCCH list.
  • the fifth PUCCH, the sixth PUCCH or the seventh PUCCH is determined according to any one of the following:
  • M represents a high-priority SR of log 2 (1 + M) bit number
  • N represents the low-priority SR log 2 (1 + N) bits, and the number of bits of the high priority determined by the HARQ-ACK , or, the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs, and the number of bits of the high-priority HARQ-ACK are determined;
  • Biaoshi M SR of high-priority log 2 (1 + M) bits indicates the N low priority SR of log 2 (1 + N) bits, and the low priority bits determine the HARQ-ACK , or, the log 2 (1+M+N) bits representing M high-priority SRs and N low-priority SRs, and the number of bits of the low-priority HARQ-ACK are determined;
  • the number of bits of the low-priority HARQ-ACK is determined, or, it represents the number of log 2 (1+M+N) bits of M high-priority SRs and N low-priority SRs, the high-priority HARQ-ACK The number of bits and the number of bits of the low-priority HARQ-ACK are determined.
  • the apparatus for processing PUCCH resource overlap provided in this embodiment of the present application can implement each process implemented by the method embodiment shown in FIG. 2 , and achieve the same technical effect. To avoid repetition, details are not described here.
  • FIG. 6 is a schematic diagram of a hardware structure of a terminal implementing an embodiment of the present application.
  • the terminal 600 includes but is not limited to: a radio frequency unit 601, a network module 602, an audio output unit 603, an input unit 604, a sensor 605, a display unit 606, a user input unit 607, an interface unit 608, a memory 609, a processor 610 and other components .
  • the terminal 600 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 610 through a power management system, so as to manage charging, discharging, and power consumption through the power management system management and other functions.
  • a power source such as a battery
  • the terminal structure shown in FIG. 6 does not constitute a limitation on the terminal, and the terminal may include more or less components than shown, or combine some components, or arrange different components, which will not be repeated here.
  • the input unit 604 may include a graphics processor (Graphics Processing Unit, GPU) 6041 and a microphone 6042. Such as camera) to obtain still pictures or video image data for processing.
  • the display unit 606 may include a display panel 6061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 607 includes a touch panel 6061 and other input devices 6072 .
  • the touch panel 6061 is also called a touch screen.
  • the touch panel 6061 may include two parts, a touch detection device and a touch controller.
  • Other input devices 6072 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which are not described herein again.
  • the radio frequency unit 601 receives the downlink data from the network side device, and then processes it to the processor 610; in addition, sends the uplink data to the network side device.
  • the radio frequency unit 601 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like.
  • Memory 609 may be used to store software programs or instructions as well as various data.
  • the memory 609 may mainly include a stored program or instruction area and a storage data area, wherein the stored program or instruction area may store an operating system, an application program or instruction required for at least one function (such as a sound playback function, an image playback function, etc.) and the like.
  • the memory 609 may include a high-speed random access memory, and may also include a non-volatile memory, wherein the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM) , PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically erasable programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • ROM Read-Only Memory
  • PROM programmable read-only memory
  • PROM erasable programmable read-only memory
  • Erasable PROM Erasable PROM
  • EPROM electrically erasable programmable read-only memory
  • EEPROM electrically erasable programmable read-only memory
  • flash memory for example at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device.
  • the processor 610 may include one or more processing units; optionally, the processor 610 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs or instructions, etc. Modem processors mainly deal with wireless communications, such as baseband processors. It can be understood that, the above-mentioned modulation and demodulation processor may not be integrated into the processor 610.
  • the terminal provided in this embodiment of the present application can implement each process implemented by the method embodiment shown in FIG. 2 and achieve the same technical effect. To avoid repetition, details are not described here.
  • the embodiment of the present application further provides a program product, the program product is stored in a non-volatile storage medium, and the program product is executed by at least one processor to implement the steps of the processing method as described in FIG. 2 .
  • An embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, each process of the method embodiment shown in FIG. To achieve the same technical effect, in order to avoid repetition, details are not repeated here.
  • the processor is the processor in the terminal described in the foregoing embodiment.
  • the readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • An embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used to run a network-side device program or instruction to implement the above-mentioned FIG. 2
  • the chip includes a processor and a communication interface
  • the communication interface is coupled to the processor
  • the processor is used to run a network-side device program or instruction to implement the above-mentioned FIG. 2
  • the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-chip, or a system-on-a-chip, or the like.
  • the disclosed apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the method of the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of this application.
  • a storage medium such as ROM/RAM, magnetic disk, CD-ROM
  • modules, units, and sub-units can be implemented in one or more Application Specific Integrated Circuits (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSP Device, DSPD) ), Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), general-purpose processor, controller, microcontroller, microprocessor, in other electronic units or combinations thereof.
  • ASIC Application Specific Integrated Circuits
  • DSP Digital Signal Processor
  • DSP Device Digital Signal Processing Device
  • DSPD Digital Signal Processing Device
  • PLD Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the technologies described in the embodiments of the present disclosure may be implemented through modules (eg, procedures, functions, etc.) that perform the functions described in the embodiments of the present disclosure.
  • Software codes may be stored in memory and executed by a processor.
  • the memory can be implemented in the processor or external to the processor.

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Abstract

本申请公开了一种物理上行控制信道资源重叠的处理方法及装置，该方法包括：在至少两个PUCCH传输资源重叠的情况下，终端将所述至少两个PUCCH传输进行复用；其中，所述至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH。

Description

物理上行控制信道资源重叠的处理方法及装置
相关申请的交叉引用
本申请主张在2020年7月21日在中国提交的中国专利申请号No.202010707996.5的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于通信技术领域，具体涉及一种物理上行控制信道资源重叠的处理方法及装置。
背景技术
现有技术中，当不同的物理上行控制信道(Physical Uplink Control Channel，PUCCH)时域资源重叠时，如果是相同的优先级，则终端(比如用户设备(User Equipment，UE))根据一定的原则将不同PUCCH承载的上行控制信息(Uplink Control Information，UCI)进行复用或传输某一个PUCCH。如果是不同优先级的PUCCH，则UE丢弃低优先级的PUCCH，传输高优先级的PUCCH。因此会对低优先级业务性能造成较大影响。
发明内容
本申请实施例的目的是提供一种物理上行控制信道资源重叠的处理方法及装置，解决如何确保低优先级业务性能的问题。
第一方面，提供一种PUCCH资源重叠的处理方法，包括：
在至少两个PUCCH传输资源重叠的情况下，终端将所述至少两个PUCCH传输进行复用；
其中，所述至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH。
第二方面，提供一种PUCCH资源重叠的处理装置，应用于终端，包括：
处理模块，用于在至少两个PUCCH传输资源重叠的情况下，将所述至少两个PUCCH传输进行复用；
其中，所述至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH。
可选地，处理模块进一步用于：根据第一信息，将所述至少两个PUCCH传输进行复用；
其中，所述第一信息包括以下至少一项：
PUCCH承载上行控制信息的类型；
PUCCH的优先级；
PUCCH的格式。
可选地，所述至少两个PUCCH包括以下至少一项：
承载高优先级HARQ-ACK的PUCCH和承载低优先级HARQ-ACK的PUCCH；
承载HARQ-ACK的PUCCH和承载调度请求SR的PUCCH；
承载CSI的PUCCH和承载SR的PUCCH；
承载CSI的PUCCH、承载HARQ-ACK的PUCCH和承载SR的PUCCH；
其中，
所述承载HARQ-ACK的PUCCH包括：承载高优先级HARQ-ACK的PUCCH和/或承载低优先级HARQ-ACK的PUCCH；
所述承载SR的PUCCH包括：M个承载高优先级SR的PUCCH和/或N个承载低优先级SR的PUCCH；
其中，M和N为正整数。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块进一步用于：将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
如果所述第一PUCCH与M’个承载高优先级SR的PUCCH重叠，则将所述第一PUCCH与所述M’个承载高优先级SR的PUCCH进行复用，其中所述M’与M相等或不相等；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH和N’个承载低优先级SR的PUCCH；
处理模块进一步用于：将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
如果所述第一PUCCH与所述N’个承载低优先级的SR的PUCCH重叠，则将所述第一PUCCH与所述N’个承载低优先级的SR的PUCCH进行复用，其中所述N’与N相等或不相等；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：将所述承载高优先级HARQ-ACK的PUCCH与所述承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
如果所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH重叠，则将所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH进行复用，其中所述N’与N相等或不相等，所述M’与M相等或不相等。
可选地，所述第一PUCCH是所述高优先级HARQ-ACK的比特数和低优先级HARQ-ACK的比特数确定的。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块进一步用于：将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及M个高优先级SR，复用在第二PUCCH上；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及所述N个低优先级SR，复用在第二PUCCH上；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，所述M个高优先级SR和所述N个低优先级SR，复用在第二PUCCH上。
可选地，所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数、所述M个高优先级SR的比特数、所述N个低优先级SR的比特数中的一项或多项组合确定的。
可选地，所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和所述M个高优先级SR的比特数确定的；
其中，所述M个高优先级SR的比特数为：log 2(1+M)；
或者，
所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和所述N个低优先级SR的比特数确定的；
其中，所述N个低优先级SR的比特数为：log 2(1+N)；
或者，
所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数、所述M个高优先级SR和所述N个低优先级SR的比特数确定的；
其中，所述M个高优先级SR和所述N个低优先级SR的比特数为：log 2(1+M)与log 2(1+N)之和，或者log 2(1+M+N)。
可选地，所述至少两个PUCCH包括：承载CSI的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：将M个高优先级SR、N个低优先级SR复用在所述承载CSI的PUCCH上。
可选地，所述至少两个PUCCH包括：承载CSI的PUCCH、M个承载高 优先级SR的PUCCH；
处理模块进一步用于：将M个高优先级SR在所述承载CSI的PUCCH上。
可选地，处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特复用在所述承载CSI的PUCCH上；
或者，
将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载CSI的PUCCH上；
或者，
将表示M个高优先级SR的log 2(1+M)比特复用在所述承载CSI的PUCCH上。
可选地，所述M个高优先级SR的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前；或者，所述M个高优先级SR的比特位置位于所述CSI的比特位置之前。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将所述M个高优先级SR、所述N个低优先级SR复用在所述承载高优先级的HARQ-ACK的PUCCH上，其中，所述承载高优先级的HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
可选地，处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)个比特复用在所述承载高优先级的HARQ-ACK的PUCCH上；
或者，
将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载高优先级HARQ-ACK的PUCCH上。
可选地，所述高优先级HARQ-ACK的比特位置位于M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于表示N个低优先级SR的比特位置之前。
可选地，所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
可选地，处理模块501进一步用于：
将M个高优先级SR、N个低优先级SR复用在所述承载低优先级HARQ-ACK的PUCCH上；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
可选地，处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特复用在所述承载低优先级HARQ-ACK的PUCCH上；
或者，
将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载低优先级HARQ-ACK的PUCCH上。
可选地，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将所述M个高优先级SR、所述N个低优先级SR和所述低优先级HARQ-ACK复用在所述承载高优先级HARQ-ACK的PUCCH上；
其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR和所述高优先级 HARQ-ACK复用在所述承载低优先级HARQ-ACK的PUCCH上；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK，复用在第三PUCCH上，所述第三PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数和所述低优先级HARQ-ACK的比特数确定的。
可选地，所述高优先级HARQ-ACK的比特位置位于M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于N个低优先级SR的比特位置之前。
可选地，所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述N个低优先级SR的比特位置之前。
可选地，所述至少两个PUCCH包括：承载CSI的PUCCH、承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将所述M个高优先级SR、所述N个低优先级SR、所述低优先级HARQ-ACK和所述CSI复用在所述承载高优先级HARQ-ACK的PUCCH上；
其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述CSI复用在所述承载低优先级HARQ-ACK的PUCCH上；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式 2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK复用在所述承载CSI的PUCCH；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK、所述低优先级HARQ-ACK和所述CSI复用在第四PUCCH，所述第四PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和CSI的比特数确定的。
可选地，所述高优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前。
可选地，所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第五PUCCH上，其中所述高优先级HARQ-ACK包含对有PDCCH调度的物理下行共享信道PDSCH的反馈；
或者，
所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述低优先级HARQ-ACK复用在第五PUCCH上，所述低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级的SR和N个低优先级的SR的log 2(1+M+N)比特，与高优先级HARQ-ACK和低优先级HARQ-ACK复用在第五PUCCH上，所述高优先级HARQ-ACK和低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈。
可选地，所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块进一步用于：
将第一SR复用在所述承载高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第一SR是M个高优先级SR中的任意一个正SR，承载所述高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
或者，
所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将第二SR复用在承载所述高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第二SR是N个低优先级SR中的任意一个正SR，承载 所述高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
或者，
所述至少两个PUCCH包括：承载高优先级或低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将第三SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH，其中，所述第三SR是M个高优先级SR和N个低优先级SR中任意一个的正SR，所述承载高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0。
可选地，所述将M个高优先级SR和所述N个低优先级SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH时，所述高优先级SR和低优先级SR采用不同的循环移位。
可选地，所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块进一步用于：将所述低优先级的HARQ-ACK复用在承载正SR的PUCCH上；
其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为M个高优先级的SR中的任意一个；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
处理模块进一步用于：将所述高优先级的HARQ-ACK复用在承载正SR的PUCCH上；
其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为N个低优先级的SR中的任意一个。
可选地，所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与高优先级HARQ-ACK的比特复用在第七PUCCH上，其中所述高优先级HARQ-ACK包含有对PDCCH调度的PDSCH的反馈；
其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1；
或者，
所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述低优先级HARQ-ACK复用在第七PUCCH上，其中所述低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1；
或者，
所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK和低优先级HARQ-ACK复用在第七PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈。
可选地，所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第六PUCCH上，其中，所述高优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
或者，
所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与低优先级HARQ-ACK复用在第六PUCCH上，其中所述低优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
或者，
所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK和低优先级HARQ-ACK复用在第六PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK均不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表。
可选地，所述第五PUCCH、第六PUCCH或第七PUCCH是根据以下任一项确定的：
表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR 的log 2(1+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的；
或者，
表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的；
或者，
表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的。
第三方面，提供一种终端，包括：处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序，所述程序被所述处理器执行时实现如第一方面所述的方法的步骤。
第四方面，提供一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如第一方面所述的方法的步骤。
第五方面，提供一种程序产品，所述程序产品被存储在非易失的存储介质中，所述程序产品被至少一个处理器执行以实现如第一方面所述的方法的步骤。
第六方面，提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如第一方面所述的方法。
第七方面，提供了一种终端，所述终端被配置成用于执行如第一方面所述的方法。
在本申请实施例中，通过对不同优先级的PUCCH传输进行复用，可以确保低优先级业务性能，提高通信系统的可靠性。
附图说明
图1是本申请实施例可应用的一种无线通信系统的框图；
图2是本申请实施例PUCCH重叠的处理方法的流程图；
图3a-图3d是承载HARQ-ACK的PUCCH与承载SR的PUCCH重叠的示意图
图4a-图4d是承载CSI或HARQ-ACK的PUCCH与承载SR的PUCCH重叠的示意图；
图5是本申请实施例的物理上行控制信道资源重叠的处理装置的示意图；
图6是本申请实施例的终端的示意图。
具体实施方式
与以往的移动通信系统相比，未来第五代移动通信技术(the fifth generation，5G)需要适应更加多样化的场景和业务需求。5G的主要场景包括移动宽带增强(Enhanced Mobile Broadband，eMBB)，超可靠和低时延通信(Ultra-Reliable and Low Latency Communications，URLLC)，大规模物联网(Massive Machine Type Communication，mMTC)，这些场景对系统提出了高可靠，低时延，大带宽，广覆盖等要求。对于某些UE可能支持不同的业务，例如UE既支持URLLC低时延高可靠业务，同时支持大容量高速率的eMBB业务。
新空口(New Radio，NR)系统由于不同的信道可以具有不同的起始符号和长度，因此会出现传输资源时域重叠的情况。通常，为了维持上行单载波特性，当一个时隙有多个重叠PUCCH传输时，会破坏UE的单载波特性，并且发射功率的不同会引起信道估计性能的恶化。对于这种情况通常被视为一种冲突，需要设计相应的冲突解决方案，合并、丢弃一些信息。
当一个UE同时支持不同的业务时，例如URLLC和eMBB，由于不同业务具有不同的时延或可靠性要求，为了保证高优先级业务的传输，UE将在区分不同信道/信号所对应的优先级，例如高优先级或低优先级，不同优先级的信道或信号可能在时域资源上重叠，UE将丢弃/取消低优先级信道/信号。
(1)关于NR版本15(Release 15，R15)PUCCH/上行物理共享信道(Physical Uplink Shared Channel，PUSCH)复用(multiplexing)：
NR R15中没有区分不同的业务类型或者优先级，当不同的信道时域资源重叠时，UE会根据预定义的规则进行复用或丢弃，例如当承载动态混合自动重传请求应答(Hybrid automatic repeat request acknowledgement，HARQ-ACK)的PUCCH和承载周期性信道状态信息(Channel State Information，CSI)的PUCCH重叠时，UE将HARQ-ACK和CSI复用在一个PUCCH上，且该PUCCH为根据HARQ-ACK和CSI的总的荷载(payload)以及HARQ-ACK对应的PUCCH指示(PUCCH resource indicator，PRI)确定的；
再例如，PUCCH和PUSCH时域资源重叠时(除了特定情况，如调度请求(Scheduling Request，SR)PUCCH和PUSCH不承载上行共享信道(Uplink Shared Channel，UL-SCH)(PUCCH without UL-SCH)等)，UE会将PUCCH承载的内容复用在PUSCH上传输。同时由于硬件要求，UE复用处理需要一定的时间要求，NR R15定义了PUCCH和PUCCH，或者PUCCH和PUSCH复用时应满足的时间要求。
(2)NR版本16(Release 16，R16)PUCCH/PUSCH优先级(priorization)：
在NR R16中，考虑到一个UE可能同时支持不同的业务，而不同的业务对应不同的业务需求，例如时延、可靠性等方面。因此引入了标记PUCCH/PUSCH信道优先级的机制，具体的引入了2级物理层优先级，即高优先级、低优先级。例如SR，配置授权(Configured Grant，CG)PUSCH，半持续性调度(Semi-Persistent Scheduling，SPS)物理下行共享信道(Physical downlink Shared channel，PDSCH)及其释放(release)的HARQ-ACK的优先级是由无线资源控制(Radio Resource Control，RRC)信令配置，对于PUCCH上的周期性信道状态信息(periodic CSI，P-CSI)或半周期性信道状态信息(semi-periodic CSI，SP-CSI)视为低优先级。对于动态调度的PDSCH的HARQ-ACK，动态调度的(DG)PUSCH，承载非周期性CSI(Aperiodic CSI，A-CSI)/半持续CSI(semi-persistent CSI，SP-CSI)的PUSCH等由对应的调度下行控制信息(Downlink Control Information，DCI)指示。PUCCH的优先级则由其承载的HARQ-ACK/SR/CSI确定。当不同的信道时域资源重叠时， 如果是相同优先级，则按照NR R15定义的复用规则处理，如果是不同优先级，则UE丢弃低优先级的信道，传输高优先级的信道。如果既有相同优先级，又有不同优先级，则UE先按照NR R15定义的复用规则处理，然后再处理不同优先级的信道。同时UE处理不同优先级时，丢弃低优先级，传输高优先级信道也需要一定的处理时间，R16协议中定义UE处理不同优先级信道时的丢弃/取消时间要求。
由此可知，现有技术中，不支持不同优先级的PUCCH之间的复用。
可以理解的是，如果PUCCH之间支持复用，UE如何复用不同的UCI需要定义，例如，当承载高优先级(High Priority，HP)HARQ-ACK，低优先级(Low Priority，LP)HARQ-ACK的PUCCH和承载SR的PUCCH在时域上重叠时，如果UE处理相同优先级的PUCCH，再复用不同优先级的PUCCH，则在有些情况下，正SR(positive SR)将被丢弃，增加了SR传输的时延。当承载CSI或HARQ-ACK的PUCCH和承载LP SR的PUCCH以及承载HP SR的PUCCH重叠时，UE如何复用SR也亟需解决。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述指定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”所区别的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”一般表示前后关联对象是一种“或”的关系。
值得指出的是，本申请实施例所描述的技术不限于长期演进型(Long Term Evolution，LTE)/LTE的演进(LTE-Advanced，LTE-A)系统，还可用于其他无线通信系统，诸如码分多址(Code Division Multiple Access，CDMA)、时分多址(Time Division Multiple Access，TDMA)、频分多址(Frequency  Division Multiple Access，FDMA)、正交频分多址(Orthogonal Frequency Division Multiple Access，OFDMA)、单载波频分多址(Single-carrier Frequency-Division Multiple Access，SC-FDMA)和其他系统。本申请实施例中的术语“系统”和“网络”常被可互换地使用，所描述的技术既可用于以上提及的系统和无线电技术，也可用于其他系统和无线电技术。然而，以下描述出于示例目的描述了新空口(New Radio，NR)系统，并且在以下大部分描述中使用NR术语，尽管这些技术也可应用于NR系统应用以外的应用，如第6代(6 th Generation，6G)通信系统。
图1示出本申请实施例可应用的一种无线通信系统的框图。无线通信系统包括终端11和网络侧设备12。其中，终端11也可以称作终端设备或者用户终端(User Equipment，UE)，终端11可以是手机、平板电脑(Tablet Personal Computer)、膝上型电脑(Laptop Computer)或称为笔记本电脑、个人数字助理(Personal Digital Assistant，PDA)、掌上电脑、上网本、超级移动个人计算机(ultra-mobile personal computer，UMPC)、移动上网装置(Mobile Internet Device，MID)、可穿戴式设备(Wearable Device)或车载设备(vehicle UE，VUE)、行人终端(pedestrian UE，PUE)等终端侧设备，可穿戴式设备包括：手环、耳机、眼镜等。需要说明的是，在本申请实施例并不限定终端11的具体类型。网络侧设备12可以是基站或核心网，其中，基站可被称为节点B、演进节点B、接入点、基收发机站(Base Transceiver Station，BTS)、无线电基站、无线电收发机、基本服务集(Basic Service Set，BSS)、扩展服务集(Extended Service Set，ESS)、B节点、演进型B节点(evolved Node B，eNB)、家用B节点、家用演进型B节点、无线局域网(wireless local area network，WLAN)接入点、无线保真(wireless fidelity，WiFi)节点、发送接收点(Transmitting Receiving Point，TRP)或所述领域中其他某个合适的术语，只要达到相同的技术效果，所述基站不限于指定技术词汇，需要说明的是，在本申请实施例中仅以NR系统中的基站为例，但是并不限定基站的具体类型。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的PUCCH重叠的处理方法及装置进行详细地说明。
参见图2，本申请实施例提供一种PUCCH重叠的处理方法，该方法的执 行主体可以为终端，具体步骤包括：步骤201。
步骤201：在至少两个PUCCH传输资源重叠的情况下，将至少两个PUCCH传输进行复用；
其中，至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH，也就是说至少两个PUCCH中包含：不同优先级的PUCCH。
在本申请实施例中，可以实现不同优先级的PUCCH之间的复用。
上述至少两个PUCCH中包含：不同优先级的PUCCH，包括：
(1)资源重叠的PUCCH的数量为两个，则两个PUCCH的优先级不同。
比如，至少两个PUCCH包括：承载UCI1的PUCCH1和承载UCI2的PUCCH2，PUCCH1和PUCCH2在时域重叠，UCI1的优先级高于UCI2的优先级，则可以将UCI1和UCI2复用在一个PUCCH上传输，比如复用在PUCCH1上传输。可以理解的是，上述UCI1和UCI2的类型可以相同，或者也可以不同。
(2)资源重叠的PUCCH的数量大于两个(比如三个PUCCH、四个PUCCH等)，则至少两个PUCCH的优先级不同。
比如，至少两个PUCCH包括：承载UCI1的PUCCH1、承载UCI2的PUCCH2、承载UCI3的PUCCH3，PUCCH1、PUCCH2和PUCCH3在时域重叠，UCI1的优先级高于UCI2的优先级，或者UCI1的优先级高于UCI3的优先级，则可以将UCI1、UCI2和UCI3复用在一个PUCCH上传输，比如复用在PUCCH1。可以理解的是，上述UCI1、UCI2和UCI3中的至少两个UCI的类型不同。比如，UCI1和UCI2为HARQ-ACK，UCI3为SR。
又比如，至少两个PUCCH包括：承载UCI1的PUCCH1、承载UCI2的PUCCH2、承载UCI3的PUCCH3和承载UCI4的PUCCH4，PUCCH1、PUCCH2、PUCCH3和PUCCH4在时域重叠，UCI1的优先级高于UCI2的优先级，UCI3的优先级高于UCI4的优先级，则可以将UCI1、UCI2、UCI3和UCI4复用在一个PUCCH上传输，比如复用在PUCCH1。可以理解的是，上述UCI1、UCI2、UCI3和UCI4中的至少两个UCI的类型不同。比如，UCI1和UCI2为HARQ-ACK，UCI3和UCI4为SR。
上述将至少两个PUCCH传输进行复用是指将至少两个优先级的PUCCH 承载的UCI复用在一个PUCCH上进行传输，比如可以根据至少两个不同优先级的PUCCH上承载的UCI的载荷(payload)确定复用的PUCCH，避免将低优先级PUCCH承载的UCI丢弃，从而可以确保低优先级业务性能。
可以理解的是，PUCCH的优先级可以通过PUCCH承载的UCI确定，比如UCI1的优先级为高优先级，则承载该UCI1的PUCCH的优先级为高优先级，UCI2的优先级为低优先级，则承载该UCI2的PUCCH的优先级为低优先级。可以理解的是，上述UCI1和UCI2的类型可以相同，或者也可以不同。
比如，承载高优先级HARQ-ACK(以下可称为HP HARQ-ACK)的PUCCH的优先级为高优先级，承载低优先级HARQ-ACK(以下可称为LP HARQ-ACK)的PUCCH的优先级为低优先级。
比如，HARQ-ACK的优先级是与HARQ-ACK码本(codebook)标识相关，第一个HARQ-ACK codebook关联一个低优先级的PUCCH，第二个HARQ-ACK codebook关联一个高优先级的PUCCH，即第一个HARQ-ACK codebook对应的HARQ-ACK优先级为低优先级，第二个HARQ-ACK codebook对应的HARQ-ACK优先级为高优先级。
又比如，承载高优先级SR(可称为HP SR)的PUCCH的优先级为高优先级，承载低优先级SR(可称为LP SR)的PUCCH的优先级为低优先级。
在本申请实施例中，可以通过调度请求资源配置(SchedulingRequestResourceConfig)中的参数，如phy-PriorityIndex-r16为UE提供SR的优先级。如果没有为UE提供SR的优先级索引，则优先级低优先级。
在本申请实施例中，PUCCH或UCI的优先级可以由优先级索引表示，例如优先级索引为0表示低优先级，优先级索引为1表示高优先级，或者，如优先级索引为0表示高优先级，优先级索引为1表示低优先级。
在本申请实施例中，终端可以根据第一信息，将至少两个PUCCH传输进行复用；其中，第一信息可以包括以至少一项：
(1)PUCCH承载UCI的类型，例如HARQ-ACK、CSI、SR(正SR(positive SR)、负SR(negative SR))等。
(2)PUCCH的优先级，例如PUCCH的优先级包括高优先级和低优先 级，该PUCCH的优先级可以由其承载的UCI(比如HARQ-ACK、CSI、SR)的优先级确定，比如，承载高优先级HARQ-ACK的PUCCH1，承载低优先级HARQ-ACK的PUCCH2，则可以理解为，PUCCH1的优先级为高优先级，PUCCH2的优先级为低优先级；
(3)PUCCH的格式(format)，例如PUCCH格式0、PUCCH格式1、PUCCH格式2、PUCCH格式3、PUCCH格式4。
在本申请实施例中，所述至少两个PUCCH包括以下至少一项：
(1)承载高优先级HARQ-ACK的PUCCH和承载低优先级HARQ-ACK的PUCCH；
(2)承载HARQ-ACK的PUCCH和承载SR的PUCCH；
(3)承载CSI的PUCCH和承载SR的PUCCH；
(4)承载CSI的PUCCH、承载HARQ-ACK的PUCCH和承载SR的PUCCH；
比如，上述CSI是具有低优先级的CSI，例如PUCCH承载的P-CSI或SP-CSI。
其中，
所述承载HARQ-ACK的PUCCH包括：承载高优先级HARQ-ACK的PUCCH和/或承载低优先级HARQ-ACK的PUCCH；
所述承载SR的PUCCH包括：M个承载高优先级SR的PUCCH和/或N个承载低优先级SR的PUCCH；
其中，M和N为正整数。
在本申请实施例中，通过PUCCH承载UCI的类型、PUCCH的优先级和/或PUCCH的格式，确定至少两个PUCCH传输的复用方式，再根据确定的复用方式将至少两个PUCCH传输进行复用，避免出现至少两个PUCCH传输资源重叠时，低优先级的UCI会被丢弃，导致增加该UCI传输的时延的问题。
下面结合场景1和场景2介绍本申请实施例。
场景1：
在场景1中，至少两个PUCCH可以包括以下四种情况：
情况(1)：承载高优先级HARQ-ACK的PUCCH1和承载低优先级 HARQ-ACK的PUCCH1；
该PUCCH1和PUCCH2在时域重叠。
情况(2)：承载高优先级HARQ-ACK的PUCCH1、承载低优先级HARQ-ACK的PUCCH2、M个承载高优先级SR的PUCCH资源3；
该PUCCH1、PUCCH2和PUCCH3在时域重叠。
情况(3)：承载高优先级HARQ-ACK的PUCCH1、承载低优先级HARQ-ACK的PUCCH2和N个承载低优先级SR的PUCCH4；
该PUCCH1、PUCCH2和PUCCH4在时域重叠。
情况(4)：承载高优先级HARQ-ACK的PUCCH1、承载低优先级HARQ-ACK的PUCCH2、M个承载高优先级SR的PUCCH3和N个承载低优先级SR的PUCCH3。
该PUCCH1、PUCCH2、PUCCH3和PUCCH4在时域重叠。
可以理解的是，M、N均为正整数。
需要说明的是，M个承载高优先级SR的PUCCH或者N个承载低优先级SR的PUCCH是指由一组调度请求资源标识(scheduleRequestResourceId)确定的时隙中各个SR的PUCCH，M个承载高优先级SR的PUCCH或者N个承载低优先级SR的PUCCH分别对应M个SR配置或者N个SR配置，其中SR传输时机可能与该时隙中承载HARQ-ACK信息的PUCCH的传输或与该时隙中承载CSI报告的PUCCH的传输重叠。M个SR PUCCH或N个SR PUCCH资源之间可以重叠，也可以不重叠。
下面介绍在情况(1)～情况(4)中高优先级的PUCCH和低优先级的PUCCH重叠的情况下，如何进行不同优先级的PUCCH传输复用。
针对上述情况(1)
UE将高优先级HARQ-ACK和低优先级HARQ-ACK复用在PUCCH1上传输。
其中，PUCCH1是根据高优先级HARQ-ACK的比特数和低优先级HARQ-ACK的比特数确定的。
针对上述情况(2)，包括方式1和方式2：
方式1：
UE优先处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的冲突，例如，UE根据HP HARQ-ACK和LP HARQ-ACK比特数确定复用后的PUCCH为PUCCH1。如果复用后的PUCCH1与承载HP SR的PUCCH，UE再处理PUCCH1与承载HP SR的PUCCH之间的冲突，例如按照现有HARQ-ACK和SR的冲突处理原则处理，或者按照方式2处理。
方式2：
UE将高优先级HARQ-ACK、低优先级HARQ-ACK，以及M个高优先级SR，复用在第二PUCCH上。
可选地，第二PUCCH是根据高优先级HARQ-ACK的比特数、低优先级HARQ-ACK的比特数、M个高优先级SR的比特数确定的，进一步地，第二PUCCH是根据高优先级HARQ-ACK、低优先级HARQ-ACK和表示M个高优先级SR的log 2(1+M)比特数确定的。
针对上述情况(3)，包括方式1和方式2：
方式1：
UE优先处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的冲突，例如，UE根据HP HARQ-ACK和LP HARQ-ACK比特数确定复用后的PUCCH为PUCCH1。如果复用后的PUCCH1与承载LP SR的PUCCH，UE再处理PUCCH1与承载LP SR的PUCCH之间的冲突，例如按照现有HARQ-ACK和SR的冲突处理原则处理，或者按照方式2处理。
方式2：
UE将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及所述N个低优先级SR，复用在第二PUCCH上。
可选地，第二PUCCH是根据高优先级HARQ-ACK的比特数、低优先级HARQ-ACK的比特数、N个低优先级SR的比特数确定的，进一步地，第二PUCCH是根据高优先级HARQ-ACK的比特数、低优先级HARQ-ACK的比特数和表示N个低优先级SR的log 2(1+N)比特数确定的。
针对上述情况(4)
不同优先级的PUCCH传输复用的方式包括：方式1和方式2。
方式1：
UE优先处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的冲突，例如，UE根据HP HARQ-ACK和LP HARQ-ACK比特数确定复用后的PUCCH为PUCCH1。如果复用后的PUCCH1与承载HP SR的PUCCH和承载LRSR的PUCCH冲突，UE再处理PUCCH1与承载HP SR的PUCCH和承载LRSR的PUCCH之间的冲突，例如按照现有HARQ-ACK和SR的冲突处理原则处理，或者按照方式2处理。
具体地，方式1包括：
(1)UE将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；如果第一PUCCH与M’个承载高优先级SR的PUCCH重叠，则将第一PUCCH与M’个承载高优先级SR的PUCCH传输进行复用；其中，所述第一PUCCH是所述高优先级HARQ-ACK的比特数和低优先级HARQ-ACK的比特数确定的，其中所述M’与M相等或不相等。
可以理解的是，HARQ-ACK和LP HARQ-ACK复用前与M个SR重叠，复用后的第一PUCCH不一定与M个SR重叠，可能是与M’个SR重叠，其中M’可能不等于M，因为第一PUCCH的时域资源可能不同于HP/LP的PUCCH的时域资源。
(2)UE将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；如果所述第一PUCCH与N’个承载低优先级的SR的PUCCH重叠，则将所述第一PUCCH与所述N’个承载低优先级的SR配置PUCCH进行复用，其中所述N’与N相等或不相等；
(3)UE将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；如果所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH重叠，则将所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH进行复用，其中所述N’与N相等或不相等，所述M’与M相等或不相等。
方式2：
UE将HP HARQ-ACK，LP HARQ-ACK以及HP SR和/或LRSR中复用 在一个PUCCH上，例如UE根据HP HARQ-ACK，LP HARQ-ACK，以及HP SR和/或LRSR的比特数确定复用后的PUCCH。
具体地，方式2包括：
(1)UE将高优先级HARQ-ACK、低优先级HARQ-ACK，以及M个高优先级SR，复用在第二PUCCH上；
比如，第二PUCCH是根据高优先级HARQ-ACK的比特数、低优先级HARQ-ACK的比特数和M个高优先级SR的比特数确定的，其中，M个高优先级SR的比特数为：log 2(1+M)；
也就是，将HP HARQ-ACK、LP HARQ-ACK和HP SR复用在一个PUCCH上，例如UE将HP HARQ-ACK，LP HARQ-ACK和M个HP SR复用在第二PUCCH上，或者UE根据复用的HP HARQ-ACK，LP HARQ-ACK和M个HP SR的比特数确定复用后的PUCCH，其中，M个HP SR的比特数为log 2(1+M)。
(2)UE将高优先级HARQ-ACK、低优先级HARQ-ACK，以及低优先级SR，复用在第二PUCCH上；
比如，第二PUCCH是根据高优先级HARQ-ACK的比特数、低优先级HARQ-ACK的比特数和N个低优先级SR的比特数确定的；其中，N个低优先级SR的比特数为：log 2(1+N)。
也就是，将HP HARQ-ACK、LP HARQ-ACK和N个LP SR复用在一个PUCCH上，例如UE将HP HARQ-ACK，LP HARQ-ACK和N个LP SR复用在第二PUCCH上，或者UE根据复用的HP HARQ-ACK，LP HARQ-ACK和N个LP SR的比特数确定复用后的PUCCH，N个LP SR的比特数为log 2(1+N)比特。
(3)UE将高优先级HARQ-ACK、低优先级HARQ-ACK，以及所述M个高优先级SR和N个低优先级SR，复用在第二PUCCH上。
比如，所述第二PUCCH是根据高优先级HARQ-ACK的比特数、低优先级HARQ-ACK的比特数、M个高优先级SR和N个低优先级SR的比特数确定的；
其中，M个高优先级SR和N个低优先级SR的比特数为：log 2(1+M) 与log 2(1+N)之和，或者log 2(1+M+N)。
也就是，将HP HARQ-ACK、LP HARQ-ACK、HP SR和LP SR复用在一个PUCCH上，例如UE将HP HARQ-ACK，LP HARQ-ACK、HP SR和LP SR复用在第二PUCCH上，或者UE根据复用的HP HARQ-ACK，LP HARQ-ACK、M个HP SR和N个LP SR的比特数确定复用后的PUCCH，M个HP SR和N个LP SR的比特数为：log 2(1+M)与log 2(1+N)之和(其中log 2(1+M)和log 2(1+N)比特分别对应M个SR和N个SR)，或者log 2(1+M+N)。
在上述场景1中，可以确保HP SR和LP SR的传输，提高通信系统的可靠性。
场景2：包括示例1和示例2。
示例1介绍的是：在CSI或HARQ-ACK PUCCH的格式PUCCH2/3/4，UE支持不同优先级PUCCH之间的复用的情况下，UE可以采用的复用方式。
示例2介绍的是：在承载高优先级或低优先级的HARQ-ACK的PUCCH的格式为PUCCH格式0/1，UE支持不同优先级PUCCH之间的复用的情况下，UE可以采用的复用方式。
首先介绍在场景2中，至少两个PUCCH可以包括以下十种情况：
情况(1)：承载CSI的PUCCH1、M个承载高优先级SR的PUCCH2和N个承载低优先级SR的PUCCH3；
该PUCCH1、PUCCH2和PUCCH3在时域重叠。
情况(2)：承载高优先级HARQ-ACK的PUCCH1、M个承载高优先级SR的PUCCH2和N个承载低优先级SR的PUCCH3；
其中，承载高优先级的HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
该PUCCH1、PUCCH2和PUCCH3在时域重叠。
情况(3)：承载低优先级HARQ-ACK的PUCCH1、M个承载高优先级SR的PUCCH2和N个承载低优先级SR的PUCCH3；
该PUCCH1、PUCCH2和PUCCH3在时域重叠。
情况(4)：承载高优先级HARQ-ACK的PUCCH1、承载低优先级 HARQ-ACK的PUCCH2、M个承载高优先级SR的PUCCH3和N个承载低优先级SR的PUCCH4；
该PUCCH1、PUCCH2、PUCCH3和PUCCH4在时域重叠。
情况(5)：承载CSI的PUCCH1、承载高优先级HARQ-ACK的PUCCH2、承载低优先级HARQ-ACK的PUCCH3、M个承载高优先级SR的PUCCH4和N个承载低优先级SR的PUCCH5；
该PUCCH1、PUCCH2、PUCCH3、PUCCH4和PUCCH5在时域重叠。
情况(6)：承载CSI的PUCCH资源、承载高优先级HARQ-ACK的PUCCH资源、M个承载高优先级SR的PUCCH资源和N个承载低优先级SR的PUCCH资源；
情况(7)：承载CSI的PUCCH资源、承载低优先级HARQ-ACK的PUCCH资源、M个承载高优先级SR的PUCCH资源和N个承载低优先级SR的PUCCH资源；
情况(8)：承载低优先级HARQ-ACK的PUCCH1、M个承载高优先级SR的PUCCH2；
该PUCCH1、PUCCH2在时域重叠。
情况(9)：承载高优先级HARQ-ACK的PUCCH1、N个承载低优先级SR的PUCCH2；
该PUCCH1、PUCCH2在时域重叠。
情况(10)：承载CSI的PUCCH、M个承载高优先级SR的PUCCH；
UE将M个高优先级SR在所述承载CSI的PUCCH上。
进一步地，将表示M个高优先级SR的log 2(1+M)比特复用在所述承载CSI的PUCCH上。
示例1：在场景2中，如果CSI或HARQ-ACK PUCCH的格式PUCCH2/3/4时，如果UE支持不同优先级PUCCH之间的复用，UE可以结合上述情况(1)～情况(7)中PUCCH重叠的情况，采用如下复用方式。
针对上述情况(1)
UE将M个高优先级SR、N个低优先级SR复用在承载CSI的PUCCH上。
比如，将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，复用在承载CSI的PUCCH上；或者，将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载CSI的PUCCH上。
可选地，所述M个高优先级SR的比特位置位于N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前，即PUCCH携带的UCI的比特顺序可以是：HP SR→LP SR→CSI。
针对上述情况(2)
UE将M个高优先级SR、N个低优先级SR复用在承载高优先级的HARQ-ACK的PUCCH上。
比如，将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特复用在承载所述高优先级的HARQ-ACK的PUCCH上；或者，将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在承载所述高优先级HARQ-ACK的PUCCH上。
比如，高优先级HARQ-ACK的比特位置位于高优先级SR的比特位置之前，高优先级SR的比特位置位于所述低优先级SR的比特位置之前，即PUCCH携带的UCI的比特顺序可以是：HP HARQ-ACK→HP SR→LP SR。
针对上述情况(3)
UE将M个高优先级SR、N个低优先级SR复用在承载低优先级HARQ-ACK的PUCCH上；
其中，承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
比如，UE将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特复用在承载低优先级HARQ-ACK的PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在承载低优先级HARQ-ACK的PUCCH上。
可选地，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前，即PUCCH携带的UCI的比特顺序可 以是：HP SR→LP HARQ-ACK→LP SR。
针对上述情况(4)
PUCCH传输复用的方式包括方式1、方式2和方式3。
方式1：UE将M个高优先级SR、N个低优先级SR和所述低优先级HARQ-ACK复用在承载所述高优先级HARQ-ACK的PUCCH上；
其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、低优先级HARQ-ACK的比特复用在承载所述高优先级HARQ-ACK的PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，以及低优先级HARQ-ACK的比特，复用在承载所述高优先级HARQ-ACK的PUCCH上。
方式2：UE将所述M个高优先级SR、所述N个低优先级SR和所述高优先级HARQ-ACK复用在承载所述低优先级HARQ-ACK的PUCCH上；
其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、高优先级HARQ-ACK的比特数复用在承载所述低优先级HARQ-ACK的PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，以及高优先级HARQ-ACK的比特，复用在承载所述低优先级HARQ-ACK的PUCCH上。
可选地，所述高优先级的HARQ-ACK的比特位置位于M个高优先级的SR的比特位置之前，所述M个高优先级的SR的比特位置位于低优先级的HARQ-ACK的比特位置之前，所述低优先级的HARQ-ACK的比特位置位于N个低优先级的SR的比特位置之前，即PUCCH携带的UCI的比特顺序可以是：HP HARQ-ACK→HP SR→LP HARQ-ACK→LP SR。
或者，所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位 于所述N个低优先级SR的比特位置之前。
方式3：
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK，复用在第三PUCCH上，所述第三PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数和所述低优先级HARQ-ACK的比特数确定的
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、高优先级HARQ-ACK的比特、低优先级HARQ-ACK比特复用在第三PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特高优先级HARQ-ACK的比特、低优先级HARQ-ACK比特复用在第三PUCCH上。
针对上述情况(5)
PUCCH复用的方式包括方式1、方式2和方式3。
方式1：UE将所述M个高优先级的SR、所述N个低优先级的SR、所述低优先级HARQ-ACK和所述CSI复用在承载所述高优先级HARQ-ACK的PUCCH上；
其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、低优先级HARQ-ACK的比特、CSI的比特复用在承载所述高优先级HARQ-ACK的PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，低优先级HARQ-ACK的比特和CSI的比特，复用在承载所述高优先级HARQ-ACK的PUCCH上。
方式2：UE将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述CSI复用在承载所述低优先级HARQ-ACK的PUCCH上；
其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、高优先级HARQ-ACK的比特、CSI的比特复用在承载所述低优先级HARQ-ACK的PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，高优先级HARQ-ACK的比特和CSI的比特，复用在承载所述低优先级HARQ-ACK的PUCCH上。
方式3：UE将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK复用在承载CSI的PUCCH。
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、高优先级HARQ-ACK的比特、低优先级HARQ-ACK的比特复用在承载CSI的PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，高优先级HARQ-ACK的比特、高优先级HARQ-ACK的比特、低优先级HARQ-ACK的比特复用在承载CSI的PUCCH上。
方式4：
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK、所述低优先级HARQ-ACK和所述CSI复用在第四PUCCH，所述第四PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和CSI的比特数确定的。
比如，UE将表示M个高优先级SR的log 2(1+M)比特，N个低优先级SR的log 2(1+N)比特、高优先级HARQ-ACK的比特、低优先级HARQ-ACK的比特、所述CSI的比特复用在第四PUCCH上；或者，UE将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，高优先级HARQ-ACK的比特、高优先级HARQ-ACK的比特、低优先级HARQ-ACK的比特、所述CSI的比特复用在第四PUCCH。
可选地，所述高优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位 于所述CSI的比特位置之前，即PUCCH携带的UCI的比特顺序可以是：HP HARQ-ACK→HP SR→LP HARQ-ACK→LP SR→CSI。
或者，所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前。
在场景2的示例1中，如果高优先级或低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈，UE可以结合上述情况(2)、情况(3)、情况(4)中PUCCH重叠的情况，采用如下复用方式：
方式1：如果高优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈，则将表示M个高优先级SR的log 2(1+M)比特数，以及N个低优先级SR的log 2(1+N)比特数，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，与所述高优先级HARQ-ACK复用在第五PUCCH；
可选地，第五PUCCH是基于：表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的(即，基于上述比特数在RRC配置的多个PUCCH集中确定的PUCCH)，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的。
方式2：如果低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈，则将表示M个高优先级SR的log 2(1+M)比特数，以及N个低优先级SR的log 2(1+N)比特数，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，与所述低优先级HARQ-ACK复用在第五PUCCH；
可选地，第五PUCCH是基于：表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，以及所述低优先级HARQ-ACK的比特数确 定的
方式3：如果高优先级HARQ-ACK和低优先级HARQ-ACK包含有对PDCCH调度的PDSCH的反馈，则将表示M个高优先级SR的log 2(1+M)比特数，以及N个低优先级SR的log 2(1+N)比特数，或者，将表示M个高优先级的SR和N个低优先级的SR的log 2(1+M+N)比特数，与高优先级HARQ-ACK和低优先级HARQ-ACK复用在第五PUCCH。
可选地，第五PUCCH是基于：表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的。
示例2：如果承载高优先级或低优先级的HARQ-ACK的PUCCH的格式为PUCCH格式0/1时，如果UE支持不同优先级PUCCH之间的复用，UE可以结合上述情况中PUCCH重叠的情况，采用如下复用方式。
方式1包括(1)～(5)：
(1)所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
UE将第一SR复用在承载所述高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第一SR是M个高优先级SR中的任意一个正SR(positive SR)，承载高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
(2)所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
UE将第二SR复用在承载所述高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述所述第二SR是N个低优先级SR中的任意一个正SR，承载高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
(3)所述至少两个PUCCH包括：承载高优先级或低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的 PUCCH；
将第三SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH，其中，所述第三SR是M个高优先级SR和所述N个低优先级SR中的任意一个正SR，所述承载高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0。
也就是，在上述(1)-(3)中，如果承载HP/LP HARQ-ACK的PUCCH的格式为PUCCH格式0，当任意一个HP/LR的SR为positive SR，则UE将该positive SR复用在HP/LP HARQ-ACK PUCCH上传输。
可选地，UE将高优先级SR和低优先级SR复用在承载所述高优先级或低优先级的HARQ-ACK的PUCCH时，所述高优先级SR和低优先级SR采用不同的循环移位(Cyclic Shift，CS)。
可选地，如果高优先级SR和低优先级SR均为positive SR，则UE优先传输高优先级SR。
(4)所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
UE将所述低优先级的HARQ-ACK复用在承载正SR的PUCCH上；
其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为M个高优先级的SR中的任意一个。
(5)所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
UE将所述高优先级的HARQ-ACK复用在承载正SR的PUCCH上；
其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为N个低优先级的SR中的任意一个
在上述(4)和(5)中，如果承载HP/LP HARQ-ACK PUCCH为PUCCH format 1，当任意一个HP/LP PUCCH format 1的SR为positive SR，且没有PUCCH format 0的HP SR为positve时，UE将HARQ-ACK复用在该positive SR PUCCH上传输，如果任意一个PUCCH format 0 HP SR为positive，且 HARQ-ACK PUCCH为LP，则UE传输positive SR，取消HARQ-ACK PUCCH传输，否则UE传输HARQ-ACK PUCCH，不传输SR。
方式2包括：(1)～(6)
(1)所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
UE将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与高优先级的HARQ-ACK的比特复用在第七PUCCH上，其中所述高优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1。
(2)所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
UE将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与低优先级HARQ-ACK的比特复用在第七PUCCH上，其中所述低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈其中，承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1。
(3)所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
UE将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK和低优先级HARQ-ACK比特复用在第七PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈其中，承载所述高优先级HARQ-ACK个低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1。
上述第七PUCCH基于复用后的HARQ-ACK和SR的比特数确定，具体的第七PUCCH的确定方式可以参考第五PUCCH的确定方式。
(4)所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
将表示M个高优先级的SR的log 2(1+M)比特，以及N个低优先级的SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第六PUCCH上；其中，高优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1；
(5)所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
将表示M个高优先级SR的log 2(1+M)比特数，以及N个低优先级SR的log 2(1+N)比特数，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，与低优先级HARQ-ACK复用在第六PUCCH上，其中，所述低优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1；
(6)所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
UE将表示M个高优先级SR的log 2(1+M)比特数，以及N个低优先级SR的log 2(1+N)比特数，或者，将表示M个高优先级的SR和N个低优先级SR的log 2(1+M+N)比特数，与所述高优先级HARQ-ACK和低优先级HARQ-ACK复用在第六PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK均不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
其中，承载所述高优先级HARQ-ACK和低优先级HARQ-ACK的PUCCH 的格式为PUCCH格式0或PUCCH格式1。
上述第六PUCCH基于复用后的HARQ-ACK和SR的比特数确定，具体的第六PUCCH的确定方式可以参考第五PUCCH的确定方式。
在本申请实施例中，可以确保CSI、HP SR和LP SR的传输，提高了通信系统的有效性。
如图3a所示，承载LP HARQ-ACK的PUCCH和承载HP HARQ-ACK的PUCCH的格式均为PUCCH format 1(简称为PF1)，即图中的LP HARQ-ACK PF1和HP HARQ-ACK PF1，承载HP SR的PUCCH的格式为PUCCH format 0(简称为PF0)，即图中的HP SR PF0。
图中所示三个PUCCH在时域上互相重叠，如果UE先处理相同优先级(same priority)的PUCCH之间的重叠，即承载HP HARQ-ACK的PUCCH和承载HP SR的PUCCH，则按照现有的HARQ-ACK和SR的冲突处理规则，UE将只传输HP HARQ-ACK，而不传输HP SR。然后处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的重叠。此时即使支持不同优先级PUCCH之间的复用，HP SR也在第一步中被丢弃，因此会影响到HP SR的传输。
如图3b所示，承载LP HARQ-ACK的PUCCH的格式为PUCCH format 1，即图中的LP HARQ-ACK PF1，承载HP HARQ-ACK的PUCCH和承载LP SR的PUCCH的格式均为PUCCH format 0，即图中的HP HARQ-ACK PF0和LP SR PF0。
图中所示三个PUCCH时域资源互相重叠，如果UE先处理相同优先级的PUCCH之间的重叠，即承载LP HARQ-ACK的PUCCH和承载LP SR的PUCCH，则按照现有的HARQ-ACK和SR的冲突处理规则，UE将只传输LP HARQ-ACK，而不传输LP SR。然后处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的重叠。此时即使支持不同优优先级上行传输之间的复用，LP SR也在第一步中被丢弃，因此会影响到LP SR的传输。
如图3c所示，承载LP HARQ-ACK的PUCCH的格式为PUCCH format 1，承载HP HARQ-ACK的PUCCH的格式为PUCCH format 1，即图中的LP  HARQ-ACK PF1，HP HARQ-ACK PF1，承载HP SR的PUCCH和承载LP SR的PUCCH的格式均为PUCCH format 0，即图中的HP SR PF0和LP SR PF0。
图中所示四个PUCCH时域资源互相重叠，如果UE先处理相同优先级的PUCCH之间的重叠，则按照现有的HARQ-ACK和SR的冲突处理规则，UE将只传输HP HARQ-ACK和LP HARQ-ACK，而不传输HP SR和LP SR。然后处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的重叠。此时即使支持不同优优先级上行传输之间的复用，LP SR和HP SR也在第一步中被丢弃，因此会影响到LP SR和HP SR的传输。
如图3d所示，承载LP HARQ-ACK的PUCCH的格式为PUCCH format 1，承载HP HARQ-ACK的PUCCH的格式为PUCCH format 0，即图中的LP HARQ-ACK PF1，HP HARQ-ACK PF0，承载LP SR的PUCCH的格式为PUCCH format 0，即图中的LP SR PF0。
图中所示三个PUCCH时域资源互相重叠，如果UE先处理相同优先级的PUCCH之间的重叠，则按照现有的HARQ-ACK和SR的冲突处理规则，UE将只传输LP HARQ-ACK，而不传输LP SR。然后处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的重叠。此时即使支持不同优优先级上行传输之间的复用，LP SR也在第一步中被丢弃，因此会影响到LP SR的传输。
为了避免UE将HP SR或者LP SR丢弃，只传输HP HARQ-ACK和LP HARQ-ACK，可以定义如下PUCCH冲突处理方法：
当承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH以及M个承载HP SR的PUCCH，N个承载LP SR的PUCCH重叠时，其中M，N为正整数。
方式1：UE优先处理承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH之间的冲突，例如UE根据复用后的HP HARQ-ACK的比特数和LP HARQ-ACK的比特数确定复用后的PUCCH为PUCCH1。
如果复用后的PUCCH1与承载HP或LRSR的PUCCH冲突，UE再处理两个PUCCH之间的冲突，例如按照现有HARQ-ACK PUCCH和SR PUCCH之间的冲突处理原则，或者按照方式2的方法处理。
方式2：
(1)UE将HP HARQ-ACK，LP HARQ-ACK和M个HP SR复用在一个PUCCH上，例如UE根据复用的HP HARQ-ACK，LP HARQ-ACK和表示M个HP SR的比特数确定复用后的PUCCH。
其中，HP SR的比特数为：log 2(1+M)比特数。
(2)UE将HP HARQ-ACK，LP HARQ-ACK和N个LP SR复用在一个PUCCH上，例如UE根据复用的HP HARQ-ACK，LP HARQ-ACK和表示N个LP SR的比特数确定复用后的PUCCH。
其中，LP SR的比特数为：log 2(1+N)比特数。
(3)UE将HP HARQ-ACK，LP HARQ-ACK、M个HP SR和N个LP SR复用在一个PUCCH上，例如UE根据复用的HP HARQ-ACK的比特数，LP HARQ-ACK的比特数、表示M个HP SR的比特数和表示N个LP SR的比特数确定复用后的PUCCH。
其中，M个HP SR的比特数和表示N个LP SR的比特数为：log 2(1+N+M)个比特数，或者，log 2(1+M)+log 2(1+N)比特数。
如图4a-图4b所示是一个CSI/HARQ-ACK PUCCH与两个SR PUCCH重叠的场景，其中SR包括HP SR和LP SR。HARQ-ACK PUCCH可以是HP HARQ-ACK PUCCH或者LP HARQ-ACK PUCCH。
在图4a和图4b中，CSI/HARQ-ACK PUCCH为PUCCH format 2/3/4，即图中所示的CSI PUCCH PF2/3/4和HARQ-ACK PUCCH PF2/3/4。
现有技术中，当承载CSI的PUCCH，或格式为PUCCH format 2/3/4的承载LP HARQ-ACK的PUCCH与N个承载LP SR的PUCCH重叠时，不管该LP SR是正SR(positive SR)还是负SR(negative SR)，UE将代表N个LP SR状态的log 2(1+N)比特复用在承载CSI的PUCCH上，或者复用在承载LP HARQ-ACK的PUCCH上传输。
如果承载CSI的PUCCH，或格式为PUCCH format 2/3/4的承载LP HARQ-ACK的PUCCH与M个承载HP SR的PUCCH重叠，且M个HP SR中有任意一个为positive SR时，UE将取消优先级较低的CSI或LP HARQ-ACK传输。因此会对优先级较低的CSI或LP HARQ-ACK的传输带 来较大影响。
当一个承载CSI的PUCCH或者承载HP/LP HARQ-ACK的PUCCH与承载HP SR的PUCCH和承载LP SR的PUCCH在时域重叠，且承载CSI或承载HP/LP HARQ-ACK的PUCCH的格式为PUCCH格式2/3/4时，如果UE支持不同优先级PUCCH之间的复用，UE可以采用如下复用方式：
方式1：UE将代表M个HP SR状态的log 2(1+M)比特(bit)，以及N个LP SR状态的log 2(1+N)bit复用在承载CSI的PUCCH，或者承载HP/LP HARQ-ACK的PUCCH上传输。
复用的PUCCH为承载CSI的PUCCH时，其携带的UCI的比特顺序可以是HP SR→LP SR→CSI。
复用的PUCCH为承载HP HARQ-ACK的PUCCH时，其携带的UCI的比特顺序可以是HP HARQ-ACK→HP SR→LP SR。
复用的PUCCH为承载LP HARQ-ACK的PUCCH时，其携带的UCI的比特顺序可以是HP SR→LP HARQ-ACK→LP SR或者LP HARQ-ACK→HP SR→LP SR
如果复用的PUCCH中还包含承载HP HARQ-ACK的PUCCH和承载LP HARQ-ACK的PUCCH(或者还包含承载CSI的PUCCH)，复用的PUCCH上携带的UCI的比特顺序可以为：HP HARQ-ACK→HP SR→LP HARQ-ACK→LP SR(→CSI)或者HP HARQ-ACK→LP HARQ-ACK→HP SR→LP SR(→CSI)。
方式2：UE将代表M个LP SR状态的log 2(1+M)bit，以及N个LP SR状态的log 2(1+N)bit和HARQ-ACK复用在一个PUCCH上传输，该PUCCH为基于复用后的HARQ-ACK和SR的比特数确定。
如图4c和图4d中，承载HARQ-ACK的PUCCH的格式为PUCCH format 0/1，现有技术中，对于相同的优先级，当格式为PUCCH format 0的承载HARQ-ACK的PUCCH与N个承载LP SR PUCCH重叠时，则UE将N个LP SR复用到承载HARQ-ACK的PUCCH上传输，其中如果LP SR为negative SR，则传输时使用的循环移位(Cyclic Shift)与只传输HARQ-ACK时相同，如果任意一个LP SR为positive SR，则UE使用不同的循环移位(相对于只传输 HARQ-ACK时相同)传输LP SR和HARQ-ACK。
当格式为PUCCH format 1的HARQ-ACK的PUCCH与N个承载LP SR的PUCCH重叠时，如果任意一个格式为PUCCH format 1的PUCCH承载的LP SR为positive SR，则UE将HARQ-ACK复用到承载SR的PUCCH上传输，如果承载positive SR的PUCCH的格式为PUCCH format 0，则UE只传输HARQ-ACK，丢弃SR。如果不同优先级，则UE丢弃低优先级的PUCCH，只传输高优先级的上行传输。
当一个承载HARQ-ACK的PUCCH与N个承载HP SR的PUCCH和M个承载LP SR的PUCCH在时域上重叠，且承载HARQ-ACK的PUCCH的格式为PUCCH格式0/1时，如果UE支持不同优先级PUCCH之间的复用，UE可以采用如下复用方式：
方式1：
a)如果承载HARQ-ACK(HP HARQ-ACK和/或LP HARQ-ACK)的PUCCH的格式为PUCCH format 0，当HP SR和/或LR SR为positive SR，则UE将该positive SR复用在承载HARQ-ACK的PUCCH上传输；
可选的，UE在承载HARQ-ACK的PUCCH上传输HP SR和LP SR时可以采用不同的CS。
如果HP SR和LP SR均为positive SR，则UE优先传输HP SR。
b)如果承载HARQ-ACK(HP HARQ-ACK和/或LP HARQ-ACK)的PUCCH的格式为PUCCH format 1，当格式为PUCCH format 1的PUCCH承载的HP SR和/或LP SR为positive SR，且没有格式为PUCCH format 0的PUCCH的HP SR和/或LP SR为positve SR时，UE将HARQ-ACK复用在承载该positive SR的PUCCH上传输；
如果格式为PUCCH format 0的PUCCH承载的HP SR为positive SR，且冲突PUCCH承载的是LP HARQ-ACK，则UE传输positive SR，取消LP HARQ-ACK传输，否则UE传输LP HARQ-ACK PUCCH，不传输positive SR。
方式2：
如果HARQ-ACK包含PDCCH调度的PDSCH的反馈，则UE将表示M个LP SR状态的log 2(1+M)bit，以及表示N个LP SR状态的log 2(1+N) bit和HARQ-ACK复用在一个PUCCH上传输，该PUCCH为基于复用后的HARQ-ACK和SR的比特数确定。
如果HARQ-ACK不包含PDCCH调度的PDSCH的反馈，且UE配置了SPS-PUCCH-AN-List，则UE将表示M个LP SR状态的log 2(1+M)bit，以及表示N个LP SR状态的log 2(1+N)bit和HARQ-ACK复用在一个PUCCH上传输，该PUCCH为基于复用后的HARQ-ACK和SR的比特数确定；否则可以采用方式1。
参见图5，本申请实施例提供一种PUCCH资源重叠的处理装置，应用于终端，该装置500包括：
处理模块501，用于在至少两个PUCCH传输资源重叠的情况下，将所述至少两个PUCCH传输进行复用；
其中，所述至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH。
在本申请实施例中，处理模块501进一步用于：根据第一信息，将所述至少两个PUCCH传输进行复用；
其中，所述第一信息包括以下至少一项：
(1)PUCCH承载上行控制信息的类型；
(2)PUCCH的优先级；
(3)PUCCH的格式。
在本申请实施例中，所述至少两个PUCCH包括以下至少一项：
(1)承载高优先级混合自动重传请求应答HARQ-ACK的PUCCH和承载低优先级HARQ-ACK的PUCCH；
(2)承载HARQ-ACK的PUCCH和承载调度请求SR的PUCCH；
(3)承载CSI的PUCCH和承载SR的PUCCH；
(4)承载CSI的PUCCH、承载HARQ-ACK的PUCCH和承载SR的PUCCH；
其中，
所述承载HARQ-ACK的PUCCH包括：承载高优先级HARQ-ACK的PUCCH和/或承载低优先级HARQ-ACK的PUCCH；
所述承载SR的PUCCH包括：M个承载高优先级SR的PUCCH和/或N个承载低优先级SR的PUCCH；
其中，M和N为正整数。
在本申请实施例中，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块501进一步用于：将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
如果所述第一PUCCH与M’个承载高优先级SR的PUCCH重叠，则将所述第一PUCCH与所述M’个承载高优先级SR的PUCCH进行复用，其中所述M’与M相等或不相等；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH和N’个承载低优先级SR的PUCCH；
处理模块501进一步用于：将承载高优先级HARQ-ACK的PUCCH与承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
如果所述第一PUCCH与所述N’个承载低优先级的SR的PUCCH重叠，则将所述第一PUCCH与所述N’个承载低优先级的SR的PUCCH进行复用，其中所述N’与N相等或不相等；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：将所述承载高优先级HARQ-ACK的PUCCH与所述承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
如果所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH重叠，则将所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH进行复用，其中所述N’与N相等或不相等，所述M’与M相等或不相等。
可选地，所述第一PUCCH是所述高优先级HARQ-ACK的比特数和低优先级HARQ-ACK的比特数确定的。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块501进一步用于：将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及M个高优先级SR，复用在第二PUCCH上；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及所述N个低优先级SR，复用在第二PUCCH上；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，所述M个高优先级SR和所述N个低优先级SR，复用在第二PUCCH上。
可选地，所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数、所述M个高优先级SR的比特数、所述N个低优先级SR的比特数中的一项或多项组合确定的。
可选地，所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和所述M个高优先级SR的比特数确定的；
其中，所述M个高优先级SR的比特数为：log 2(1+M)；
或者，
所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和所述N个低优先级SR的比特数确定的；
其中，所述N个低优先级SR的比特数为：log 2(1+N)；
或者，
所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数、所述M个高优先级SR和所述N个低优先级SR的比特数确定的；
其中，所述M个高优先级SR和所述N个低优先级SR的比特数为：log 2(1+M)与log 2(1+N)之和，或者log 2(1+M+N)。
可选地，所述至少两个PUCCH包括：承载CSI的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：将M个高优先级SR、N个低优先级SR复用在所述承载CSI的PUCCH上。
可选地，所述至少两个PUCCH包括：承载CSI的PUCCH、M个承载高优先级SR的PUCCH；
处理模块501进一步用于：将M个高优先级SR在所述承载CSI的PUCCH上。
可选地，处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特复用在所述承载CSI的PUCCH上；
或者，
将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载CSI的PUCCH上；
或者，
将表示M个高优先级SR的log 2(1+M)比特复用在所述承载CSI的PUCCH上。
可选地，所述M个高优先级SR的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前；或者，所述M个高优先级SR的比特位置位于所述CSI的比特位置之前。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的 PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将所述M个高优先级SR、所述N个低优先级SR复用在所述承载高优先级的HARQ-ACK的PUCCH上，其中，所述承载高优先级的HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
可选地，处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)个比特复用在所述承载高优先级的HARQ-ACK的PUCCH上；
或者，
将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载高优先级HARQ-ACK的PUCCH上。
可选地，所述高优先级HARQ-ACK的比特位置位于M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于表示N个低优先级SR的比特位置之前。
可选地，所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
可选地，处理模块501进一步用于：
将M个高优先级SR、N个低优先级SR复用在所述承载低优先级HARQ-ACK的PUCCH上；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
可选地，处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特复用在所述承载低优先级HARQ-ACK的PUCCH上；
或者，
将表示M个高优先级SR和N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载低优先级HARQ-ACK的PUCCH上。
可选地，所述M个高优先级SR的比特位置位于所述低优先级 HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将所述M个高优先级SR、所述N个低优先级SR和所述低优先级HARQ-ACK复用在所述承载高优先级HARQ-ACK的PUCCH上；
其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR和所述高优先级HARQ-ACK复用在所述承载低优先级HARQ-ACK的PUCCH上；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK，复用在第三PUCCH上，所述第三PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数和所述低优先级HARQ-ACK的比特数确定的。
可选地，所述高优先级HARQ-ACK的比特位置位于M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于N个低优先级SR的比特位置之前。
可选地，所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述N个低优先级SR的比特位置之前。
可选地，所述至少两个PUCCH包括：承载CSI的PUCCH、承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将所述M个高优先级SR、所述N个低优先级SR、所述低优先级HARQ-ACK和所述CSI复用在所述承载高优先级HARQ-ACK的PUCCH上；
其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述CSI复用在所述承载低优先级HARQ-ACK的PUCCH上；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK复用在所述承载CSI的PUCCH；
或者，
将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK、所述低优先级HARQ-ACK和所述CSI复用在第四PUCCH，所述第四PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和CSI的比特数确定的。
可选地，所述高优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前。
可选地，所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所 述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前。
可选地，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第五PUCCH上，其中所述高优先级HARQ-ACK包含对有PDCCH调度的物理下行共享信道PDSCH的反馈；
或者，
所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述低优先级HARQ-ACK复用在第五PUCCH上，所述低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级的SR和N个低优先级的SR的log 2(1+M+N)比特，与高优先级HARQ-ACK和低优先级HARQ-ACK复用在第五PUCCH上，所述高优先级HARQ-ACK和低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈。
可选地，所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块501进一步用于：
将第一SR复用在所述承载高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第一SR是M个高优先级SR中的任意一个正SR，承载所述高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
或者，
所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将第二SR复用在承载所述高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第二SR是N个低优先级SR中的任意一个正SR，承载所述高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
或者，
所述至少两个PUCCH包括：承载高优先级或低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将第三SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH，其中，所述第三SR是M个高优先级SR和N个低优先级SR中任意一个的正SR，所述承载高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0。
可选地，所述将M个高优先级SR和所述N个低优先级SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH时，所述高优先级SR和低优先级SR采用不同的循环移位。
可选地，所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
处理模块501进一步用于：将所述低优先级的HARQ-ACK复用在承载正SR的PUCCH上；
其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式 1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为M个高优先级的SR中的任意一个；
或者，
所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
处理模块501进一步用于：将所述高优先级的HARQ-ACK复用在承载正SR的PUCCH上；
其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为N个低优先级的SR中的任意一个。
可选地，所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及表示N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与高优先级HARQ-ACK的比特复用在第七PUCCH上，其中所述高优先级HARQ-ACK包含有对PDCCH调度的PDSCH的反馈；
其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1；
或者，
所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述低优先级HARQ-ACK复用在第七PUCCH上，其中所述低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈；
其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0或PUCCH格式1；
或者，
所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK和低优先级HARQ-ACK复用在第七PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈。
可选地，所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第六PUCCH上，其中，所述高优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
或者，
所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与低优先级HARQ-ACK复用在第六PUCCH上，其中所述低优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
或者，
所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低 优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
处理模块501进一步用于：
将表示M个高优先级SR的log 2(1+M)比特，以及N个低优先级SR的log 2(1+N)比特，或者，将表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK和低优先级HARQ-ACK复用在第六PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK均不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表。
可选地，所述第五PUCCH、第六PUCCH或第七PUCCH是根据以下任一项确定的：
表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的；
或者，
表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的；
或者，
表示M个高优先级SR的log 2(1+M)比特数，表示N个低优先级SR的log 2(1+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的，或者，表示M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的。
本申请实施例提供的PUCCH资源重叠的处理装置能够实现图2所示的方法实施例实现的各个过程，并达到相同的技术效果，为避免重复，这里不再赘述。
图6为实现本申请实施例的一种终端的硬件结构示意图。
该终端600包括但不限于：射频单元601、网络模块602、音频输出单元603、输入单元604、传感器605、显示单元606、用户输入单元607、接口单元608、存储器609、以及处理器610等部件。
本领域技术人员可以理解，终端600还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器610逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图6中示出的终端结构并不构成对终端的限定，终端可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
应理解的是，本申请实施例中，输入单元604可以包括图形处理器(Graphics Processing Unit，GPU)6041和麦克风6042，图形处理器6041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元606可包括显示面板6061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板6061。用户输入单元607包括触控面板6061以及其他输入设备6072。触控面板6061，也称为触摸屏。触控面板6061可包括触摸检测装置和触摸控制器两个部分。其他输入设备6072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
本申请实施例中，射频单元601将来自网络侧设备的下行数据接收后，给处理器610处理；另外，将上行的数据发送给网络侧设备。通常，射频单元601包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。
存储器609可用于存储软件程序或指令以及各种数据。存储器609可主要包括存储程序或指令区和存储数据区，其中，存储程序或指令区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器609可以包括高速随机存取存储器，还可以包括非易失性存储器，其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储 器(Electrically EPROM，EEPROM)或闪存。例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。
处理器610可包括一个或多个处理单元；可选的，处理器610可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序或指令等，调制解调处理器主要处理无线通信，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器610中。
本申请实施例提供的终端能够实现图2所示的方法实施例实现的各个过程，并达到相同的技术效果，为避免重复，这里不再赘述。
本申请实施例还提供一种程序产品，所述程序产品被存储在非易失的存储介质中，所述程序产品被至少一个处理器执行以实现如图2所述的处理的方法的步骤。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述图2所示方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的终端中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行网络侧设备程序或指令，实现上述图2所示方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片，系统芯片，芯片系统或片上系统芯片等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方 法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本公开的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通 过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
可以理解的是，本公开实施例描述的这些实施例可以用硬件、软件、固件、中间件、微码或其组合来实现。对于硬件实现，模块、单元、子单元可以实现在一个或多个专用集成电路(Application Specific Integrated Circuits，ASIC)、数字信号处理器(Digital Signal Processor，DSP)、数字信号处理设备(DSP Device，DSPD)、可编程逻辑设备(Programmable Logic Device，PLD)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、通用处理器、控制器、微控制器、微处理器、用于执行本公开所述功能的其它电子单元或其组合中。
对于软件实现，可通过执行本公开实施例所述功能的模块(例如过程、函数等)来实现本公开实施例所述的技术。软件代码可存储在存储器中并通过处理器执行。存储器可以在处理器中或在处理器外部实现。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (33)

  1. 一种物理上行控制信道PUCCH资源重叠的处理方法，包括：
    在至少两个PUCCH传输资源重叠的情况下，终端将所述至少两个PUCCH传输进行复用；
    其中，所述至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH。
  2. 根据权利要求1所述的方法，其中，所述终端将所述至少两个PUCCH传输进行复用，包括：
    根据第一信息，所述终端将所述至少两个PUCCH传输进行复用；
    其中，所述第一信息包括以下至少一项：
    PUCCH承载上行控制信息的类型；
    PUCCH的优先级；
    PUCCH的格式。
  3. 根据权利要求1或2所述的处理方法，其中，所述至少两个PUCCH包括以下至少一项：
    承载高优先级混合自动重传请求应答HARQ-ACK的PUCCH和承载低优先级HARQ-ACK的PUCCH；
    承载HARQ-ACK的PUCCH和承载调度请求SR的PUCCH；
    承载信道状态信息CSI的PUCCH和承载SR的PUCCH；
    承载CSI的PUCCH、承载HARQ-ACK的PUCCH和承载SR的PUCCH；
    其中，
    所述承载HARQ-ACK的PUCCH包括：承载高优先级HARQ-ACK的PUCCH和/或承载低优先级HARQ-ACK的PUCCH；
    所述承载SR的PUCCH包括：M个承载高优先级SR的PUCCH和/或N个承载低优先级SR的PUCCH；
    其中，M和N为正整数。
  4. 根据权利要求3所述的方法，其中，所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、 M个承载高优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述承载高优先级HARQ-ACK的PUCCH与所述承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
    如果所述第一PUCCH与M’个承载高优先级SR的PUCCH重叠，则将所述第一PUCCH与所述M’个承载高优先级SR的PUCCH进行复用，其中所述M’与M相等或不相等；
    或者，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述承载高优先级HARQ-ACK的PUCCH与所述承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
    如果所述第一PUCCH与N’个承载低优先级的SR的PUCCH重叠，则将所述第一PUCCH与所述N’个承载低优先级的SR的PUCCH进行复用，其中所述N’与N相等或不相等；
    或者，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述承载高优先级HARQ-ACK的PUCCH与所述承载低优先级HARQ-ACK的PUCCH复用，得到第一PUCCH；
    如果所述第一PUCCH与M’个承载高优先级SR的PUCCH和N’个承载低优先级SR的PUCCH重叠，则将所述第一PUCCH与所述M’个承载高优先级SR的PUCCH和所述N’个承载低优先级SR的PUCCH进行复用，其中所述N’与N相等或不相等，所述M’与M相等或不相等。
  5. 根据权利要求4所述的方法，其中，所述第一PUCCH是所述高优先级HARQ-ACK的比特数和低优先级HARQ-ACK的比特数确定的。
  6. 根据权利要求3所述的方法，其中，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及所述M个高优先级SR，复用在第二PUCCH上；
    或者，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，以及所述N个低优先级SR，复用在第二PUCCH上；
    或者，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述高优先级HARQ-ACK、所述低优先级HARQ-ACK，所述M个高优先级SR和所述N个低优先级SR，复用在第二PUCCH上。
  7. 根据权利要求6所述的方法，其中，
    所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数、所述M个高优先级SR的比特数、所述N个低优先级SR的比特数中的一项或多项组合确定的。
  8. 根据权利要求7所述的方法，其中，
    所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和所述M个高优先级SR的比特数确定的；
    其中，所述M个高优先级SR的比特数为：log 2(1+M)；
    或者，
    所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优 先级HARQ-ACK的比特数和所述N个低优先级SR的比特数确定的；
    其中，所述N个低优先级SR的比特数为：log 2(1+N)；
    或者，
    所述第二PUCCH是根据所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数、所述M个高优先级SR和所述N个低优先级SR的比特数确定的；
    其中，所述M个高优先级SR和所述N个低优先级SR的比特数为：log 2(1+M)与log 2(1+N)之和，或者log 2(1+M+N)。
  9. 根据权利要求3所述的处理方法，其中，
    所述至少两个PUCCH包括：承载CSI的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述M个高优先级SR、所述N个低优先级SR复用在所述承载CSI的PUCCH上；
    或者
    所述至少两个PUCCH包括：承载CSI的PUCCH、M个承载高优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述M个高优先级SR在所述承载CSI的PUCCH上。
  10. 根据权利要求9所述的处理方法，其中，所述终端将所述M个高优先级SR、所述N个低优先级SR复用在所述承载CSI的PUCCH上，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特复用在所述承载CSI的PUCCH上；
    或者，
    所述终端将表示所述M个高优先级SR和所述N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载CSI的PUCCH上；
    或者
    所述终端将所述M个高优先级SR复用在所述承载CSI的PUCCH上，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特复用在所述承载CSI的PUCCH上。
  11. 根据权利要求9或10所述的处理方法，其中，
    所述M个高优先级SR的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前；
    或者，
    所述M个高优先级SR的比特位置位于所述CSI的比特位置之前。
  12. 根据权利要求3所述的处理方法，其中，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将所述至少两个PUCCH传输进行复用，包括：
    所述终端将所述M个高优先级SR、所述N个低优先级SR复用在所述承载高优先级的HARQ-ACK的PUCCH上，其中，所述承载高优先级的HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
  13. 根据权利要求12所述的处理方法，其中，所述终端将所述M个高优先级SR、所述N个低优先级SR复用在所述承载高优先级HARQ-ACK的PUCCH上，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特复用在所述承载高优先级的HARQ-ACK的PUCCH上；
    或者，
    所述终端将表示所述M个高优先级SR和所述N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载高优先级HARQ-ACK的PUCCH上。
  14. 根据权利要求12或13所述的处理方法，其中，
    所述高优先级HARQ-ACK的比特位置位于M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于表示N个低优先级SR的比特位置之前。
  15. 根据权利要求3所述的处理方法，其中，
    所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述M个高优先级SR、所述N个低优先级SR复用在所述承载低优先级HARQ-ACK的PUCCH上；
    其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4。
  16. 根据权利要求15所述的处理方法，其中，所述终端将M个高优先级SR、N个低优先级SR复用在所述承载低优先级HARQ-ACK的PUCCH上，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特复用在所述承载低优先级HARQ-ACK的PUCCH上；
    或者，
    所述终端将表示所述M个高优先级SR和所述N个的低优先级SR的log 2(1+M+N)比特，复用在所述承载低优先级HARQ-ACK的PUCCH上。
  17. 根据权利要求15或16所述的处理方法，其中，
    所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前。
  18. 根据权利要求3所述的处理方法，其中，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述M个高优先级SR、所述N个低优先级SR和所述低优先级HARQ-ACK复用在所述承载高优先级HARQ-ACK的PUCCH上；
    其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
    或者，
    所述终端将所述M个高优先级SR、所述N个低优先级SR和所述高优先级HARQ-ACK复用在所述承载低优先级HARQ-ACK的PUCCH上；
    其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
    或者，
    所述终端将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK，复用在第三PUCCH上，所述第三PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数和所述低优先级HARQ-ACK的比特数确定的。
  19. 根据权利要求18所述的处理方法，其中，
    所述高优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前；
    或者
    所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述N个低优先级SR的比特位置之前。
  20. 根据权利要求3所述的处理方法，其中，
    所述至少两个PUCCH包括：承载CSI的PUCCH、承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述M个高优先级SR、所述N个低优先级SR、所述低优先级HARQ-ACK和所述CSI复用在所述承载高优先级HARQ-ACK的PUCCH上；
    其中，所述承载高优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
    或者，
    所述终端将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述CSI复用在所述承载低优先级HARQ-ACK的PUCCH上；
    其中，所述承载低优先级HARQ-ACK的PUCCH的格式为PUCCH格式2，PUCCH格式3或者PUCCH格式4；
    或者，
    所述终端将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK和所述低优先级HARQ-ACK复用在所述承载CSI的PUCCH；
    或者，
    所述终端将所述M个高优先级SR、所述N个低优先级SR、所述高优先级HARQ-ACK、所述低优先级HARQ-ACK和所述CSI复用在第四PUCCH，所述第四PUCCH是基于所述M个高优先级SR的比特数、所述N个低优先级SR的比特数、所述高优先级HARQ-ACK的比特数、所述低优先级HARQ-ACK的比特数和CSI的比特数确定的。
  21. 根据权利要求20所述的处理方法，其中，
    所述高优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前；
    或者，
    所述高优先级HARQ-ACK的比特位置位于所述低优先级HARQ-ACK的比特位置之前，所述低优先级HARQ-ACK的比特位置位于所述M个高优先级SR的比特位置之前，所述M个高优先级SR的比特位置位于N个低优先级SR的比特位置之前，所述N个低优先级SR的比特位置位于所述CSI的比特位置之前。
  22. 根据权利要求3所述的处理方法，其中，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)个比特，以及表示所述N个低优先级SR的log 2(1+N)比特，或者，将表示所述M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第五PUCCH上，所述所述高优先级HARQ-ACK包含对有物理下行控制信道PDCCH调度的物理下行共享信道PDSCH的反馈；
    或者，
    所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特，或者，将表示所述M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述低优先级HARQ-ACK复用在第五PUCCH上，所述低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈；
    或者，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将表示所述M高优先级SR的log 2(1+M)比特，以及所述N个低优先级SR的log 2(1+N)比特，或者，将表示所述M个高优先级的SR和N个低优先级的SR的log 2(1+M+N)比特，与高优先级HARQ-ACK和低优先级HARQ-ACK复用在第五PUCCH上，所述高优先级HARQ-ACK和或低优先级HARQ-ACK包含对有PDCCH调度的PDSCH的反馈。
  23. 根据权利要求3所述的方法，其中，
    所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将第一SR复用在所述承载高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第一SR是M个高优先级SR中的任意一个正SR，承载所述高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
    或者，
    所述至少两个PUCCH包括：承载高优先级或低优先级的HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将第二SR复用在承载所述高优先级或低优先级的HARQ-ACK的PUCCH，其中，所述第二SR是N个低优先级SR中的任意一个正SR，承载所述高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0；
    或者，
    所述至少两个PUCCH包括：承载高优先级或低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将第三SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH，其中，所述第三SR是所述M个高优先级SR和N个低优先级SR中任意一个的正SR，所述承载高优先级或低优先级HARQ-ACK的PUCCH的格式为PUCCH格式0。
  24. 根据权利要求23所述的方法，其中，所述将M个高优先级SR和所述N个低优先级SR复用在所述承载高优先级或低优先级HARQ-ACK的PUCCH时，所述高优先级SR和低优先级SR采用不同的循环移位。
  25. 根据权利要求3所述的方法，其中，
    所述至少两个PUCCH包括：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述低优先级的HARQ-ACK复用在承载正SR的PUCCH上；
    其中，承载所述低优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为所述M个高优先级的SR中的任意一个；
    或者，
    所述至少两个PUCCH包括：承载高优先级HARQ-ACK的PUCCH、N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将所述高优先级的HARQ-ACK复用在承载正SR的PUCCH上；
    其中，承载所述高优先级HARQ-ACK的PUCCH的格式为PUCCH格式1，所述承载正SR的PUCCH的格式为PUCCH格式1，所述正SR为所述N个低优先级的SR中的任意一个。
  26. 根据权利要求3所述的方法，其中，
    所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特，或者，将表示所述M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK复用在第六PUCCH上，其中，所述高优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
    或者，
    所述至少两个PUCCH：承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特，或者，将表示所述M个高优先 级SR和N个低优先级SR的log 2(1+M+N)比特，与所述低优先级HARQ-ACK复用在第六PUCCH上，其中所述低优先级HARQ-ACK不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表；
    或者，
    所述至少两个PUCCH：承载高优先级HARQ-ACK的PUCCH、承载低优先级HARQ-ACK的PUCCH、M个承载高优先级SR的PUCCH和N个承载低优先级SR的PUCCH；
    所述终端将至少两个PUCCH传输进行复用，包括：
    所述终端将表示所述M个高优先级SR的log 2(1+M)比特，以及表示所述N个低优先级SR的log 2(1+N)比特，或者，将表示所述M个高优先级SR和N个低优先级SR的log 2(1+M+N)比特，与所述高优先级HARQ-ACK和低优先级HARQ-ACK复用在第六PUCCH上，其中所述高优先级HARQ-ACK和低优先级HARQ-ACK均不包含对有PDCCH调度的PDSCH的反馈，且所述终端配置了SPS HARQ-ACK反馈PUCCH列表。
  27. 根据权利要求22或26所述的方法，其中，所述第五PUCCH或第六PUCCH是根据以下任一项确定的：
    表示所述M个高优先级SR的log 2(1+M)比特数，表示所述N个低优先级SR的log 2(1+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的，或者，表示所述M个高优先级SR和所述N个低优先级SR的log 2(1+M+N)比特数，以及所述高优先级HARQ-ACK的比特数确定的；
    或者，
    表示所述M个高优先级SR的log 2(1+M)比特数，表示所述N个低优先级SR的log 2(1+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的，或者，表示所述M个高优先级SR和所述N个低优先级SR的log 2(1+M+N)比特数，以及所述低优先级HARQ-ACK的比特数确定的；
    或者，
    表示所述M个高优先级SR的log 2(1+M)比特数，表示所述N个低优先级SR的log 2(1+N)比特数，所述高优先级HARQ-ACK的比特数以及所 述低优先级HARQ-ACK的比特数确定的，或者，表示所述M个高优先级SR和所述N个低优先级SR的log 2(1+M+N)比特数，所述高优先级HARQ-ACK的比特数以及所述低优先级HARQ-ACK的比特数确定的。
  28. 一种PUCCH资源重叠的处理装置，应用于终端，包括：
    处理模块，用于在至少两个PUCCH传输资源重叠的情况下，将所述至少两个PUCCH传输进行复用；
    其中，所述至少两个PUCCH中包含：高优先级的PUCCH和低优先级的PUCCH。
  29. 一种终端，包括：处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序，所述程序被所述处理器执行时实现如权利要求1至27中任一项所述的方法的步骤。
  30. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1至27中任一项所述的方法的步骤。
  31. 一种程序产品，所述程序产品被存储在非易失的存储介质中，所述程序产品被至少一个处理器执行以实现如权利要求1至27中任一项所述的方法的步骤。
  32. 一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如权利要求1至27中任一项所述的方法。
  33. 一种终端，所述终端被配置成用于执行如权利要求1至27中任一项所述的方法。
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