WO2022016983A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2022016983A1
WO2022016983A1 PCT/CN2021/095607 CN2021095607W WO2022016983A1 WO 2022016983 A1 WO2022016983 A1 WO 2022016983A1 CN 2021095607 W CN2021095607 W CN 2021095607W WO 2022016983 A1 WO2022016983 A1 WO 2022016983A1
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Prior art keywords
wafer
conductive plug
layer
conductive
groove
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English (en)
French (fr)
Inventor
吴秉桓
张志伟
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/389,693 priority Critical patent/US20220028796A1/en
Publication of WO2022016983A1 publication Critical patent/WO2022016983A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Definitions

  • the embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor structure and a method for forming the same.
  • components with good thermal conductivity are usually built into the wafer to conduct and dissipate heat from a certain position of the wafer, such as pseudo-conductive plugs.
  • the existing technology usually adjusts the poorly deposited part, however, the existing technology has some problems.
  • Some embodiments of the present application provide a semiconductor structure and a method for forming the same, which are beneficial to improve the performance of the semiconductor structure.
  • some embodiments of the present application provide a method for forming a semiconductor structure, including: providing a wafer, the wafer has a front surface and a back surface, and the wafer has conductive plugs, the conductive plugs are The front surface extends to the back surface, and the bottom surface of the conductive plug is located in the wafer; an etching process is performed on the back surface of the wafer to form a groove at least exposing the bottom surface of the conductive plug; forming a groove covering the bottom surface of the conductive plug The functional layer on the bottom surface of the conductive plug is described.
  • the method further includes: performing a planarization process on the back surface of the wafer.
  • the wafer has a plurality of the conductive plugs, and in a direction perpendicular to the back surface of the wafer, the bottom surfaces of the plurality of conductive plugs have different heights; the groove exposes any of the conductive plugs. the underside of the plug.
  • the groove also exposes part of the sidewall of the conductive plug; in the process step of forming the functional layer, the functional layer is also formed on the part of the sidewall of the conductive plug.
  • the bottom surface of the conductive plug is covered with a protective layer; in the process step of forming the groove, the etching process is also used to remove the protective layer.
  • the functional layer includes a blocking layer covering the bottom surface of the conductive plug and a dielectric layer filling the groove, where the blocking layer is used to block metal ions in the conductive plug from migrating into the dielectric layer.
  • the material of the dielectric layer includes at least one of silicon dioxide, silicon nitride or silicon oxynitride
  • the material of the blocking layer includes silicon carbonitride
  • the functional layer includes a bonding layer for performing a fusion bonding process.
  • some embodiments of the present application further provide a semiconductor structure, including: a wafer, the wafer has a front surface and a back surface, and the wafer has conductive plugs, the conductive plugs face from the front surface to the the back surface extends, and the bottom surface of the conductive plug is located in the wafer; a groove, the top opening of the groove is located on the plane where the back surface of the wafer is located, and the groove at least exposes the bottom surface of the conductive plug; function layer, the functional layer covers the bottom surface of the conductive plug.
  • the groove exposes the bottom surface and part of the sidewall of the conductive plug
  • the functional layer covers the bottom surface and part of the sidewall of the conductive plug.
  • the height difference between the bottom surface of the groove and the bottom surface of the conductive plug is 2 nm ⁇ 10 nm.
  • the functional layer is a laminated structure
  • the laminated structure includes a blocking layer covering the bottom surface of the conductive plug, and a dielectric layer filling the groove, and the blocking layer is used to block the conductive plug
  • the metal ions in the medium migrate into the dielectric layer.
  • the material of the blocking layer includes silicon carbonitride, or the blocking layer includes a tantalum layer and a tantalum nitride layer stacked in sequence, the tantalum layer covers the bottom surface of the conductive plug, and the tantalum nitride layer layer overlies the tantalum layer.
  • the conductive plugs and the grooves are arranged in a marking pattern.
  • the use of an etching process to expose the bottom surface of the conductive plug is beneficial to avoid stress damage to the conductive plug and its adjacent structures during the exposure process, and to avoid the conductive plug and its adjacent structures due to the exposure process.
  • the structural change occurs due to the stress problem, so as to ensure that the semiconductor structure has good performance.
  • the groove exposes the bottom surface of any conductive plug, so that the bottom surface of any conductive plug can be covered by the functional layer, which is beneficial to avoid performance defects of the semiconductor structure caused by the bottom surface of some conductive plugs not being covered by the functional layer.
  • 1 to 4 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure
  • 5 to 12 are schematic structural diagrams corresponding to each step of a method for forming a semiconductor structure according to an embodiment of the present application
  • FIG. 13 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present application.
  • a semiconductor structure includes: a wafer 10 having a front side 101 and a back side 102 opposite to the front side 101, the wafer 10 having conductive plugs 11 therein, the conductive plugs 11 extending from the front side 101 to the back side 102, and The bottom surface of the conductive plug 11 is located in the wafer 10 ; the protective layer 12 covers the bottom surface and sidewalls of the conductive plug 11 ; the marking pattern 13 is located on the front surface 101 of the wafer.
  • the protective layer 12 can be a laminated structure, and the protective layer 12 can include a blocking layer covering the bottom surface and sidewalls of the conductive plug 11 and a dielectric layer covering the surface of the blocking layer, and the blocking layer is used to avoid metal ions in the conductive plug 11. Migrating into the wafer 10 , the dielectric layer is used to prevent the conductive plug 11 from leaking.
  • the bottom corner area also includes a portion of the sidewall of the groove.
  • the problem of poor deposition may cause the protection layer 12 to fail to achieve a good protection effect, thereby causing performance defects in the semiconductor structure, such as diffusion of metal ions in the conductive plug 11 and leakage of the conductive plug 11 .
  • the marking pattern 13 is located on the front side 101, when processing the back side 102 of the wafer 10, it is necessary to identify and utilize the marking pattern 13 located on the front side 101, which is difficult and has a large alignment error.
  • a first planarization process is performed to remove the wafer 10 located on the bottom surface of the conductive plugs 11 to expose the bottom surface of the conductive plugs 11 ;
  • an etching process is performed to remove part of the side covering the conductive plugs 11 .
  • the protective layer 12 of the walls and the wafer 10 between adjacent conductive plugs 11 are used to expose part of the sidewalls of the conductive plugs 11 , which usually have the problem of poor deposition of the protective layer 12 .
  • the removal rate of the planarization process is generally higher than that of the etching process, the bottom surface of the conductive plug 11 is exposed by the planarization process first, and then part of the sidewall of the conductive plug 11 is exposed by the etching process, which can shorten the cycle of the entire process.
  • the planarization process will generate a certain tensile stress.
  • the planarization process is performed based on the bottom surface of the conductive plug 11, the tensile stress will be exerted on the conductive plug 11, so that the conductive plug 11 will continue to move toward the periphery during the process.
  • the structure exerts compressive stress, thereby causing the conductive plug 11 to be delaminated from the protective layer 12 , forming the first void 111 , and causing part of the protective layer 12 to crack.
  • the broken protective layer 12 debris may fall into the first gap 111, and when the protective layer 12 and the conductive plug 11 are re-sealed and joined, the existence of the protective layer 12 debris may cause the protective layer 12 and the conductive plug 11.
  • the existence of debris in the protective layer 12 may lead to stress concentration problems, and further damage the intact protective layer 12 .
  • a dielectric material is deposited on the back surface 102 of the wafer 10 , and a second planarization process is performed to form a dielectric layer 14 exposing the bottom surface of the conductive plug 11 .
  • the second planarization process is also performed based on the bottom surface of the conductive plug 11. That is to say, the second planarization process also pulls the conductive plug 11, thereby causing conductive A second void 131 is created between the plug 11 and the dielectric layer 14 , and a portion of the dielectric layer 14 close to the conductive plug 11 is cracked.
  • the present application provides a semiconductor structure and a method for forming the same.
  • an etching process is used instead of the planarization process to form a groove for exposing the bottom surface of the conductive plug. , to avoid damage to the conductive plug and the structure around the conductive plug caused by the pulling stress of the planarization process, thereby ensuring that the semiconductor structure has good performance.
  • FIG. 5 to FIG. 12 are schematic structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present application.
  • a wafer 20 is provided, the wafer 20 has a front side 201 and a back side 202 opposite to the front side 201, the wafer 20 has conductive plugs 21 therein, the conductive plugs 21 extend from the front side 201 to the back side 202, and the conductive plugs The bottom surface 21 is located within the wafer 20 .
  • the planarization process has a lower removal rate and higher surface finish quality, and can be used to remove deep scratches formed during the thinning process.
  • the planarization process uses the polishing head to apply pressure to the polishing pad and drive the polishing pad to rotate, so that the polishing liquid between the polishing pad and the wafer can be evenly distributed on the surface of the wafer, so that the chemical composition in the polishing liquid can be matched with that of the wafer.
  • the surface material of the wafer undergoes a chemical reaction to convert insoluble substances into soluble substances, or soften substances with high hardness, and then remove these chemical reactants through the micro-mechanical friction of abrasive particles in the grinding fluid to achieve the purpose of planarization .
  • setting the distance between the bottom surface of the conductive plug 21 and the back surface 202 of the wafer 20 is greater than or equal to the first preset distance, which is beneficial to prevent the conductive plug 21 from being affected by the tensile stress of the planarization process, and to avoid the conductive plug 21 and the surrounding area. Delamination of the membrane layer and avoidance of rupture of the surrounding membrane layer.
  • an etching process needs to be performed on the back surface 202 of the wafer 20 to form a groove for exposing the bottom surface of the conductive plug 21 .
  • the formation process of the groove includes the following steps:
  • a mask is used to form a patterned mask layer 23 on the back surface 202 .
  • the orthographic projection of the bottom surface of the conductive plug 21 is located within the orthographic projection of the opening of the mask layer 23 .
  • the wafer 20 has a plurality of conductive plugs 21 for heat conduction.
  • the conductive plugs 21 may be made of through-silicon via (TSV) process, and the mask layer 23 has a single opening, referring to FIG. 7 .
  • TSV through-silicon via
  • the orthographic projection of the bottom surface of any conductive plug 21 is located within the orthographic projection of the single opening, which is beneficial to reduce the difficulty of preparing the mask.
  • the mask layer 33 has a plurality of openings, and the orthographic projection of one or more conductive plugs 31 is located within the orthographic projection of one opening.
  • the intermediate structures when openings are used to etch the wafer 30 to form grooves exposing the bottom surfaces of the conductive plugs 31 , the intermediate structures will not be exposed or damaged.
  • an etching process is performed on the back surface 202 of the wafer 20 to form a groove 24 exposing at least the bottom surface of the conductive plug 21 ; the mask layer is removed after the groove 24 is formed.
  • the bottom surfaces of the plurality of conductive plugs 21 are of different heights, and the groove 24 exposes the bottom surface of any conductive plug 21 .
  • the groove 24 also exposes part of the sidewall of the conductive plug 21 , so that the functional layer formed subsequently can also cover part of the sidewall of the conductive plug 21 , so as to make up for the protection of the part of the sidewall of the conductive plug 21
  • the problem of poor deposition of layer 22 further improves the performance of the semiconductor structure.
  • the height difference d between the bottom surface of the groove 24 and the bottom surface of the conductive plug 21 is 2nm-10nm, such as 4nm, 6nm or 8nm. In this way, it is beneficial to ensure that the subsequently formed functional layer can completely cover the corner area of the conductive plug 21, that is, cover the sidewall area of the conductive plug 21 where the protective layer 22 is poorly deposited, so as to ensure that the semiconductor structure has good performance; in addition, the height is limited.
  • the size of the difference d is beneficial to ensure that the functional layer material can better cover the sidewalls of the conductive plugs 21 when the functional layer is subsequently filled, and is conducive to ensuring that the functional layer material fills the area between the adjacent conductive plugs 21 , to avoid the phenomenon of premature sealing during filling due to the large depth-to-width ratio of the grooves between the adjacent conductive plugs 21 , and to ensure that the functional layer material has a better filling effect.
  • the bottom surface and sidewalls of the conductive plugs 21 are covered with a protective layer 22 .
  • the etching process is also used to remove the protective layer 22 located on the bottom surface and part of the sidewalls of the conductive plugs 21 . , so as to expose the bottom surface and part of the sidewall of the conductive plug 21 . In this way, it is beneficial to ensure that the functional layer can be uniformly coated on the surface of the conductive plug 21 to achieve its preset performance.
  • the protective layer 22 Before the protective layer 22 is removed, the protective layer 22 may have been cracked, and the surface of the cracked protective layer 22 away from the conductive plug 21 is usually uneven. In addition, the protective layer 22 may be delaminated from the conductive plug 21, and the conductive plug 21 has poor structural stability at this time, that is, it may change with the semiconductor structure.
  • the protective layer 22 is removed to form a functional layer on the surface of the conductive plug 21, which is beneficial to fix the conductive plug 21, improve the structural stability of the conductive plug 21, and avoid the tremor of the conductive plug 21 from causing the functional layer. damage to further ensure that the functional layer can achieve its preset performance. Referring to FIG. 10 , a functional layer 25 covering the conductive plugs 21 is formed.
  • the blocking layer 251 , the dielectric layer 252 and the bonding layer 253 are sequentially formed to form the functional layer 25 .
  • the blocking layer 251 is used for blocking the migration of metal ions in the conductive plugs 21 into the wafer 20 and the dielectric layer 252
  • the dielectric layer 252 is used for preventing the leakage of the conductive plugs 21
  • the bonding layer 253 is used for the fusion bonding process. , to realize the connection and packaging of multiple semiconductor structures.
  • the dielectric layer 252 needs to undergo a planarization process to ensure that the bonding layer 253 can be formed on the planarized surface, thereby enabling effective connection between different semiconductor structures, without the need for special
  • the connection object sets a unique bonding structure.
  • the dielectric layer 252 is away from the blocking layer 251 in the direction perpendicular to the surface of the dielectric layer 252 .
  • the distance between the surface and the bottom surface of the conductive plug 21 should be greater than or equal to the second predetermined distance.
  • the size of the second preset spacing is related to the material of the dielectric layer 252 and the material of the blocking layer 251 . Specifically, the stronger the ability of the material of the dielectric layer 252 and the material of the blocking layer 251 to transmit stress, the larger the second preset spacing. , so as to avoid a large pulling stress acting on the conductive plug 21 .
  • the functional layer 25 covers the bottom surface of the conductive plug 21, which is beneficial to avoid the conductive plug 21 being pulled by a large stress in the subsequent application process, thereby avoiding the risk of chip quality caused by the stress pulling; in addition, it is beneficial to avoid The conductive plug 21 misleads electricity.
  • the material of the blocking layer 251 includes silicon carbonitride, or includes a tantalum layer and a tantalum nitride layer stacked in sequence, the tantalum layer covers the surface of the conductive plug 21, and the tantalum nitride layer covers the tantalum layer; the dielectric layer 252
  • the material includes at least one of silicon oxide, silicon nitride or silicon oxynitride.
  • the heat dissipation performance of the functional layer 25 may be better than that of the wafer 20 .
  • the heat on the front side 201 of the wafer 20 can be conducted through the conductive plugs 21 and radiated from the back side 202 of the wafer 20 through the functional layer 25 , so as to prevent the heat from the front side 201 of the wafer 20 from accumulating continuously, thereby avoiding the heat generated on the front side 201 of the wafer 20 .
  • the components are damaged by high heat; and most of the heat on the front surface 201 of the wafer 20 is dissipated in the wafer 20 , so as to prevent the components inside the wafer 20 from being damaged by the high heat, so as to ensure that the semiconductor structure has good performance.
  • the functional layer 25 may contain various materials, and the heat dissipation performance of at least one material in the functional layer 25 is better than that of the wafer 20 .
  • the functional layer 25 not only covers the bottom surface of the conductive plug 21, but also covers part of the sidewall of the conductive plug 21. In this way, the contact area between the functional layer 25 and the conductive plug 21 can be increased, thereby accelerating the transfer of heat from the conductive plug 21
  • the conduction rate transmitted to the functional layer 25 ensures that the heat of the front surface 201 can be dissipated at a faster rate.
  • the bottom surface of the conductive plug 21 can be used for alignment and positioning, thereby improving the processing efficiency. Alignment accuracy of the process.
  • the transparency of the functional layer 25 may be higher than that of the wafer 20 .
  • the conductive plugs 21 and the grooves 24 are arranged in a marking pattern; in other embodiments, the conductive plugs or the grooves are a marking pattern.
  • an etching process is used instead of the planarization process to form a groove for exposing the bottom surface of the conductive plug, so as to avoid the pulling stress of the planarization process on the conductive plug and the conductive plug.
  • the layers and structures surrounding the conductive plugs cause damage to ensure good performance of the semiconductor structure.
  • the embodiments of the present application further provide a semiconductor structure, and the semiconductor structure can be fabricated by using the above-mentioned method for forming a semiconductor structure.
  • the semiconductor structure includes: a wafer 20, the wafer 20 has a front side 201 and a back side 202 opposite the front side 201, the wafer 20 has conductive plugs 21 therein, the conductive plugs 21 extend from the front side 201 to the back side 202, and The bottom surface of the conductive plug 21 is located in the wafer 20; the groove 24, the top opening of the groove 24 is located on the plane where the back surface 202 of the wafer 20 is located, and the groove 24 exposes at least the bottom surface of the conductive plug 21; the functional layer 25, the functional layer 25 covers the conductive plug Plug 21 underside.
  • the groove 24 exposes the bottom surface and part of the sidewall of the conductive plug 21
  • the functional layer 25 covers the bottom surface and part of the sidewall of the conductive plug 21 .
  • the height difference between the bottom surface of the groove 24 and the bottom surface of the conductive plug 21 is 2 nm ⁇ 10 nm, such as 3 nm, 5 nm or 7 nm.
  • the functional layer 25 is a laminated structure.
  • the laminated structure 25 includes a blocking layer 251 covering the bottom surface of the conductive plug 21 and a dielectric layer 252 covering the blocking layer 251.
  • the blocking layer 251 is used to block the conductive plug 21
  • the metal ions migrate into the dielectric layer 252 .
  • the material of the blocking layer 251 includes silicon carbonitride, or the blocking layer 251 includes a tantalum layer and a tantalum nitride layer stacked in sequence, the tantalum layer covering the surface of the conductive plug 21, and the tantalum nitride layer covering the tantalum layer.
  • the heat dissipation performance of the functional layer 25 is better than that of the wafer 20 ; the transparency of the functional layer 25 is higher than that of the wafer 20 ; the conductive plugs 21 and the grooves 24 are arranged in a marking pattern.
  • the conductive plug is located in the groove and is covered by the functional layer, which is beneficial to avoid being affected by tensile stress, avoid the occurrence of leakage, and help to ensure good performance of the semiconductor structure.
  • FIG. 13 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a semiconductor structure provided by another embodiment of the present application.
  • the semiconductor structure includes a plurality of conductive plugs 31, and in the direction perpendicular to the surface of the wafer 30, the bottom surfaces of the plurality of conductive plugs 31 have the same height; The corners are rounded.
  • This embodiment provides a new semiconductor structure.

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Abstract

一种半导体结构及其形成方法，半导体结构的形成方法包括：提供晶圆（20），晶圆（20）具有正面（201）和背面（202），晶圆（20）内具有导电插塞（21），导电插塞（21）自正面（201）向背面（202）延伸，且导电插塞（21）底面位于晶圆（20）内；对晶圆（20）背面（202）进行刻蚀工艺，形成至少暴露导电插塞（21）底面的凹槽（24）；形成覆盖导电插塞（21）底面的功能层（25）。

Description

半导体结构及其形成方法
交叉引用
本申请要求于2020年7月21日递交的名称为“半导体结构及其形成方法”、申请号为2020107046694的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体领域，特别涉及一种半导体结构及其形成方法。
背景技术
在3D芯片结构的研发过程中，为了强化芯片封装体的导热效果，通常会在晶圆内置入导热性能良好的元件，以传导并散发晶圆某一位置的热量，例如伪导电插塞。
在导电插塞的形成过程中，当用于填充导电材料和形成保护膜层的凹槽深宽比较大时，通过沉积工艺形成的覆盖凹槽底部和侧壁的膜层存在沉积不良的问题，进而导致性能缺陷。为解决这一性能缺陷，现有技术通常会对沉积不良的部分进行调整，然而现有技术存在一些问题。
发明内容
本申请部分实施例提供了一种半导体结构及其形成方法，有利于提高半导体结构的性能。
为解决上述问题，本申请部分实施例提供一种半导体结构的形成方法，包括：提供晶圆，所述晶圆具有正面和背面，所述晶圆内具有导电插塞，所述导电插塞自所述正面向所述背面延伸，且所述导电插塞底面位于所述晶圆内；对所述晶圆背面进行刻蚀工艺，形成至少暴露所述导电插塞底面的凹槽；形成覆盖所述导电插塞底面的功能层。
另外，在进行所述刻蚀工艺之前，还包括：对所述晶圆背面进行平坦化工艺。
另外，所述晶圆内具有多个所述导电插塞，在垂直于所述晶圆背面的方 向上，多个所述导电插塞的底面高度不同；所述凹槽暴露出任意所述导电插塞的底面。
另外，所述凹槽还暴露出所述导电插塞的部分侧壁；在形成所述功能层的工艺步骤中，还在所述导电插塞的部分侧壁形成所述功能层。
另外，所述导电插塞底面覆盖有保护层；在形成所述凹槽的工艺步骤中，所述刻蚀工艺还用于去除所述保护层。
另外，所述功能层包括覆盖所述导电插塞底面的阻拦层和填充所述凹槽的介质层，阻拦层用于阻拦所述导电插塞中的金属离子迁移至所述介质层内。
另外，所述介质层的材料包括二氧化硅、氮化硅或氮氧化硅中的至少一者，所述阻拦层的材料包括碳氮化硅。
另外，所述功能层包括键合层，所述键合层用于进行熔融键合工艺。
相应地，本申请部分实施例还提供一种半导体结构，包括：晶圆，所述晶圆具有正面和背面，所述晶圆内具有导电插塞，所述导电插塞自所述正面向所述背面延伸，且所述导电插塞底面位于所述晶圆内；凹槽，所述凹槽顶部开口位于所述晶圆背面所在平面，所述凹槽至少暴露所述导电插塞底面；功能层，所述功能层覆盖所述导电插塞底面。
另外，所述凹槽暴露所述导电插塞的底面和部分侧壁，所述功能层覆盖所述导电插塞的底面和部分侧壁。
另外，在垂直于所述晶圆背面的方向上，所述凹槽底面与所述导电插塞底面之间的高度差为2nm～10nm。
另外，所述功能层为叠层结构，所述叠层结构包括覆盖所述导电插塞底面的阻拦层，以及填充所述凹槽的介质层，所述阻拦层用于阻拦所述导电插塞中的金属离子迁移至所述介质层内。
另外，，所述阻拦层的材料包括碳氮化硅，或者，所述阻拦层包括依次层叠的钽层和氮化钽层，所述钽层覆盖所述导电插塞底面，所述氮化钽层覆盖所述钽层。
另外，所述导电插塞与所述凹槽排列为标记图案。
与现有技术相比，本申请部分实施例提供的技术方案具有以下优点：
上述技术方案中，采用刻蚀工艺暴露出导电插塞底面，有利于避免暴露过程中对导电插塞及其相邻的结构造成应力损伤，以及避免导电插塞及其相邻结构因为暴露过程中的应力问题而发生结构性改变，从而保证半导体结构具有良好的性能。
另外，凹槽暴露出任意导电插塞的底面，使得任意导电插塞的底面都能被功能层覆盖，有利于避免部分导电插塞因底面未被功能层覆盖而导致半导体结构出现性能缺陷。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1至图4为一种半导体结构的形成方法各步骤对应的结构示意图；
图5至图12为本申请实施例提供的一种半导体结构的形成方法各步骤对应的结构示意图；
图13为本申请又一实施例提供的一种半导体结构的结构示意图。
具体实施方式
参考图1，半导体结构包括：晶圆10，晶圆10具有正面101和与正面101相对的背面102，晶圆10内具有导电插塞11，导电插塞11自正面101向背面102延伸，且导电插塞11底面位于晶圆10内；保护层12，保护层12覆盖导电插塞11底面和侧壁；标记图案13，标记图案13位于晶圆正面101。
保护层12可以是叠层结构，保护层12可包括包覆导电插塞11底面和侧壁的阻拦层和包覆阻拦层表面的介质层，阻拦层用于避免导电插塞11内的金属离子向晶圆10内迁移，介质层用于防止导电插塞11漏电。
随着容纳导电插塞11和保护层12的凹槽的深宽比不断增大，在沉积形成保护层12的过程中，凹槽的底部会存在沉积不良的问题，其中较为严重的是底部拐角区域，底部拐角区域还包括凹槽的部分侧壁。沉积不良的问题会导致保护层12无法实现较好的保护效果，进而导致半导体结构出现性能缺陷，例如， 导电插塞11内的金属离子扩散和导电插塞11漏电。
另外，由于标记图案13位于正面101，在对晶圆10背面102进行加工处理时，需要识别并利用位于正面101的标记图案13，而这存在一定的难度，并且存在较大的对准误差。
为解决上述沉积不良的技术问题，且为了保证导电插塞11具有良好的散热效果，当前工艺通常选择对导电插塞11的底面和侧壁进行一定的工艺处理。具体步骤如下：
参考图2，进行第一平坦化工艺，去除位于导电插塞11底面的晶圆10，以暴露出导电插塞11的底面；参考图3，进行刻蚀工艺，去除覆盖导电插塞11部分侧壁的保护层12以及位于相邻导电插塞11之间的晶圆10，以暴露出导电插塞11的部分侧壁，该部分侧壁表面通常存在保护层12沉积不良的问题。
由于平坦化工艺的去除速率通常大于刻蚀工艺，先采用平坦化工艺暴露出导电插塞11的底面，再采用刻蚀工艺暴露导电插塞11的部分侧壁，能够缩短整个工艺流程的周期。然而，平坦化工艺会产生一定的拉扯应力，在以导电插塞11底面为基准进行平坦化工艺时，拉扯应力会施加在导电插塞11上，使得导电插塞11在工艺过程中不断向周边结构施加压应力，从而导致导电插塞11与保护层12脱层，形成第一空隙111，以及导致部分保护层12发生破裂。
其中，破裂的保护层12碎屑可能掉落至第一空隙111内，在使保护层12与导电插塞11重新密闭接合时，保护层12碎屑的存在可能导致保护层12和导电插塞11无法有效密合；此外，在对保护层12和导电插塞11进行密闭接合时，保护层12碎屑的存在可能导致应力集中问题，进而对完好的保护层12造成破坏。
参考图4，在晶圆10背面102沉积介质材料，并进行第二平坦化工艺，以形成暴露导电插塞11底面的介电层14。
由于介电层14暴露导电插塞11底面，因此第二平坦化工艺也是以导电插塞11底面为基准进行的，也就是说，第二平坦化工艺也会拉扯导电插塞11，进而导致导电插塞11和介电层14之间产生第二空隙131，以及使得靠近导电插塞11的部分介电层14发生破裂。
此外，通过包覆的方式保护导电插塞11侧壁，而将导电插塞11底面暴露出来以导出热量，会导致导电插塞11在没有其他膜层覆盖的情况下出现损伤，且导电插塞11的暴露本身就具有漏电风险。
为解决上述问题，本申请实施提供一种半导体结构及其形成方法，在暴露位于晶圆内的导电插塞底面时，通过采用刻蚀工艺代替平坦化工艺，形成暴露导电插塞底面的凹槽，避免平坦化工艺的拉扯应力对导电插塞以及位于导电插塞周围的结构造成损伤，从而保证半导体结构具有良好性能。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图5至图12为本申请实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
参考图5，提供晶圆20，晶圆20具有正面201和与正面201相对的背面202，晶圆20内具有导电插塞21，导电插塞21自正面201向背面202延伸，且导电插塞21底面位于晶圆20内。
本实施例中，在垂直于晶圆20背面202的方向上，晶圆20背面202与导电插塞21底面之间具有第一预设间距，第一预设间距由对晶圆20背面202进行减薄工艺和平坦化工艺后得到。平坦化工艺相对于减薄工艺而言，具有较低的去除速率以及较高的表面加工品质，且可用于去除减薄工艺过程中形成的较深刮伤。
目前，平坦化工艺是通过抛光头向抛光垫施加压力且带动抛光垫转动，使得位于抛光垫和晶圆之间的研磨液能够均匀分布在晶圆表面，从而使得研磨液中的化学成分能够与晶圆表面材料产生化学反应，将不溶的物质转化为易溶物质，或者将硬度高的物质进行软化，然后通过研磨液中磨粒的微机械摩擦作用将这些化学反应物去除，实现平坦化目的。
其中，磨粒在某一结构表面摩擦时，会对该结构施加一定的拉扯应力。在某一结构为独立设置的一部分时，由于相邻的其他结构与其材料不同，无法 起到较好的力传导作用，且在受力时可能存在应力集中问题，因此该结构可能对相邻的其他结构造成挤压，进而导致该结构与相邻的其他结构脱层以及导致相邻的其他结构发生损伤，例如发生破碎。
需要说明的是，在远离摩擦表面的方向上，磨粒造成的拉扯应力会逐渐降低。因此，设置导电插塞21底面与晶圆20背面202之间的间距大于或等于第一预设间距，有利于避免导电插塞21受到平坦化工艺拉扯应力的影响，避免导电插塞21与周围膜层发生脱层，以及避免周围膜层发生破裂。
在提供晶圆20之后，需要对晶圆20背面202进行刻蚀工艺，形成暴露导电插塞21底面的凹槽。凹槽的形成工艺包括以下步骤：
参考图6，采用掩膜版在背面202形成图案化掩膜层23，在垂直于背面202的方向上，导电插塞21底面的正投影位于掩膜层23开口的正投影内。
本实施例中，晶圆20内具有多个用于导热的导电插塞21，导电插塞21可由硅穿孔工艺(Through Silicon Via，TSV)制成，掩膜层23具有单个开口，参考图7，任意导电插塞21底面的正投影都位于该单一开口的正投影内，如此，有利于降低掩膜版的制备难度。
在其他实施例中，参考图8，掩膜层33具有多个开口，一个或多个导电插塞31的正投影位于一个开口的正投影内，如此，当相邻导电插塞31之间具有其他中间结构时，利用开口刻蚀晶圆30形成暴露导电插塞31底面的凹槽时，不会暴露出中间结构或者对中间结构造成损伤。
参考图9，对晶圆20背面202进行刻蚀工艺，形成至少暴露导电插塞21底面的凹槽24；在形成凹槽24之后去除掩膜层。
本实施例中，在垂直于晶圆20背面202的方向上，多个导电插塞21的底面高度不同，凹槽24暴露出任意导电插塞21的底面。如此，有利于保证每个导电插塞21的底面都能够覆盖功能层，以实现功能层的效果，例如防护隔离。
本实施例，凹槽24还暴露出导电插塞21的部分侧壁，如此，后续形成的功能层还可以覆盖导电插塞21的部分侧壁，从而弥补位于导电插塞21部分侧壁的保护层22沉积不良问题，从而进一步提高半导体结构的性能。
本实施例中，凹槽24底面与导电插塞21底面之间的高度差d为 2nm-10nm，例如4nm、6nm或8nm。如此，有利于保证后续形成的功能层能够完全覆盖导电插塞21的拐角区域，即覆盖保护层22沉积不良的导电插塞21侧壁区域，从而保证半导体结构具有良好的性能；此外，限制高度差d的大小，有利于保证后续进行功能层的填充时，功能层材料能够较好地覆盖导电插塞21侧壁，以及有利于保证功能层材料填充满相邻导电插塞21之间的区域，避免因为相邻导电插塞21之间的凹槽的深宽比较大而出现填充时提前封口现象，保证功能层材料具有较好的填充效果。
本实施例中，导电插塞21底面和侧壁覆盖有保护层22，在形成凹槽24的工艺步骤中，刻蚀工艺还用于去除位于导电插塞21底面和部分侧壁的保护层22，以暴露出导电插塞21底面和部分侧壁。如此，有利于保证功能层能够均匀涂覆在导电插塞21表面，实现其预设性能。
在去除保护层22之前，保护层22可能已经发生破裂，破裂的保护层22远离导电插塞21的表面通常会呈现凹凸不平的状态，而在凹凸不平的表面涂覆功能层，很容易出现功能层未涂覆均匀，进而无法实现预设性能的情况；此外，保护层22可能与导电插塞21发生脱层，此时导电插塞21具有较差的结构稳定性，即可能随着半导体结构的移动而发生震颤，去除保护层22而在导电插塞21表面形成功能层，有利于固定导电插塞21，提升导电插塞21的结构稳定性，避免导电插塞21的震颤对功能层造成损伤，进一步保证功能层能够实现其预设性能。参考图10，形成覆盖导电插塞21的功能层25。
本实施例中，在形成凹槽24之后，依次形成阻拦层251、介质层252和键合层253，以构成功能层25。其中，阻拦层251用于阻拦导电插塞21内的金属离子向晶圆20以及介质层252内迁移，介质层252用于防止导电插塞21漏电，键合层253用于进行熔融键合工艺，以实现多个半导体结构的连接和封装。
本实施例中，在形成键合层253之前，需要介质层252进行平坦化工艺，以保证键合层253能够形成在平坦化表面上，进而使得不同半导体结构之间能够有效连接，无需专门为连接对象设置独有的键合结构。
为避免介质层252的平坦化工艺对导电插塞21、覆盖导电插塞21的保护层22和阻拦层251造成影响，在垂直于介质层252表面的方向上，介质层252远离阻拦层251的表面与导电插塞21底面之间的间距应该大于或等于第二预设 间距。第二预设间距的大小与介质层252的材料和阻拦层251的材料有关，具体来说，介质层252的材料和阻拦层251的材料传递应力的能力越强，第二预设间距越大，如此才能够避免较大的拉扯应力作用在导电插塞21上。
本实施例中，功能层25覆盖导电插塞21底面，有利于避免导电插塞21在后续应用过程中被较大的应力拉扯，进而避免应力拉扯所造成的芯片质量风险；此外，有利于避免导电插塞21误导电。
本实施例中，阻拦层251的材料包括碳氮化硅，或者，包括依次层叠的钽层和氮化钽层，钽层覆盖导电插塞21表面，氮化钽层覆盖钽层；介质层252的材料包括氧化硅、氮化硅或氮氧化硅中的至少一者。
参考图11，本实施例中，功能层25的散热性能可以优于晶圆20的散热性能。如此，晶圆20正面201的热量能够通过导电插塞21进行传导，并通过功能层25从晶圆20背面202散发出来，避免晶圆20正面201的热量不断堆积，进而避免设置于正面201的元器件受到高热量的损伤；以及避免晶圆20正面201的热量大多散发在晶圆20内，避免位于晶圆20内部的元器件受到高热量的损伤，保证半导体结构具有良好的性能。
功能层25中可包含多种材料，功能层25中至少一种材料的散热性能优于晶圆20的散热性能。
本实施例中，功能层25不仅覆盖导电插塞21底面，还覆盖导电插塞21部分侧壁，如此，能够增加功能层25与导电插塞21的接触面积，从而加快热量从导电插塞21传输至功能层25的传导速率，保证正面201的热量能够被以较快的速率散发掉。
本实施例中，在形成功能层25之后，由于功能层25不会对视线造成阻挡，因此在对晶圆20背面进行加工处理时，可以通过导电插塞21底面进行对准定位，进而提高加工处理的对准精度。优选地，功能层25的透明度可以高于晶圆20的透明度。
本实施例中，参考图12，导电插塞21和凹槽24排列为标记图案；在其他实施例中，导电插塞或凹槽为标记图案。
本实施例中，在暴露位于晶圆内的导电插塞底面时，通过采用刻蚀工艺 代替平坦化工艺，形成暴露导电插塞底面的凹槽，避免平坦化工艺的拉扯应力对导电插塞以及位于导电插塞周围的膜层和结构造成损伤，从而保证半导体结构具有良好性能。
相应地，本申请实施例还提供一种半导体结构，该半导体结构可采用上述半导体结构的形成方法制成。
参考图10，半导体结构包括：晶圆20，晶圆20具有正面201和与正面201相对的背面202，晶圆20内具有导电插塞21，导电插塞21自正面201向背面202延伸，且导电插塞21底面位于晶圆20内；凹槽24，凹槽24顶部开口位于晶圆20背面202所在平面，凹槽24至少暴露导电插塞21底面；功能层25，功能层25覆盖导电插塞21底面。
本实施例中，凹槽24暴露导电插塞21的底面和部分侧壁，功能层25覆盖导电插塞21的底面和部分侧壁。
本实施例中，在垂直于晶圆20背面202的方向上，凹槽24底面与导电插塞21底面之间的高度差为2nm～10nm，例如3nm、5nm或7nm。
本实施例中，功能层25为叠层结构，叠层结构25包括覆盖导电插塞21底面的阻拦层251，以及覆盖阻拦层251的介质层252，阻拦层251用于阻拦导电插塞21中的金属离子迁移至介质层252内。
示例性地，阻拦层251的材料包括碳氮化硅，或者，阻拦层251包括依次层叠的钽层和氮化钽层，钽层覆盖导电插塞21表面，氮化钽层覆盖钽层。
本实施例中，功能层25的散热性能优于晶圆20的散热性能；功能层25的透明度高于晶圆20的透明度；导电插塞21与凹槽24排列为标记图案。
本实施例中，导电插塞位于凹槽内，且被功能层覆盖，有利于避免受到拉扯应力的影响，以及避免漏电现象发生，有利于保证半导体结构具有良好的性能。
本申请又一实施例还提供一种半导体结构，与前一实施例不同的是，本实施例中，多个导电插塞的底面高度相同，导电插塞底面具有圆角。以下将结合图13进行详细说明，图13为本申请又一实施例提供的半导体结构的结构示意图。与上一实施例相同或者相应的部分，可参考上一实施例的相应说明，以 下不做赘述。
参考图13，半导体结构中包括多个导电插塞31，在垂直于晶圆30表面的方向上，多个导电插塞31的底面高度相同；另外，导电插塞31的底部表面与侧壁之间的拐角为圆角。
本实施例提供了一种新的半导体结构。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (14)

  1. 一种半导体结构的形成方法，包括：
    提供晶圆，所述晶圆具有正面和背面，所述晶圆内具有导电插塞，所述导电插塞自所述正面向所述背面延伸，且所述导电插塞底面位于所述晶圆内；
    对所述晶圆背面进行刻蚀工艺，形成至少暴露所述导电插塞底面的凹槽；
    形成覆盖所述导电插塞底面的功能层。
  2. 根据权利要求1所述的形成方法，其中，在进行所述刻蚀工艺之前，还包括：
    对所述晶圆背面进行平坦化工艺。
  3. 根据权利要求1所述的形成方法，其中，所述晶圆内具有多个所述导电插塞，在垂直于所述晶圆背面的方向上，多个所述导电插塞的底面高度不同；所述凹槽暴露出任意所述导电插塞的底面。
  4. 根据权利要求1所述的形成方法，其中，所述凹槽还暴露出所述导电插塞的部分侧壁；在形成所述功能层的工艺步骤中，还在所述导电插塞的部分侧壁形成所述功能层。
  5. 根据权利要求1所述的形成方法，其中，所述导电插塞底面覆盖有保护层；在形成所述凹槽的工艺步骤中，所述刻蚀工艺还用于去除所述保护层。
  6. 根据权利要求1所述的形成方法，其中，所述功能层包括覆盖所述导电插塞底面的阻拦层和填充所述凹槽的介质层，所述阻拦层用于阻拦所述导电插塞中的金属离子迁移至所述介质层内。
  7. 根据权利要求6所述的形成方法，其中，所述介质层的材料包括二氧化硅、氮化硅或氮氧化硅中的至少一者，所述阻拦层的材料包括碳氮化硅。
  8. 根据权利要求1所述的形成方法，其中，所述功能层包括键合层，所述键合层用于进行熔融键合工艺。
  9. 一种半导体结构，包括：
    晶圆，所述晶圆具有正面和背面，所述晶圆内具有导电插塞，所述导电插塞自所述正面向所述背面延伸，且所述导电插塞底面位于所述晶圆内；
    凹槽，所述凹槽顶部开口位于所述晶圆背面所在平面，所述凹槽至少暴露所 述导电插塞底面；
    功能层，所述功能层覆盖所述导电插塞底面。
  10. 根据权利要求9所述的半导体结构，其中，所述凹槽暴露所述导电插塞的底面和部分侧壁，所述功能层覆盖所述导电插塞的底面和部分侧壁。
  11. 根据权利要求10所述的半导体结构，其中，在垂直于所述晶圆背面的方向上，所述凹槽底面与所述导电插塞底面之间的高度差为2nm～10nm。
  12. 根据权利要求9所述的半导体结构，其中，所述功能层为叠层结构，所述叠层结构包括覆盖所述导电插塞底面的阻拦层，以及填充所述凹槽的介质层，所述阻拦层用于阻拦所述导电插塞中的金属离子迁移至所述介质层内。
  13. 根据权利要求12所述的半导体结构，其中，所述阻拦层的材料包括碳氮化硅，或者，所述阻拦层包括依次层叠的钽层和氮化钽层，所述钽层覆盖所述导电插塞底面，所述氮化钽层覆盖所述钽层。
  14. 据权利要求9所述的半导体结构，其中，所述导电插塞与所述凹槽排列为标记图案。
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