WO2022015963A1 - Transistor à effet de champ quaternaire - Google Patents

Transistor à effet de champ quaternaire Download PDF

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Publication number
WO2022015963A1
WO2022015963A1 PCT/US2021/041799 US2021041799W WO2022015963A1 WO 2022015963 A1 WO2022015963 A1 WO 2022015963A1 US 2021041799 W US2021041799 W US 2021041799W WO 2022015963 A1 WO2022015963 A1 WO 2022015963A1
Authority
WO
WIPO (PCT)
Prior art keywords
quaternary
field effect
effect transistor
gate electrode
gate
Prior art date
Application number
PCT/US2021/041799
Other languages
English (en)
Inventor
Tzu-Yi Kuo
Original Assignee
Kkt Holdings Syndicate
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kkt Holdings Syndicate filed Critical Kkt Holdings Syndicate
Publication of WO2022015963A1 publication Critical patent/WO2022015963A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

  • the invention provides a quaternary field effect transistor, comprising a substrate; a first well with a first conductivity type inside said substrate; a second well with the first conductivity type inside said substrate; a channel region, with a second conductivity, inside said substrate and between said first well and said second well; a dielectric layer overlying said channel region; a first gate electrode on the dielectric layer and partially covering said channel region; and a second gate electrode, electrically isolating from said first gate electrode, on the dielectric layer and partially covering said channel region, wherein the second conductivity of the channel region is changed when one or both of said first gate electrode and said second gate electrode is applied with a threshold voltage.
  • the first conductivity can be positive, and said second conductivity is positive.
  • the first gate electrode and the second gate electrode can be serially configured along a direction from the first well to the second well.
  • the first gate electrode and the second gate electrode can be parallelly configured along a direction from the first well to the second well.
  • the present invention also provides a NOR gate, which comprises a first quaternary field effect transistor in the present invention, wherein a source thereof is provided with a voltage potential; a second quaternary field effect transistor in the present invention, wherein a drain thereof is grounded; a first input electrically connecting the first gate electrode of the first quaternary field effect transistor and the first gate electrode of the second quaternary field effect transistor; a second input electrically connecting to the second gate electrode of the first quaternary field effect transistor and the second gate of the second quaternary field effect transistor; and an output electrically connecting to a drain of the first quaternary field effect transistor and a source of the second quaternary field effect transistor.
  • the present invention provides a logic gate, which comprises a quaternary field effect transistor in the present invention; and a resistor electrically coupling to the quaternary field effect transistor.
  • the present invention provides a logic gate, which comprises a quaternary field effect transistor in the present invention; and two MOSFETs electrically coupling to the quaternary field effect transistor.
  • the first conductivity can be positive.
  • the first conductivity can be positive.
  • the first conductivity can be negative.
  • Figure 2B is a schematic cross-view illustration of a serial quaternary MOSFET in according to one embodiment of the present invention.
  • Figures 3A to 3D provide electric circuit diagrams corresponding to different channel conductive types and different arrangements of gate electrodes of quaternary MOSFETs in according to embodiments of the present invention;
  • Figures 5A to 5D are schematic electronic circuits diagram of logic gates by configuring conventional MOSFETs and quaternary field effect transistors in accordance with several embodiments of the present invention.
  • Figure 6A is a schematic electronic circuits diagram of a NOR gate configured by the quaternary field effect transistors in accordance with one embodiment of the present invention;
  • Figure 6B is a schematic design layout illustration of the NOR gate in Figure 6A in accordance with one embodiment of the present invention
  • Figure 7A is a schematic electronic circuits diagram of a NAND gate configured by the quaternary field effect transistors in accordance with one embodiment of the present invention
  • Figure 9A is a schematic cross-view illustration of a negative doping region in the channel region of a n-type serial quaternary MOSFET in accordance with one embodiment of the present invention
  • Figure 9B is a schematic cross-view illustration of a negative doping region in the channel region of a p-type parallel quatemay MOSFET in accordance with one embodiment of the present invention
  • gate refers to “logic gate”.
  • the quaternary field effect transistor in the present invention can be assembled with two conventional MOSFETs into a logic gate, and the logic gate in the present invention takes the low power consumption advantage of the conventional CMOSFET. Compared to the conventional logic gate configured by CMOSFETs, the area of the logic gate of the present invention can be reduced one-fourth to that of the conventional logic gate formed by CMOSFETs.
  • FIG. IB Please refer to Figure IB, wherein a schematic cross-sectional view along a cross-section line AA’ in Figure 1A is illustrated.
  • a source 12 and a drain 14 in the substrate 10 is disclosed, wherein both are doped wells.
  • a doped channel region 16 is formed between the source 12 and the drain 14.
  • a gate dielectric layer 20 is formed on the channel region 16, and two gate electrodes 22 and 24 are formed on the gate dielectric layer 20. Uncovered region in the channel region 16 by the two gate electrodes 22 and 24 will also be inverted due to hot electron effect when the two gate electrodes 22 and 24 are applied with threshold voltage, as long as a distance between the two gate electrodes 22 and 24 is not too far away.
  • FIG. 2A a top view of the quaternary field effect transistor in the present invention is disclosed, wherein a first gate electrode 26 and a second gate electrode 28 are arranged in parallel, and between a source 12 and a drain 14.
  • the quaternary field effect transistor is an n-type parallel MOS field effect transistor.
  • the quaternary field effect transistor is a p-type parallel MOS field effect transistor.
  • the two embodiments are enhancement n-type quaternary field effect transistor and depletion p-type quaternary field effect transistor respectively. If conductivity of the channel region is negative, and if conductivity of source/drain is also n-type, it is the depletion n-type quaternary field effect transistor, while if conductivity of the channel region is negative, and if conductivity of source/drain is p-type, it is the enhancement p-type quaternary field effect transistor.
  • Material of the gate electrode can be polysilicon, metal silicide including cobalt, nickel, titanium or tungsten, metal aluminum, metal tungsten, metal titanium, metal tantalum, metal nickel, metal cobalt, or combination thereof.
  • the material of the gate is always a combination of several metal/silicide and cap layers.
  • the p-type serial MOSFET 304 When the gate electrode A and gate electrode B are not applied with voltage, the p-type serial MOSFET 304 is turned on, and the working voltage Vdd will provide an output signal to the output Y through the p-type serial MOSFET 304; the output Y is 1. When one or both of the gate electrode A and gate electrode B are applied with voltage, the p-type serial MOSFET 304 is turned off, and the output Y is grounded through the resistor 310; the output Y is 0.
  • the truth table of the device in the Figure 4B is identical to the truth table of the NOR gate.
  • FIG. 4D Please refer to Figure 4D, wherein a p-type parallel MOSFET 308 is connecting to a resistor 310 in parallel.
  • a working voltage Vdd is provided to the source of the p-type parallel MOSFET 308, and the drain of the p-type parallel MOSFET 308 is connecting to one end of the resistor 310 and output Y. The other end of the resistor 310 is grounded.
  • the p-type parallel MOSFET 308 is turned on, and the working voltage Vdd will provide an output signal to the output Y through the p-type parallel MOSFET 308; the output Y is 1.
  • An inverter can be provided in the present invention, if one of the two gate electrodes of the NOR gate in Figure 6A is grounded. Thus, the output Y will be provided inversely to the other input.
  • Another embodiment to provide the inverter is to keep one input of the NAND gate in Figure 7 A in 1, and thus the output Y will be provided inversely to the other input.
  • the quaternary field effect transistors in the present invention can be formed not only in the planar structure, but also the stereo finFFT structure or GAA(Gate All Around) FET.
  • the serial gate electrode structure there is no issue to apply the finFFT structure to serial gate electrodes.
  • the fin structure to the parallel gate electrodes structure.
  • Figure 8A wherein a top view illustration of the parallel quaternary field effect transistor with fin structure in the present invention is shown.
  • the fin structure includes the sourcel2, drain 14 and the gate dielectric layer 20 which is sandwiched by the gate electrodes 26 and 28.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un transistor à effet de champ quaternaire ayant deux électrodes de grille pour commander individuellement un type de conductivité d'une région de canal entre une source et un drain, de telle sorte que le transistor à effet de champ quaternaire est allumé ou éteint. Le transistor à effet de champ quaternaire présente des opérations similaires à des portes logiques, et la zone d'un transistor à effet de champ quaternaire est proche d'un MOSFET classique.
PCT/US2021/041799 2020-07-17 2021-07-15 Transistor à effet de champ quaternaire WO2022015963A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202063053020P 2020-07-17 2020-07-17
US63/053,020 2020-07-17

Publications (1)

Publication Number Publication Date
WO2022015963A1 true WO2022015963A1 (fr) 2022-01-20

Family

ID=79556023

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2021/041799 WO2022015963A1 (fr) 2020-07-17 2021-07-15 Transistor à effet de champ quaternaire

Country Status (2)

Country Link
TW (1) TW202226245A (fr)
WO (1) WO2022015963A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120268994A1 (en) * 2009-11-06 2012-10-25 Hiroyuki Nagashima Memory system
US20170077116A1 (en) * 2002-04-18 2017-03-16 Renesas Electronics Corporation Semiconductor integrated circuit device and a method of manufacturing the same
US20190027212A1 (en) * 2015-03-31 2019-01-24 Renesas Electronics Corporation Semiconductor device
US20190273146A1 (en) * 2016-11-11 2019-09-05 Robert Bosch Gmbh Mos component, electric circuit, and battery unit for a motor vehicle

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170077116A1 (en) * 2002-04-18 2017-03-16 Renesas Electronics Corporation Semiconductor integrated circuit device and a method of manufacturing the same
US20120268994A1 (en) * 2009-11-06 2012-10-25 Hiroyuki Nagashima Memory system
US20190027212A1 (en) * 2015-03-31 2019-01-24 Renesas Electronics Corporation Semiconductor device
US20190273146A1 (en) * 2016-11-11 2019-09-05 Robert Bosch Gmbh Mos component, electric circuit, and battery unit for a motor vehicle

Also Published As

Publication number Publication date
TW202226245A (zh) 2022-07-01

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