WO2022012437A1 - 薄膜体声波谐振器及其制造方法 - Google Patents

薄膜体声波谐振器及其制造方法 Download PDF

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Publication number
WO2022012437A1
WO2022012437A1 PCT/CN2021/105530 CN2021105530W WO2022012437A1 WO 2022012437 A1 WO2022012437 A1 WO 2022012437A1 CN 2021105530 W CN2021105530 W CN 2021105530W WO 2022012437 A1 WO2022012437 A1 WO 2022012437A1
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Prior art keywords
layer
lead
sacrificial layer
gap
external electrode
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PCT/CN2021/105530
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English (en)
French (fr)
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黄河
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中芯集成电路（宁波）有限公司
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Publication of WO2022012437A1 publication Critical patent/WO2022012437A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/173—Air-gaps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02015—Characteristics of piezoelectric layers, e.g. cutting angles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type

Definitions

  • the invention relates to the field of semiconductor device manufacturing, in particular to a thin-film bulk acoustic wave resonator and a manufacturing method thereof.
  • RF front-end modules have gradually become the core components of communication equipment.
  • filters have become the most rapidly growing and most promising components.
  • the performance of the filter is determined by the resonator units that make up the filter.
  • FBARs thin-film bulk acoustic resonators
  • FBARs thin-film bulk acoustic resonators
  • a thin-film bulk acoustic wave resonator includes two thin-film electrodes, and a piezoelectric thin-film layer is arranged between the two thin-film electrodes.
  • the bulk acoustic wave propagating in the thickness direction of the electric film layer is transmitted to the interface between the upper and lower electrodes and the air and is reflected back, and then reflected back and forth inside the film to form an oscillation.
  • Standing wave oscillations are formed when a sound wave propagates in a piezoelectric film layer that is exactly an odd multiple of a half-wavelength.
  • the quality factor (Q) of the cavity-type thin-film bulk acoustic wave resonators produced at present cannot be further improved, so it cannot meet the needs of high-performance radio frequency systems.
  • the purpose of the present invention is to provide a thin-film bulk acoustic wave resonator and a manufacturing method thereof, which can improve the quality factor of the thin-film bulk acoustic wave resonator, thereby improving the device performance.
  • the present invention provides a thin film bulk acoustic wave resonator, comprising: a stacked lead-out electrode, a piezoelectric layer and an external electrode, and the effective resonant region includes the lead-out electrode, the piezoelectric layer and the external electrode in a vertical direction to the external electrode.
  • the area where the surface of the piezoelectric layer overlaps each other in the direction of the surface, and the outside of the effective resonance area is an inactive area;
  • the first dielectric layer, a first gap is set between the surface of the first dielectric layer and the surface of the lead-out electrode
  • the part of the lead-out electrode extending out of the first gap from the effective resonance region is the first lead-out part;
  • the second dielectric layer, a surface of the second dielectric layer and the surface of the external electrode are provided with The second gap;
  • the external electrode is located in the area enclosed by the second gap or the boundaries of the two overlap;
  • the conductive column, one end is connected to the external electrode, and the other end is connected to a second lead-out portion, the second lead-out A portion extends out of the second gap from the effective resonance region; one of the lead-out electrode and the external electrode is located above the other.
  • the present invention also provides a method for manufacturing a thin-film bulk acoustic resonator, comprising: forming a first structure, the first structure comprising: an extraction electrode, at least covering the extraction electrode and avoiding the region where the first extraction part is located a first sacrificial layer, at least a first dielectric layer surrounding the first sacrificial layer on the side of the first sacrificial layer; forming a piezoelectric layer; forming a second structure, the second structure comprising: an external electrode, at least covering the the second sacrificial layer of the external electrode, the second dielectric layer surrounding the second sacrificial layer at least on the side of the second sacrificial layer; forming a conductive column, penetrating the second sacrificial layer and connecting the external electrode; forming One end of the second lead-out portion is connected to the conductive column, and the other end extends out of the effective resonance region; the first and second sacrificial layers are removed to form the first and second gaps
  • the beneficial effect of the present invention is that: connecting the external electrode with the external signal through the conductive column and the second lead-out part can increase the lead-out area and impedance of the external electrode, suppress the coupling effect between the electrodes, and enhance the heat conduction; the first gap and the second gap As an acoustic wave reflection structure, the quality factor of the resonator is improved; the area where the conductive column is located forms an acoustic impedance mismatch area, which can make the boundary of the effective resonance area and the acoustic impedance inside the effective resonance area mismatch, which is beneficial to improve the quality factor of the resonator.
  • the projection of the conductive column on the surface of the carrier substrate is a closed or annular shape with a gap, which can further suppress the loss of transverse acoustic wave energy and improve the quality factor of the resonator.
  • the edge of the piezoelectric layer is exposed in the cavity, which can further suppress the shear wave loss.
  • the piezoelectric layer is a complete film layer, which can ensure the piezoelectric properties of the piezoelectric layer.
  • the piezoelectric layer is formed on the flat electrode layer, which can make the piezoelectric layer have better lattice orientation, improve the piezoelectric properties of the piezoelectric layer, and further improve the overall performance of the resonator.
  • FIG. 1 shows a schematic structural diagram of a thin film bulk acoustic wave resonator according to Embodiment 1 of the present invention.
  • FIG. 2 shows a schematic structural diagram of a thin film bulk acoustic wave resonator according to Embodiment 2 of the present invention.
  • FIG. 3 shows a schematic structural diagram of a thin film bulk acoustic wave resonator according to Embodiment 3 of the present invention.
  • FIGS. 4 to 13 are schematic diagrams of structures corresponding to different steps in a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 4 of the present invention.
  • FIG. 14 to FIG. 19 are schematic structural diagrams corresponding to different steps of a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 5 of the present invention.
  • FIG. 20 to FIG. 27 show schematic structural diagrams corresponding to different steps of a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 6 of the present invention.
  • FIG. 28 to FIG. 33 are schematic structural diagrams corresponding to different steps of a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 7 of the present invention.
  • 100-carrying substrate 101A-dielectric layer surrounding the first sacrificial layer at least on the side of the first sacrificial layer; 101B-first passivation layer; 101-first dielectric layer; 102A- A dielectric layer surrounding the second sacrificial layer at least on the side of the second sacrificial layer; 102B—the second passivation layer; 102—the second dielectric layer; 200—the temporary substrate; 201′—the lead-out electrode layer; 201— 202-piezoelectric layer; 203'-external electrode layer; 203-external electrode; 210-first sacrificial layer; 220-second sacrificial layer; 211-first gap; 221-second gap; 401-conductive Column; 402-second lead-out part; 403-first lead-out part; 10-first cavity; 2021-resonance part; 2022-overlap.
  • the cavity-type thin-film bulk acoustic wave resonator produced at present has the problem of shear wave loss, so that the quality factor (Q) cannot be further improved, so it cannot meet the needs of high-performance radio frequency systems.
  • Embodiment 1 of the present invention provides a thin-film bulk acoustic resonator.
  • FIG. 1 is a schematic structural diagram of the thin-film bulk acoustic resonator according to Embodiment 1 of the present invention. Please refer to FIG. 1.
  • the thin-film bulk acoustic resonator includes: The electrode 201, the piezoelectric layer 202 and the external electrode 203, the effective resonance area includes the area where the lead-out electrode 201, the piezoelectric layer 202 and the external electrode 203 overlap each other in the direction perpendicular to the surface of the piezoelectric layer 202, the effective resonance area
  • the outside of the resonance area is an inactive area;
  • the first dielectric layer 101, a first gap 211 is set between the surface of the first dielectric layer 101 and the surface of the lead-out electrode 201;
  • the second dielectric layer 102, the second A second gap 221 is provided between the surface of the dielectric layer 102 and the surface of the external electrode 203;
  • the external electrode 203 is located in the area enclosed by the second gap 221 or the boundaries of the two overlap;
  • the conductive column 401, one end is connected to the external electrode 203, and the other end is connected with a second lead-out portion 402, the second lead-out portion
  • a carrier substrate 100 is further included.
  • the first dielectric layer 101 and the carrier substrate 100 may be combined by bonding layers or deposition.
  • the material of the bonding layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or ethyl silicate.
  • the first dielectric layer 101 is formed on the carrier substrate 100 by means of deposition.
  • the first dielectric layer may have a single-layer structure or a stacked-layer structure.
  • the material of the first dielectric layer may include, but is not limited to, one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., but the technology of the present invention is not limited to this.
  • the material of the carrier substrate 100 can be any suitable substrate known to those skilled in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe) , silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors.
  • the upper part of the first dielectric layer 101 includes a lead-out electrode 201 , a piezoelectric layer 202 , and an external electrode 203 arranged in layers in order from bottom to top.
  • the external electrode 203 and the lead-out electrode 201 can use any suitable conductive material or semiconductor material known in the art, wherein the conductive material can be a metal material with conductive properties, for example, made of molybdenum (Mo), aluminum (Al), Copper (Cu), Tungsten (W), Tantalum (Ta), Platinum (Pt), Ruthenium (Ru), Rhodium (Rh), Iridium (Ir), Chromium (Cr), Titanium (Ti), Gold (Au), Osmium (Os), rhenium (Re), palladium (Pd) and other metals, or a laminate of the above metals.
  • the semiconductor material is, for example, Si, Ge, SiGe, SiC, SiGeC, or the like.
  • the piezoelectric layer 202 can be made of aluminum nitride (AlN), zinc oxide (ZnO), lead zirconate titanate (PZT), lithium niobate (LiNbO3), quartz (Quartz), potassium niobate (KNbO3) or tantalic acid Piezoelectric materials having a wurtzite crystal structure, such as lithium (LiTaO3), and combinations thereof.
  • the piezoelectric layer 202 may further include a rare earth metal such as at least one of scandium (Sc), erbium (Er), yttrium (Y), and lanthanum (La).
  • the piezoelectric layer 202 may further include a transition metal such as at least one of zirconium (Zr), titanium (Ti), manganese (Mn), and hafnium (Hf). kind.
  • the piezoelectric layer 202 may be deposited using any suitable method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the upper surface of the first dielectric layer 101 is concave in the middle and protruding at the outer periphery.
  • a first gap 211 is provided between the lower surface of the lead-out electrode 201 and the upper surface of the recessed area of the first dielectric layer 101 .
  • the lead-out electrode 201 includes two parts, one part is located in the first gap 211 , and the other part is located outside the first gap 211 , and the two parts have an integrated structure.
  • the part outside the first gap 211 is the first lead-out portion 403 for connecting external signals.
  • the edge of the portion located in the first gap 211 is exposed in the first gap 211 .
  • the bottom surface of the piezoelectric layer 202 on the periphery of the edge of the extraction electrode 201 is also exposed in the first gap 211 .
  • the piezoelectric layer 202 is a horizontally complete film layer, and the periphery extends to above the surface of the protruding area of the first dielectric layer 101 .
  • Part of the edge of the lead-out electrode 201 is exposed in the first gap 211, which can make the edge of the lead-out electrode 201 form a reflective interface with the air, make the acoustic impedance mismatch, suppress the leakage of transverse waves, and further improve the quality factor (Q value) of the resonator.
  • the second dielectric layer 102 is located above the first dielectric layer 101 .
  • the material of the second dielectric layer 102 may include, but is not limited to, one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc.
  • the second dielectric layer may have a single-layer structure or a stacked-layer structure . In this embodiment, the middle of the lower surface of the second dielectric layer 102 is concave, and the outer periphery is convex.
  • a second gap 221 is provided between the upper surface of the external electrode 203 and the lower surface of the recessed area of the second dielectric layer 102 .
  • the boundary of the second gap 221 is larger than the boundary of the external electrode 203 , so that the periphery of the edge of the external electrode 203 is exposed in the second gap 221 .
  • the edge of the external electrode 203 is completely exposed in the second gap 221, which can make the edge of the external electrode 203 and the air form a reflection interface, make the acoustic impedance mismatch, suppress the leakage of shear waves, and further improve the quality factor (Q value) of the resonator.
  • the recessed area and the second gap 221 of the second dielectric layer 102 are disposed opposite to the recessed area and the first gap 211 of the first dielectric layer 101 , and the protruding area of the second dielectric layer 102 is opposite to the first dielectric layer 101
  • the convex area of is set relatively. Between the two recessed areas is the area where the effective resonance area of the resonator is located, and the effective resonance area includes the area where the lead-out electrode 201 , the piezoelectric layer 202 and the external electrode 203 overlap each other in a direction perpendicular to the surface of the piezoelectric layer 202 .
  • the boundary of the projection of the first gap 211 and the second gap 221 in the direction of the piezoelectric layer 202 surrounds the boundary of the projection of the effective resonance region in the direction of the piezoelectric layer 202 .
  • “Enclosed” means that the boundary of the effective resonance region is within the first gap 211 and the second gap 221 , or the boundary of the effective resonance region coincides with the boundary of the first gap 211 and/or the second gap 221 .
  • the situation shown in FIG. 1 is that the boundary of the effective resonance region is within the first gap 211 and the second gap 221 .
  • the boundary of the projection of the first gap 211 and the second gap 221 in the direction of the piezoelectric layer 202 surrounds the lead-out electrode 201 and the external electrode 203 on the piezoelectric layer 202 The bounds of the projection in the direction.
  • the meaning of "surrounding" is the same as that described above.
  • the piezoelectric layer 202 includes a resonance portion 2021 and a lap portion 2022 located on the outer periphery of the resonance portion.
  • the resonance portion 2021 is located in the effective resonance region, and the overlap portion 2022 is located in the effective resonance region. outside the resonance region.
  • the piezoelectric layer 202 is a complete film layer, and the resonance portion 2021 and the overlapping portion 2022 are integral structures.
  • the first gap 305 and the second gap 306 are isolated from each other by the piezoelectric layer 202 .
  • first gap and the second gap may be communicated through a plurality of through holes distributed in the inactive region, for example, the through holes penetrate through the piezoelectric layer of the inactive region (or through the piezoelectric layer and the lead-out at the same time) electrode).
  • first gap and the second gap are communicated through an unclosed annular through hole surrounding the effective area.
  • the inner wall of the unclosed annular through hole can constitute the boundary of the effective resonance area, and the inner wall can also be located at the boundary of the effective resonance area. the exterior.
  • conductive pillars 401 are provided on the upper surface of the external electrode 203 .
  • the conductive pillars 401 may be single or multiple discontinuous pillars.
  • the conductive pillars 401 are arranged at the edge of the effective resonance region, and the projection on the surface direction of the piezoelectric layer 202 is a ring shape, wherein the ring shape includes a discontinuous or closed ring shape.
  • the shape of the ring can be a circle, an ellipse, a polygon, or an irregular shape composed of arcs and straight sides.
  • a closed ring means that the conductive pillars 401 are continuous, and an open ring means that the conductive pillars 401 are discontinuous.
  • the area where the conductive column 401 is located forms an acoustic impedance mismatch with the effective resonant area, so that the transverse acoustic waves propagating outward can be reflected back to the effective resonant area, so as to suppress the leakage of transverse clutter, reduce energy loss, and improve the quality of the resonator factor (Q value).
  • Q value quality of the resonator factor
  • the other end of the conductive column 401 is connected with the second lead-out portion 402 .
  • the second lead-out portion 402 is embedded in the second dielectric layer 102 .
  • the second lead-out portion 402 may also be located on the lower surface of the recessed area of the second dielectric layer 102 . It can be seen from FIG. 1 that the second lead-out portion 402 is led out from the side where the effective resonance region is located to the outside.
  • the second lead-out portion 402 can be used as a signal input terminal to introduce an electrical signal into the external electrode 203 of the effective resonance region, and can also be used as a signal output terminal to output the electrical signal on the external electrode 203 .
  • the first lead-out portion 403 serves as a signal input end
  • the second lead-out portion 402 serves as a signal output end, and vice versa.
  • the projections of the first lead-out portion 403 and the second lead-out portion 402 in the direction of the piezoelectric layer are staggered from each other. Avoid high-frequency coupling due to potential floating, and prevent parasitic capacitance effects.
  • the material of the conductive column 401 is a conductive material, such as gold, silver, tungsten, platinum, aluminum, copper and other materials with low resistivity.
  • the material of the second lead-out portion 402 may refer to the material of the conductive column, and the material of the conductive column may be the same as or different from the material of the second lead-out portion.
  • Embodiment 2 of the present invention provides a thin-film bulk acoustic resonator.
  • FIG. 2 is a schematic structural diagram of the thin-film bulk acoustic resonator of Embodiment 2 of the present invention.
  • the difference between this embodiment and Embodiment 1 is that in this embodiment, the pressure
  • the resonance portion 2021 of the electrical layer 202 is located in the effective resonance region, the overlapping portion 2022 is located outside the effective resonance region, and the resonance portion 2021 and the overlapping portion 2022 are separated from each other. Please refer to FIG.
  • the specific structure is as follows: the first void 211 and the second void 221 are connected to each other to form a cavity, the resonance portion 2021 is completely located in the cavity, the overlapping portion 2022 is located outside the cavity, and the overlapping portion 2022 and the resonance portion 2021 Complete separation, so that the outer periphery of the resonance part 2021 is exposed in the cavity.
  • the edge of the resonance part 2021 of the piezoelectric layer overlaps with the edge of the lead-out electrode 201 and part of the edge of the external electrode 203 to form the edge of the effective resonance region.
  • the resonance part 2021 is all located in the effective resonance region. Area.
  • the resonating part 2021 and the overlapping part 2022 have both parts connected to each other and parts separated from each other.
  • the edge of the resonant part 2021 exposed in the cavity forms a reflection interface with the air, which makes the acoustic impedance mismatch, suppresses the leakage of shear waves, and further improves the quality factor (Q value) of the resonator.
  • Q value quality factor
  • the resonance portion 2021 is completely separated from the overlapping portion, so that the edge of the resonance portion 2021 is completely exposed in the cavity, the effect of preventing the leakage of shear waves is the best.
  • the resonating part 2021 and the overlapping part 2022 have both mutually connected parts and mutually separated parts, the structural strength of the resonator can be improved.
  • Embodiment 1 refer to Embodiment 1, which will not be repeated here.
  • Embodiment 3 of the present invention provides a thin-film bulk acoustic resonator.
  • FIG. 3 is a schematic structural diagram of the thin-film bulk acoustic resonator of Embodiment 3 of the present invention.
  • the difference between this embodiment and Embodiment 1 is that the piezoelectric layer 202 is complete
  • the film layer, the overlapping part 2022 and the resonating part 2021 are connected together, forming an integrated structure.
  • a part of the conductive pillar 401 is located at the edge of the second gap 221 in contact with the second dielectric layer 102 , and a part is located in the second gap 221 with a distance from the boundary of the second gap 221 .
  • the conductive pillars 401 may all be located at the edge of the second gap 221 , or the conductive pillars 401 and the edge of the second gap 221 may not be in contact.
  • the external electrodes are all located above the extraction electrodes, but in these embodiments, the external electrodes may all be located below the extraction electrodes.
  • the manufacturing method for forming a thin film bulk acoustic wave resonator in the present invention includes: step S1, forming a first structure, and the first structure includes: an extraction electrode, at least covering the extraction electrode and avoiding the area where the first extraction part is located a first sacrificial layer, a dielectric layer surrounding the first sacrificial layer at least on the side of the first sacrificial layer; step S2, forming a piezoelectric layer; step S3, forming a second structure, the second structure includes: an external electrode , at least cover the second sacrificial layer of the external electrode, at least surround the dielectric layer of the second sacrificial layer on the side of the second sacrificial layer; step S4, forming a conductive column, penetrating the second sacrificial layer, connecting the the external electrode; step S5, forming a second lead-out portion, one end of which is connected to the conductive column, and the other end extending out of the effective resonance region; step S6,
  • a temporary substrate is provided; step S1 is performed on the temporary substrate to form a first structure.
  • a carrier substrate is bonded on the first structure, and the temporary substrate is removed; then steps S3-S5 are sequentially performed on the carrier substrate to form a second structure, a conductive column, and a second lead-out portion in sequence.
  • a temporary substrate is provided; step S3 is performed on the temporary substrate to form a second structure, and then step S2 is performed to form a piezoelectric layer, and then the In step S1, a first structure is formed, a carrier substrate is bonded on the first structure, and after the temporary substrate is removed, steps S4 and S5 are performed in sequence to form a conductive column and a second lead-out portion.
  • a temporary substrate is provided; steps S3 , S4 , and S5 are sequentially performed on the temporary substrate to form the second structure, the conductive pillars and the first For the second lead-out portion, the carrier substrate is bonded on the side where the second lead-out portion is located, the temporary substrate is removed, and step S1 is performed on the carrier substrate to form a first structure.
  • the step S2 of forming the piezoelectric layer can be formed before 1) Step S1 is performed.
  • an external electrode layer and a piezoelectric layer are first formed on the temporary substrate, and then Step S1 is performed to form the first structure.
  • It can also be 2) formed after step S1 is performed and before step S3 is performed, for example, step S1 is performed on the temporary substrate to form a first structure, step S2 is performed on the first structure to form a piezoelectric layer, and then a piezoelectric layer is formed.
  • Step S3 is performed on the layer to form a second structure.
  • the piezoelectric layer is a film layer in which both the effective resonance region and the ineffective region are distributed, or it can be a film layer only located in the effective resonance region after being patterned.
  • FIGS. 4 to 13 are schematic structural diagrams corresponding to different steps in a method for manufacturing a thin film bulk acoustic resonator according to Embodiment 4 of the present invention, and the embodiment will be described in detail below with reference to FIGS. 4 to 13 .
  • a temporary substrate 200 is provided, and a first structure is formed on the temporary substrate, and the first structure includes: an extraction electrode 201 , at least covering the extraction electrode 201 and avoiding the first extraction part The first sacrificial layer 210 in the region where 403 is located, and the dielectric layer 101A surrounding the first sacrificial layer 210 at least on the side of the first sacrificial layer 210 .
  • a temporary substrate 200 is provided on which an external electrode layer 203', a piezoelectric layer 202, and an extraction electrode layer 201' are formed.
  • the material of the temporary substrate 200 may be at least one of the following mentioned materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (Si), silicon carbon germanium (SiGe), arsenic Indium (Ins), Gallium Arsenide (Gs), Indium Phosphide (InP) or other III/V compound semiconductors.
  • an isolation layer may also be formed on the temporary substrate 200, and the isolation layer is located between the temporary substrate 200 and the external electrode layer 203'.
  • the isolation layer may be etched by etching In this way, the temporary substrate 200 is separated from the external electrode layer 203 ′ formed later, which helps to peel off the temporary substrate quickly and improves the manufacturing efficiency of the process. If no isolation layer is formed between the temporary substrate 200 and the external electrode layer 203 ′ , the temporary substrate can be subsequently removed by mechanical grinding or the like.
  • the materials of the isolation layers include but are not limited to at least one of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3) and aluminum nitride (AlN).
  • the isolation layer can be formed by chemical vapor deposition, magnetron sputtering, or evaporation.
  • an external electrode layer 203' is deposited on the temporary substrate 200, then a piezoelectric layer 202 is deposited on the external electrode layer 203', and finally an extraction electrode layer 201' is deposited on the piezoelectric layer 202.
  • the piezoelectric layer 202 is formed on the flat external electrode layer 203', which can make the piezoelectric layer 202 have a better lattice orientation, improve the piezoelectric properties of the piezoelectric layer 202, and further improve the overall performance of the resonator.
  • the material of the piezoelectric layer 202 refers to the description of the foregoing structural embodiments.
  • the piezoelectric layer 202 may be deposited using any suitable method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
  • the lead-out electrode layer 201 ′ and the external electrode layer 203 ′ referring to the introduction of the lead-out electrode and the external electrode material in the previous structural embodiment, the lead-out electrode layer 201 can be formed by physical vapor deposition such as magnetron sputtering, evaporation, or chemical vapor deposition. ' or the external electrode layer 203'.
  • the lead-out electrode layer 201 ′ is patterned to form the lead-out electrode 201 .
  • the method of patterning the lead-out electrode layer 201 ′ can use an etching process to etch the lead-out electrode layer 201 ′.
  • the etching process can be a wet etching process or a dry etching process, wherein preferably a dry etching process is used. Dry etching includes but is not limited to reactive ion etching (RIE), ion beam etching, plasma Etching or laser cutting.
  • the lead-out electrode 201 includes two parts, one part is located in the first gap formed later, and the other part is located outside the first gap, and the part extending out of the first gap is the first lead-out part, and the two parts have an integrated structure .
  • a first sacrificial layer material is formed to cover the lead-out electrode 201 and the piezoelectric layer 202 .
  • the first sacrificial material is patterned to form a first sacrificial layer 210.
  • the first sacrificial layer 210 covers a part of the lead-out electrode 201 and the piezoelectric layer around the lead-out electrode 210, and covers a part of the edge of the lead-out electrode.
  • the portion of the lead-out electrode not covered by the first sacrificial layer constitutes a first lead-out portion for connecting with an external electrical signal.
  • the first sacrificial layer 210 forms a first gap after being released in a subsequent process.
  • the position of the first sacrificial layer 210 determines the position of the first gap, and the height of the first sacrificial layer 210 determines the height of the first gap.
  • the material of the first sacrificial layer includes phosphosilicate glass, low temperature silicon dioxide, borophosphosilicate glass, germanium, carbon, polyimide or photoresist, and can be formed by chemical vapor deposition.
  • a dielectric layer 101A surrounding the first sacrificial layer at least on the side of the first sacrificial layer is formed, and covering the first sacrificial layer 210 and the lead-out electrode 201 and the piezoelectric layer 202 on the periphery of the first sacrificial layer 210 .
  • the material of the dielectric layer 101A surrounding the first sacrificial layer at least on the side of the first sacrificial layer may be one of silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3) and aluminum nitride or several combinations. It can be formed by physical vapor deposition or chemical vapor deposition.
  • a release hole 212 is formed in the dielectric layer 101A above the first sacrificial layer at least surrounding the first sacrificial layer at the side of the first sacrificial layer, and the first sacrificial layer is removed through the release hole 212 .
  • the number of release holes may be multiple and distributed in different regions above the first sacrificial layer.
  • a corresponding removal method is adopted. For example, when the material of the first sacrificial layer is polyimide or photoresist, it is removed by ashing method. The ashing method is specifically at 250 degrees Celsius.
  • the oxygen in the release hole 212 chemically reacts with the material of the first sacrificial layer, and the generated gaseous substances are volatilized. Reaction removed. After the first sacrificial layer is removed, a first gap 211 is formed between the surface of the extraction electrode 201 and the first dielectric layer 101A.
  • this embodiment further includes forming a carrier substrate 100 on the upper surface of the dielectric layer 101A surrounding the first sacrificial layer at least on the side surfaces of the first sacrificial layer.
  • the carrier substrate 100 may be bonded on the dielectric layer 101A surrounding the first sacrificial layer at least at the side of the first sacrificial layer by means of bonding.
  • the material of the bonding layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or ethyl silicate.
  • the purpose of forming the carrier substrate 100 is to provide support strength, and at least the thickness of the dielectric layer 101A surrounding the first sacrificial layer at the side of the first sacrificial layer can be formed thinner, thereby saving process time.
  • the temporary substrate 200 is removed.
  • the temporary substrate 200 can be removed by etching the isolation layer. If no isolation layer is formed between the temporary substrate 200 and the external electrode layer 203', mechanical grinding can be performed. way to remove the temporary substrate 200 .
  • the external electrode 203 is formed by patterning the external electrode layer.
  • the edge of the external electrode 203 is located above the area surrounded by the first gap 211 .
  • the edge of the external electrode 203 is also located in the area enclosed by the second gap formed in the subsequent process.
  • the outer periphery of the external electrode and the piezoelectric layer 202 above the first gap 211 may also be etched, so that the piezoelectric layer 202 is divided into a resonance part 2021 and a piezoelectric layer 202 located in the The overlapping portion 2022 on the outer periphery of the resonance portion 2021.
  • All or a part of the edge of the resonance part 2021 is exposed in the cavity.
  • the edges of the resonance part 2021 are all exposed in the cavity, the first gap and the second gap formed in the subsequent process communicate with each other.
  • a second sacrificial layer material is formed to cover the external electrode 203 and the piezoelectric layer 202 .
  • the second sacrificial material is patterned to form a second sacrificial layer 220 , and the second sacrificial layer 220 covers at least the external electrode 203 .
  • the second sacrificial layer 220 also covers the piezoelectric layer 202 on the outer periphery of the external electrode 201 .
  • the second sacrificial layer 220 forms a second gap after being released in a subsequent process.
  • the material and formation method of the second sacrificial layer refer to the material and formation method of the first sacrificial layer.
  • a dielectric layer 102A surrounding the second sacrificial layer at least on the side of the second sacrificial layer is formed, covering the second sacrificial layer 220 and the piezoelectric layer 202 on the periphery of the second sacrificial layer.
  • the material and formation method of the dielectric layer 102A surrounding the second sacrificial layer at least on the side of the second sacrificial layer refer to the material and formation method of the first dielectric layer.
  • conductive pillars 401 are formed on the surfaces of the external electrodes. Specifically, a first through hole is formed, penetrating the second sacrificial layer 220 and the dielectric layer 102A above the second sacrificial layer 220 at least surrounding the second sacrificial layer at the side of the second sacrificial layer, and in the first through hole A conductive material is formed to form conductive pillars 401 .
  • the first through holes may be formed through an etching process or a punching process.
  • a conductive material may be formed in the first through hole by deposition or electroplating, and the conductive material includes low resistivity materials such as gold, silver, tungsten, platinum, aluminum, and copper.
  • the conductive pillar 401 is formed at the edge of the effective resonance region, and the position, structure and function of the conductive column 401 can be referred to the related description of the structure embodiment above.
  • release holes are formed in the dielectric layer 102A above the second sacrificial layer at least surrounding the second sacrificial layer at the side of the second sacrificial layer, and the second sacrificial layer is removed through the release holes.
  • a second gap 221 is formed between the surface of the external electrode 203 and the dielectric layer 102A surrounding the second sacrificial layer at least on the side surfaces of the second sacrificial layer.
  • forming the second lead-out portion 402 includes: forming a second passivation layer 102B; etching the second passivation layer 102B to form a groove; forming a conductive material layer in the groove, as the second lead-out portion 402; or, forming a conductive material layer, patterning the conductive material layer to form the second lead-out portion 402; forming a second passivation layer 102B to cover the second lead-out portion 402; the The dielectric layer surrounding the second sacrificial layer at least at the side of the second sacrificial layer includes the second passivation layer 102B.
  • the surfaces of the second passivation layer 102B and the second lead-out portion 402 are flush, and then a dielectric layer can be formed on the flush surface to facilitate subsequent Bonding of the carrier substrate; when the second lead-out portion 402 is formed first and then the second passivation layer 102B is formed, the surfaces of the second passivation layer 102B and the second lead-out portion 402 are flush or cover the second lead-out portion 402, if flush level, and then a dielectric layer is formed on the flush surface to facilitate subsequent bonding of the carrier substrate.
  • the second lead-out portion 402 extends out of the area where the second gap 221 is located.
  • the second lead-out portion 402 is strip-shaped and leads out from the side where the second gap 221 is located.
  • the second lead-out portion 402 is planar. It should be understood that the function of the second lead-out portion 402 is to connect external signals and play the role of electrical connection, and its shape and area can be flexibly selected according to the situation.
  • the projections of the first lead-out portion 403 and the second lead-out portion 402 in the direction of the piezoelectric layer 202 are staggered from each other.
  • a release hole may be formed to remove the second sacrificial layer.
  • Example 4 an external electrode layer, a piezoelectric layer, and a lead-out electrode layer are sequentially formed on the temporary substrate; after that, the lead-out electrode layer is patterned to form the lead-out electrode; after the first structure is formed, the carrier liner is bonded After the temporary substrate is removed at the bottom, the external electrode layer is patterned to form an external electrode; and then a second structure, a conductive column, and a second lead-out portion are formed.
  • the lead-out electrode or the external electrode is formed by etching, the piezoelectric layer is not etched all the time, the integrity of the piezoelectric layer is preserved, and the piezoelectric layer is distributed in both the effective area and the ineffective area.
  • the second gaps are separated from each other by the piezoelectric layer. Therefore, the first sacrificial layer and the second sacrificial layer are not connected to each other and need to be removed respectively.
  • the piezoelectric layer may be patterned after forming the lead-out electrode or after forming the external electrode to remove the piezoelectric layer in the inactive region or form an air gap around the piezoelectric layer in the effective resonance region.
  • the first sacrificial layer still exists, and the second sacrificial layer is also filled around the patterned piezoelectric layer.
  • the second sacrificial layers are communicated with each other, and the first sacrificial layer and the second sacrificial layer can be removed simultaneously.
  • a piezoelectric layer and an extraction electrode layer are sequentially formed on a temporary substrate; the extraction electrode layer is patterned to form the extraction electrode. Then, referring to the method of Embodiment 4, the first sacrificial layer, a dielectric layer surrounding the first sacrificial layer at least on the side of the first sacrificial layer, is formed, and the first sacrificial layer covers the top of the lead-out electrode. face and side surface; remove the temporary substrate, bond the carrier substrate, and turn over to form an external electrode layer, and pattern the external electrode layer to form the external electrode.
  • a conductive column, a second lead-out portion, a second sacrificial layer, and a dielectric layer surrounding the second sacrificial layer at least on the side surfaces of the second sacrificial layer are formed.
  • the piezoelectric layers can be kept distributed in both the inactive region and the effective resonance region. At this time, since the first sacrificial layer and the second sacrificial layer are separated from each other, the first sacrificial layer and the second sacrificial layer need to be removed separately.
  • the piezoelectric layer may be patterned to remove the piezoelectric layer in the inactive region or the piezoelectric layer in the effective resonance region after forming the lead-out electrode or after forming the external electrode. Air gaps are formed around the perimeter of the layers.
  • the first sacrificial layer still exists, and the second sacrificial layer is also filled around the patterned piezoelectric layer.
  • the first sacrificial layer and the second sacrificial layer are The layers are connected with each other, and the first sacrificial layer and the second sacrificial layer can be removed at the same time.
  • the external electrode layer, the piezoelectric layer, and the extraction electrode layer are not sequentially formed on the temporary substrate.
  • an extraction electrode and a flat layer are formed on the temporary substrate, and the extraction electrode is flush with the surface of the flat layer; after that, referring to the method of Embodiment 4, a first sacrificial layer is formed, at least in the first sacrificial layer.
  • a sacrificial layer laterally surrounds the dielectric layer of the first sacrificial layer.
  • the carrier substrate is bonded, the temporary substrate is removed, and a piezoelectric layer is formed on the flush surface of the extraction electrode and the flat layer on the carrier substrate.
  • an external electrode layer is formed on the piezoelectric layer; the external electrode layer is patterned to form an external electrode; and the second sacrificial layer is formed at least on the side of the second sacrificial layer to surround the second sacrificial layer.
  • the piezoelectric layer may be located in the effective resonance region and the inactive region.
  • the first sacrificial layer and the second sacrificial layer are separated from each other and need to be removed respectively.
  • the piezoelectric layer can also be patterned before or after the external electrode layer is patterned to remove the piezoelectric layer in the inactive region or form an air edge around the piezoelectric layer in the effective resonance region gap.
  • the first sacrificial layer still exists, and the second sacrificial layer is also filled around the patterned piezoelectric layer.
  • the first sacrificial layer and the second sacrificial layer are The layers are connected with each other, and the first sacrificial layer and the second sacrificial layer can be removed at the same time.
  • Embodiment 5 of the present invention provides a method for manufacturing a thin-film bulk acoustic resonator.
  • FIGS. 14 to 19 are schematic structural diagrams corresponding to different steps in a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 5 of the present invention. The present embodiment will be described in detail with reference to FIGS. 14 to 19 .
  • the first structure is first formed on the temporary substrate, and in this embodiment, the second structure is first formed on the temporary substrate.
  • a temporary substrate 200 is provided on which a second structure is formed.
  • the second sacrificial layer 220 and the dielectric layer 102A surrounding the second sacrificial layer at least on the side of the second sacrificial layer are formed first, and then the external electrodes 203 are formed, and the second sacrificial layer only covers the external electrodes 203 on the top surface (the surface close to the temporary substrate 200 ) or cover the top and side surfaces of the external electrodes.
  • the dielectric layer 102A surrounding the second sacrificial layer at least on the side of the second sacrificial layer, covering the side of the second sacrificial layer and the side of the external electrode, or covering the side and top surface of the second sacrificial layer and the side of the external electrode.
  • a specific method for forming an external electrode includes: referring to FIG. 15 , etching the second sacrificial layer 220 to form a groove, and filling the groove with a conductive material as the external electrode. If the conductive material is formed outside the groove, the groove needs to be removed The external conductive material can be removed by chemical mechanical grinding or etching.
  • a variant of forming the external electrode may also be: forming an external electrode layer on the surface of the second sacrificial layer and the dielectric layer surrounding the second sacrificial layer at least on the side of the second sacrificial layer, and then patterning the external electrode layer to form an external electrode layer. External electrode. At this time, the external electrodes are located on the second sacrificial layer instead of being embedded in the second sacrificial layer.
  • the method for forming the second sacrificial layer 220 and the dielectric layer 102A surrounding the second sacrificial layer at least on the side surfaces of the second sacrificial layer may refer to Embodiment 4.
  • a piezoelectric layer 202 is formed on the temporary substrate.
  • a first structure is formed on the temporary substrate.
  • the specific method includes: forming an extraction electrode layer, and patterning the extraction electrode layer to form an extraction electrode 201 .
  • a first sacrificial layer 210 and a dielectric layer 101A surrounding the first sacrificial layer at least on the side surfaces of the first sacrificial layer are formed.
  • the relevant content in Embodiment 4 can be cited here.
  • the dielectric layer 101A surrounding the first sacrificial layer at least on the side of the first sacrificial layer also covers the surface of the first sacrificial layer 210 .
  • the dielectric layer 101A of the sacrificial layer surrounding the first sacrificial layer is bonded to the carrier substrate 100 .
  • the formed structure is turned over, the temporary substrate is removed, and the conductive pillar 401 and the second lead-out portion 402 are formed in sequence.
  • the conductive pillar 401 and the second lead-out portion 402 are formed in sequence.
  • the second passivation layer 102B is also formed. The relevant content in Embodiment 4 can be cited here.
  • the method of removing the first sacrificial layer and the second sacrificial layer in the fourth embodiment can be cited in the fifth embodiment.
  • Example 5 the piezoelectric layer is not etched all the time, the integrity of the piezoelectric layer is preserved, and the piezoelectric layer is distributed in both the effective area and the ineffective area, and the first gap and the second gap pass through the The piezoelectric layers are separated from each other, therefore, the first sacrificial layer and the second sacrificial layer are not connected to each other and need to be removed separately.
  • the piezoelectric layer may be patterned to remove the piezoelectric layer in the inactive region or form an air gap around the piezoelectric layer in the effective resonance region.
  • the advantages of this kind of situation please refer to the description of the corresponding part in the structural embodiment.
  • the second sacrificial layer still exists, and the first sacrificial layer is also filled around the patterned piezoelectric layer.
  • the second sacrificial layers are communicated with each other, and the first sacrificial layer and the second sacrificial layer can be removed simultaneously.
  • the piezoelectric layer may be located in the effective resonance region and the ineffective region.
  • the first sacrificial layer and the second sacrificial layer are separated from each other and need to be removed respectively.
  • the piezoelectric layer may be patterned before or after patterning the lead-out electrode layer to remove the piezoelectric layer in the inactive region or form an air edge around the piezoelectric layer in the effective resonance region gap.
  • the first sacrificial layer after the first sacrificial layer is formed, the second sacrificial layer still exists, and the first sacrificial layer is also filled around the patterned piezoelectric layer.
  • the first sacrificial layer and the second sacrificial layer are The layers are connected with each other, and the first sacrificial layer and the second sacrificial layer can be removed at the same time.
  • Embodiment 6 of the present invention provides a method for manufacturing a thin-film bulk acoustic resonator.
  • FIGS. 20 to 27 are schematic structural diagrams corresponding to different steps in a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 6 of the present invention. The present embodiment will be described in detail with reference to FIGS. 20 to 27 .
  • a carrier substrate 100 is provided, and a second lead-out portion 402 is formed on the carrier substrate 100 .
  • the material of the second lead-out portion 402 refers to Embodiment 1.
  • a conductive material layer can be formed by a physical vapor deposition method, and then patterned The conductive material layer forms the second lead-out portion 402 .
  • the relevant content in Embodiment 4 can be cited here.
  • a dielectric layer 102A and a second sacrificial layer 220 are formed that surround the second sacrificial layer at least on the side surfaces of the second sacrificial layer.
  • a dielectric layer 102A surrounding the second sacrificial layer at least on the side of the second sacrificial layer is formed on and above the outer periphery of the second lead-out portion 402 , and etching is performed to surround the second sacrificial layer at least on the side of the second sacrificial layer.
  • the dielectric layer 102A of the two sacrificial layers forms a second gap 221 , so that one end of the second lead-out portion 402 is located in the second gap 221 and the other end is located outside the second gap 221 .
  • the second sacrificial layer 220 is filled in the second gap.
  • the material and formation method of the second sacrificial layer refer to Embodiment 4.
  • the second sacrificial layer 210 and the second sacrificial layer surround the The upper surfaces of the dielectric layers 102A of the two sacrificial layers are flush.
  • the second sacrificial layer may also be formed first, and then a dielectric layer surrounding the second sacrificial layer at least on the side surfaces of the second sacrificial layer is formed.
  • the relevant content in Embodiment 4 can be cited here.
  • conductive pillars 401 are formed in the second sacrificial layer, and the lower ends of the conductive pillars 401 are connected to the second lead-out portion 402 .
  • the relevant N contents of the structure, shape, and position of the conductive pillars in Embodiment 4 can be cited here.
  • an external electrode layer is sequentially formed on the second sacrificial layer 220, at least on the dielectric layer 102A surrounding the second sacrificial layer on the side of the second sacrificial layer, and the external electrode layer is patterned to form an external electrode 203,
  • the external electrode 203 is completely located in the area surrounded by the second sacrificial layer.
  • a sacrificial material is formed on the second sacrificial layer on the periphery of the external electrode, and the top surface of the newly formed sacrificial material is flush with the top surface of the external electrode. Refer to Example 4 for the material and formation method of the external electrode layer.
  • a piezoelectric layer 202 is formed on the outer periphery of the external electrode 203 and the external electrode 203 , a lead electrode layer 201 ′ is formed on the upper surface of the piezoelectric layer 202 , and the materials and formation methods of the lead electrode layer 201 ′ and the piezoelectric layer 202 are formed Refer to Example 4.
  • the lead-out electrode layer is etched to form the lead-out electrode 201 .
  • a part of the edge of the lead-out electrode 201 is located above the area surrounded by the first sacrificial layer 220 , and another part of the edge extends out of the area where the second sacrificial layer 220 is located.
  • the lead-out electrode 201 extending out of the region where the second sacrificial layer 220 is located constitutes the first lead-out portion 403 .
  • the first sacrificial layer 210 is formed, which covers the surface of the extraction electrode 201 except the first extraction portion 403 and the surface of the piezoelectric layer on the periphery of the extraction electrode opposite to the first extraction portion 403 .
  • a first gap is formed after the first sacrificial layer is released in a later process.
  • the first sacrificial layer and the second sacrificial layer are arranged almost opposite to each other.
  • a dielectric layer 101A surrounding the first sacrificial layer at least on the side surfaces of the first sacrificial layer is formed on the outer periphery of the first sacrificial layer 210 .
  • the first and second sacrificial layers are removed to form first and second gaps 211 and 221 .
  • a via hole can be formed in the piezoelectric layer on the periphery of the external electrode to connect the first sacrificial layer with the second sacrificial layer, a release hole can be formed on the second dielectric layer 102 above the second sacrificial layer, and the through hole release hole can be removed at one time A first sacrificial layer and a second sacrificial layer.
  • the first sacrificial layer may be removed first and then the second sacrificial layer may be removed.
  • Example 6 the piezoelectric layer is not etched all the time, the integrity of the piezoelectric layer is preserved, and the piezoelectric layer is distributed in both the effective area and the ineffective area, and the first gap and the second gap pass through the The piezoelectric layers are separated from each other, therefore, the first sacrificial layer and the second sacrificial layer are not connected to each other and need to be removed separately.
  • the piezoelectric layer may be patterned after the piezoelectric layer is formed or after the electrode is drawn out to remove the piezoelectric layer in the inactive region or form an air gap around the piezoelectric layer in the effective resonance region.
  • the second sacrificial layer still exists, and the first sacrificial layer is also filled around the patterned piezoelectric layer.
  • the second sacrificial layers are communicated with each other, and the first sacrificial layer and the second sacrificial layer can be removed simultaneously.
  • Embodiment 7 of the present invention provides a method for manufacturing a thin-film bulk acoustic resonator.
  • FIGS. 28 to 33 are schematic structural diagrams corresponding to different steps in a method for manufacturing a thin-film bulk acoustic resonator according to Embodiment 7 of the present invention. The present embodiment will be described in detail with reference to FIGS. 28 to 33 .
  • the external electrode is located below the lead-out electrode, and the second structure, the conductive column, the second lead-out portion and the first structure are formed in sequence.
  • a temporary substrate 200 is provided, on which an extraction electrode layer 201', a piezoelectric layer 202, and an external electrode layer 203' are formed.
  • the content of Example 4 can be cited here.
  • the external electrode layer 203' is patterned to form the external electrode 203.
  • a second sacrificial layer material is formed to cover the external electrodes 203 and the piezoelectric layer 202 .
  • the second sacrificial material is patterned to form the second sacrificial layer 220 .
  • the second sacrificial layer 220 covers the surface of the external electrode 203 and the periphery thereof.
  • a dielectric layer 102A surrounding the second sacrificial layer at least on the side surfaces of the second sacrificial layer is formed, and the piezoelectric layer 202 covering the outer periphery of the second sacrificial layer 220 is formed.
  • the upper surface of the second sacrificial layer 220 is also covered.
  • a conductive pillar 401 is formed on the surface of the external electrode, the second sacrificial layer is removed, a second gap is formed, and a second lead-out portion 402 and a second passivation layer 102B are formed above the conductive pillar 401 .
  • the carrier substrate 100 is further formed on the surface of the second passivation layer 102B.
  • the temporary substrate is removed, the lead-out electrode layer is patterned, and the lead-out electrode 201 is formed.
  • a first sacrificial layer material is formed to cover the lead-out electrode 201 and the piezoelectric layer 202 .
  • the first sacrificial material is patterned to form a first sacrificial layer.
  • the first sacrificial layer covers a part of the lead-out electrode 201 and the piezoelectric layer around the lead-out electrode 210, and covers a part of the edge of the lead-out electrode.
  • the portion of the lead-out electrode not covered by the first sacrificial layer constitutes a first lead-out portion for connecting with an external electrical signal.
  • a dielectric layer 101A surrounding the first sacrificial layer is formed at least on the side of the first sacrificial layer, covering the first sacrificial layer and the lead-out electrode 201 and piezoelectric layer 202 on the periphery of the first sacrificial layer, and then the first sacrificial layer is removed.
  • the piezoelectric layer is not etched all the time, the integrity of the piezoelectric layer is preserved, and the piezoelectric layers are distributed in both the active area and the inactive area, and the first gap and the second gap pass through the piezoelectric layer.
  • the electrical layers are separated from each other, therefore, the first sacrificial layer and the second sacrificial layer are not connected to each other and need to be removed separately.
  • the piezoelectric layer may be patterned after forming the external electrode or the lead-out electrode to remove the piezoelectric layer in the inactive region or form an air gap around the piezoelectric layer in the effective resonance region.
  • the second sacrificial layer still exists, and the first sacrificial layer is also filled around the patterned piezoelectric layer.
  • the first sacrificial layer and the second sacrificial layer are mutually connected, the first sacrificial layer and the second sacrificial layer can be removed at the same time.

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Abstract

本发明涉及薄膜体声波谐振器及其制造方法，其中，薄膜体声波谐振器包括：叠置的引出电极、压电层和外接电极，有效谐振区包括引出电极、压电层和外接电极在垂直于压电层表面方向上相互重叠的区域，有效谐振区的外部为无效区；第一介质层，第一介质层的表面与引出电极的表面之间设有第一间隙；引出电极从有效谐振区延伸出第一间隙的部分为第一引出部；第二介质层，第二介质层的表面与外接电极的表面之间设有第二间隙；外接电极位于第二间隙围成的区域内或者二者边界重合；导电柱，一端连接于外接电极，另一端连接有第二引出部，第二引出部从有效谐振区延伸出第二间隙；引出电极和外接电极其中之一位于另一上方。

Description

薄膜体声波谐振器及其制造方法 技术领域
本发明涉及半导体器件制造领域，尤其涉及一种薄膜体声波谐振器及其制造方法。
 背景技术
自模拟射频通讯技术在上世纪90代初被开发以来，射频前端模块已经逐渐成为通讯设备的核心组件。在所有射频前端模块中，滤波器已成为增长势头最猛、发展前景最大的部件。随着无线通讯技术的高速发展，5G通讯协议日渐成熟，市场对射频滤波器的各方面性能也提出了更为严格的标准。滤波器的性能由组成滤波器的谐振器单元决定。在现有的滤波器中，薄膜体声波谐振器(FBAR)因其体积小、插入损耗低、带外抑制大、品质因数高、工作频率高、功率容量大以及抗静电冲击能力良好等特点，成为最适合5G应用的滤波器之一。
通常，薄膜体声波谐振器包括两个薄膜电极，并且两个薄膜电极之间设有压电薄膜层，其工作原理为利用压电薄膜层在交变电场下产生振动，该振动激励出沿压电薄膜层厚度方向传播的体声波，此声波传至上下电极与空气交界面被反射回来，进而在薄膜内部来回反射，形成震荡。当声波在压电薄膜层中传播正好是半波长的奇数倍时，形成驻波震荡。
 技术问题
但是，目前制作出的空腔型薄膜体声波谐振器，其品质因子（Q）无法进一步提高，因此无法满足高性能的射频系统的需求。
 技术解决方案
本发明的目的在于提供一种薄膜体声波谐振器及其制造方法，能够提高薄膜体声波谐振器的品质因子，进而提高器件性能。
为了实现上述目的，本发明提供一种薄膜体声波谐振器，包括：叠置的引出电极、压电层和外接电极，有效谐振区包括所述引出电极、压电层和外接电极在垂直于所述压电层表面方向上相互重叠的区域，所述有效谐振区的外部为无效区；第一介质层，所述第一介质层的表面与所述引出电极的表面之间设有第一间隙；所述引出电极从所述有效谐振区延伸出所述第一间隙的部分为第一引出部；第二介质层，所述第二介质层的表面与所述外接电极的表面之间设有第二间隙；所述外接电极位于所述第二间隙围成的区域内或者二者边界重合；导电柱，一端连接于所述外接电极，另一端连接有第二引出部，所述第二引出部从所述有效谐振区延伸出所述第二间隙；所述引出电极和所述外接电极其中之一位于另一上方。
本发明还提供一种薄膜体声波谐振器的制造方法，包括：形成第一结构，所述第一结构包括：引出电极、至少遮盖所述引出电极且避开所述第一引出部所在区域的第一牺牲层、至少在所述第一牺牲层侧面包围所述第一牺牲层的第一介质层；形成压电层；形成第二结构，所述第二结构包括：外接电极、至少遮盖所述外接电极的第二牺牲层、至少在所述第二牺牲层侧面包围所述第二牺牲层的第二介质层；形成导电柱，贯穿所述第二牺牲层、连接所述外接电极；形成第二引出部，一端连接所述导电柱，另一端延伸出所述有效谐振区；去除所述第一牺牲层、第二牺牲层，形成所述第一间隙、第二间隙。
 有益效果
本发明的有益效果在于：通过导电柱和第二引出部将外接电极与外部信号连接，可以增大外接电极导出面积及阻抗，同时抑制电极间耦合效应，增强导热；第一空隙和第二间隙作为声波反射结构提高谐振器的品质因数；导电柱所在的区域形成声阻抗失配区，能够使有效谐振区的边界与有效谐振区内部的声阻抗失配，有利于提高谐振器的品质因数。
进一步地，导电柱在承载衬底表面的投影为封闭或带有间隙的环形，能够进一步抑制横向声波能量损失，提高谐振器的品质因数。
进一步地，外接电极的全部侧边以及引出电极的部分侧边暴露在空腔中，能够抑制电极侧边的横波损失。
进一步地，压电层的边缘暴露在空腔中，能够进一步的抑制横波损失。
进一步地，压电层为完整的膜层，可以保证压电层的压电特性。
进一步地，压电层形成在平整的电极层上，可以使压电层具有较好的晶格取向，提高压电层的压电特性，进而提高谐振器的整体性能。
 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本发明实施例1的一种薄膜体声波谐振器的结构示意图。
图2示出了本发明实施例2的一种薄膜体声波谐振器的结构示意图。
图3示出了本发明实施例3的一种薄膜体声波谐振器的结构示意图。
图4至图13示出了本发明实施例4的一种薄膜体声波谐振器的制造方法不同步骤中对应的结构示意图。
图14至图19示出了本发明实施例5的一种薄膜体声波谐振器的制造方法不同步骤中对应的结构示意图。
图20至图27示出了本发明实施例6的一种薄膜体声波谐振器的制造方法不同步骤中对应的结构示意图。
图28至图33示出了本发明实施例7的一种薄膜体声波谐振器的制造方法不同步骤中对应的结构示意图。
附图标记说明：100-承载衬底；101A-至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层；101B-第一钝化层；101-第一介质层；102A-至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层；102B-第二钝化层；102-第二介质层；200-临时衬底；201’-引出电极层；201-引出电极；202-压电层；203’-外接电极层；203-外接电极；210-第一牺牲层；220-第二牺牲层；211-第一间隙；221-第二间隙；401-导电柱；402-第二引出部；403-第一引出部；10-第一空腔；2021-谐振部；2022-搭接部。
 本发明的实施方式
目前制作出的空腔型薄膜体声波谐振器，存在横波损失，使品质因子（Q）无法进一步提高的问题，因此无法满足高性能的射频系统的需求。
以下结合附图和具体实施例对本发明的薄膜体声波谐振器及其制作方法作进一步详细说明。根据下面的说明和附图，本发明的优点和特征将更清楚，然而，需说明的是，本发明技术方案的构思可按照多种不同的形式实施，并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
在说明书和权利要求书中的术语“第一”“第二”等用于在类似要素之间进行区分，且未必是用于描述特定次序或时间顺序。要理解，在适当情况下，如此使用的这些术语可替换，例如可使得本文所述的本发明实施例能够以不同于本文所述的或所示的其他顺序来操作。类似的，如果本文所述的方法包括一系列步骤，且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序，且一些所述的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同，虽然在所有附图中都可轻易辨认出这些构件，但为了使附图的说明更为清楚，本说明书不会将所有相同构件的标号标于每一图中。
实施例 1
本发明实施例1提供了一种薄膜体声波谐振器，图1为本发明实施例1的薄膜体声波谐振器的结构示意图，请参考图1，所述薄膜体声波谐振器包括：层叠的引出电极201、压电层202和外接电极203，有效谐振区包括所述引出电极201、压电层202和外接电极203在垂直于所述压电层202表面方向上相互重叠的区域，所述有效谐振区的外部为无效区；第一介质层101，所述第一介质层101的表面与所述引出电极201的表面之间设有第一间隙211；第二介质层102，所述第二介质层102的表面与所述外接电极203的表面之间设有第二间隙221；所述外接电极203位于所述第二间隙221围成的区域内或者二者边界重合；导电柱401，一端连接于所述外接电极203，另一端连接有第二引出部402，所述第二引出部402从所述有效谐振区延伸出所述第二间隙221；所述引出电极201和所述外接电极203其中之一位于另一上方。
参考图1，本实施例中，还包括承载衬底100。第一介质层101和承载衬底100可以通过键合层或沉积的方式进行结合。键合层的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯。本实施例中，第一介质层101通过沉积的方式形成在承载衬底100上。第一介质层可以为单层结构，也可以为叠层结构。第一介质层的材料可以包括但不限于氧化硅、氮化硅、氮氧化硅、碳氮化硅等材料中的一种，但本发明的技术不仅仅限定于此。
承载衬底100的材质可以为本领域技术人员熟知的任意合适的底材，例如可以是以下所提到的材料中的至少一种：硅(Si)、锗(Ge)、锗硅 (SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体。
第一介质层101的上方从下至上依次包括叠层设置的引出电极201、压电层202，外接电极203。外接电极203和引出电极201可以使用本领域技术任意熟知的任意合适的导电材料或半导体材料，其中，导电材料可以为具有导电性能的金属材料，例如，由钼（Mo）、铝（Al）、铜（Cu）、钨（W）、钽（Ta）、铂（Pt）、钌（Ru）、铑（Rh）、铱（Ir）、铬（Cr）、钛（Ti）、金(Au)、锇(Os)、铼(Re)、钯(Pd)等金属中一种制成或由上述金属形成的叠层制成。半导体材料例如是Si、Ge、SiGe、SiC、SiGeC等。压电层202的材料可以使用氮化铝(AlN)、氧化锌(ZnO)、锆钛酸铅(PZT)、铌酸锂(LiNbO3)、石英(Quartz)、铌酸钾(KNbO3)或钽酸锂(LiTaO3)等具有纤锌矿型结晶结构的压电材料及它们的组合。当压电层202包括氮化铝(AlN)时，压电层202还可包括稀土金属，例如钪(Sc)、铒(Er)、钇(Y)和镧(La)中的至少一种。此外，当压电层202包括氮化铝(AlN) 时，压电层202还可包括过渡金属，例如锆(Zr)、钛(Ti)、锰(Mn)和铪(Hf)中的至少一种。可以使用化学气相沉积、物理气相沉积或原子层沉积等本领域技术人员熟知的任何适合的方法沉积形成压电层202。
本实施例中，第一介质层101的上表面中间凹陷，外周凸出。其中引出电极201的下表面与第一介质层101凹陷区域的上表面之间设有第一间隙211。本实施例中，引出电极201包括两部分，一部分位于第一间隙211内，一部分位于第一间隙211外，两部分为一体结构。其中位于第一间隙211外的部分为第一引出部403，用于连接外部信号。位于第一间隙211内的部分其边缘暴露在第一间隙211中。引出电极201边缘外周的压电层202的底面也暴露在第一间隙211中。压电层202为水平完整的膜层，四周延伸至第一介质层101凸出区域的表面上方。引出电极201的部分边缘暴露在第一间隙211中，可以使引出电极201的边缘与空气形成反射界面，使声阻抗失配，抑制横波泄露，进而提升谐振器的品质因子（Q值）。
第二介质层102位于第一介质层101上方。第二介质层102的材料可以包括但不限于氧化硅、氮化硅、氮氧化硅、碳氮化硅等材料中的一种，第二介质层可以为单层结构，也可以为叠层结构。本实施例中，第二介质层102的下表面中间凹陷，外周凸出。其中外接电极203的上表面与第二介质层102凹陷区域的下表面之间设有第二间隙221。本实施例中，第二间隙221的边界大于外接电极203的边界，使外接电极203边缘外周暴露在第二间隙221中。外接电极203的边缘完全暴露在第二间隙221中，可以使外接电极203的边缘与空气形成反射界面，使声阻抗失配，抑制横波泄露，进而提升谐振器的品质因子（Q值）。
本实施例中，第二介质层102的凹陷区域及第二间隙221与第一介质层101的凹陷区域及第一间隙211相对设置，第二介质层102的凸出区域与第一介质层101的凸出区域相对设置。两个凹陷区域之间为谐振器有效谐振区所在的区域，有效谐振区包括所述引出电极201、压电层202和外接电极203在垂直于所述压电层202表面方向上相互重叠的区域。本实施例中，所述第一间隙211且所述第二间隙221在所述压电层202方向上的投影的边界包围所述有效谐振区在所述压电层202方向上的投影的边界。其中“包围”的意思为有效谐振区的边界在第一间隙211且第二间隙221内，或者有效谐振区的边界和第一间隙211和/或第二间隙221的边界重合。图1示出的情况为有效谐振区的边界在第一间隙211且第二间隙221内。本实施例中，所述第一间隙211且所述第二间隙221在所述压电层202方向上的投影的边界包围所述引出电极201和所述外接电极203在所述压电层202方向上的投影的边界。其中“包围”的含义同前文所述。
本实施例中，所述压电层202包括谐振部2021和位于所述谐振部外周的搭接部2022，所述谐振部2021位于所述有效谐振区，所述搭接部2022位于所述有效谐振区外。具体地，本实施例中，压电层202为完整的膜层，谐振部2021和搭接部2022为一体结构。第一间隙305和第二间隙306被压电层202相互隔离。在另一个实施例中，所述第一间隙和所述第二间隙可以通过分布于无效区的多个通孔连通，例如通孔贯穿无效区的压电层（或同时贯穿压电层和引出电极）。或者所述第一间隙、第二间隙通过包围有效区的非封闭的环形通孔连通，此时非封闭的环形通孔的内壁可以构成有效谐振区的边界，其内壁也可以位于有效谐振区边界的外部。
本实施例中，外接电极203的上表面设有导电柱401。导电柱401可以为单个或多个间断的柱状。本实施例中，导电柱401设置在有效谐振区的边缘，在压电层202表面方向上的投影为环形，其中环形包括间断或者封闭的环形。环形的形状可以是圆形，椭圆形，多边形，或者由弧线和直边共同构成的不规则形状。封闭的环形意味着导电柱401是连续的，不封闭的环形意味着导电柱401是不连续的。导电柱401所在的区域与有效谐振区形成声阻抗失配，从而能够将向外传播的横向声波反射回有效谐振区内，以抑制横向杂波的泄露，减小能量损耗，提高谐振器的品质因子（Q值）。当导电柱401在压电层302表面的投影为封闭的环形时，更有利于防止声波的横向泄露。
导电柱401的另一端连接有第二引出部402。本实施例中第二引出部402埋设于所述第二介质层102中。在其他实施例中，第二引出部402也可以位于第二介质层102凹陷区域的下表面。从图1中可以看出，所述第二引出部402从所述有效谐振区所在侧向外侧引出。第二引出部402可以作为信号输入端将电信号引入有效谐振区的外接电极203，也可以作为信号输出端将外接电极203上的电信号输出。当第一引出部403作为信号输入端时，第二引出部402作为信号输出端，反之，亦然。
本实施例中，所述第一引出部403和所述第二引出部402在所述压电层方向上的投影相互错开。避免由于电位浮空产生的高频耦合，防止寄生电容效应。
导电柱401的材料为导电材料，如：金、银、钨、铂、铝、铜等低电阻率的材料。第二引出部402的材料可以参照导电柱的材料，导电柱的材料可以和第二引出部的材料可以相同或者不同。
实施例 2
本发明实施例2提供了一种薄膜体声波谐振器，图2为本发明实施例2的薄膜体声波谐振器的结构示意图，本实施例与实施例1的区别在于，本实施例中，压电层202的谐振部2021位于有效谐振区，搭接部2022位于有效谐振区外，谐振部2021与搭接部2022相互分离。请参考图2，具体结构如下：第一空隙211和第二空隙221相互连通形成空腔，谐振部2021完全位于空腔内，搭接部2022位于空腔外，搭接部2022和谐振部2021完全分离，使谐振部2021的外周均暴露在空腔中。图2中所示，压电层的谐振部2021的边缘与引出电极201的边缘以及外接电极203的部分边缘三者重合，构成了有效谐振区的边缘，此时谐振部2021全部位于位于有效谐振区。在另一个实施例中，谐振部2021与搭接部2022既有相互连接的部分，也有相互分离的部分。暴露在空腔中的谐振部2021的边缘与空气形成反射界面，使声阻抗失配，抑制横波泄露，进而提升谐振器的品质因子（Q值）。当谐振部2021与搭接部完全分离，使谐振部2021的边缘完全暴露在空腔中时，防止横波泄露的效果最好。当谐振部2021与搭接部2022既有相互连接的部分，也有相互分离的部分时，可以提高谐振器的结构强度。本实施例其他结构部分参照实施例1，此处不在赘述。
实施例 3
本发明实施例3提供了一种薄膜体声波谐振器，图3为本发明实施例3的薄膜体声波谐振器的结构示意图，本实施例与实施例1的区别在于：压电层202为完整的膜层，搭接部2022和谐振部2021连接在一起，为一体结构。导电柱401一部分位于第二间隙221的边缘与第二介质层102接触，一部分位于第二间隙221中，与第二间隙221的边界设有距离。导电柱401也可以全部位于第二间隙221的边缘处，或导电柱401与第二间隙221的边缘均不接触。
以上实施例1至实施例3中，外接电极均位于引出电极上方，但这些实施例中，也可以是外接电极均位于引出电极下方。
本发明中形成薄膜体声波谐振器的制造方法包括：步骤S1，形成第一结构，所述第一结构包括：引出电极、至少遮盖所述引出电极且避开所述第一引出部所在区域的第一牺牲层、至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层；步骤S2，形成压电层；步骤S3，形成第二结构，所述第二结构包括：外接电极、至少遮盖所述外接电极的第二牺牲层、至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层；步骤S4，形成导电柱，贯穿所述第二牺牲层、连接所述外接电极；步骤S5，形成第二引出部，一端连接所述导电柱，另一端延伸出所述有效谐振区；步骤S6，去除所述第一牺牲层、第二牺牲层，形成所述第一间隙、第二间隙。以上各个步骤之间的顺序可以依次进行，也可以不按照顺序依次进行。
其中一个方案中（对应实施例4，参考图4至图13）：提供临时衬底；在所述临时衬底上执行步骤S1，形成第一结构。在第一结构上键合承载衬底，去除所述临时衬底；然后在承载衬底上依次执行步骤S3-S5，依次形成第二结构、导电柱和第二引出部。
另一个方案中（可以对应实施例5，参考图14至图19）：提供临时衬底；在临时衬底上执行步骤S3，形成第二结构，之后执行步骤S2，形成压电层，然后执行步骤S1，形成第一结构，在第一结构上键合承载衬底，去除临时衬底后，依次执行步骤S4和步骤S5，形成导电柱和第二引出部。
再一个方案中（可以对应实施例6，参考图20-图27）：提供承载；在承载衬底上执行步骤S5，形成第二引出部，再执行步骤S4，形成导电柱，然后执行步骤S3，形成第二结构，然后执行步骤S2，形成压电层，覆盖第二结构，最后执行步骤S1，在第二结构上形成第一结构。
又一个方案中（可以对应实施例7，参考图28-图33）：提供临时衬底；在临时衬底上依次执行步骤S3、步骤S4、步骤S5，依次形成第二结构，导电柱和第二引出部，在第二引出部所在侧键合承载衬底，去除临时衬底，在承载衬底上执行步骤S1，形成第一结构。
以上几个方案中，形成压电层的步骤S2：可以在1）执行步骤S1之前形成，如，先在临时衬底上形成外接电极层，压电层，之后执行步骤S1，形成第一结构。也可以2）在执行步骤S1之后，执行步骤S3之前形成，如，在临时衬底上执行步骤S1，形成第一结构，在第一结构上执行步骤S2，形成压电层，之后在压电层上执行步骤S3，形成第二结构。压电层为有效谐振区和无效区均分布的膜层，也可以是经过图形化仅位于有效谐振区的膜层。
下面结合附图对各个实施例进行详细的说明：
实施例 4
图4至图13为本发明实施例4的一种薄膜体声波谐振器的制造方法中不同步骤对应的结构示意图，以下将参考图4至图13详细说明本实施例。
参考图4-图7，提供临时衬底200，在临时衬底上形成第一结构，所述第一结构包括：引出电极201、至少遮盖所述引出电极201且避开所述第一引出部403所在区域的第一牺牲层210、至少在所述第一牺牲层210侧面包围所述第一牺牲层210的介质层101A。
具体地，参考图4，提供临时衬底200，在所述临时衬底200上形成外接电极层203’、压电层202和引出电极层201’。
临时衬底200的材料可以是以下所提到的材料中的至少一种：硅(Si)、锗(Ge)、锗硅 (SiGe)、碳硅(Si)、碳锗硅(SiGe)、砷化铟(Ins)、砷化镓(Gs)、磷化铟(InP)或者其它III/V化合物半导体。
另外，为便于后续剥离临时衬底200，还可以在临时衬底200上形成隔离层，隔离层位于临时衬底200和外接电极层203’之间，在后续剥离工艺中，可以通过腐蚀隔离层的方式，使临时衬底200与后续形成的外接电极层203’分离，有助于快速剥离临时衬底，提高工艺制作效率，若临时衬底200与外接电极层203’之间未形成隔离层，则后续可通过机械研磨等方式去除临时衬底。隔离层的材质均包括但不限于二氧化硅(SiO2)、氮化硅 (Si3N4)、氧化铝（Al2O3）和氮化铝（AlN）中的至少一种。隔离层可通过化学气相沉积、磁控溅射或蒸镀等方式形成。
首先在临时衬底200上沉积外接电极层203’，然后在外接电极层203’上沉积压电层202，最后在压电层202上沉积引出电极层201’。压电层202形成在平整的外接电极层203’上，可以使压电层202具有较好的晶格取向，提高压电层202的压电特性，进而提高谐振器的整体性能。
压电层202的材料参照前文结构实施例的描述。可以使用化学气相沉积、物理气相沉积或原子层沉积等本领域技术人员熟知的任何适合的方法沉积形成压电层202。引出电极层201’和外接电极层203’材料参照前文结构实施例关于引出电极和外接电极材料的介绍，可以通过磁控溅射、蒸镀等物理气相沉积或者化学气相沉积方法形成引出电极层201’或外接电极层203’。
参考图5，形成引出电极层201’之后，对引出电极层201’进行图形化，形成引出电极201，图形化引出电极层201’的方法可以利用刻蚀工艺刻蚀引出电极层201’，该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺，其中较佳地使用干法刻蚀工艺，干法刻蚀包括但不限于反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀或者激光切割。本实施例中，引出电极201包括两部分，一部分位于后续形成的第一间隙内，另一部分位于第一间隙外，其中延伸出第一间隙外的部分为第一引出部，两部分为一体结构。
参考图6，形成第一牺牲层材料，覆盖引出电极201、压电层202。图形化第一牺牲材料，形成第一牺牲层210，本实施例中，第一牺牲层210覆盖一部分引出电极201及引出电极210外周的压电层，将一部分引出电极的边缘遮盖在内。引出电极未被第一牺牲层覆盖的部分构成第一引出部，用于与外部电信号连接。第一牺牲层210在后续工艺中释放后形成第一间隙。第一牺牲层210的位置决定了第一间隙的位置，第一牺牲层210的高度决定了第一间隙的高度。第一牺牲层材料包括磷硅玻璃、低温二氧化硅、硼磷硅玻璃、锗、碳、聚酰亚胺或光阻剂，可以通过化学气相沉积的方法形成。
参考图7，形成至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A，覆盖第一牺牲层210及第一牺牲层210外周的引出电极201和压电层202。至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A的材料可以为二氧化硅（SiO2）、氮化硅(Si3N4)、氧化铝（Al2O3）和氮化铝的一种或几种组合。可以通过物理气相沉积或化学气相沉积形成。
参考图8，在第一牺牲层上方的至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A中形成释放孔212，通过释放孔212去除第一牺牲层。为将第一牺牲层释放干净，释放孔的数量可以为多个，分布于第一牺牲层上方的不同区域。根据选择的第一牺牲层材料，采用相对应的去除方法，比如当第一牺牲层材料为聚酰亚胺或光阻剂时，采用灰化的方法去除，灰化的方法具体为在250摄氏度的温度下，通过释放孔212的氧与第一牺牲层材料发生化学反应，生成气体物质挥发掉，当第一牺牲层材料为低温二氧化硅时，用氢氟酸溶剂和低温二氧化硅发生反应去除。去除第一牺牲层后，在引出电极201的表面和第一层第一介质层101A之间形成第一间隙211。
参考图9，本实施例中，还包括在至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A的上表面形成承载衬底100。可以通过键合的方式将承载衬底100键合在至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A上。键合层的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯。形成承载衬底100的目的是，提供支撑强度，至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A的厚度可以形成的薄一些，节省工艺时间。
参考图10，去除临时衬底200。当临时衬底200上形成有隔离层时，可以通过腐蚀隔离层的方式，去除临时衬底200，若临时衬底200与外接电极层203’之间未形成隔离层，则可通过机械研磨等方式去除临时衬底200。
参考图11，图形化外接电极层形成外接电极203，本实施例中，外接电极203的边缘位于第一间隙211围成的区域上方。本实施例中，外接电极203的边缘也位于后续工艺中，形成的第二间隙围成的区域内。参考图2，在另一实施例中，形成外接电极203后，还可以刻蚀外接电极外周、第一间隙211上方的压电层202，使压电层202分为谐振部2021和位于所述谐振部2021外周的搭接部2022。谐振部2021的边缘全部或一部分暴露在空腔中。当谐振部2021的边缘全部暴露在空腔中时，第一间隙和后续工艺中形成的第二间隙相互连通。谐振部2021的边缘暴露在空腔中的作用参照前文结构实施例的相关描述。
参考图12，形成第二牺牲层材料，覆盖外接电极203、压电层202。图形化第二牺牲材料，形成第二牺牲层220，第二牺牲层220至少覆盖外接电极203。本实施例中，第二牺牲层220还覆盖在外接电极201外周的压电层202上。第二牺牲层220在后续工艺中释放后形成第二间隙。第二牺牲层材料和形成方法参考第一牺牲层材料和形成方法。形成完第二牺牲层220后，形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，覆盖第二牺牲层220及第二牺牲层外周的压电层202上。至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A的材料和形成方法参照第一介质层的材料和形成方法。形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A后，在外接电极203表面形成导电柱401。
继续参考图12，在外接电极表面形成导电柱401。具体为，形成第一通孔，贯穿第二牺牲层220和第二牺牲层220上方的至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，在第一通孔中形成导电材料，以形成导电柱401。可以通过刻蚀工艺或打孔工艺形成第一通孔。可以通过沉积或电镀的方法在第一通孔中形成导电材料，导电材料包括：金、银、钨、铂、铝、铜等低电阻率的材料。本实施例中，导电柱401形成在有效谐振区的边缘处，其位置、结构和作用参照前文关于结构实施例的相关描述。
参考图13，在第二牺牲层上方的至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A中形成释放孔，通过释放孔去除第二牺牲层。在外接电极203的表面和至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A之间形成第二间隙221。去除第二牺牲层后，形成第二引出部402，包括：形成第二钝化层102B；刻蚀所述第二钝化层102B形成凹槽；在所述凹槽中形成导电材料层，作为所述第二引出部402；或者，形成导电材料层，图形化所述导电材料层形成所述第二引出部402；形成第二钝化层102B，覆盖所述第二引出部402；所述至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层包括所述第二钝化层102B。先形成第二钝化层102B后形成第二引出部402时，第二钝化层102B和第二引出部402的表面齐平，之后可以在该齐平的表面上再形成介质层，方便后续承载衬底的键合；先形成第二引出部402后形成第二钝化层102B时，第二钝化层102B和第二引出部402的表面齐平或覆盖第二引出部402，如果齐平，在该齐平的表面上再形成介质层，方便后续承载衬底的键合。
所述第二引出部402延伸出所述第二空隙221所在的区域，本实施例中，第二引出部402为条形，从第二间隙221所在侧向外侧引出。在另一实施例中，第二引出部402为面状，应当理解，第二引出部402的作用为连接外部信号，起到电连接的作用，其形状、面积可根据情况灵活选择。
本实施例中，在有效谐振区外部，第一引出部403和第二引出部402在压电层202方向上的投影相互错开。
本发明中，也可以在形成第二引出部之后，形成释放孔去除第二牺牲层。
实施例 4 的变形例一：
实施例4中，在临时衬底上依次形成外接电极层、压电层、引出电极层；之后，图形化所述引出电极层，形成所述引出电极；形成第一结构后，键合承载衬底去除临时衬底后，图形化所述外接电极层形成外接电极；之后形成第二结构、导电柱、第二引出部。在刻蚀形成引出电极或外接电极时，压电层始终未被刻蚀，保留压电层的完整性，保持在有效区和无效区均分布有压电层，所述第一间隙和所述第二间隙通过所述压电层相互隔开，因此，第一牺牲层和第二牺牲层相互之间不连通，需要分别去除。
在变形例一中，可以在形成引出电极后，或形成外接电极后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。关于该种情形的优点请参照结构实施例中相应部分的阐述。
相应的，本变形例一中，形成第二牺牲层后，第一牺牲层依然存在，第二牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
实施例 4 的变形例二：
在该变形例二中，在临时衬底上依次形成压电层、引出电极层；图形化所述引出电极层，形成所述引出电极。之后，参考实施例4的方法，形成所述第一牺牲层、至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层，所述第一牺牲层覆盖所述引出电极的顶面和侧面；去除临时衬底、键合承载衬底，并翻转后，形成外接电极层，图形化所述外接电极层形成所述外接电极。然后，继续参考实施例4的方法，形成导电柱、第二引出部、第二牺牲层、至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层。
在该变形例二中，压电层可以保持在无效区和有效谐振区均分布有，此时，由于第一牺牲层和第二牺牲层相互隔开，第一牺牲层和第二牺牲层需要分别去除。
在该变形例二中，也可以是，在形成所述引出电极之后或者形成所述外接电极之后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。在该情形下，形成第二牺牲层后，第一牺牲层依然存在，第二牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
实施例 4 的变形例三
在变形例三中，并没有在临时衬底上依次形成外接电极层、压电层、引出电极层。该实施例中，在临时衬底上形成引出电极和平坦层，所述引出电极和所述平坦层表面齐平；之后，参考实施例4的方法，形成第一牺牲层、至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层。
然后，键合承载衬底、去除临时衬底，在承载衬底上的引出电极和平坦层的齐平表面上形成压电层。
接着，参考实施例4的方法，在所述压电层上形成外接电极层；图形化所述外接电极层形成外接电极；以及形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层、第二牺牲层、导电柱、第二引出部。
在该变形例三中，压电层可以压电层位于有效谐振区和无效区，此时第一牺牲层和第二牺牲层相互隔开，需要分别去除。
在该变形例三中，也可以在图形化所述外接电极层之前或者之后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。在该情形下，形成第二牺牲层后，第一牺牲层依然存在，第二牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
实施例 5
本发明实施例5提供了一种薄膜体声波谐振器的制造方法，图14至图19为本发明实施例5的一种薄膜体声波谐振器的制造方法中不同步骤对应的结构示意图，以下将参考图14至图19详细说明本实施例。
实施例4中，先在临时衬底上形成第一结构，本实施例中，先在临时衬底上形成第二结构。
参考图14和图15，提供临时衬底200，在临时衬底200上形成第二结构。具体为，先形成第二牺牲层220和至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，之后形成外接电极203，所述第二牺牲层仅覆盖所述外接电极203顶面（靠近临时衬底200的面）或覆盖所述外接电极顶面及侧面。其中，至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，覆盖所述第二牺牲层的侧面及外接电极的侧面或覆盖所述第二牺牲层的侧面、顶面及外接电极的侧面。
具体的形成外接电极的方法包括：参考图15，对第二牺牲层220进行刻蚀形成凹槽，在凹槽中填充导电材料作为外接电极，如果导电材料形成在凹槽外，需要去除凹槽外部的导电材料，可以通过化学机械研磨或刻蚀的方式去除。
形成外接电极的变形方式，也可以为：在第二牺牲层和至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层的表面形成外接电极层，之后图形化外接电极层形成外接电极。此时，外接电极位于第二牺牲层上而非嵌入在第二牺牲层。
其中，形成第二牺牲层220和至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A的方法可以参考实施例4。
参考图16，形成第一结构后，在所述临时衬底上形成压电层202。具体形成方法可以参考实施例4中形成压电层的相关内容。
继续参考图16，形成压电层202后，在所述临时衬底上形成第一结构。具体方法包括：形成引出电极层，对引出电极层进行图形化形成引出电极201。
参考图17，之后形成第一牺牲层210和至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A。实施例4中的相关内容可以援引于此。
本实施例中，至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A还覆盖第一牺牲层210的表面，形成第一结构后，还包括在至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A键合承载衬底100。
参考图18，键合承载衬底100后，翻转已形成的结构，去除所述临时衬底，依次形成所述导电柱401、所述第二引出部402。形成导电柱401、所述第二引出部402的方法参照实施例4。形成第二引出部402的过程中，也形成了第二钝化层102B。实施例4中的相关内容可以援引于此。
实施例4中去除第一牺牲层、第二牺牲层的方法可以援引于实施例5中。
实施例 5 的变形例一
实施例5中，压电层始终未被刻蚀，保留压电层的完整性，保持在有效区和无效区均分布有压电层，所述第一间隙和所述第二间隙通过所述压电层相互隔开，因此，第一牺牲层和第二牺牲层相互之间不连通，需要分别去除。
在变形例一中，可以在形成压电层后或形成引出电极后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。关于该种情形的优点请参照结构实施例中相应部分的阐述。
相应的，本变形例一中，形成第一牺牲层后，第二牺牲层依然存在，第一牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
实施例 5 的变形例二
在变形例二中，在临时衬底上形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A和第二牺牲层后，在临时衬底上形成外接电极和平坦层（外接电极不嵌入第二牺牲层中），所述外接电极和所述平坦层表面齐平；之后，参考实施例5的方法，形成压电层。之后的各个结构的形成步骤以及方法参考实施例5。
在该变形例二中，压电层可以位于有效谐振区和无效区，此时第一牺牲层和第二牺牲层相互隔开，需要分别去除。
在该变形例二中，也可以在图形化所述引出电极层之前或者之后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。在该情形下，形成第一牺牲层后，第二牺牲层依然存在，第一牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
实施例 6
本发明实施例6提供了一种薄膜体声波谐振器的制造方法，图20至图27为本发明实施例6的一种薄膜体声波谐振器的制造方法中不同步骤对应的结构示意图，以下将参考图20至图27详细说明本实施例。
参考图20，提供承载衬底100，在承载衬底100上形成第二引出部402，第二引出部402的材料参照实施例1，可以通过物理气相沉积的方法形成导电材料层，之后图形化导电材料层形成第二引出部402。实施例4中的相关内容可以援引于此。
参考图21和图22，形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A和第二牺牲层220。具体为：在第二引出部402的外周及上方形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，刻蚀至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，形成第二间隙221，使第二引出部402一端位于第二间隙221内，另一端位于第二间隙221外。
参考图22，在所述第二间隙中填充第二牺牲层220，第二牺牲层的材料和形成方法参照实施4，第二牺牲层210和至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A的上表面齐平。也可以先形成第二牺牲层，再形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层。实施例4中的相关内容可以援引于此。
继续参考图22，在第二牺牲层中形成导电柱401，导电柱401的下端连接于第二引出部402。实施例4中导电柱的结构、形状、位置的相关N内容可以援引于此。
参考图23，在所述第二牺牲层220、至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A上依次形成外接电极层，图形化外接电极层形成外接电极203，本实施例中外接电极203完全位于第二牺牲层围成的区域内。在外接电极外周的第二牺牲层上形成牺牲材料，新形成的牺牲材料的顶面和外接电极的顶面齐平。外接电极层的的材料和形成方法参照实施例4。
参考图24，在外接电极203及外接电极203的外周形成压电层202，在压电层202的上表面形成引出电极层201’，引出电极层201’和压电层202的材料和形成方法参照实施例4。
参考图25，刻蚀引出电极层形成引出电极201，本实施例中，引出电极201的一部分边缘位于第一牺牲层220围成的区域上方，另一部分边缘延伸出第二牺牲层220所在的区域。其中，延伸出第二牺牲层220所在区域的引出电极201构成第一引出部403。形成第一牺牲层210，第一牺牲层210遮盖除第一引出部403之外的引出电极201的表面以及与第一引出部403相对的引出电极外周的压电层的表面。第一牺牲层在后期工艺中释放后形成第一间隙，本实施例中，第一牺牲层和第二牺牲层几乎相对设置。
参考图26，在第一牺牲层210的外周形成至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A。
参考图27，去除第一牺牲层和第二牺牲层形成第一间隙211和第二间隙221。可以在外接电极外周的压电层中形成连通孔，使第一牺牲层和第二牺牲层连通，在第二牺牲层上方的第二介质层102上形成释放孔，通孔释放孔一次性去除第一牺牲层和第二牺牲层。在其他实施例中，也可以先去除第一牺牲层后去除第二牺牲层。
实施例 6 的变形例一
实施例6中，压电层始终未被刻蚀，保留压电层的完整性，保持在有效区和无效区均分布有压电层，所述第一间隙和所述第二间隙通过所述压电层相互隔开，因此，第一牺牲层和第二牺牲层相互之间不连通，需要分别去除。
在变形例一中，可以在形成压电层后或引出电极后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。关于该种情形的优点请参照结构实施例中相应部分的阐述。
相应的，本变形例一中，形成第一牺牲层后，第二牺牲层依然存在，第一牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
实施例 7
本发明实施例7提供了一种薄膜体声波谐振器的制造方法，图28至图33为本发明实施例7的一种薄膜体声波谐振器的制造方法中不同步骤对应的结构示意图，以下将参考图28至图33详细说明本实施例。
本实施例中，外接电极位于引出电极的下方，依次形成第二结构、导电柱、第二引出部和第一结构。
参考图28，提供临时衬底200，在所述临时衬底200上形成引出电极层201’、压电层202和外接电极层203’。实施例4的内容可以援引于此。
参考图29，形成外接电极层203’之后，对外接电极层203’进行图形化，形成外接电极203。形成第二牺牲层材料，覆盖外接电极203、压电层202。图形化第二牺牲材料，形成第二牺牲层220，本实施例中，第二牺牲层220覆盖外接电极203的表面及其外周。
参考图30，形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层102A，覆盖第二牺牲层220外周的压电层202。本实施例中，也覆盖第二牺牲层220的上表面。
参考图31，在外接电极表面形成导电柱401，去除第二牺牲层，形成第二间隙，在导电柱401的上方形成第二引出部402及第二钝化层102B。
参考图32，本实施例中，还包括在第二钝化层102B的表面形成承载衬底100。去除临时衬底，图形化引出电极层，形成引出电极201。
参考图33，形成第一牺牲层材料，覆盖引出电极201、压电层202。图形化第一牺牲材料，形成第一牺牲层，本实施例中，第一牺牲层覆盖一部分引出电极201及引出电极210外周的压电层，将一部分引出电极的边缘遮盖在内。引出电极未被第一牺牲层覆盖的部分构成第一引出部，用于与外部电信号连接。形成至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层101A，覆盖第一牺牲层及第一牺牲层外周的引出电极201和压电层202，再出去第一牺牲层。
本实施例中压电层始终未被刻蚀，保留压电层的完整性，保持在有效区和无效区均分布有压电层，所述第一间隙和所述第二间隙通过所述压电层相互隔开，因此，第一牺牲层和第二牺牲层相互之间不连通，需要分别去除。
在另一实施例中，可以在形成外接电极或引出电极后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。关于该种情形的优点请参照结构实施例中相应部分的阐述。
相应的，形成第一牺牲层后，第二牺牲层依然存在，第一牺牲层也填充在图形化后的压电层的周边，此时所述第一牺牲层、所述第二牺牲层相互连通，可以同时去除所述第一牺牲层、第二牺牲层。
需要说明的是，本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于结构实施例，所以描述的比较简单，相关之处参见结构实施例的部分说明即可。实施例5、实施例6和实施例7中部件结构、位置关系、形成方法等参照实施4中的相关描述。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (26)

  1. 一种薄膜体声波谐振器，其特征在于，包括：叠置的引出电极、压电层和外接电极，有效谐振区包括所述引出电极、压电层和外接电极在垂直于所述压电层表面方向上相互重叠的区域，所述有效谐振区的外部为无效区；第一介质层，所述第一介质层的表面与所述引出电极的表面之间设有第一间隙；所述引出电极从所述有效谐振区延伸出所述第一间隙的部分为第一引出部；第二介质层，所述第二介质层的表面与所述外接电极的表面之间设有第二间隙；所述外接电极位于所述第二间隙围成的区域内或者二者边界重合；导电柱，一端连接于所述外接电极，另一端连接有第二引出部，所述第二引出部从所述有效谐振区延伸出所述第二间隙；所述引出电极和所述外接电极其中之一位于另一上方。
  2. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述第一间隙且所述第二间隙在所述压电层方向上的投影的边界包围所述有效谐振区在所述压电层方向上的投影的边界。
  3. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述第一间隙和所述第二间隙相互连通，或者，所述第一间隙和所述第二间隙相互隔离。
  4. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述第一间隙和所述第二间隙通过分布于所述无效区的多个通孔连通；或者，所述第一间隙、第二间隙通过包围部分所述有效谐振区的非封闭的环形通孔连通。
  5. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述压电层从所述有效谐振区延伸出所述第一间隙且所述第二间隙外；或者，所述压电层位于有效谐振区，还包括与所述压电层同层的平坦层，所述平坦层位于所述压电层周围延伸至间隙外；或者，所述压电层仅位于所述有效谐振区。
  6. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述压电层包括谐振部和位于所述谐振部外周的搭接部，所述谐振部至少部分位于所述有效谐振区，所述搭接部位于所述有效谐振区外，所述谐振部与所述搭接部相接或分离。
  7. 根据权利要求6所述的薄膜体声波谐振器，其特征在于，所述搭接部和所述谐振部相接，所述压电层为完整的膜层。
  8. 根据权利要求6所述的薄膜体声波谐振器，其特征在于，所述搭接部和所述谐振部相互分离，所述第一空隙和所述第二空隙连通成空腔，所述谐振部的外周暴露在所述空腔中。
  9. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述导电柱设置于所述有效谐振区的边界处。
  10. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述导电柱设置在所述第二间隙的边界处或，所述导电柱与所述第二间隙的边界设有距离或，一部分所述导电柱设置在所述第二间隙边界处，另一部分所述导电柱与所述第二间隙的边界设有距离。
  11. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述导电柱在所述压电层方向上的投影为封闭或间断的环形。
  12. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述第二引出部埋设于所述第二介质层中。
  13. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，在所述有效谐振区外部，所述第二引出部和所述第一引出部在所述压电层方向上的投影相互错开。
  14. 根据权利要求1所述的薄膜体声波谐振器，其特征在于，所述导电柱或所述第二引出部的材料包括：金、银、钨、铂、铝或铜。
  15. 一种权利要求1、2、5、9-14任一项所述的薄膜体声波谐振器的制造方法，其特征在于，包括：形成第一结构，所述第一结构包括：引出电极、至少遮盖所述引出电极且避开所述第一引出部所在区域的第一牺牲层、至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层；形成压电层；形成第二结构，所述第二结构包括：外接电极、至少遮盖所述外接电极的第二牺牲层、至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层；形成导电柱，贯穿所述第二牺牲层、连接所述外接电极；形成第二引出部，一端连接所述导电柱，另一端延伸出所述有效谐振区；去除所述第一牺牲层、第二牺牲层，形成所述第一间隙、第二间隙。
  16. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，所述制造方法包括：提供临时衬底；在所述临时衬底上形成所述第一结构；在所述第一结构上键合承载衬底，去除所述临时衬底；在所述承载衬底上依次形成所述第二结构、所述导电柱、所述第二引出部。
  17. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，所述制造方法包括：提供临时衬底；在所述临时衬底上形成所述第二结构；形成压电层，覆盖所述第二结构；在所述压电层上形成所述第一结构；在所述第一结构上键合承载衬底，去除所述临时衬底，形成所述导电柱和所述第二引出部。
  18. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，所述制造方法包括：提供承载衬底；在所述承载衬底上形成所述第二引出部，之后形成所述导电柱和所述第二结构；形成压电层，覆盖所述第二结构；在所述第二结构上形成所述第一结构。
  19. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，所述制造方法包括：提供临时衬底；在所述临时衬底上依次形成所述第二结构、所述第二导电柱、所述第二引出部；在所述第二引出部所在侧键合承载衬底，去除所述临时衬底；在所述承载衬底上形成所述第一结构。
  20. 根据权利要求16-19任一项所述的薄膜体声波谐振器的制造方法，其特征在于，依次形成外接电极层、压电层、引出电极层；图形化所述引出电极层，形成所述引出电极；形成第一结构后，图形化所述外接电极层形成外接电极；保留压电层的完整性，所述第一间隙和所述第二间隙通过所述压电层相互隔开；或者，依次形成外接电极层、压电层、引出电极层；图形化所述引出电极层，形成所述引出电极；形成第一结构后，图形化所述外接电极层形成外接电极；在图形化所述引出电极之后或者图形化所述外接电极之后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙；或者，形成引出电极层、压电层、外接电极层；图形化所述引出电极层、压电层、外接电极层，去除位于无效区的引出电极层部分、压电层部分、外接电极层部分，以形成所述引出电极、外接电极、压电层；之后，形成所述第一牺牲层、第一介质层，所述第一牺牲层覆盖所述引出电极、外接电极、压电层的顶面和侧面；或者，形成引出电极层、压电层、外接电极层；图形化所述引出电极层，形成所述引出电极；之后，形成所述第一牺牲层、至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层，所述第一牺牲层覆盖所述引出电极、外接电极、压电层的顶面和侧面；在图形化所述引出电极之后或者图形化所述外接电极之后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙；或者，形成引出电极和平坦层，所述引出电极和所述平坦层表面齐平；在所述齐平的表面上形成压电层；在所述压电层上形成外接电极层；图形化所述外接电极层形成外接电极；在图形化所述外接电极层之前或者之后，图形化所述压电层，以去除无效区的压电层或者在有效谐振区的压电层周边形成空气边隙。
  21. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，形成所述第二结构的方法包括：形成外接电极层，对所述外接电极层进行图形化形成所述外接电极；形成第二牺牲层，所述第二牺牲层仅覆盖所述外接电极顶面或覆盖所述外接电极顶面及侧面；形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层，覆盖所述第二牺牲层的侧面及所述外接电极的侧面或覆盖所述第二牺牲层的侧面、顶面及外接电极的侧面；或者，形成外接电极层，对所述外接电极层进行图形化形成所述外接电极；形成至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层，覆盖所述外接电极及周边区域；刻蚀所述至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层形成第二空隙，在所述第二空隙中形成所述第二牺牲层。
  22. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，形成所述导电柱包括：图形化所述外接电极及第二引出部之间的膜层，形成通孔；在所述通孔内填充导电材料形成所述导电柱。
  23. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，形成第二引出部包括：形成第二钝化层；刻蚀所述第二钝化层形成凹槽；在所述凹槽中形成导电材料层，作为所述第二引出部；或者，形成导电材料层，图形化所述导电材料层形成所述第二引出部；形成第二钝化层，覆盖所述第二引出部；所述至少在所述第二牺牲层侧面包围所述第二牺牲层的介质层包括所述第二钝化层。
  24. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，形成所述第一结构包括：形成引出电极层，对所述引出电极层进行图形化形成所述引出电极；形成第一牺牲层，所述第一牺牲层至少覆盖所述引出电极且避开所述第一引出部的区域；形成至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层，覆盖所述第一牺牲层的侧面或覆盖所述第一牺牲层的侧面、顶面及引出电极的侧面；或者，形成引出电极层，对所述引出电极层进行图形化形成所述引出电极；
    形成至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层，覆盖所述引出电极及周边区域；刻蚀所述至少在所述第一牺牲层侧面包围所述第一牺牲层的介质层，在所述第一引出部以外的所述引出电极上方形成第一空隙，在所述第一空隙中形成所述第一牺牲层。
  25. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，所述第一牺牲层形成于所述第二牺牲层前，去除所述第一牺牲层、第二牺牲层包括:
    形成所述第二牺牲层前去除所述第一牺牲层或形成所述第二牺牲层后，去除所述第一牺牲层和所述第二牺牲层；或，所述第一牺牲层形成于所述第二牺牲层后，去除所述第一牺牲层、第二牺牲层包括:形成所述第一牺牲层前去除所述第二牺牲层或形成所述第一牺牲层后，去除所述第一牺牲层和所述第二牺牲层。
  26. 根据权利要求15所述的薄膜体声波谐振器的制造方法，其特征在于，所述第一牺牲层或所述第二牺牲层的材料包括：磷硅玻璃、低温二氧化硅、硼磷硅玻璃、锗、碳、聚酰亚胺或光阻剂。
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