WO2022012269A1 - 反熔丝存储单元状态检测电路及存储器 - Google Patents

反熔丝存储单元状态检测电路及存储器 Download PDF

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Publication number
WO2022012269A1
WO2022012269A1 PCT/CN2021/100976 CN2021100976W WO2022012269A1 WO 2022012269 A1 WO2022012269 A1 WO 2022012269A1 CN 2021100976 W CN2021100976 W CN 2021100976W WO 2022012269 A1 WO2022012269 A1 WO 2022012269A1
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Prior art keywords
memory cell
fuse memory
time point
detection circuit
state detection
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PCT/CN2021/100976
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English (en)
French (fr)
Inventor
季汝敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/446,289 priority Critical patent/US11854633B2/en
Publication of WO2022012269A1 publication Critical patent/WO2022012269A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components

Definitions

  • the present disclosure relates to the technical field of integrated circuits, exemplarily, to an anti-fuse memory cell state detection circuit and a memory using the circuit.
  • the storage state of the anti-fuse memory cell is often detected through a simple logic gate circuit.
  • FIG. 1 take the anti-fuse memory cell 11 whose word line is connected to the FsBlin3 signal as an example: if the anti-fuse memory cell is programmed during programming, the anti-fuse memory cell changes from a non-storage state to a storage state , the path resistance is reduced to a small value (tens of thousands of ohms to hundreds of thousands of ohms), then when the anti-fuse memory cell is selected, the path current flows through the equivalent resistance in the storage state, generating a relatively small amount on the node Node1.
  • the low voltage makes the logic gate 12 output signal D_out high; on the contrary, if the anti-fuse memory cell is not programmed during programming, the equivalent resistance of the anti-fuse memory cell in the path will be compared. If it is large (several megaohms to several hundreds of megaohms), then the voltage drop generated by the fixed circuit on this path will exceed the switching point of the logic gate 12, so that the output signal D_out of the logic gate 12 is at a low level.
  • the resistance of the anti-fuse memory cell in the non-storage state usually fluctuates in a wide range, and changes in process, voltage, temperature and other factors will also make the switching point of the logic gate circuit in a wide range. These factors may cause errors in the storage state detection of the anti-fuse memory cells, such as misjudging the programmed anti-fuse memory cells as unprogrammed anti-fuse memory cells, or The recorded anti-fuse memory cell is misjudged as the programmed anti-fuse memory cell, resulting in a decrease in yield.
  • the purpose of the present disclosure is to provide an anti-fuse memory cell state detection circuit and a memory using the same, which are used to at least to a certain extent overcome the storage state detection of anti-fuse memory cells due to the limitations and defects of the related art Inaccurate results.
  • an anti-fuse memory cell state detection circuit comprising: a first switch element, a first end connected to a power supply, a second end connected to a first node, and a control end connected to a controller;
  • a fuse memory cell array comprising a plurality of anti-fuse memory cell sub-arrays, the bit lines of the plurality of anti-fuse memory cell sub-arrays are all connected to the first node, the plurality of anti-fuse memory cell sub-arrays
  • the word lines of the array are all connected to the controller;
  • the first input terminal of the comparator is connected to the first node, and the second input terminal is connected to a reference voltage;
  • the anti-fuse memory cell sub-array includes a plurality of anti-fuse memory cells.
  • the controller detects the states of the plurality of anti-fuse storage units one by one by controlling the opening and closing of the first switching element.
  • FIG. 1 is a schematic diagram of an anti-fuse memory cell state detection circuit in the prior art.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a detection method of the controller CON applied to the circuit shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of an equivalent circuit of the circuit shown in FIG. 2 .
  • FIG. 5 is a schematic diagram of a manner in which a third time point is determined according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a first voltage change curve and a second voltage change curve.
  • FIG. 7 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in another embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of an anti-fuse memory cell in an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a detection method corresponding to the circuit shown in FIG. 10 .
  • FIG. 12 is a schematic diagram of a comparator in one embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • the anti-fuse memory cell state detection circuit 200 may include:
  • the first switching element M1 the first end is connected to the power supply VDD, the second end is connected to the first node N1, and the control end is connected to the controller CON;
  • the anti-fuse memory cell array 21 includes a plurality of anti-fuse memory cell sub-arrays, the bit lines of the plurality of anti-fuse memory cell sub-arrays are all connected to the first node N1, and the word lines of the plurality of anti-fuse memory cell sub-arrays are connected to the first node N1.
  • the lines are all connected to the controller CON;
  • the comparator 22 has a first input terminal connected to the first node N1, and a second input terminal connected to the reference voltage Vtrip.
  • the sub-array of anti-fuse memory cells includes a plurality of anti-fuse memory cells, and the controller CON controls the on and off of the first switching element M1 to detect the states of the plurality of anti-fuse memory cells one by one.
  • the controller CON controls the on and off of the first switching element M1 to detect the states of the plurality of anti-fuse memory cells one by one.
  • FIG. 9 shows three anti-fuse memory cell sub-arrays, corresponding to three bit lines, each The anti-fuse memory cell sub-array includes a plurality of anti-fuse cells 91, and each anti-fuse cell 91 includes a second switching element M2 and an anti-fuse element F.
  • the controller CON includes not only a control logic circuit for the second switching element M2 in the anti-fuse memory unit, but also a processing logic circuit for further processing of the output result of the comparator 22 .
  • the control logic circuit will make Xadd_00 to Xadd_nn valid one by one, so as to detect the states of the antifuse elements F_00 to F_nn one by one, and the processing logic circuit will use the states of F_00 to F_nn to perform operations such as redundant replacement. .
  • FIG. 3 is a flowchart of a detection method of the controller CON applied to the circuit shown in FIG. 2 .
  • the controller CON may be configured to perform a detection method 300, which may include:
  • Step S1 outputting a first control signal at a first time point to turn on the first switching element
  • Step S2 outputting a second control signal at a second time point to turn off the first switching element, and outputting a third control signal to turn on one of the plurality of anti-fuse memory cells;
  • Step S3 obtaining the output signal of the comparator at the third time point
  • the third time point is after the second time point, and the second time point is after the first time point.
  • the first switching element When the first switching element is a P-type transistor, the first control signal is at a low level, and the second control signal is at a high level; when the first switching element is an N-type transistor, the first control signal is at a high level, and the second control signal is at a high level. The second control signal is low level.
  • the first control signal and the second control signal may also be other types of signals, which are not particularly limited in the present disclosure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of the circuit shown in FIG. 2 .
  • the control method shown in FIG. 3 will be described below with reference to FIGS. 2 to 4 .
  • the state of the memory cell is detected by a precharge method and a comparator.
  • the voltage of the first node N1 can be detected by using the parasitic capacitance C1 existing at the first node N1.
  • the power supply VDD reaches the first node N1 through the first switching element M1. Affected by the parasitic capacitance C1, the voltage of the first node N1 is maintained at the power supply VDD , this process can be regarded as the precharge to the parasitic capacitance C1.
  • the first switching element is controlled to be turned off by the second control signal, and the word line corresponding to the anti-fuse memory cell to be tested is controlled to select the anti-fuse memory cell to be tested by the third control signal.
  • the voltage is discharged through the resistance of the anti-fuse memory cell to be tested, and the rate of discharge is inversely proportional to the resistance value of the resistance of the anti-fuse memory cell to be tested. That is, if the anti-fuse memory cell to be tested is in a breakdown state, the resistance is low and the discharge rate is high; if the anti-fuse memory cell under test is in a non-breakdown state, the resistance is high and the discharge rate is low.
  • the second control signal can be either before the third control signal or at the same time as the third control signal, so as to prevent the power supply VDD from continuing to connect to the first node through the first switching element M1 in the conductive state when the path is discharged. N1 charge.
  • the method of acquiring the output signal of the comparator 22 can be either reading the output signal of the comparator 22 at the third time point, or controlling the comparator 22 through the enable pin of the comparator 22 when the first switching element M1 is turned on In the disabled state, it is turned into the enabled state at the third time point, and the comparison result between the voltage of the first node N1 and the reference voltage Vtrip is output.
  • the storage state of the anti-fuse memory cell to be tested can be obtained.
  • Using a suitable reference voltage and a comparator for detection at a suitable time point can accurately control the inversion point of the comparator, and prevent the storage state detection error caused by the resistance shift or the logic gate's own inversion point shift. Therefore, in the embodiment of the present disclosure, the selection of the third time point and the setting of the voltage value of the reference voltage Vtrip are important means to achieve accurate detection.
  • FIG. 5 is a schematic diagram of a manner in which a third time point is determined according to an embodiment of the present disclosure.
  • the third time point may be determined according to the following manner:
  • Step S51 obtaining the maximum resistance after the anti-fuse memory cell is broken down and the minimum resistance that is not broken down;
  • Step S52 determining the first voltage change curve and the second voltage change curve of the first node according to the power supply, the maximum resistance and the minimum resistance;
  • Step S53 taking the time point when the difference between the first voltage change curve and the second voltage change curve is the largest as the third time point.
  • the difference between the second time point T2 and the first time point T1 is related to the capacitance of the parasitic capacitance C1 .
  • T2 and T1 is extremely small, it can be ignored, and T2 and T1 are considered equal.
  • the difference between the third time point T3 and the second time point T2 is related to the difference between the first voltage change curve and the second voltage change curve.
  • FIG. 6 is a schematic diagram of a first voltage change curve and a second voltage change curve.
  • R1 the minimum resistance of the anti-fuse memory cell not be broken down
  • R2 the maximum resistance after being broken down
  • R1 can be obtained by detecting the resistance of multiple anti-fuse memory cells when they are not broken down
  • R2 can be obtained. It is obtained by detecting the resistance of multiple anti-fuse memory cells after being broken down.
  • the above R1 and R2 are statistical results.
  • statistical analysis of R1 and R2 is performed to determine the specific values of R1 and R2.
  • the voltage V1(t) of the first node N1 as a function of time t decreases from VDD from the second time point T2 to the first voltage change curve as follows:
  • the second voltage variation curve of the voltage V2(t) of the first node N1 decreasing from the second time point T2 from the VDD as a function of time t is:
  • the time point T3 at which the difference ⁇ V(t) between the first voltage change curve and the second voltage change curve is the largest can be obtained.
  • R1, R2, VDD, and T2 are determined, the difference between T3 and T2 is determined.
  • the reference voltage Vtrip may also be determined according to the curve shown in FIG. 6 .
  • the first voltage value V1(T3) of the first voltage change curve V1(t) at the third time point T3 and the second voltage value V2(t) of the second voltage change curve V2(t) at the third time point T3 may be determined first. T3); then set the average value of the first voltage value V1 (T3) and the second voltage value V2 (T3) as the reference voltage Vtrip, that is:
  • FIG. 7 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in another embodiment of the present disclosure.
  • an additional capacitor C2 may be added to the first node N1 . That is, the detection circuit 200 may further include:
  • the detection capacitor C2 the first end of the detection capacitor C2 is connected to the first node N1, and the second end is grounded.
  • the function of the detection capacitor C2 is the same as that of the parasitic capacitor C1, both for detecting the voltage of the first node N1.
  • the capacitance value of the detection capacitor C2 is quite different from the capacitance value of the parasitic capacitance C1
  • the equivalent capacitance connected to the first node N1 can be regarded as the detection capacitance C2.
  • the C1 involved in the formulas (1) to (5) Can be replaced with C2.
  • FIG. 8 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the detection circuit 200 may further include:
  • a flip-flop 23 the input terminal of the flip-flop 23 is connected to the output terminal of the comparator 22, and the first output terminal and the second output terminal of the flip-flop 23 are both connected to the controller CON.
  • the flip-flop 23 can be, for example, a D flip-flop, which is used to latch the output signal of the comparator 22 so as to facilitate reading by the controller CON.
  • Those skilled in the art can set the model of the trigger 23 by themselves, and the present disclosure is not limited thereto.
  • the setting of the detection capacitor C2 or the trigger 23 does not affect the implementation of the control method shown in FIG. 3 , and does not affect the selection logic of the third time point and the reference voltage.
  • FIG. 9 is a schematic diagram of an anti-fuse memory cell in an embodiment of the present disclosure.
  • the anti-fuse memory unit 91 may include:
  • the second switching element M2, the first end of the second switching element M2 is used as the bit line of the anti-fuse memory unit 91;
  • an anti-fuse element F the first end of the anti-fuse element F is connected to the second end of the second switching element M2;
  • the control end of the second switching element M2 and the control end of the anti-fuse element F are both connected to the controller.
  • FIG. 10 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the first node N1 may be used to connect a plurality of bit lines
  • the anti-fuse memory cell array 21 may include:
  • a plurality of anti-fuse memory cell sub-arrays 21m (m is a bit line serial number), each anti-fuse memory cell sub-array 21m corresponds to a bit line BLm, and each anti-fuse memory cell sub-array 21m includes a plurality of anti-fuses storage unit;
  • a plurality of third switching elements M3m corresponding to the anti-fuse memory cell sub-array 21m the first end of each third switching element M3m is connected to the bit line BLm of the corresponding anti-fuse memory cell sub-array 21m, and each th
  • the second terminal of the three switching elements M3m is connected to the first node N1
  • the control terminal of each third switching element M3m is connected to the controller CON
  • the default state of the third switching element M3m is an off state.
  • each anti-fuse memory cell sub-array 21m may include, for example, 16 anti-fuse memory cells connected to one bit line, that is, a column of anti-fuse memory cells.
  • one bit line corresponds to one first switching element M1 and one comparator 22 .
  • FIG. 11 is a flowchart of a detection method corresponding to the circuit shown in FIG. 10 .
  • controller CON can be set up to perform the following methods:
  • Step S1 outputting a first control signal at a first time point to turn on the first switching element
  • Step S2 outputting a second control signal at a second time point to turn off the first switching element, and outputting a third control signal to turn on one of the plurality of anti-fuse memory cells;
  • Step S111 at a fourth time point, send a fourth control signal to the third switch element corresponding to the anti-fuse memory cell that is turned on to turn on the third switch element;
  • Step S3 obtaining the output signal of the comparator at the third time point
  • the fourth time point is after the first time point and before the third time point.
  • the method shown in FIG. 3 may include step S111, and the order of step S111 and step S2 may be interchanged, or may be performed simultaneously.
  • the fourth time point may be before the second time point, or after the second time point, and may also be equal to the second time point, as long as the fourth time point and the second time point are both
  • the discharge path can be opened after the voltage configuration of the first node N1 is completed at the first time point and before the voltage of the first node N1 is detected at the third time point.
  • the fourth control signal When the third switching element is a P-type transistor, the fourth control signal is at a low level; when the third switching element is an N-type transistor, the fourth control signal is at a high level.
  • the fourth control signal may also be other types of signals, which is not particularly limited in the present disclosure.
  • FIG. 12 is a schematic diagram of the comparator 22 in one embodiment of the present disclosure.
  • a differential amplifier may be used to implement the function of comparator 22, in which a self-biasing circuit is employed.
  • the differential amplifier uses a simple two-stage comparator to accurately control the flip point, with self-biasing circuitry to avoid excessive bias current traces.
  • the first switching element and the anti-fuse memory cell array are connected by using the parasitic capacitance or the detection capacitance at the first time point
  • the first node is precharged at the second time point, and the resistance of the anti-fuse memory cell to be tested is used to discharge the first node at the second time point, and the voltage of the first node is detected at the third time point.
  • the voltage of the node is compared with the reference voltage, which can precisely control the output switching point of the comparator.
  • a memory including the anti-fuse memory cell state detection circuit according to any one of the above.
  • the memory may be DRAM memory.
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • This embodiment of the present disclosure obtains the resistance value of the anti-fuse memory cell currently to be tested in the anti-fuse memory cell array by detecting the voltage of the connection point between the first switching element and the anti-fuse memory cell array, and comparing it with the reference voltage, which can make the use of
  • the voltage inversion point for detecting the storage state of the anti-fuse memory cell is precisely controlled, so as to avoid the storage state of the anti-fuse memory cell caused by the resistance shift of the anti-fuse memory cell and the inversion voltage shift of the logic gate in the related art misjudgment.

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Abstract

提供一种反熔丝存储单元状态检测电路及应用该电路的存储器，包括：第一开关元件，第一端连接于电源，第二端连接于第一节点，控制端连接于控制器；反熔丝存储单元阵列，包括多个反熔丝存储单元子阵列，多个反熔丝存储单元子阵列的位线均连接于第一节点，多个反熔丝存储单元子阵列的字线均连接于控制器；比较器，第一输入端连接于第一节点，第二输入端连接参考电压；其中，反熔丝存储单元子阵列包括多个反熔丝存储单元，控制器通过控制第一开关元件的打开和关断以逐一检测多个反熔丝存储单元的状态。可以提高反熔丝存储单元存储状态检测的准确度。

Description

反熔丝存储单元状态检测电路及存储器
交叉引用
本公开要求于2020年07月16日提交的申请号为202010687642.9、名称为“反熔丝存储单元状态检测电路及存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，示例性而言，涉及一种反熔丝存储单元状态检测电路及应用该电路的存储器。
背景技术
现有技术往往通过简单的逻辑门电路对反熔丝存储单元的存储状态进行检测。参见图1，以字线连接FsBlin3信号的反熔丝存储单元11为例：如果在编程的时候对该反熔丝存储单元进行烧录，该反熔丝存储单元由未存储状态转变为存储状态，通路电阻降低到较小值(几十千欧姆到几百千欧姆)，则当该反熔丝存储单元被选中时，通路电流流经存储状态下的等效电阻，在节点Node1上产生较低的电压，使逻辑门12输出信号D_out为高电平；反之，如果在编程的时候没有对该反熔丝存储单元进行烧录，该反熔丝存储单元在通路中的等效电阻会比较大(几兆欧姆到几百兆欧姆)，那么固定电路在该通路上产生的压降将超过逻辑门12的翻转点，使得逻辑门12的输出信号D_out为低电平。
在实际生产中，反熔丝存储单元在未存储状态下的电阻通常会在一个较宽的范围内波动，工艺、电压、温度等因素发生变化也会使得逻辑门电路的翻转点在较宽的范围内变化，这些因素都可能会导致对反熔丝存储单元的存储状态检测发生错误，例如将烧录过的反熔丝存储单元误判为未烧录反熔丝存储单元，或者将未烧录反熔丝存储单元误判为已烧录反熔丝存储单元，造成良率下降。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种反熔丝存储单元状态检测电路及应用该电路的存储器，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的反熔丝存储单元的存储状态检测结果不准确的问题。
根据本公开的一个方面，提供一种反熔丝存储单元状态检测电路，包括：第一开关元件，第一端连接于电源，第二端连接于第一节点，控制端连接于控制器；反熔丝存储单元阵列，包括多个反熔丝存储单元子阵列，所述多个反熔丝存储单元子阵列的位线均连接于 所述第一节点，所述多个反熔丝存储单元子阵列的字线均连接于所述控制器；比较器，第一输入端连接于所述第一节点，第二输入端连接参考电压；其中，所述反熔丝存储单元子阵列包括多个反熔丝存储单元，所述控制器通过控制所述第一开关元件的打开和关断以逐一检测所述多个反熔丝存储单元的状态。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中反熔丝存储单元状态检测电路的示意图。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
图3是应用于图2所示电路的控制器CON的检测方法的流程图。
图4是图2所示电路的等效电路示意图。
图5是本公开实施例确定第三时间点的方式的示意图。
图6是第一电压变化曲线和第二电压变化曲线的示意图。
图7是本公开另一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图8是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图9本公开实施例中反熔丝存储单元的示意图。
图10是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图11是图10所示电路对应的检测方法的流程图。
图12是本公开一个实施例中比较器的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分， 因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图2，反熔丝存储单元状态检测电路200可以包括：
第一开关元件M1，第一端连接于电源VDD，第二端连接于第一节点N1，控制端连接于控制器CON；
反熔丝存储单元阵列21，包括多个反熔丝存储单元子阵列，多个反熔丝存储单元子阵列的位线均连接于第一节点N1，多个反熔丝存储单元子阵列的字线均连接于控制器CON；
比较器22，第一输入端连接于第一节点N1，第二输入端连接参考电压Vtrip。
其中，所述反熔丝存储单元子阵列包括多个反熔丝存储单元，控制器CON通过控制第一开关元件M1的打开和关断以逐一检测多个反熔丝存储单元的状态。图2所示的反熔丝存储单元阵列21和反熔丝存储单元子阵列的结构请参见图9，图9中示意出3个反熔丝存储单元子阵列，对应3条位线，每个反熔丝存储单元子阵列包括多个反熔丝单元91，每个反熔丝单元91包括一个第二开关元件M2和一个反熔丝元件F。
控制器CON不仅包括对反熔丝存储单元中第二开关元件M2的控制逻辑电路，也包括对比较器22输出结果的进一步处理的处理逻辑电路。例如，在图9中，控制逻辑电路会使得Xadd_00到Xadd_nn逐一有效，从而逐一检测反熔丝元件F_00到F_nn的状态，而处理逻辑电路则会利用F_00到F_nn的状态去做冗余替换等操作。
图3是应用于图2所示电路的控制器CON的检测方法的流程图。
参考图3，控制器CON可以设置为执行检测方法300，检测方法300可以包括：
步骤S1，在第一时间点输出第一控制信号以打开第一开关元件；
步骤S2，在第二时间点输出第二控制信号以关断第一开关元件，并输出第三控制信号以打开多个反熔丝存储单元的一个；
步骤S3，在第三时间点获取比较器的输出信号；
其中，第三时间点在第二时间点之后，第二时间点在第一时间点之后。
当第一开关元件为P型晶体管时，第一控制信号为低电平，第二控制信号为高电平；当第一开关元件为N型晶体管时，第一控制信号为高电平，第二控制信号为低电平。当第一开关元件为其他类型的元件时，第一控制信号和第二控制信号也可以为其他类型的信号，本公开对此不作特殊限制。
图4是图2所示电路的等效电路示意图。下面将结合图2～图4对图3所述控制方法进行说明。
参考图4，在本公开实施例中，通过预充电方式并采用比较器对存储单元的状态进行检测。
在一个实施例中，可以利用第一节点N1存在的寄生电容C1来检测第一节点N1的电压。
在第一时间点通过第一控制信号控制第一开关元件导通后，电源VDD通过第一开关元件M1到达第一节点N1，受寄生电容C1的影响，第一节点N1的电压维持在电源VDD，此过程可以看作是对寄生电容C1的预充电。
在第二时间点通过第二控制信号控制第一开关元件关断、通过第三控制信号控制待测反熔丝存储单元对应的字线选中待测反熔丝存储单元后，第一节点N1的电压通过待测反熔丝存储单元的电阻进行放电，放电的速率与待测反熔丝存储单元的电阻的阻值成反比。即，如果待测反熔丝存储单元处于被击穿状态，电阻较低，放电速率较大；如果测反熔丝存储单元处于未被击穿状态，电阻较高，放电速率较小。
可以理解的是，第二控制信号既可以在第三控制信号之前，也可以与第三控制信号同时，以防止在通路放电时电源VDD通过导通状态的第一开关元件M1继续对第一节点N1充电。
获取比较器22的输出信号的方法既可以为在第三时间点读取比较器22的输出信号，也可以为通过比较器22的使能引脚控制比较器22在第一开关元件M1打开时处于未使能状态，在第三时间点转变为使能状态，输出第一节点N1的电压和参考电压Vtrip的比较结果。
使用比较器22和参考电压Vtrip在第三时间点对第一节点N1的电压进行检测，即可得到待测反熔丝存储单元的存储状态。在合适的时间点采用合适的参考电压和比较器进行检测，可以使比较器的翻转点得到精确控制，防止电阻偏移或者逻辑门自身翻转点偏移导致的存储状态检测错误。因此，本公开实施例中，对第三时间点的选择和对参考电压Vtrip的电压值的设置是实现精确检测的重要手段。
图5是本公开实施例确定第三时间点的方式的示意图。
参考图5，在本公开的一种示例性实施例中，第三时间点可以根据以下方式确定：
步骤S51，获取反熔丝存储单元被击穿后的最大电阻和未被击穿的最小电阻；
步骤S52，根据电源、最大电阻和最小电阻确定第一节点的第一电压变化曲线和第二电压变化曲线；
步骤S53，将第一电压变化曲线与第二电压变化曲线的差值最大的时间点作为第三时间点。
在本公开实施例中，第二时间点T2与第一时间点T1的差值与寄生电容C1的容值相关。寄生电容C1的容值越大，第一节点N1的电压达到VDD的时间越长，T2与T1的差值越大；寄生电容C1的容值越小，第一节点N1的电压达到VDD的时间越短，T2与T1的差值越小。当T2与T1的差值极小时，可以忽略不计，认为T2与T1相等。
第三时间点T3与第二时间点T2的差值与第一电压变化曲线和第二电压变化曲线的差值相关。
图6是第一电压变化曲线和第二电压变化曲线的示意图。
设反熔丝存储单元未被击穿的最小电阻为R1，在被击穿后的最大电阻为R2，R1可以通过检测多个反熔丝存储单元未被击穿时的电阻得出，R2可以通过检测多个反熔丝存储单元被击穿后的电阻得出。上述R1和R2都是统计结果，当反熔丝存储单元在研发和生产过程中，会对R1和R2进行统计分析，以此确定R1和R2的具体值。
参考图6，在通路电阻包括R1时，随时间t的变化第一节点N1的电压V1(t)从第二时间点T2开始由VDD下降的第一电压变化曲线为：
Figure PCTCN2021100976-appb-000001
在通路电阻包括R2时，随时间t的变化第一节点N1的电压V2(t)从第二时间点T2开始由VDD下降的第二电压变化曲线为：
Figure PCTCN2021100976-appb-000002
则第一电压变化曲线和第二电压变化曲线的差值为：
Figure PCTCN2021100976-appb-000003
由图6可知，ΔV(t)随着时间t的变化先变大后变小。为了确定ΔV(t)的最大值，令：
Figure PCTCN2021100976-appb-000004
即可得到第一电压变化曲线和第二电压变化曲线的差值ΔV(t)最大的时间点T3。从图6可以看出，在R1、R2、VDD、T2确定的情况下，T3与T2的差值确定。
在本公开的一种示例性实施例中，还可以根据图6所示曲线确定参考电压Vtrip。可以首先确定第一电压变化曲线V1(t)在第三时间点T3的第一电压值V1(T3)和第二电压变化曲线V2(t)在第三时间点T3的第二电压值V2(T3)；然后将第一电压值V1(T3)和第二电压值V2(T3)的平均值设置为参考电压Vtrip，即：
Figure PCTCN2021100976-appb-000005
通过以上方式确定检测比较器输出信号的第三时间点T3和用于控制比较器翻转点的参考电压Vtrip，可以在检测比较器输出信号时获得更加准确的检测结果，有效提高检测精度。
图7是本公开另一个实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图7，为了减小第一节点N1的寄生电容偏差造成的放电曲线随机偏差，可以对第一节点N1添加一个额外的电容C2。即，检测电路200还可以包括：
检测电容C2，检测电容C2的第一端连接于第一节点N1，第二端接地。
检测电容C2的作用与寄生电容C1相同，均是为了检测第一节点N1的电压。在检测电容C2的容值与寄生电容C1的容值相差较大时，可以将第一节点N1连接的等效电容看作是检测电容C2，此时公式(1)～(5)涉及的C1可以替换为C2。
图8是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图8，在本公开的其他实施例中，检测电路200还可以包括：
触发器23，触发器23的输入端连接于比较器22的输出端，触发器23的第一输出端和第二输出端均连接于控制器CON。
触发器23例如可以为D触发器，用于对比较器22的输出信号进行锁存，以方便控制器CON读取。本领域技术人员可以自行设置触发器23的型号，本公开不以此为限。
可以理解的是，检测电容C2或触发器23的设置不影响图3所示控制方法的实施，不影响第三时间点和参考电压的选取逻辑。
图9本公开实施例中反熔丝存储单元的示意图。
参考图9，反熔丝存储单元91可以包括：
第二开关元件M2，第二开关元件M2的第一端作为反熔丝存储单元91的位线；
反熔丝元件F，反熔丝元件F的第一端连接于第二开关元件M2的第二端；
其中，第二开关元件M2的控制端和反熔丝元件F的控制端均连接于控制器。
图10是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图10，在一个实施例中，第一节点N1可以用于连接多个位线，反熔丝存储单元阵列21可以包括：
多个反熔丝存储单元子阵列21m(m为位线序号)，每个反熔丝存储单元子阵列21m对应一条位线BLm，每个反熔丝存储单元子阵列21m包括多个反熔丝存储单元；
与反熔丝存储单元子阵列21m对应的多个第三开关元件M3m，每个第三开关元件M3m的第一端连接于对应的反熔丝存储单元子阵列21m的位线BLm，每个第三开关元件M3m的第二端连接于第一节点N1，每个第三开关元件M3m的控制端连接于控制器CON，第三开关元件M3m的默认状态为关断状态。
其中，每个反熔丝存储单元子阵列21m，例如可以包括连接在一条位线上的16个反熔丝存储单元，即一列反熔丝存储单元。在一些实施例中，一条位线对应一个第一开关元件M1和一个比较器22。
通过在第一节点连接多个反熔丝存储单元子阵列21m，可以实现对多个反熔丝存储单元子阵列21m中的反熔丝存储单元的存储状态的检测，示例性方式如图11所示。
图11是图10所示电路对应的检测方法的流程图。
参考图10所示电路，控制器CON可以设置为执行以下方法：
步骤S1，在第一时间点输出第一控制信号以打开第一开关元件；
步骤S2，在第二时间点输出第二控制信号以关断第一开关元件，并输出第三控制信号以打开多个反熔丝存储单元的一个；
步骤S111，在第四时间点对被对打开的反熔丝存储单元对应的第三开关元件发送第四控制信号以打开该第三开关元件；
步骤S3，在第三时间点获取比较器的输出信号；
其中，第四时间点在第一时间点之后，在第三时间点之前。
即，图3所示方法可以包括步骤S111，步骤S111和步骤S2的顺序可以互换，也可以为同时执行。
在图11所示实施例中，第四时间点可以在第二时间点之前，也可以在第二时间点之后，还可以与第二时间点相等，只要第四时间点和第二时间点均在第一时间点和第三时间点之间即可，以在第一时间点完成对第一节点N1的电压配置之后、在第三时间点开始检测第一节点N1的电压之前开启放电通路。
当第三开关元件为P型晶体管时，第四控制信号为低电平；当第三开关元件为N型晶体管时，第四控制信号为高电平。当第三开关元件为其他类型的元件时，第四控制信号也可以为其他类型的信号，本公开对此不作特殊限制。
图12是本公开一个实施例中比较器22的示意图。
参考图12，在一个实施例中，可以使用差分放大器实现比较器22的功能，在比较器22中采用自偏置电路。差分放大器采用简单的两级比较器，可以准确控制翻转点，通过自偏置电路以避免过多的偏置电流走线。
本公开实施例提供的反熔丝存储单元状态检测电路和反熔丝存储单元状态检测方法，通过在第一时间点利用寄生电容或检测电容对第一开关元件和反熔丝存储单元阵列的连接点(第一节点)进行预充电，在第二时间点利用待测反熔丝存储单元的电阻对第一节点进行放电，在第三时间点检测第一节点的电压，使用比较器将第一节点的电压与参考电压进行比较，可以精确控制比较器的输出翻转点。通过确定反熔丝存储单元未被击穿时的最小电阻R1和被击穿后的最大电阻R2，进而确定第一节点电压在R1和R2下的电压变化曲线的差值最大的时间点，可以确定状态检测最准确的第三时间点，通过使用第三时间点对应的两条电压变化曲线的值的平均值作为参考电压，可以使比较器的输出更为准确，避免相关技术中由于反熔丝存储单元的电阻偏移和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。
根据本公开的一个方面，提供一种存储器，包括如上述任意一项所述的反熔丝存储单元状态检测电路。例如，该存储器可以是DRAM存储器。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者 适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过检测第一开关元件和反熔丝存储单元阵列连接点的电压，与参考电压比较得出反熔丝存储单元阵列中当前待测反熔丝存储单元的电阻值，可以使得用于检测反熔丝存储单元的存储状态的电压翻转点得到精确控制，避免相关技术中由于反熔丝存储单元的电阻偏移和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。

Claims (10)

  1. 一种反熔丝存储单元状态检测电路，包括：
    第一开关元件，第一端连接于电源，第二端连接于第一节点，控制端连接于控制器；
    反熔丝存储单元阵列，包括多个反熔丝存储单元子阵列，所述多个反熔丝存储单元子阵列的位线均连接于所述第一节点，所述多个反熔丝存储单元子阵列的字线均连接于所述控制器；
    比较器，第一输入端连接于所述第一节点，第二输入端连接参考电压；
    其中，所述反熔丝存储单元子阵列包括多个反熔丝存储单元，所述控制器通过控制所述第一开关元件的打开和关断以逐一检测所述多个反熔丝存储单元的状态。
  2. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述控制器设置为：
    在第一时间点输出第一控制信号以打开所述第一开关元件；
    在第二时间点输出第二控制信号以关断所述第一开关元件，并输出第三控制信号以打开所述多个反熔丝存储单元的一个；
    在第三时间点获取所述比较器的输出信号；
    其中，所述第三时间点在所述第二时间点之后，所述第二时间点在所述第一时间点之后。
  3. 如权利要求2所述的反熔丝存储单元状态检测电路，其中，所述第三时间点根据以下方式确定：
    获取所述反熔丝存储单元被击穿后的最大电阻和未被击穿的最小电阻；
    根据所述电源、所述最大电阻和所述最小电阻确定所述第一节点的第一电压变化曲线和第二电压变化曲线；
    将所述第一电压变化曲线与所述第二电压变化曲线的差值最大的时间点作为所述第三时间点。
  4. 如权利要求3所述的反熔丝存储单元状态检测电路，其中，所述参考电压根据以下方式确定：
    确定所述第一电压变化曲线在所述第三时间点的第一电压值和第二电压变化曲线在所述第三时间点的第二电压值；
    将所述第一电压值和所述第二电压值的平均值设置为所述参考电压。
  5. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：检测电容，所述检测电容的第一端连接于所述第一节点，第二端接地。
  6. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：触发器，所述触发器的输入端连接于所述比较器的输出端，所述触发器的第一输出端和第二输出端均连接于所述控制器。
  7. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述反熔丝存储单元包 括：
    第二开关元件，所述第二开关元件的第一端连接所述反熔丝存储单元的位线；
    反熔丝元件，所述反熔丝元件的第一端连接于所述第二开关元件的第二端；
    所述第二开关元件的控制端和所述反熔丝元件的控制端均连接于所述控制器。
  8. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述比较器在所述第一开关元件打开时处于未使能状态。
  9. 如权利要求8所述的反熔丝存储单元状态检测电路，其中，所述比较器采用自偏置电路。
  10. 一种存储器，包括如权利要求1～9任一项所述的反熔丝存储单元状态检测电路。
PCT/CN2021/100976 2020-07-16 2021-06-18 反熔丝存储单元状态检测电路及存储器 Ceased WO2022012269A1 (zh)

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