WO2022012236A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2022012236A1
WO2022012236A1 PCT/CN2021/099459 CN2021099459W WO2022012236A1 WO 2022012236 A1 WO2022012236 A1 WO 2022012236A1 CN 2021099459 W CN2021099459 W CN 2021099459W WO 2022012236 A1 WO2022012236 A1 WO 2022012236A1
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Prior art keywords
light
emitting unit
circuit
segment
emitting
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Ceased
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PCT/CN2021/099459
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English (en)
French (fr)
Inventor
张文强
晏荣建
陈文斌
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US17/767,061 priority Critical patent/US11790846B2/en
Publication of WO2022012236A1 publication Critical patent/WO2022012236A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0653—Controlling or limiting the speed of brightness adjustment of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display panel, a method for driving the same, and a display device.
  • OLED Organic Light Emitting Diode
  • OLED is an active light-emitting display device, which has the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, high response speed, etc., and has been widely used in mobile phones, tablet computers, digital cameras, etc. Display products.
  • the OLED display is current driven, and it is necessary to output current to the OLED through the pixel circuit to drive the OLED to emit light.
  • An embodiment of the present disclosure provides a method for driving a display panel
  • the display panel includes a plurality of regularly arranged pixel units, at least one of the plurality of pixel units includes a first light emitting unit that emits light of a first color, a second light-emitting unit that emits light of a second color and a third light-emitting unit that emits light of a third color
  • each light-emitting unit includes a pixel circuit and a light-emitting device electrically connected to the pixel circuit
  • the pixel circuit includes: a driving sub-circuit, a light-emitting control sub-circuit and a data writing sub-circuit, the driving sub-circuit is electrically connected to the light-emitting control sub-circuit and the data writing sub-circuit, respectively, the data writing sub-circuit is configured to transmit a data voltage
  • the light-emitting control sub-circuit is The sub-circuit is configured to control the conduction period of the driving sub-circuit, and
  • the duty cycle corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment is smaller than a preset reference duty cycle; a plurality of transistors in the pixel circuit All are P-type transistors.
  • the data writing sub-circuit transmits data to the pixel circuit of the first light-emitting unit The voltage is lower than the first reference voltage, the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the second light-emitting unit is lower than the second reference voltage, and the data writing sub-circuit transmits the data to the pixel of the third light-emitting unit.
  • the data voltage transmitted by the circuit is smaller than the third reference voltage, and the first reference voltage, the second reference voltage and the third reference voltage are respectively corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment
  • the duty cycle of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit is the data voltage transmitted by the data writing sub-circuit to the pixel circuits of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit when the duty cycle is a preset reference duty cycle.
  • the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the first light-emitting unit is between 5/1000 and 15/1000 of the first reference voltage
  • the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the second light-emitting unit is between 10/1000 and 20/1000 of the second reference voltage
  • the data voltage transmitted by the pixel circuit of the third light-emitting unit is between 6/1000 and 16/1000 of the third reference voltage.
  • the duty cycle corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment is smaller than a preset reference duty cycle; a plurality of transistors in the pixel circuit All are N-type transistors.
  • the data writing sub-circuit transmits data to the pixel circuit of the first light-emitting unit The voltage is greater than the first reference voltage, the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the second light-emitting unit is greater than the second reference voltage, and the data writing sub-circuit transmits the data to the pixel of the third light-emitting unit.
  • the data voltage transmitted by the circuit is greater than the third reference voltage, and the first reference voltage, the second reference voltage and the third reference voltage are respectively corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment
  • the duty cycle of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit is the data voltage transmitted by the data writing sub-circuit to the pixel circuits of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit when the duty cycle is a preset reference duty cycle.
  • the duty ratio corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment is a preset reference duty cycle, and in the (NM)th luminance segment to the Nth luminance segment
  • the data voltages transmitted by the data writing sub-circuit to the pixel circuits of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are respectively the first reference voltage, a second reference voltage and a third reference voltage
  • the plurality of transistors in the pixel circuit are all P-type transistors, after determining the input data voltage corresponding to the at least one light-emitting unit, the method further includes: when the determined brightness When the segment is in the (NM)th luminance segment to the Nth luminance segment, the duty cycle corresponding to the determined luminance segment is reduced, the input data voltage corresponding to at least one light-emitting unit is reduced, and the reduced duty cycle is adopted.
  • the duty ratio corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment is a preset reference duty cycle, and in the (NM)th luminance segment to the Nth luminance segment
  • the data voltages transmitted by the data writing sub-circuit to the pixel circuits of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are respectively the first reference voltage, the second reference voltage and the third reference voltage
  • the plurality of transistors in the pixel circuit are all N-type transistors, after determining the input data voltage corresponding to at least one light-emitting unit, the method further includes: when the determined brightness When the segment is in the (NM)th luminance segment to the Nth luminance segment, the duty cycle corresponding to the determined luminance segment is reduced, the input data voltage corresponding to at least one light-emitting unit is increased, and the reduced duty cycle is adopted.
  • N 9 and M is 1 or 0.
  • the duty cycle corresponding to each of the (N-M)th luminance segment to the Nth luminance segment is between 1% and 4%.
  • the first light-emitting unit is a red light-emitting unit
  • the second light-emitting unit is a green light-emitting unit
  • the third light-emitting unit is a blue light-emitting unit.
  • the pixel circuit includes: a first transistor, the control electrode of which is connected to the second scan signal line, the first electrode of which is connected to the first initial signal line, and the second electrode of which is connected to the second node ; the second transistor, its control electrode is connected with the first scanning signal line, its first electrode is connected with the second node, and its second electrode is connected with the third node; the third transistor, its control electrode is connected with the second node, its The first pole is connected to the first node, and the second pole is connected to the third node; the control pole of the fourth transistor is connected to the first scan signal line, the first pole is connected to the data signal line, and the second pole is connected to the first scan signal line.
  • a node is connected; the control electrode of the fifth transistor is connected to the light-emitting signal line, the first electrode is connected to the second power supply line, and the second electrode is connected to the first node; the control electrode of the sixth transistor is connected to the light-emitting signal line , its first pole is connected to the third node, its second pole is connected to the first pole of the light-emitting device; the seventh transistor, its control pole is connected to the first scan signal line, and its first pole is connected to the second initial signal line , its second pole is connected with the first pole of the light-emitting device, and the second pole of the light-emitting device is connected with the first power line; the storage capacitor, its first end is connected with the second power line, and its second end is connected with the second node .
  • Embodiments of the present disclosure also provide a display panel, which is driven by the above-mentioned driving method for a display panel.
  • Embodiments of the present disclosure also provide a display device including the aforementioned display panel.
  • FIG. 1 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure
  • FIG. 2 is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional structure diagram of a display panel according to an exemplary embodiment of the present disclosure
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 5 is a working timing diagram of a pixel circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of a method for driving a display panel according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a gamma curve of an exemplary embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a simulation result of RGB light-emitting unit lighting speed simulation results under different grayscales
  • Fig. 9 is a schematic diagram of analyzing the principle of smear color cast when the duty cycle is the reference duty cycle
  • FIG. 10 is a schematic diagram of analysis of the principle of smear color cast improvement after reducing the duty cycle.
  • the terms “installed”, “connected” and “connected” should be construed broadly unless otherwise expressly specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • installed may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode and a source electrode, and may be a thin film transistor or a field effect transistor or other devices with the same characteristics.
  • the transistor has a channel region between the drain electrode (or drain electrode terminal, drain region or drain electrode) and the source electrode (or source electrode terminal, source region or source electrode), and current can flow through the drain electrode, channel region and source electrode.
  • the channel region refers to a region through which current mainly flows.
  • the gate of the transistor is referred to as the control electrode
  • the first electrode may be the drain electrode and the second electrode may be the source electrode
  • the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • the “element having a certain electrical effect” may be, for example, electrodes or wirings, or switching elements such as transistors, or other functional elements such as resistors, inductors, and capacitors.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes a state in which an angle of 85° or more and 95° or less is included.
  • film and “layer” are interchangeable.
  • conductive layer may be replaced by “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • FIG. 1 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure.
  • the OLED display device may include a scan signal driver, a data signal driver, a lighting signal driver, an OLED display panel, a first power supply unit, a second power supply unit and an initial power supply unit.
  • the display panel at least includes a plurality of scan signal lines (S1 to SN), a plurality of data signal lines (D1 to DM) and a plurality of light emitting signal lines (EM1 to EMN), and the scan signal driver is configured to pass the plurality of scan signal lines ( S1 to SN) sequentially provide scan signals to the display panel, the data signal driver is configured to provide data signals to the display panel through a plurality of data signal lines (D1 to DM), and the light emission signal driver is configured to pass a plurality of light emission signal lines (EM1) to EMN) in turn to provide lighting control signals to the display panel.
  • S1 to SN scan signal lines
  • D1 to DM data signal lines
  • EM1 to EMN light emitting signal lines
  • a plurality of scan signal lines and a plurality of light emission signal lines extend in a horizontal direction
  • a plurality of data signal lines extend in a vertical direction
  • the plurality of scan signal lines, light emission signal lines and data signal lines intersect A plurality of light emitting units.
  • the first power supply unit, the second power supply unit and the initial power supply unit are respectively configured to supply the first power supply voltage, the second power supply voltage and the initial power supply voltage to the pixel circuit through the first power supply line, the second power supply line and the initial signal line.
  • FIG. 2 is a schematic plan view of a display panel according to an exemplary embodiment of the present disclosure.
  • the display panel includes a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first light-emitting unit P1 that emits light of a first color, a second light-emitting unit P1 that emits light of a second color
  • the light emitting unit P2 and the third light emitting unit P3 emitting light of the third color, the first light emitting unit P1, the second light emitting unit P2 and the third light emitting unit P3 all include pixel circuits and light emitting devices.
  • the pixel circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the scan signal line and the data signal line, and the pixel circuit is configured to receive the data signal line under the control of the scan signal line. the data voltage, and output the corresponding current to the light-emitting device.
  • the light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2 and the third light-emitting unit P3 are respectively electrically connected to the pixel circuits of the light-emitting units, and the light-emitting devices are configured to emit corresponding brightness in response to the current output by the pixel circuits of the light-emitting units. of light.
  • the pixel unit P may include a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit, or the pixel unit may include a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit.
  • the shape of the light emitting unit in the pixel unit may be a rectangle shape, a diamond shape, a pentagon shape or a hexagon shape.
  • the pixel unit includes three light-emitting units, the three light-emitting units can be arranged horizontally, vertically, or in a square pattern.
  • the pixel unit includes four light-emitting units, the four light-emitting units can be horizontally, vertically, or square. (Square) arrangement, which is not limited in the present disclosure.
  • FIG. 3 is a schematic cross-sectional structure diagram of a display panel according to an exemplary embodiment of the present disclosure, illustrating the structures of two light-emitting units of an OLED display panel.
  • the display panel includes a driving circuit layer 62 provided on a substrate 61 , a light-emitting structure layer 63 provided on the driving circuit layer 62 , and a light-emitting structure layer 63 provided on the light-emitting structure layer 63 .
  • Encapsulation layer 64 may include other film layers, which are not limited in this disclosure.
  • substrate 61 may be a flexible substrate, or may be a rigid substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be made of polymer.
  • the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • PI imide
  • PET polyethylene terephthalate
  • surface-treated soft polymer film the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the driving circuit layer 62 may include transistors and storage capacitors constituting a pixel circuit.
  • each light-emitting unit includes one transistor and one storage capacitor as an example.
  • the driving circuit layer 62 of each light-emitting unit may include: a first insulating layer disposed on the substrate, an active layer disposed on the first insulating layer, and a second insulating layer covering the active layer layer, the gate electrode and the first capacitor electrode arranged on the second insulating layer, the third insulating layer covering the gate electrode and the first capacitor electrode, the second capacitor electrode arranged on the third insulating layer, covering the second capacitor electrode
  • the fourth insulating layer, the fourth insulating layer is provided with a via hole, the via hole exposes the active layer, the source electrode and the drain electrode arranged on the fourth insulating layer, the source electrode and the drain electrode respectively pass through the via hole and the active layer.
  • the layers are connected, covering the flat layers of the aforementioned structure.
  • the active layer, gate electrode, source electrode and drain electrode form a transistor, and the first capacitor electrode and the second capacitor electrode form a storage capacitor.
  • the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON). Any one or more of them can be single layer, multi-layer or composite layer.
  • the first insulating layer may be called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second insulating layer and the third insulating layer may be called a gate insulating (GI) layer, and the fourth insulating layer may be called a layer inter-insulation (ILD) layer.
  • GI gate insulating
  • ILD layer inter-insulation
  • the first metal thin film, the second metal thin film and the third metal thin film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Various, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene or polythiophene, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene or polythiophene hexathiophene
  • the active layer based on oxide technology can employ oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten and indium and zinc, oxides containing titanium and indium, oxides containing titanium and indium and tin , oxides containing indium and zinc, oxides containing silicon and indium and tin, oxides containing indium and gallium and zinc, etc.
  • the light emitting structure layer 63 may include an anode, a pixel definition layer, an organic light emitting layer and a cathode, the anode is disposed on the flat layer, and is connected to the drain electrode through a via hole opened on the flat layer, and the pixel definition layer is disposed on the flat layer.
  • a pixel opening is arranged thereon, the pixel opening exposes the anode, the organic light-emitting layer is arranged in the pixel opening, and the cathode is arranged on the organic light-emitting layer. color light.
  • the organic light-emitting layer may include at least a stacked hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) ), the hole injection layer and the hole transport layer may be collectively referred to as the hole layer, and the electron transport layer and the electron injection layer may be collectively referred to as the electron layer.
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EML emission layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the encapsulation layer 64 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of The organic material, the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that the outside water vapor cannot enter the light emitting structure layer 63 .
  • the pixel circuit may be a 5T1C, 5T2C, 6T1C or 7T1C structure. In some possible implementations, the pixel circuit may be a 6T1C or 7T1C structure, and the theoretical charge voltage of the storage capacitor at the end of the charging phase is the difference between the data voltage and the threshold voltage of the driving transistor.
  • FIG. 4 is an equivalent circuit diagram of a pixel circuit according to an exemplary embodiment of the present disclosure.
  • the pixel circuit may include 7 switching transistors (the first transistor T1 to the seventh transistor T7), 1 storage capacitor C and 8 signal lines (the data signal line DATA, the first scan signal line S1, the Two scan signal lines S2, a first initial signal line INIT1, a second initial signal line INIT2, a first power line VSS, a second power line VDD, and a light-emitting signal line EM).
  • the control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second scan signal line S2.
  • Node N2 is connected.
  • the control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the control electrode of the third transistor T3 is connected to the second node N2, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the second power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the first end of the storage capacitor C is connected to the second power line VDD, and the second end of the storage capacitor C is connected to the second node N2.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.
  • the second pole of the light emitting device is connected to the first power supply line VSS, the signal of the first power supply line VSS is a low-level signal, and the signal of the second power supply line VDD is a continuous high-level signal.
  • the display panel may include a display area and a non-display area, the plurality of light emitting units are located in the display area, and the first power line VSS is located in the non-display area.
  • the non-display area may surround the display area.
  • the display panel may include a scan signal driver, a timing controller, and a clock signal line located in a non-display area.
  • the scan signal driver is connected to the first scan signal line S1 and the second scan signal line S2, the clock signal line is connected to the timing controller and the scan signal driver respectively, and the clock signal line is configured to be under the control of the timing controller, to the scan signal
  • the driver provides the clock signal.
  • the number of clock signal lines is multiple, and the clock signals are respectively provided to multiple scan signal drivers.
  • the display panel may include a data signal driver connected to the data signal line.
  • the vertical intersection of the scan signal lines and the data signal lines defines a plurality of light emitting units arranged in a matrix manner
  • the first scan signal lines and the second scan signal lines define a display row
  • the adjacent data signal lines define a display row.
  • the first light emitting unit P1, the second light emitting unit P2 and the third light emitting unit P3 may be periodically arranged along the display row direction.
  • the first light emitting unit P1 , the second light emitting unit P2 and the third light emitting unit P3 may be periodically arranged along the display column direction.
  • the first scan signal line S1 is the scan signal line in the pixel circuit of the display row
  • the second scan signal line S2 is the scan signal line in the pixel circuit of the previous display row, that is, for the nth display row
  • the first scanning signal line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display line and the first scanning signal in the pixel circuit of the previous display line
  • the line S1 is the same signal line, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first scan signal line S1, the second scan signal line S2, the lighting signal line EM, the first initial signal line INIT1 and the second initial signal line INIT2 extend in the horizontal direction
  • the first power supply lines VSS, The second power supply line VDD and the data signal line DATA extend in the vertical direction.
  • the light emitting device may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer and a second electrode (cathode).
  • OLED organic electroluminescent diode
  • FIG. 5 is an operation timing diagram of a pixel circuit according to an exemplary embodiment of the present disclosure.
  • the following describes an exemplary embodiment of the present disclosure through the operation process of the pixel circuit illustrated in FIG. 4 .
  • the pixel circuit in FIG. 4 includes 7 transistors (the first transistor T1 to the sixth transistor T7 ), 1 storage capacitor C and 8 signals lines (data signal line DATA, first scan signal line S1, second scan signal line S2, first initial signal line INIT1, second initial signal line INIT2, first power supply line VSS, second power supply line VDD and light emitting signal line EM), all 7 transistors are P-type transistors.
  • the working process of the pixel circuit may include:
  • the first stage A1 is called a reset stage
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are a high-level signal.
  • the signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1
  • the signal of the first initial signal line INIT1 is supplied to the second node N2 to initialize the storage capacitor C and clear the original data in the storage capacitor. Voltage.
  • the signals of the first scanning signal line S1 and the light-emitting signal line EM are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Not glowing.
  • the second stage A2 is called the data writing stage or the threshold compensation stage.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line EM are a high-level signal
  • the data The signal line DATA outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scan signal line S1 is a low level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on.
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line DATA is supplied to the second through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2 Node N2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, and the voltage of the second end of the storage capacitor C (the second node N2) is Vdata-Vth, Vdata is the data voltage output by the data signal line DATA, and Vth is the threshold voltage of the third transistor T3.
  • the seventh transistor T7 is turned on so that the initial voltage of the second initial signal line INIT2 is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the internal pre-stored voltage is cleared, and the initialization is completed to ensure that the OLED does not emit light .
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line EM is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line EM is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the second power supply line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the data signal driver is provided with a gamma (Gamma) correction curve, with a black picture 0 grayscale as the lowest grayscale, and a white picture 255 grayscale as the highest grayscale, and the data signal driver corrects according to the gamma
  • the curve provides data voltages for the light-emitting unit to display grayscales from 0 to 255.
  • the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode and the first electrode. Since the voltage of the second node N2 is Vdata-Vth, the driving current of the third transistor T3 is:
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3
  • Vth is the third transistor.
  • Vdata is the data voltage output by the data signal line DATA
  • Vdd is the power supply voltage output by the second power line VDD.
  • the OLED voltage and brightness have a nonlinear power-level relationship. If the brightness grading is achieved by voltage driving, the driving voltage requirements are too high and sophisticated, the design requirements for the power supply part of the driving circuit are too high, and the cost is high and cannot be mass-produced.
  • the current-brightness curve of OLED is a nearly linear relationship, so the current driving method is adopted. However, using the current driving method usually results in asynchronous lighting of different pixels, which is mainly caused by the delay in the charging and discharging of the parasitic capacitance existing in the backplane.
  • the edge of the image will appear smear color cast, such as smear red, smear blue, etc., which seriously affects the user experience. .
  • At least one embodiment of the present disclosure provides a method for driving a display panel.
  • the display panel includes a plurality of regularly arranged pixel units, and at least one of the plurality of pixel units emits a first color.
  • the pixel circuit includes: A driving sub-circuit, a light-emitting control sub-circuit and a data writing sub-circuit, the driving sub-circuit is electrically connected to the light-emitting control sub-circuit and the data writing sub-circuit respectively, the data writing sub-circuit is configured to transmit the data voltage, and the light-emitting control sub-circuit is configured In order to control the on-time of the driving sub-circuit
  • step 100 Determine the brightness segment in which the display panel is located, the brightness segment includes the first brightness segment to the Nth brightness segment, and the maximum grayscale brightness of the first brightness segment to the Nth brightness segment decreases sequentially, and each brightness segment includes Three gamma correction curves corresponding to the first light-emitting unit, the second light-emitting unit and the third light-emitting unit respectively; each luminance segment in the (NM)th luminance segment to the Nth luminance segment also corresponds to at least one duty cycle respectively , the duty cycle is the effective pulse duty cycle of the light-emitting signal line, the light-emitting control sub-circuit controls the on-time duration of the driving sub-circuit according to the duty cycle, N is an integer greater than 1, M is greater than or equal to 0 and less than N the integer;
  • Step 200 Determine an input data voltage corresponding to at least one light-emitting unit based on the determined gamma correction curve corresponding to the luminance segment and the image to be displayed;
  • Step 300 Based on the determined input data voltage, or, based on the determined input data voltage and duty cycle, the display panel is driven to display the image to be displayed, and the display panel is driven to display the (NM)th luminance segment to the Nth luminance segment.
  • the current flowing through each light-emitting device is greater than the preset reference current of each light-emitting device, and the on-time is shorter than the preset reference on-time.
  • the luminance value in each luminance segment refers to "gray-scale luminance".
  • the "gray-scale brightness” in the embodiment of the present disclosure refers to the "brightness” seen visually, that is, the brightness value of the display screen detected by the brightness detector, which is related to the lighting time and the actual current brightness, wherein, “Current brightness” refers to the corresponding brightness of the light emitted by the light-emitting device in response to the current output by the pixel circuit of the light-emitting unit where it is located.
  • the driving method of the display panel provided by the embodiment of the present disclosure is such that when each frame of image from the (NM)th luminance segment to the Nth luminance segment is driven to display, the current flowing through each light-emitting device is greater than the predetermined value of each light-emitting device.
  • Set the reference current, and the on-time is shorter than the preset reference on-time, so that the turn-on time of at least one light-emitting unit tends to be consistent at low gray-scale brightness, thereby significantly improving the problem of smear and color cast, and improving the display of the display panel. Effect.
  • the preset reference current is the current flowing through each light-emitting device in the at least one pixel circuit when the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the at least one light-emitting unit is the preset reference voltage;
  • the reference turn-on duration is the turn-on duration of the driving sub-circuit controlled by the light-emitting control subcircuit when the duty ratio corresponding to each luminance segment in the (NM)th to Nth luminance segment is a preset reference duty cycle.
  • Gamma correction is usually debugged in multi-segment (Band) mode to ensure the screen display effect when the display brightness value (Display Brightness Value, DBV) changes.
  • a general digital integrated circuit Integrated Circuit, IC
  • IC has more than 10 groups of gamma registers (each group corresponds to a segment) that can be used for gamma correction for debugging the DBV curve style. Sections in special modes (for example, Always On Display (AOD), High Brightness Mode (HBM), etc.) are removed, and the remaining sections are all in Normal mode.
  • AOD Always On Display
  • HBM High Brightness Mode
  • the gamma correction curve is derived from the response curve of the early Cathode Ray Tube (CRT) display, that is, the nonlinear relationship between the output brightness and the input data voltage.
  • CRT Cathode Ray Tube
  • the gamma correction curve describes the functional relationship between the binary number (ie gray scale) and the input data voltage.
  • the abscissa of the gamma correction curve is the binary number
  • the ordinate is the input data voltage corresponding to the binary number.
  • the gamma correction curve makes the input data voltage and output brightness satisfy the following relationship:
  • L C* ⁇ ⁇ , where L is the output brightness, C is the system constant, ⁇ is the input data voltage, and ⁇ is its exponent.
  • N may be 9 and M may be 1 or 0.
  • the maximum gray-scale brightness from the first stage to the ninth stage gradually decreases.
  • the gray-scale brightness range of the third stage is 0 to 150nits, ..., and the gray-scale brightness range of the ninth stage is 0 to 2nits.
  • the transistors in the simulation circuit are P-type transistors
  • the time for the current and voltage to stabilize in the first frame is shortened.
  • the turn-on speeds of the light-emitting units tend to be the same.
  • the light-emitting duration of the light-emitting device can be adjusted by adjusting the effective pulse duty ratio of the light-emitting signal line.
  • the actual grayscale brightness is lower.
  • the effective pulse duty ratio 100%, it means that the light-emitting device has the maximum light-emitting duration.
  • FIG. 9 to FIG. 10 by reducing the effective pulse duty ratio of the light-emitting signal line and increasing the current flowing through the light-emitting device, it is possible to make at least one light-emitting unit turn on without affecting the actual grayscale brightness. The speed tends to be consistent, which effectively improves the problem of smear and color cast at the edge of the light and dark transition of the picture.
  • the duty cycle corresponding to each of the (N-M)th luminance segment to the Nth luminance segment is smaller than the preset reference duty cycle.
  • the light-emitting device is driven to display each frame of the image from the (NM) th luminance segment to the N th luminance segment.
  • the on-time duration is less than the preset reference on-time duration.
  • the preset reference duty cycle may be 10%.
  • the duty ratio corresponding to each of the (N-M)th luminance segment to the Nth luminance segment is between 1% and 4%.
  • the (N-M)th luminance segment to the Nth luminance segment correspond to a duty cycle, and the duty cycle is 2%.
  • the plurality of transistors in the pixel circuit of each light-emitting unit are P-type transistors, and in the plurality of gamma correction curves corresponding to the (NM)th luminance segment to the Nth luminance segment, the data
  • the data voltage transmitted by the writing sub-circuit to the pixel circuit of the first light-emitting unit is less than the first reference voltage
  • the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the second light-emitting unit is less than the second reference voltage
  • the data voltage transmitted to the pixel circuit of the third light emitting unit is smaller than the third reference voltage
  • the first reference voltage, the second reference voltage and the third reference voltage are respectively in each of the (NM)th luminance segment to the Nth luminance segment
  • the duty cycle corresponding to the luminance segment is the preset reference duty cycle
  • the data writing sub-circuit transmits the data voltage to the pixel circuits of the first light-emitting unit, the second light-emitting
  • the present exemplary embodiment writes the duty cycle and data corresponding to each of the reduced (NM)th luminance segment to the Nth luminance segment into the sub-circuit to the first light-emitting unit, the second light-emitting unit, and the first light-emitting unit, the second light-emitting unit, and the The data voltage transmitted by the pixel circuit of the three light-emitting units is directly written into the driving chip, which can greatly simplify the computational workload of the driving chip.
  • the driving current flowing through the third transistor T3 is:
  • the first reference voltages corresponding to different grayscales are different, and the first data voltages corresponding to different grayscales are also different,
  • the first data voltage corresponding to the same grayscale must be smaller than the first reference voltage corresponding to the grayscale.
  • the second reference voltages corresponding to different grayscales are different, and the second data voltages corresponding to different grayscales are also different.
  • the same grayscale The corresponding second data voltage must be lower than the second reference voltage corresponding to the gray scale.
  • the third reference voltages corresponding to different grayscales are different, and the third data voltages corresponding to different grayscales are also different.
  • the same grayscale The corresponding third data voltage must be smaller than the third reference voltage corresponding to the gray scale.
  • the first light-emitting unit is a red light-emitting unit
  • the second light-emitting unit is a green light-emitting unit
  • the third light-emitting unit is a blue light-emitting unit.
  • the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the first light emitting unit is about 5/1000 to 15/1000 of the first reference voltage
  • the data writing sub-circuit The data voltage transmitted by the circuit to the pixel circuit of the second light-emitting unit is about 10/1000 to 20/1000 of the second reference voltage
  • the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the third light-emitting unit About 6/1000 to 16/1000 of the third reference voltage.
  • the first reference voltage corresponding to the first light-emitting unit is 5.57V
  • the voltage corresponding to the second light-emitting unit is 5.57V
  • the second reference voltage is 5.8V
  • the third reference voltage corresponding to the third light-emitting unit is 5.37V.
  • the driving method of the present disclosure has low cost, does not need to change hardware, and has high practicability.
  • the duty ratio corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment is a preset reference duty cycle.
  • the data voltages transmitted by the data writing subcircuit to the pixel circuits of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are the first reference voltage, the second A reference voltage and a third reference voltage; a plurality of transistors in the pixel circuit are all P-type transistors.
  • the method further includes: when the determined luminance segment is in the (NM)th luminance segment to the Nth luminance segment, reducing the duty corresponding to the determined luminance segment ratio, reducing the input data voltage corresponding to at least one light-emitting unit, so that the brightness generated by using the reduced duty cycle and the input data voltage corresponding to the at least one light-emitting unit is different from using the preset reference duty cycle.
  • the duty ratio is the same as the gray-scale brightness generated by the first reference voltage, the second reference voltage and the third reference voltage.
  • the duty cycle corresponding to each of the (N-M)th luminance segment to the Nth luminance segment is smaller than the preset reference duty cycle.
  • the plurality of transistors in the pixel circuit of each light-emitting unit are N-type transistors.
  • the data writing sub-circuit sends the data to the first light-emitting unit.
  • the data voltage transmitted by the pixel circuit of the second light-emitting unit is greater than the first reference voltage
  • the data voltage transmitted by the data writing sub-circuit to the pixel circuit of the second light-emitting unit is greater than the second reference voltage
  • the data writing sub-circuit is writing to the pixel of the third light-emitting unit.
  • the data voltage transmitted by the circuit is greater than the third reference voltage, and the first reference voltage, the second reference voltage and the third reference voltage are respectively the duty cycle corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment
  • the data writing sub-circuit transmits the data voltage to the pixel circuits of the first light-emitting unit, the second light-emitting unit and the third light-emitting unit.
  • the positions of the first transistor T1, the seventh transistor T7 and the storage capacitor C in FIG. 4 can be adjusted as follows:
  • the pole is connected to the second power supply line VDD
  • the second pole of the first transistor T1 is still connected to the second node N2
  • the control pole of the first transistor T1 is still connected to the second scanning signal line S2
  • the control pole of the seventh transistor T7 Connected to the third scanning signal line S3
  • the first pole of the seventh transistor T7 is still connected to the second initial signal line INIT2
  • the second pole of the seventh transistor T7 is still connected to the fourth node N4, connecting the first pole of the storage capacitor C to the second initial signal line INIT2.
  • the terminal is connected to the fourth node N4, the second terminal of the storage capacitor C is still connected to the second node N2, and the positions/connections of other transistors are still the same as those in FIG.
  • the drive current is:
  • the current input to the light-emitting device of at least one light-emitting unit can be increased by increasing the data voltage Vdata output by the data signal line DATA, and the data voltage The higher the Vdata, the higher the current of the light emitting device.
  • the first reference voltages corresponding to different grayscales are different, and the first data voltages corresponding to different grayscales are also different, However, the first data voltage corresponding to the same grayscale must be greater than the first reference voltage corresponding to the grayscale.
  • the second reference voltages corresponding to different grayscales are different, and the second data voltages corresponding to different grayscales are also different.
  • the same grayscale The corresponding second data voltage must be greater than the second reference voltage corresponding to the gray scale.
  • the third reference voltages corresponding to different grayscales are different, and the third data voltages corresponding to different grayscales are also different.
  • the same grayscale The corresponding third data voltage must be greater than the third reference voltage corresponding to the gray scale.
  • the duty ratio corresponding to each luminance segment in the (NM)th luminance segment to the Nth luminance segment is a preset reference duty cycle.
  • the data voltages transmitted by the data writing subcircuit to the pixel circuits of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are the first reference voltage, the second A reference voltage and a third reference voltage; a plurality of transistors in the pixel circuit are all N-type transistors.
  • the method further includes: when the determined luminance segment is in the (NM)th luminance segment to the Nth luminance segment, reducing the duty corresponding to the determined luminance segment ratio, increase the input data voltage corresponding to at least one light-emitting unit, so that the brightness generated by using the reduced duty cycle and the input data voltage corresponding to the increased at least one light-emitting unit is different from using the preset reference duty cycle.
  • the duty ratio is the same as the gray-scale brightness generated by the first reference voltage, the second reference voltage and the third reference voltage.
  • the driving method of the display panel by increasing the input data voltage corresponding to at least one light-emitting unit in the low-brightness segment, the current flowing through each light-emitting device is increased, and the effective pulse occupation of the light-emitting signal line is reduced.
  • the RGB lighting speed tends to be consistent without affecting the actual gray-scale brightness.
  • the RGB brightness is matched to a white balance, thereby The problem of smear and color cast has been significantly improved, and the display effect of the display panel has been improved.
  • the method is low cost, does not change the hardware, and is highly implementable.
  • Exemplary embodiments of the present disclosure also provide a display panel, which is driven by the driving method for a display panel of any one of the foregoing embodiments.
  • Exemplary embodiments of the present disclosure also provide a display device including the aforementioned display panel.
  • the display device can be: a mobile phone, a tablet computer, a TV, a display device, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.

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Abstract

一种显示面板及其驱动方法、显示装置，其中，驱动方法包括：确定显示面板所处的亮度段，亮度段包括第一至第N亮度段，第一至第N亮度段的最大灰阶亮度依次降低，第(N-M)亮度段至第N亮度段中的每个亮度段分别对应至少一个占空比；基于所确定的亮度段对应的伽马校正曲线和待显示图像确定至少一个发光单元对应的输入数据电压（200）；基于所确定的输入数据电压，或者，基于所确定的输入数据电压和占空比，驱动显示面板显示待显示图像，且在驱动显示第(N-M)亮度段至第N亮度段的每一帧图像时，流过每个发光器件的电流大于每个发光器件的预设基准电流，导通时长小于预设基准导通时长（300）。该驱动方法改善拖影偏色问题，提高显示效果。

Description

显示面板及其驱动方法、显示装置
本公开要求于2020年7月16日提交中国专利局、申请号为2020106848819、发明名称为“显示面板及其驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示面板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点，已广泛应用于手机、平板电脑、数码相机等显示产品。OLED显示属于电流驱动，需要通过像素电路向OLED输出电流，驱动OLED发光。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示面板的驱动方法，所述显示面板包括规则排布的多个像素单元，所述多个像素单元中的至少一个包括出射第一颜色光线的第一发光单元、出射第二颜色光线的第二发光单元和出射第三颜色光线的第三发光单元，每个发光单元包括像素电路和电连接所述像素电路的发光器件，所述像素电路包括：驱动子电路、发光控制子电路和数据写入子电路，所述驱动子电路分别电连接所述发光控制子电路和数据写入子电路，所述数据写入子电路被配置为传输数据电压，所述发光控制子电路被配置为控制驱动子电路的导通时长，所述驱动子电路被配置为在所述导通时长内根据所述数据电压控制流过所述发光器件的电流；所述驱动方法包括：确定显示面板 所处的亮度段，所述亮度段包括第一亮度段至第N亮度段，所述第一亮度段至第N亮度段的最大灰阶亮度依次降低，每个亮度段包括分别与第一发光单元、第二发光单元和第三发光单元对应的三个伽马校正曲线；第(N-M)亮度段至第N亮度段中的每个亮度段还分别对应至少一个占空比，所述占空比为发光信号线的有效脉冲占空比，所述发光控制子电路根据所述占空比控制所述驱动子电路的导通时长，N为大于1的整数，M为大于或等于0且小于N的整数；基于所确定的亮度段对应的伽马校正曲线和待显示图像确定至少一个发光单元对应的输入数据电压；基于所确定的输入数据电压，或者，基于所确定的输入数据电压和占空比，驱动所述显示面板显示待显示图像，且在驱动显示所述第(N-M)亮度段至第N亮度段的每一帧图像时，流过每个所述发光器件的电流大于每个所述发光器件的预设基准电流，导通时长小于预设基准导通时长。
在一些可能的实现方式中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均小于预设基准占空比；所述像素电路中的多个晶体管均为P型晶体管，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元的像素电路传输的数据电压小于第一基准电压，所述数据写入子电路向所述第二发光单元的像素电路传输的数据电压小于第二基准电压，所述数据写入子电路向所述第三发光单元的像素电路传输的数据电压小于第三基准电压，所述第一基准电压、第二基准电压和第三基准电压分别为在所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压。
在一些可能的实现方式中，所述数据写入子电路向所述第一发光单元的像素电路传输的数据电压为所述第一基准电压的千分之五至千分之十五之间，所述数据写入子电路向所述第二发光单元的像素电路传输的数据电压为所述第二基准电压的千分之十至千分之二十之间；所述数据写入子电路向所述第三发光单元的像素电路传输的数据电压为所述第三基准电压的千分之六至千分之十六之间。
在一些可能的实现方式中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均小于预设基准占空比；所述像素电路中的多个晶体管均为N型晶体管，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元的像素电路传输的数据电压大于第一基准电压，所述数据写入子电路向所述第二发光单元的像素电路传输的数据电压大于第二基准电压，所述数据写入子电路向所述第三发光单元的像素电路传输的数据电压大于第三基准电压，所述第一基准电压、第二基准电压和第三基准电压分别为在所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压。
在一些可能的实现方式中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压分别为第一基准电压、第二基准电压和第三基准电压；所述像素电路中的多个晶体管均为P型晶体管，在确定至少一个发光单元对应的输入数据电压之后，所述方法还包括：当所确定的亮度段在第(N-M)亮度段至第N亮度段中时，减小所确定的亮度段对应的占空比，减小至少一个发光单元对应的输入数据电压，并使得采用减小后的占空比和减小后的至少一个发光单元对应的输入数据电压产生的亮度，与采用所述预设基准占空比和第一基准电压、第二基准电压以及第三基准电压产生的灰阶亮度相同。
在一些可能的实现方式中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压分别为第一基准电压、第二基准电压和第三基准电压；所述像素电路中的多个晶体管均为N型晶体管，在确定至少一个发光单元对应的输入数据电压之后，所述方法还包括：当所确定的亮度段在第(N-M)亮度段至第N亮度段中时，减小所 确定的亮度段对应的占空比，增大至少一个发光单元对应的输入数据电压，并使得采用减小后的占空比和增大后的至少一个发光单元对应的输入数据电压产生的亮度，与采用所述预设基准占空比和第一基准电压、第二基准电压以及第三基准电压产生的灰阶亮度相同。
在一些可能的实现方式中，N为9，M为1或0。
在一些可能的实现方式中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均在1％到4％之间。
在一些可能的实现方式中，第一发光单元为红色发光单元，第二发光单元为绿色发光单元，第三发光单元为蓝色发光单元。
在一些可能的实现方式中，所述像素电路包括：第一晶体管，其控制极与第二扫描信号线连接，其第一极与第一初始信号线连接，其第二极与第二节点连接；第二晶体管，其控制极与第一扫描信号线连接，其第一极与第二节点连接，其第二极与第三节点连接；第三晶体管，其控制极与第二节点连接，其第一极与第一节点连接，其第二极与第三节点连接；第四晶体管，其控制极与第一扫描信号线连接，其第一极与数据信号线连接，其第二极与第一节点连接；第五晶体管，其控制极与发光信号线连接，其第一极与第二电源线连接，其第二极与第一节点连接；第六晶体管，其控制极与发光信号线连接，其第一极与第三节点连接，其第二极与发光器件的第一极连接；第七晶体管，其控制极与第一扫描信号线连接，其第一极与第二初始信号线连接，其第二极与发光器件的第一极连接，发光器件的第二极与第一电源线连接；存储电容，其第一端与第二电源线连接，其第二端与第二节点连接。
本公开实施例还提供了一种显示面板，所述显示面板采用如上所述的显示面板的驱动方法驱动。
本公开实施例还提供了一种显示装置，包括前述的显示面板。
在阅读并理解了附图概述和本公开的实施方式后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部 分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开示例性实施例一种显示装置的结构示意图；
图2为本公开示例性实施例一种显示面板的平面结构示意图；
图3为本公开示例性实施例一种显示面板的剖面结构示意图；
图4为本公开示例性实施例一种像素电路的等效电路图；
图5为本公开示例性实施例一种像素电路的工作时序图；
图6为本公开示例性实施例一种显示面板的驱动方法的流程示意图；
图7为本公开示例性实施例的伽马曲线示意图；
图8为不同灰阶下RGB发光单元启亮速度仿真结果示意图；
图9为占空比为基准占空比时，拖影偏色原理分析示意图；
图10为降低占空比后，拖影偏色改善原理分析示意图。
具体实施方式
本文中的实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是实现方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，可能夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的任意一个实现方式并不一定限定于图中所示尺寸，附图中部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的任意一个实现方式不局限于附图所示的形状或数值等。
本文中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本文中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖 直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述实施方式和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系可根据描述的构成要素的方向进行适当地改变。因此，不局限于在文中说明的词句，根据情况可以适当地更换。
在本文中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本文中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件，可以为薄膜晶体管或场效应管或其它特性相同的器件。晶体管在漏电极(或称漏电极端子、漏区域或漏电极)与源电极(或称源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本文中，沟道区域是指电流主要流过的区域。
在本文中，将晶体管的栅极称为控制极，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本文中，“源电极”和“漏电极”可以互相调换。
在本文中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其它功能元件等。
在本文中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线 形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本文中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本文中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为本公开示例性实施例一种显示装置的结构示意图。如图1所示，OLED显示装置可以包括扫描信号驱动器、数据信号驱动器、发光信号驱动器、OLED显示面板、第一电源单元、第二电源单元和初始电源单元。显示面板至少包括多条扫描信号线(S1到SN)、多条数据信号线(D1到DM)和多条发光信号线(EM1到EMN)，扫描信号驱动器被配置为通过多条扫描信号线(S1到SN)依次向显示面板提供扫描信号，数据信号驱动器被配置为通过多条数据信号线(D1到DM)向显示面板提供数据信号，发光信号驱动器被配置为通过多条发光信号线(EM1到EMN)依次向显示面板提供发光控制信号。在示例性实施方式中，多条扫描信号线和多条发光信号线沿着水平方向延伸，多条数据信号线沿着竖直方向延伸，多条扫描信号线、发光信号线和数据信号线交叉限定出多个发光单元。第一电源单元、第二电源单元和初始电源单元分别被配置为通过第一电源线、第二电源线和初始信号线向像素电路提供第一电源电压、第二电源电压和初始电源电压。
图2为本公开示例性实施例一种显示面板的平面结构示意图。如图2所示，显示面板包括矩阵方式排布的多个像素单元P，多个像素单元P中的至少一个包括出射第一颜色光线的第一发光单元P1、出射第二颜色光线的第二发光单元P2和出射第三颜色光线的第三发光单元P3，第一发光单元P1、第二发光单元P2和第三发光单元P3均包括像素电路和发光器件。第一发光单元P1、第二发光单元P2和第三发光单元P3中的像素电路分别与扫描信号线和数据信号线连接，像素电路被配置为在扫描信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一发光单元P1、第二发光单元P2和第三发光单元P3中的发光器件分别与所在发光单元的像素电路电连接，发光器件被配置为响应所在发光单元的像素电路输出的电流 发出相应亮度的光。
在示例性实施方式中，像素单元P中可以包括红色发光单元、绿色发光单元和蓝色发光单元，或者像素单元中可以包括红色发光单元、绿色发光单元、蓝色发光单元和白色发光单元，本公开在此不做限定。在示例性实施方式中，像素单元中发光单元的形状可以是矩形状、菱形、五边形或六边形。像素单元包括三个发光单元时，三个发光单元可以采用水平并列、竖直并列或品字方式排列，像素单元包括四个发光单元时，四个发光单元可以采用水平并列、竖直并列或正方形(Square)方式排列，本公开在此不做限定。
图3为本公开示例性实施例一种显示面板的剖面结构示意图，示意了OLED显示面板两个发光单元的结构。如图3所示，在垂直于显示面板的平面上，显示面板包括设置在基底61上的驱动电路层62、设置在驱动电路层62上的发光结构层63以及设置在发光结构层63上的封装层64。在一些可能的实现方式中，显示面板可以包括其它膜层，本公开在此不做限定。
在示例性实施方式中，基底61可以是柔性基底，或者可以是刚性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，驱动电路层62可以包括构成像素电路的晶体管和存储电容，图3中以每个发光单元包括一个晶体管和一个存储电容为例进行示意。在一些可能的实现方式中，每个发光单元的驱动电路层62可以包括：设置在基底上的第一绝缘层，设置在第一绝缘层上的有源层，覆盖有源层的第二绝缘层，设置在第二绝缘层上的栅电极和第一电容电极，覆盖栅电极和第一电容电极的第三绝缘层，设置在第三绝缘层上的第二电容电极，覆盖第二电容电极的第四绝缘层，第四绝缘层上开设有过孔，过孔暴露出有源层，设置在第四绝缘层上的源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接，覆盖前述结构的平坦层。有源层、栅电极、源电极和漏电极组成 晶体管，第一电容电极和第二电容电极组成存储电容。在一些可能的实现方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层可称为栅绝缘(GI)层，第四绝缘层可称为层间绝缘(ILD)层。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或者上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。基于氧化物技术的有源层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物、包含铟和镓和锌的氧化物等。
在示例性实施方式中，发光结构层63可以包括阳极、像素定义层、有机发光层和阴极，阳极设置在平坦层上，通过平坦层上开设的过孔与漏电极连接，像素定义层设置在阳极和平坦层上，其上设置有像素开口，像素开口暴露出阳极，有机发光层设置在像素开口内，阴极设置在有机发光层上，有机发光层在阳极和阴极施加电压的作用下出射相应颜色的光线。
在示例性实施方式中，有机发光层可以至少包括叠设的空穴注入层(HIL)、空穴传输层(HTL)、发射层(EML)、电子传输层(ETL)和电子注入层(EIL)，空穴注入层和空穴传输层可统称为空穴层，电子传输层和电子注入层可统称为电子层。
在示例性实施方式中，封装层64可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层63。
在示例性实施方式中，像素电路可以是5T1C、5T2C、6T1C或7T1C结构。在一些可能的实现方式中，像素电路可以是6T1C或7T1C结构，存储电容在充电阶段结束时的理论应充电压为数据电压与驱动晶体管的阈值电压的差值。
图4为本公开示例性实施例一种像素电路的等效电路图。如图4所示，像素电路可以包括7个开关晶体管(第一晶体管T1到第七晶体管T7)、1个存储电容C和8个信号线(数据信号线DATA、第一扫描信号线S1、第二扫描信号线S2、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VSS、第二电源线VDD和发光信号线EM)。
在示例性实施方式中，第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第二节点N2连接。第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。第三晶体管T3的控制极与第二节点N2连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第一节点N1连接。第五晶体管T5的控制极与发光信号线EM连接，第五晶体管T5的第一极与第二电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一极连接。存储电容C的第一端与第二电源线VDD连接，存储电容C的第二端与第二节点N2连接。
第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，发光器件的第二极与第一电源线VSS连接，第一电源线VSS的信号为低电平信号，第二电源线VDD的信号为持续提供高电平信号。
在示例性实施方式中，显示面板可以包括显示区域和非显示区域，多个发光单元位于显示区域，第一电源线VSS位于非显示区域。在一些可能的实现方式中，非显示区域可以包围显示区域。
在示例性实施方式中，显示面板可以包括位于非显示区域的扫描信号驱动器、时序控制器和时钟信号线。扫描信号驱动器与第一扫描信号线S1和第二扫描信号线S2连接，时钟信号线分别与时序控制器和扫描信号驱动器连接，时钟信号线被配置为在时序控制器的控制下，向扫描信号驱动器提供时钟信号。在一些可能的实现方式中，时钟信号线的数量为多个，分别向多个扫描信号驱动器提供时钟信号。在示例性实施方式中，显示面板可以包括数据信号驱动器，数据信号驱动器与数据信号线连接。
在示例性实施方式中，扫描信号线和数据信号线垂直交叉限定出呈矩阵方式排布的多个发光单元，第一扫描信号线和第二扫描信号线限定一显示行，相邻数据信号线限定一显示列。第一发光单元P1、第二发光单元P2和第三发光单元P3可以沿着显示行方向周期性排布。在一些可能的实现方式中，第一发光单元P1、第二发光单元P2和第三发光单元P3可以沿着显示列方向周期性排布。
在示例性实施方式中，第一扫描信号线S1为本显示行像素电路中的扫描信号线，第二扫描信号线S2为上一显示行像素电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一扫描信号线S1、第二扫描信号线S2、发光信号线EM、第一初始信号线INIT1和第二初始信号线INIT2沿水平方向延伸，第一电源线VSS、第二电源线VDD和数据信号线DATA沿竖直方向延伸。
在示例性实施方式中，发光器件可以是有机电致发光二极管(OLED)，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。
图5为本公开示例性实施例一种像素电路的工作时序图。下面通过图4示例的像素电路的工作过程说明本公开示例性实施例，图4中的像素电路包括7个晶体管(第一晶体管T1到第六晶体管T7)、1个存储电容C和8个信号线(数据信号线DATA、第一扫描信号线S1、第二扫描信号线S2、第一初始信号线INIT1、第二初始信号线INIT2、第一电源线VSS、第二电源线VDD和发光信号线EM)，7个晶体管均为P型晶体管。
在示例性实施方式中，像素电路的工作过程可以包括：
第一阶段A1，称为复位阶段，第二扫描信号线S2的信号为低电平信号，第一扫描信号线S1和发光信号线EM的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，第一初始信号线INIT1的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线EM的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段A2，称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线EM的信号为高电平信号，数据信号线DATA输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据信号线DATA输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线DATA输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vdata-Vth，Vdata为数据信号线DATA输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得第二初始信号线INIT2的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的 信号为高电平信号，使第一晶体管T1断开。发光信号线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3，称为发光阶段，发光信号线EM的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第二电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在示例性实施方式中，数据信号驱动器设置有伽马(Gamma)校正曲线，以黑画面0灰阶作为最低灰阶，以白画面255灰阶作为最高灰阶，数据信号驱动器根据该伽马校正曲线为发光单元显示0灰阶到255灰阶提供数据电压。在像素电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其控制极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-Vth，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vdata+Vth)-Vth] 2＝K*(Vdd-Vdata) 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的控制极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vdata为数据信号线DATA输出的数据电压，Vdd为第二电源线VDD输出的电源电压。
OLED电压与亮度呈现非线性的幂级关系，如果用电压驱动的方式来实现亮度分级，那么驱动电压要求过于高精尖，对驱动电路电源部分的设计要求过高，成本高无法量产，而OLED的电流亮度曲线则为近线性关系，因此采用电流驱动方式。然而，采用电流驱动方式通常会导致不同像素点启亮不同步，这主要是背板中存在的寄生电容的充放电会产生延迟所致。由于不同像素点启亮不同步，在拖动画面或者快速刷新等情况下，图片亮暗交接边缘会出现拖影偏色的问题，比如拖影发红，拖影发蓝等，严重影响用户体验。
如图6所示，本公开至少一实施例提供了一种显示面板的驱动方法，所述显示面板包括规则排布的多个像素单元，该多个像素单元中的至少一个包括出射第一颜色光线的第一发光单元、出射第二颜色光线的第二发光单元和 出射第三颜色光线的第三发光单元，每个发光单元包括像素电路和电连接该像素电路的发光器件，像素电路包括：驱动子电路、发光控制子电路和数据写入子电路，驱动子电路分别电连接发光控制子电路和数据写入子电路，数据写入子电路被配置为传输数据电压，发光控制子电路被配置为控制驱动子电路的导通时长，驱动子电路被配置为在导通时长内根据数据电压控制流过发光器件的电流；该驱动方法包括步骤100至步骤300。
其中，步骤100：确定显示面板所处的亮度段，该亮度段包括第一亮度段至第N亮度段，第一亮度段至第N亮度段的最大灰阶亮度依次降低，每个亮度段包括分别与第一发光单元、第二发光单元和第三发光单元对应的三个伽马校正曲线；第(N-M)亮度段至第N亮度段中的每个亮度段还分别对应至少一个占空比，该占空比为发光信号线的有效脉冲占空比，发光控制子电路根据该占空比控制驱动子电路的导通时长，N为大于1的整数，M为大于或等于0且小于N的整数；
步骤200：基于所确定的亮度段对应的伽马校正曲线和待显示图像确定至少一个发光单元对应的输入数据电压；
步骤300：基于所确定的输入数据电压，或者，基于所确定的输入数据电压和占空比，驱动该显示面板显示待显示图像，且在驱动显示第(N-M)亮度段至第N亮度段的每一帧图像时，流过每个发光器件的电流大于每个发光器件的预设基准电流，导通时长小于预设基准导通时长。
本公开实施例中，每个亮度段中的亮度值指的是“灰阶亮度”。本公开实施例中的“灰阶亮度”指的是从视觉上看到的“亮度”，即亮度探测器探测到的显示屏幕的亮度值，它和发光时间以及实际的电流亮度有关，其中，“电流亮度”是指发光器件响应所在发光单元的像素电路输出的电流发出的光的相应亮度。
本公开实施例提供的显示面板的驱动方法，通过使得在驱动显示第(N-M)亮度段至第N亮度段的每一帧图像时，流过每个发光器件的电流大于每个发光器件的预设基准电流，导通时长小于预设基准导通时长，使得低灰阶亮度时至少一个发光单元的启亮时间趋于一致，从而显著改善了拖影偏色的问题， 提高了显示面板的显示效果。
本公开实施例中，预设基准电流为数据写入子电路向至少一个发光单元的像素电路传输的数据电压为预设基准电压时，至少一个像素电路中流过每个发光器件的电流；预设基准导通时长为当第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，发光控制子电路控制驱动子电路的导通时长。
伽马校正通常采用多段(Band)模式进行调试，以保证显示亮度值(Display Brightness Value，DBV)变动时的屏幕显示效果。一般数字集成电路(Integrated Circuit，IC)会有10组以上伽马寄存器(每组对应一个段)可以用于伽马校正，以供调试DBV曲线样式。去除特殊模式的段(比如，常亮模式(Always On Display，AOD)、高亮模式(High Brightness Mode，HBM)等)，剩余段全为正常(Normal)模式。
伽马校正曲线源于早期的阴极射线管(Cathode Ray Tube，CRT)显示器的响应曲线，也就是输出亮度和输入数据电压的非线性关系。为了使显示画面更加符合人的视觉感受，需要根据伽马校正曲线对画面进行校正。伽马校正曲线描述的是二进制数(即灰阶)与输入数据电压的函数关系，通常来说，伽马校正曲线的横坐标是二进制数，纵坐标是二进制数对应的输入数据电压。伽马校正曲线使得输入数据电压与输出亮度满足以下关系：
L＝C*α γ，其中，L为输出亮度，C为系统常数，α为输入数据电压，γ为其指数。
在一种示例性实施例中，N可以为9，M可以为1或0。如图7所示，从第一段到第九段的最大灰阶亮度逐渐降低，例如，第一段的灰阶亮度范围为0至500nits，第二段的灰阶亮度范围为0至400nits，第三段的灰阶亮度范围为0至150nits，……，第九段的灰阶亮度范围为0至2nits。
如图8所示，通过仿真电路(该仿真电路中的晶体管为P型晶体管)的仿真结果可以看出，随灰阶增大，第一帧内电流电压稳定的时间是缩短的，由于灰阶越大，流过发光器件的电流越大，因此，可以得出结论，随着流过发光器件的电流变大，第四节点N4(即发光器件的阳极)电压的稳定时间大 大缩短，RGB三个发光单元的启亮速度趋于一致。
由于流过发光器件的电流变大，在不影响实际灰阶亮度情况下，需要减小发光器件的发光时长，可以通过调节发光信号线的有效脉冲占空比来调节发光器件的发光时长。发光信号线的有效脉冲占空比越大则发光器件的发光时间越长，实际灰阶亮度就越高；反之，发光信号线的有效脉冲占空比越小则发光器件的发光时间越短，实际灰阶亮度就越低。有效脉冲占空比为100％时表示发光器件具有最大的发光时长。如图9至图10所示，通过降低发光信号线的有效脉冲占空比，增大流过发光器件的电流，可以在不影响实际灰阶亮度的情况下，使得至少一个发光单元的启亮速度趋于一致，从而有效改善了图片亮暗交接边缘出现的拖影偏色的问题。
在一种示例性实施例中，第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均小于预设基准占空比。通过减小第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比，使得在驱动显示第(N-M)亮度段至第N亮度段的每一帧图像时，发光器件的导通时长小于预设基准导通时长。
在一种示例性实施例中，预设基准占空比可以为10％。
在一种示例性实施例中，第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均在1％到4％之间。示例性的，第(N-M)亮度段至第N亮度段对应一个占空比，且该占空比为2％。
在一种示例性实施例中，每个发光单元的像素电路中的多个晶体管均为P型晶体管，在第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，数据写入子电路向第一发光单元的像素电路传输的数据电压小于第一基准电压，数据写入子电路向第二发光单元的像素电路传输的数据电压小于第二基准电压，数据写入子电路向第三发光单元的像素电路传输的数据电压小于第三基准电压，第一基准电压、第二基准电压和第三基准电压分别为在第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，数据写入子电路向第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压。
本示例性实施例将减小后的第(N-M)亮度段至第N亮度段中的每个亮 度段对应的占空比和数据写入子电路向第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压直接写入驱动芯片，可以大大简化驱动芯片的计算工作量。
当第一晶体管到第七晶体管均为P型晶体管时，流过第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vdata+Vth)-Vth] 2＝K*(Vdd-Vdata) 2
通过上述公式可以看出，数据电压Vdata越低，发光器件的电流越大。由于像素电路设计过程中第二电源线VDD与开关晶体管T2的栅极走线存在交叠，即在第二电源线VDD与开关晶体管T2的栅极走线交叠位置会产生寄生电容。在寄生电容的充放电能力一致的情况下，数据电压Vdata的大小直接影响第四节点N4的电压的稳定速度。
本实施例中，在第(N-M)亮度段至第N亮度段对应的任意一条伽马校正曲线中，不同灰阶对应的第一基准电压不同，不同灰阶对应的第一数据电压也不同，但是，同一灰阶对应的第一数据电压必然小于该灰阶对应的第一基准电压。
在第(N-M)亮度段至第N亮度段对应的任意一条伽马校正曲线中，不同灰阶对应的第二基准电压不同，不同灰阶对应的第二数据电压也不同，但是，同一灰阶对应的第二数据电压必然小于该灰阶对应的第二基准电压。
在第(N-M)亮度段至第N亮度段对应的任意一条伽马校正曲线中，不同灰阶对应的第三基准电压不同，不同灰阶对应的第三数据电压也不同，但是，同一灰阶对应的第三数据电压必然小于该灰阶对应的第三基准电压。
在一种示例性实施例中，第一发光单元为红色发光单元，第二发光单元为绿色发光单元，第三发光单元为蓝色发光单元。
在一种示例性实施例中，数据写入子电路向第一发光单元的像素电路传输的数据电压约为第一基准电压的千分之五至千分之十五之间，数据写入子电路向第二发光单元的像素电路传输的数据电压约为第二基准电压的千分之十至千分之二十之间；数据写入子电路向第三发光单元的像素电路传输的数据电压约为第三基准电压的千分之六至千分之十六之间。
例如，在第九亮度段(Band 9)的某一灰阶下，当预设基准占空比为10％时，第一发光单元对应的第一基准电压为5.57V，第二发光单元对应的第二基准电压为5.8V，第三发光单元对应的第三基准电压为5.37V。此时，黑画面到白画面滑动边界的蓝色拖影比较明显。
当降低发光信号线的有效脉冲占空比至2％，且调节数据写入子电路向第一发光单元的像素电路传输的数据电压为5.52V，调节数据写入子电路向第二发光单元的像素电路传输的数据电压为5.7V，调节数据写入子电路向第三发光单元的像素电路传输的数据电压为5.31V之后，拖影问题得到大大改善，无明显偏色，视觉效果较好。本公开的驱动方法成本低廉，不需要更改硬件，具有高可实施性。
在本公开另一种示例性实施例中，第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比，在第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，数据写入子电路向第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压分别为第一基准电压、第二基准电压和第三基准电压；像素电路中的多个晶体管均为P型晶体管。
在确定至少一个发光单元对应的输入数据电压之后，所述方法还包括：当所确定的亮度段在第(N-M)亮度段至第N亮度段中时，减小所确定的亮度段对应的占空比，减小至少一个发光单元对应的输入数据电压，并使得采用减小后的占空比和减小后的至少一个发光单元对应的输入数据电压产生的亮度，与采用所述预设基准占空比和第一基准电压、第二基准电压以及第三基准电压产生的灰阶亮度相同。
在本公开另一种示例性实施例中，第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均小于预设基准占空比。
每个发光单元的像素电路中的多个晶体管均为N型晶体管，在第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，数据写入子电路向第一发光单元的像素电路传输的数据电压大于第一基准电压，数据写入子电路向第二发光单元的像素电路传输的数据电压大于第二基准电压，数据写入子电路向所述第三发光单元的像素电路传输的数据电压大于第三基准电压，第一基 准电压、第二基准电压和第三基准电压分别为在第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，数据写入子电路向第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压。
当第一晶体管到第七晶体管均为N型晶体管时(此时，可以对图4中第一晶体管T1、第七晶体管T7和存储电容C的位置进行如下调整：将第一晶体管T1的第一极与第二电源线VDD连接，第一晶体管T1的第二极仍与第二节点N2连接，第一晶体管T1的控制极仍与第二扫描信号线S2连接，将第七晶体管T7的控制极与第三扫描信号线S3连接，第七晶体管T7的第一极仍与第二初始信号线INIT2连接，第七晶体管T7的第二极仍与第四节点N4连接，将存储电容C的第一端与第四节点N4连接，存储电容C的第二端仍与第二节点N2连接，其他晶体管的位置/连接关系仍与图4中的位置/连接关系一样)，流过第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdata+Vth–Vinit2)-Vth] 2＝K*(Vdata-Vinit2) 2
通过上述公式可以看出，当第一晶体管到第七晶体管均为N型晶体管时，可以通过增大数据信号线DATA输出的数据电压Vdata来增大输入至少一个发光单元发光器件的电流，数据电压Vdata越高，发光器件的电流越大。
本实施例中，在第(N-M)亮度段至第N亮度段对应的任意一条伽马校正曲线中，不同灰阶对应的第一基准电压不同，不同灰阶对应的第一数据电压也不同，但是，同一灰阶对应的第一数据电压必然大于该灰阶对应的第一基准电压。
在第(N-M)亮度段至第N亮度段对应的任意一条伽马校正曲线中，不同灰阶对应的第二基准电压不同，不同灰阶对应的第二数据电压也不同，但是，同一灰阶对应的第二数据电压必然大于该灰阶对应的第二基准电压。
在第(N-M)亮度段至第N亮度段对应的任意一条伽马校正曲线中，不同灰阶对应的第三基准电压不同，不同灰阶对应的第三数据电压也不同，但是，同一灰阶对应的第三数据电压必然大于该灰阶对应的第三基准电压。
在本公开另一种示例性实施例中，第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比，在第(N-M)亮度段至第N亮 度段对应的多条伽马校正曲线中，数据写入子电路向第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压分别为第一基准电压、第二基准电压和第三基准电压；像素电路中的多个晶体管均为N型晶体管。
在确定至少一个发光单元对应的输入数据电压之后，所述方法还包括：当所确定的亮度段在第(N-M)亮度段至第N亮度段中时，减小所确定的亮度段对应的占空比，增大至少一个发光单元对应的输入数据电压，并使得采用减小后的占空比和增大后的至少一个发光单元对应的输入数据电压产生的亮度，与采用所述预设基准占空比和第一基准电压、第二基准电压以及第三基准电压产生的灰阶亮度相同。
本公开实施例的显示面板的驱动方法，通过增大低亮度段的至少一个发光单元对应的输入数据电压，以增大流过每个发光器件的电流，且减小发光信号线的有效脉冲占空比，以减小导通时长，在不影响实际灰阶亮度情况下实现RGB启亮速度趋于一致，在拖影过程中的第一帧或前几帧内RGB亮度匹配成白平衡，从而显著改善了拖影偏色的问题，提高了显示面板的显示效果。该方法成本低廉，不更改硬件，具有高实施性。
本公开示例性实施例还提供了一种显示面板，显示面板采用前述任一个实施例的显示面板的驱动方法驱动。
本公开示例性实施例还提供了一种显示装置，包括前述的显示面板。显示装置可以为：手机、平板电脑、电视机、显示装置、笔记本电脑、数码相框或导航仪，或任何其它具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (14)

  1. 一种显示面板的驱动方法，所述显示面板包括规则排布的多个像素单元，所述多个像素单元中的至少一个包括出射第一颜色光线的第一发光单元、出射第二颜色光线的第二发光单元和出射第三颜色光线的第三发光单元，每个发光单元包括像素电路和电连接所述像素电路的发光器件，所述像素电路包括：驱动子电路、发光控制子电路和数据写入子电路，所述驱动子电路分别电连接所述发光控制子电路和数据写入子电路，所述数据写入子电路被配置为传输数据电压，所述发光控制子电路被配置为控制驱动子电路的导通时长，所述驱动子电路被配置为在所述导通时长内根据所述数据电压控制流过所述发光器件的电流；所述驱动方法包括：
    确定显示面板所处的亮度段，所述亮度段包括第一亮度段至第N亮度段，所述第一亮度段至第N亮度段的最大灰阶亮度依次降低，每个亮度段包括分别与第一发光单元、第二发光单元和第三发光单元对应的三个伽马校正曲线；第(N-M)亮度段至第N亮度段中的每个亮度段还分别对应至少一个占空比，所述占空比为发光信号线的有效脉冲占空比，所述发光控制子电路根据所述占空比控制所述驱动子电路的导通时长，N为大于1的整数，M为大于或等于0且小于N的整数；
    基于所确定的亮度段对应的伽马校正曲线和待显示图像确定至少一个发光单元对应的输入数据电压；
    基于所确定的输入数据电压，或者，基于所确定的输入数据电压和占空比，驱动所述显示面板显示待显示图像，且在驱动显示所述第(N-M)亮度段至第N亮度段的每一帧图像时，流过每个所述发光器件的电流大于每个所述发光器件的预设基准电流，导通时长小于预设基准导通时长。
  2. 根据权利要求1所述的驱动方法，其中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均小于预设基准占空比；
    所述像素电路中的多个晶体管均为P型晶体管，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元的像素电路传输的数据电压小于第一基准电压，所述数据写入子 电路向所述第二发光单元的像素电路传输的数据电压小于第二基准电压，所述数据写入子电路向所述第三发光单元的像素电路传输的数据电压小于第三基准电压，所述第一基准电压、第二基准电压和第三基准电压分别为在所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压。
  3. 根据权利要求2所述的驱动方法，其中，所述数据写入子电路向所述第一发光单元的像素电路传输的数据电压为所述第一基准电压的千分之五至千分之十五之间，所述数据写入子电路向所述第二发光单元的像素电路传输的数据电压为所述第二基准电压的千分之十至千分之二十之间；所述数据写入子电路向所述第三发光单元的像素电路传输的数据电压为所述第三基准电压的千分之六至千分之十六之间。
  4. 根据权利要求1所述的驱动方法，其中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均小于预设基准占空比；
    所述像素电路中的多个晶体管均为N型晶体管，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元的像素电路传输的数据电压大于第一基准电压，所述数据写入子电路向所述第二发光单元的像素电路传输的数据电压大于第二基准电压，所述数据写入子电路向所述第三发光单元的像素电路传输的数据电压大于第三基准电压，所述第一基准电压、第二基准电压和第三基准电压分别为在所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比时，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压。
  5. 根据权利要求1所述的驱动方法，其中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压分别为第一基准电压、第二基准电压和第三基准电压；所述像素电路中的多 个晶体管均为P型晶体管，在确定至少一个发光单元对应的输入数据电压之后，所述方法还包括：
    当所确定的亮度段在第(N-M)亮度段至第N亮度段中时，减小所确定的亮度段对应的占空比，减小至少一个发光单元对应的输入数据电压，并使得采用减小后的占空比和减小后的至少一个发光单元对应的输入数据电压产生的亮度，与采用所述预设基准占空比和第一基准电压、第二基准电压以及第三基准电压产生的灰阶亮度相同。
  6. 根据权利要求1所述的驱动方法，其中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比为预设基准占空比，在所述第(N-M)亮度段至第N亮度段对应的多条伽马校正曲线中，所述数据写入子电路向所述第一发光单元、第二发光单元和第三发光单元的像素电路传输的数据电压分别为第一基准电压、第二基准电压和第三基准电压；所述像素电路中的多个晶体管均为N型晶体管，在确定至少一个发光单元对应的输入数据电压之后，所述方法还包括：
    当所确定的亮度段在第(N-M)亮度段至第N亮度段中时，减小所确定的亮度段对应的占空比，增大至少一个发光单元对应的输入数据电压，并使得采用减小后的占空比和增大后的至少一个发光单元对应的输入数据电压产生的亮度，与采用所述预设基准占空比和第一基准电压、第二基准电压以及第三基准电压产生的灰阶亮度相同。
  7. 根据权利要求1至6任一项所述的驱动方法，其中，N为9，M为1或0。
  8. 根据权利要求1至6任一项所述的驱动方法，其中，所述第(N-M)亮度段至第N亮度段中的每个亮度段对应的占空比均在1％到4％之间。
  9. 一种显示面板，所述显示面板采用如权利要求1至8任一项所述的显示面板的驱动方法驱动。
  10. 根据权利要求9所述的显示面板，其中，第一发光单元为红色发光单元，第二发光单元为绿色发光单元，第三发光单元为蓝色发光单元。
  11. 根据权利要求9所述的显示面板，其中，所述像素电路包括：
    第一晶体管，其控制极与第二扫描信号线连接，其第一极与第一初始信号线连接，其第二极与第二节点连接；
    第二晶体管，其控制极与第一扫描信号线连接，其第一极与第二节点连接，其第二极与第三节点连接；
    第三晶体管，其控制极与第二节点连接，其第一极与第一节点连接，其第二极与第三节点连接；
    第四晶体管，其控制极与第一扫描信号线连接，其第一极与数据信号线连接，其第二极与第一节点连接；
    第五晶体管，其控制极与发光信号线连接，其第一极与第二电源线连接，其第二极与第一节点连接；
    第六晶体管，其控制极与发光信号线连接，其第一极与第三节点连接，其第二极与发光器件的第一极连接；
    第七晶体管，其控制极与第一扫描信号线连接，其第一极与第二初始信号线连接，其第二极与发光器件的第一极连接，发光器件的第二极与第一电源线连接；
    存储电容，其第一端与第二电源线连接，其第二端与第二节点连接。
  12. 根据权利要求9所述的显示面板，其中，在垂直于所述显示面板的平面上，所述显示面板包括设置在基底上的驱动电路层、设置在所述驱动电路层上的发光结构层以及设置在所述发光结构层上的封装层，所述驱动电路层包括构成像素电路的晶体管和存储电容，所述发光结构层包括阳极、像素定义层、有机发光层和阴极。
  13. 根据权利要求9所述的显示面板，其中，所述显示面板包括显示区域和非显示区域，多个发光单元位于所述显示区域，所述显示面板包括位于所述非显示区域的扫描信号驱动器、时序控制器和时钟信号线，所述扫描信号驱动器与第一扫描信号线和第二扫描信号线连接，所述时钟信号线分别与所述时序控制器和所述扫描信号驱动器连接，所述时钟信号线被配置为在所 述时序控制器的控制下，向所述扫描信号驱动器提供时钟信号。
  14. 一种显示装置，包括如权利要求9至13任一项所述的显示面板。
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