WO2022011989A1 - 一种视频编码系统 - Google Patents

一种视频编码系统 Download PDF

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Publication number
WO2022011989A1
WO2022011989A1 PCT/CN2020/141574 CN2020141574W WO2022011989A1 WO 2022011989 A1 WO2022011989 A1 WO 2022011989A1 CN 2020141574 W CN2020141574 W CN 2020141574W WO 2022011989 A1 WO2022011989 A1 WO 2022011989A1
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module
video
output
data
image processing
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PCT/CN2020/141574
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English (en)
French (fr)
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王晓杰
卢汀
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威创集团股份有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion

Definitions

  • the present application relates to the technical field of video coding, and in particular, to a video coding system.
  • the common method of real-time encoding and sending of video is generally that the front-end video signal source is input to the video data processing module in the system module through a standard video interface, and the processed video signal stream is transmitted to the H.264 encoder, and then the encoded The video signal is output to the IP network through the network port. Since there are many input interface signals at the front end of the system module, it is not suitable for real-time flexible scheduling of video signal sources in the front end. In addition, the use of H.264 encoder is not efficient for encoding and compression, and the bandwidth utilization rate is relatively low, which is difficult to support in ultra-high-definition video applications above K.
  • the existing technology is only applicable to the video signal stream of the standard interface for the input video stream. It is difficult to realize in the front-end flexible scheduling scenario, such as the video wall field. Simultaneous scheduling of multiple video channels will increase the complexity of the front-end system and reduce reliability. .
  • the audio and video are separately encoded in the manner of splitting the audio and video encoding modules, which will lead to an increase in the complexity of the system.
  • the existing system will greatly increase the system scale year-on-year, making the overall solution more complex.
  • the embodiments of the present application provide a video coding system, which solves the technical problem that the existing video coding system is difficult to apply in a flexible scheduling scenario, and once applied to a flexible scheduling scenario, the system scale will increase and the complexity will increase.
  • the present application provides a video coding system, the system includes:
  • control module and a deserialization and image processing module, a video encoding module, a first transfer protocol module and a switch module connected in sequence;
  • the control module is respectively connected with the deserialization and image processing module, the video encoding module and the switch module;
  • the control module is used to manage the startup and running status of the video coding system
  • the deserialization and image processing module is used to deserialize the serial video signal input to the video coding system, and restore the deserialized video signal to the original video data;
  • the video encoding module is configured to perform video encoding on the original video data and output a video stream;
  • the first protocol conversion module is used to perform protocol conversion on the video code stream, and input the data after the protocol conversion to the switch module;
  • the switch module is used to output the data after the protocol conversion to the wide area network
  • the local output module is configured to receive the original video data output by the deserialization and image processing module, and convert the original video data into a standard format image for output.
  • control module further includes an alarm module
  • the alarm module is used to issue an alarm signal when an abnormality in the running state is detected.
  • the deserialization and image processing module includes an FPGA chip
  • It is used to deserialize the high-bandwidth serial video signal input to the video coding system, and restore the original video data from the deserialized video signal under the horizontal and vertical synchronization clock.
  • the local output module includes an HDMI interface chip
  • the deserialization and image processing module for receiving the original video data output by the deserialization and image processing module, and converting the original video data into a standard HDMI image for output.
  • the local output module includes an HDMI interface chip
  • the deserialization and image processing module for receiving the original video data output by the deserialization and image processing module, and converting the original video data into a standard HDMI image for output.
  • the video encoding module includes an H.265 encoder
  • a local code stream output module connected to the video encoding module
  • it also includes a network port module connected to the switch module;
  • the network port module is used to connect network devices in the wide area network, and the data output by the switch module is input into the wide area network through the network port module.
  • it also includes a second transfer protocol module connected to the switch module;
  • the second protocol conversion module is used to perform protocol conversion on the data output by the switch module, and convert it into data transmitted in the optical fiber network.
  • it also includes an optical port module connected to the second transfer protocol module;
  • the optical port module is used to connect to the optical fiber network, and the data output by the second protocol transfer module is input into the optical fiber network through the optical port module,
  • the present application has the following advantages:
  • a video encoding system including a control module, a deserialization and image processing module, a video encoding module, a first transfer protocol module and a switch module connected in sequence; the control module is respectively connected with the deserialization and image processing module , the video encoding module is connected with the switch module; it also includes a local output module connected with the deserialization and image processing module; the control module is used to manage the startup and running status of the video encoding system; the deserialization and image processing module is used to encode the input video The serial video signal of the system is deserialized, and the deserialized video signal is restored to the original video data; the video encoding module is used to encode the original video data and output the video stream; the first transfer protocol module is used to convert the Convert the video stream to the protocol, and input the converted data to the switch module; the switch module is used to output the converted data to the WAN; the local output module is used to receive the original video output from the deserialization and image
  • the application uses the deserialization and image processing module to quickly deserialize and restore the audio and video signals for the audio and video input in the flexible scheduling scenario, and the restored video and audio data can be respectively used for output to the local or to the wide area network; restoration;
  • the original video data can also be encoded by the encoder unit to output the code stream to local storage or output to the WAN for more users;
  • the control module is used to control the deserialization and image processing module, video encoding module and switch.
  • the module enables real-time monitoring of the operating status of the system to respond in real time.
  • the present application can process the input of multiple signals in real time, and can well control the simultaneous scheduling of multiple video channels.
  • FIG. 1 is a system architecture diagram of an embodiment of a video coding system of the present application
  • FIG. 2 is a system architecture diagram of another embodiment of a video coding system of the present application.
  • FIG. 3 is a schematic structural diagram of a prior art
  • FIG. 4 is a schematic structural diagram of another prior art.
  • FIG. 3 is a schematic structural diagram of a prior art
  • the system includes a video interface module, an H.264 encoding module, a physical layer interface chip, a gigabit switch, and a gigabit network port connected thereby.
  • the video interface module collects and parses the input standard video, and then transmits it to the H.264 encoding module for compression and encoding. After the physical layer protocol conversion, it is connected to the IP network through a gigabit switch and outputs the video stream.
  • the problem with this technical solution is that the input video stream is only applicable to the video signal stream of the standard interface, which is difficult to achieve in the front-end flexible scheduling scenario, such as the video wall field, and the simultaneous scheduling of multiple video channels will increase the complexity of the front-end system. degree, reducing reliability.
  • the system includes an input serial-to-parallel conversion and audio de-embedding module, a video processing module, an H.265 encoder, an audio encoding module, an audio and video multiplexing module, an IP Video stream output module.
  • the input serial-to-parallel conversion and audio de-embedding module converts the input standard video signal stream into a parallel video signal, parses the audio signal, and transmits the video processing module and audio encoding module respectively, and the processed video data will be sent to H .265 encoder performs compression encoding, and the encoded video and audio data will be simultaneously transmitted to the audio and video multiplexing module.
  • the audio and video multiplexing module multiplexes and merges the two streams and outputs them to the IP video stream output module, thereby Complete the real-time encoding and sending of the video.
  • the application uses the deserialization and image processing module to quickly deserialize and restore the audio and video signals for the audio and video input in the flexible scheduling scenario, and the restored video and audio data can be respectively used for output to the local or to the wide area network; restoration;
  • the original video data can also be encoded by the encoder unit to output the code stream to local storage or output to the WAN for more users;
  • the control module is used to control the deserialization and image processing module, video encoding module and switch. The module enables real-time monitoring of the operating status of the system to respond in real time.
  • the present application can process the input of multiple signals in real time, and can well control the simultaneous scheduling of multiple video channels.
  • the problem existing in this technical solution is that the audio and video are separately encoded in the manner of splitting the audio and video encoding modules, which will lead to an increase in the complexity of the system.
  • the existing system will greatly increase the system scale year-on-year, making the overall solution more complex.
  • FIG. 1 is a system architecture diagram of an embodiment of a video coding system of the present application. As shown in FIG. 1, FIG. 1 includes:
  • control module 101 and a deserialization and image processing module 102, a video encoding module 103, a first transfer protocol module 104, and a switch module 105 connected in sequence;
  • the control module 101 is respectively connected with the deserialization and image processing module 102, the video encoding module 103 and the switch module 105;
  • the control module 101 is used to manage the startup and running status of the video coding system
  • the deserialization and image processing module 102 is used to deserialize the serial video signal input to the video coding system, and restore the deserialized video signal to the original video data;
  • the video encoding module 103 is used to perform video encoding on the original video data, and output a video stream;
  • the first protocol conversion module 104 is used to perform protocol conversion on the video stream, and input the data after the protocol conversion to the switch module 105;
  • the switch module 105 is used to output the data after the protocol conversion to the wide area network
  • the local output module 106 is configured to receive the original video data output by the deserialization and image processing module, and convert the original video data into standard format images for output.
  • the input in this application can be input through a high-bandwidth multi-channel video signal, that is, multi-channel serial video signals can be received at the same time, and the audio data corresponding to the screen can also be input together with the video signal;
  • the input signal First enter the deserialization and image processing module 102, in the deserialization and image processing module 102, the deserialization of the multi-channel video signals is completed, and the deserialized multiple video signals are restored to the original video data.
  • the original video data is subjected to operations such as image overlay and/or scaling; the video signal processed by the deserialization and image processing module 102 can be converted into a standard format video suitable for local output through the local output module 106 for local output.
  • multi-channel video data can be output on the local video wall device; the video signal processed by the deserialization and image processing module 102 can also be compressed and encoded by the video encoding module 103, and the compressed video stream data It can be saved locally or transmitted to the WAN for use by other users; specifically, the video stream data transmitted to the WAN can first pass through the first transfer protocol module 104 to perform protocol conversion on the video stream data, so that Because it can be spread in the wide area network; the data after the protocol conversion can pass through the switch module, so that the video data can interact with the wide area network.
  • the present application also includes a control module, which controls the deserialization and image processing module 102, the video encoding module 103, and the switch module 105 to be connected to complete the control of processes such as video deserialization, image processing, video encoding, and network interaction. It realizes the monitoring of the startup and running status of the video coding system and the scheduling of video streams.
  • a control module which controls the deserialization and image processing module 102, the video encoding module 103, and the switch module 105 to be connected to complete the control of processes such as video deserialization, image processing, video encoding, and network interaction. It realizes the monitoring of the startup and running status of the video coding system and the scheduling of video streams.
  • the application uses the deserialization and image processing module to quickly deserialize and restore the audio and video signals for the audio and video input in the flexible scheduling scenario, and the restored video and audio data can be respectively used for output to the local or to the wide area network; restoration;
  • the original video data can also be encoded by the encoder unit to output the code stream to local storage or output to the WAN for more users;
  • the control module is used to control the deserialization and image processing module, video encoding module and switch.
  • the module enables real-time monitoring of the operating status of the system to respond in real time.
  • the present application can process the input of multiple signals in real time, and can well control the simultaneous scheduling of multiple video channels.
  • control module 101 further includes an alarm module; the alarm module is configured to issue an alarm signal when an abnormality in the running state is detected.
  • control module can monitor the abnormal signal in real time and issue an alarm signal.
  • the deserialization and image processing module 102 includes an FPGA chip; it is used to deserialize the high-bandwidth serial video signal input to the video coding system, and deserialize the deserialized video signal under the horizontal and vertical synchronization clock.
  • the video signal restores the original video data.
  • the FPGA chip in this application can directly receive the input high-bandwidth serial video signal, and complete the deserialization of the high-bandwidth serial video signal inside the FPGA, and then restore the video signal to the horizontal and vertical synchronization clock.
  • Raw video data in addition, image processing can be completed inside the FPGA, including but not limited to image overlay and scaling.
  • the local output module includes an HDMI interface chip; it is used for receiving the original video data output by the deserialization and image processing module, and converting the original video data into a standard HDMI image for output.
  • the HDMI interface chip can replace the processed video data output by the FPGA chip with a standard HDMI image for output, and output it to a local playback device.
  • the number of HDMI interface chips is multiple; the multiple HDMI interface chips are used to output multiple standard HDMI images locally.
  • the multiple HDMI interface chips can convert all the multiple video data output by the FPGA chip into standard HDMI images for output, for example, can be output to a local video wall.
  • the video encoding module 103 includes an H.265 encoder, which is used to perform video encoding on the original video data, and output a code stream in an H.265 encoding format.
  • H.265 encoder to encode the video data output by the FPGA chip can improve the video compression efficiency and can be used to play ultra-high-definition video data.
  • a local code stream output module connected to the video encoding module 103 is also included; it is used for outputting the video code stream to the local device.
  • the local code stream output module can be used to output the video code stream data encoded by the H.265 encoder to the local for preservation and storage.
  • it also includes a network port module connected to the switch module 105; the network port module is used to connect network devices in the wide area network, and the data output by the switch module 105 is input into the wide area network through the network port module.
  • a second protocol conversion module connected to the switch module is also included; the second protocol conversion module is used to perform protocol conversion on the data output by the switch module, and convert it into data transmitted in the optical fiber network.
  • it also includes an optical port module connected to the second transfer protocol module; the optical port module is used to connect to the optical fiber network, and the data output by the second transfer protocol module is input to the optical fiber network through the optical port module middle.
  • the video stream data encoded by the H.265 encoder after the video stream data encoded by the H.265 encoder has undergone protocol conversion, it can flow into the WAN through the switch module 105 through the network port; The protocol format of the transmission in the medium, so that the data after the protocol conversion can enter the optical network through the optical port for transmission.
  • the present application also provides a system architecture diagram of another embodiment of a video coding system, as shown in FIG. 2 , which includes:
  • the FPGA module, the H.265 encoding module, the physical layer chip module, the gigabit switch module and the gigabit network port module are connected in sequence; the FPGA module is respectively connected with two HDMI interface chips; the H.265 encoding module is connected with the HDMI output interface
  • the gigabit switch module, the physical chip layer and the gigabit optical port are connected in sequence; and also includes a control module respectively connected with the FPGA module, the H.265 encoding module and the gigabit switch module.
  • the serial video signal completes the high-speed video signal deserialization and image processing in the FPGA module, and is output to the HDMI interface chip for local output of two video images.
  • the video data will also be sent to the H.265 encoder for video compression encoding, and the H.265 encoder is connected to the local area network of the Gigabit switch after the protocol conversion of the physical layer chip, and the network port or optical port selected by the user is used.
  • the H.265 encoder connected to the network can provide other users with compressed and encoded video data; in addition, there is a control module in the video encoding system, which is used to control the startup and status of each module in the system monitoring and other functions.
  • the FPGA directly receives the input high-bandwidth serial video signal, completes the deserialization within the FPGA, and restores the original video data under the horizontal and vertical synchronization clock.
  • image processing is completed within the FPGA, including but not limited to image overlay. and zoom etc.
  • the processed video image information will be transmitted to the HDMI interface chip and the H.265 encoder respectively.
  • the HDMI interface chip receives the video image information, it outputs the standard HDMI image locally, and the H.265 encoder receives the video image data. Then realize H.265 encoding, and connect to Ethernet to complete the output of IP video stream.
  • the FPGA is used as the video input interface, so that the input video data can be transmitted through a pair of high-bandwidth differential SERDES signals.
  • Multiple pairs of SERDES signals receive multiple pictures, each pair of SERDES signals has a bandwidth of up to 6Gbps, and the audio corresponding to the picture is also transmitted together on the SERDES channel.
  • the audio and video are all analyzed and processed inside the FPGA, and there is no need to add additional processing devices.
  • At least one (item) refers to one or more, and "a plurality” refers to two or more.
  • “And/or” is used to describe the relationship between related objects, indicating that there can be three kinds of relationships, for example, “A and/or B” can mean: only A, only B, and both A and B exist , where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • At least one item(s) below” or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ", where a, b, c can be single or multiple.

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Abstract

本申请公开了一种视频编码系统，包括：控制模块，以及依次相连的解串及图像处理模块、视频编码模块、第一转协议模块及交换机模块；控制模块分别与解串及图像处理模块、视频编码模块及交换机模块相连；还包括与解串及图像处理模块相连的本地输出模块。本申请解决了现有视频编码系统难以应用于灵活调度场景下，且一旦应用于灵活调度场景下会导致系统规模加大，复杂度变高的技术问题。

Description

一种视频编码系统
本申请要求于2020年07月16日提交中国专利局、申请号为202010685649.7、发明名称为“一种视频编码系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及视频编码技术领域，尤其涉及一种视频编码系统。
背景技术
视频的实时编码与发送的常用方法一般为前端视频信号源通过标准的视频接口输入到系统模块中的视频数据处理模块，把处理后的视频信号流传输到H.264编码器，再把编码后的视频信号经由网口输出至IP网络。由于该系统模块前端的输入接口信号较多，在前端实现视频信号源的实时灵活调度时不适用。并且使用H.264编码器对编码压缩效率不高，带宽利用率相对较低，在K以上的超高清视频应用上较难支持。
现有技术对输入视频流均只适用于标准接口视频信号流，在前端的灵活调度场景下如拼接墙领域较难实现，多路的视频信道的同时调度会加重前端系统复杂度，降低可靠性。并且现有技术中采用拆分音视频编码模块的方式分别对音频和视频进行编码，会导致系统的复杂度提高。在多画面、高带宽的调度使用场景下，现有系统会同比大幅增加系统规模，使得整体方案复杂度较高。
发明内容
本申请实施例提供了一种视频编码系统，解决了现有视频编码系统难以应用于灵活调度场景下，且一旦应用于灵活调度场景下会导致系统规模加大，复杂度变高的技术问题。
有鉴于此，本申请提供了一种视频编码系统，所述系统包括：
控制模块，以及依次相连的解串及图像处理模块、视频编码模块、第一转协议模块及交换机模块；
所述控制模块分别与所述解串及图像处理模块、所述视频编码模块及所述交换机模块相连；
还包括与所述解串及图像处理模块相连的本地输出模块；
所述控制模块用于管理视频编码系统的启动及运行状态；
所述解串及图像处理模块用于对输入视频编码系统的串行视频信号进行解串，及将解串后的视频信号恢复至原始视频数据；
所述视频编码模块用于将所述原始视频数据进行视频编码，输出视频码流；
所述第一转协议模块用于将所述视频码流进行协议转换，并将协议转换后的数据输入至所述交换机模块；
所述交换机模块用于将协议转换后的数据输出至广域网中；
所述本地输出模块用于接收所述解串及图像处理模块输出的所述原始视频数据，并将所述原始视频数据转换成标准格式图像进行输出。
可选的，所述控制模块还包括报警模块；
所述报警模块用于当检测到运行状态出现异常时，发出报警信号。
可选的，所述解串及图像处理模块包括FPGA芯片；
用于对输入视频编码系统的高带宽串行视频信号进行解串，并在行场同步时钟下将解串后的视频信号恢复原始视频数据。
可选的，所述本地输出模块包括HDMI接口芯片；
用于接收所述解串及图像处理模块输出的所述原始视频数据，并将所述原始视频数据转换成标准HDMI图像进行输出。
可选的，所述本地输出模块包括HDMI接口芯片；
用于接收所述解串及图像处理模块输出的所述原始视频数据，并将所述原始视频数据转换成标准HDMI图像进行输出。
可选的，所述视频编码模块包括H.265编码器；
用于将所述原始视频数据进行视频编码，输出H.265编码格式的码流。
可选的，与所述视频编码模块相连的本地码流输出模块；
用于将所述视频码流输出至本地设备。
可选的，还包括与所述交换机模块相连的网口模块；
所述网口模块用于连接广域网中的网络设备，所述交换机模块输出的数据经过所述网口模块输入广域网中。
可选的，还包括与所述交换机模块相连的第二转协议模块；
所述第二转协议模块用于将所述交换机模块输出的数据进行协议转换，转换成光纤网络中传输的数据。
可选的，还包括与所述第二转协议模块相连的光口模块；
所述光口模块用于连接至光纤网络中，所述第二转协议模块输出的数据经过所述光口模块输入至光纤网络中，
从以上技术方案可以看出，本申请具有以下优点：
本申请中，提供了一种视频编码系统，包括控制模块，以及依次相连的解串及图像处理模块、视频编码模块、第一转协议模块及交换机模块；控制模块分别与解串及图像处理模块、视频编码模块及交换机模块相连；还包括与解串及图像处理模块相连的本地输出模块；控制模块用于管理视频编码系统的启动及运行状态；解串及图像处理模块用于对输入视频编码系统的串行视频信号进行解串，及将解串后的视频信号恢复至原始视频数据；视频编码模块用于将原始视频数据进行视频编码，输出视频码流；第一转协议模块用于将视频码流进行协议转换，并将协议转换后的数据输入至交换机模块；交换机模块用于将协议转换后的数据输出至广域网中；本地输出模块用于接收解串及图像处理模块输出的原始视频数据，并将原始视频数据转换成标准格式图像进行输出。
本申请通过针对灵活调度场景中的音视频输入，采用解串及图像处理模块对音视频信号进行快速解串和恢复，恢复后的视频音频数据可以分别用于输出至本地或者输出至广域网；恢复后的原始视频数据还可以通过编码器单元进行编码用于输出码流至本地存储或者输出至广域网中供更多用户使用；控制模块用于控制解串及图像处理模块、视频编码模块及及交换机模块，使得能够实时监测系统的运行状态，从而实时做出反应。本申请通过控制模块对解串及图像处理模块、视频编码模块及及交换机模块的联合调度，能够实时处理多路信号的输入，并能够很好的控制多路的视频信道的同时调度。
附图说明
图1为本申请一种视频编码系统的一个实施例的系统架构图；
图2为本申请一种视频编码系统的另一个实施例的系统架构图；
图3为一种现有技术的结构示意图；
图4为另一种现有技术的结构示意图。
具体实施方式
如图3所示的一种现有技术的结构示意图，该系统包括以此连接的视频接口模块、H.264编码模块、物理层接口芯片、千兆交换机、千兆网口。视频接口模块对输入的标准视频进行采集、解析，然后传输给H.264编码模块进行压缩编码，经物理层协议转换后通过千兆交换机接入到IP网络，输出视频码流。该技术方案存在的问题是，对输入视频流均只适用于标准接口视频信号流，在前端的灵活调度场景下如拼接墙领域较难实现，多路的视频信道的同时调度会加重前端系统复杂度，降低可靠性。
如图4所示的另一种现有技术的结构示意图，该系统包括输入串并转换及音频解嵌模块、视频处理模块、H.265编码器、音频编码模块、音视频复用模块、IP视频流输出模块。输入串并转换及音频解嵌模块对输入的标准视频信号流转化为并行视频信号，并解析其中的音频信号，分别传输视频处理模块和音频编码模块，经处理过的视频数据会被发送至H.265编码器进行压缩编码，而编码后的视频和音频数据会被同时传输至音视频复用模块，音视频复用模块把两个码流复用合并后输出至IP视频流输出模块，从而完成视频的实时编码发送。
本申请通过针对灵活调度场景中的音视频输入，采用解串及图像处理模块对音视频信号进行快速解串和恢复，恢复后的视频音频数据可以分别用于输出至本地或者输出至广域网；恢复后的原始视频数据还可以通过编码器单元进行编码用于输出码流至本地存储或者输出至广域网中供更多用户使用；控制模块用于控制解串及图像处理模块、视频编码模块及及交换机模块，使得能够实时监测系统的运行状态，从而实时做出反应。本申请通过控制模块对解串及图像处理模块、视频编码模块及及交换机模块的联合调度，能够实时处理多路信号的输入，并能够很好的控制多路的视频信道的同时调度。该技术方案存在的问题是，采用拆分音视频编码模块的方式分别对音频和视频进行编码，会导致系统的复杂度提高。在多画面、高带宽的调度使用场景下，现有系统会同比大幅增加系统规模，使得整体方 案复杂度较高。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，图1为本申请一种视频编码系统的一个实施例的系统架构图，如图1所示，图1中包括：
控制模块101，以及依次相连的解串及图像处理模块102、视频编码模块103、第一转协议模块104及交换机模块105；
控制模块101分别与解串及图像处理模块102、视频编码模块103及交换机模块105相连；
还包括与解串及图像处理模块102相连的本地输出模块106；
控制模块101用于管理视频编码系统的启动及运行状态；
解串及图像处理模块102用于对输入视频编码系统的串行视频信号进行解串，及将解串后的视频信号恢复至原始视频数据；
视频编码模块103用于将原始视频数据进行视频编码，输出视频码流；
第一转协议模块104用于将视频码流进行协议转换，并将协议转换后的数据输入至交换机模块105；
交换机模块105用于将协议转换后的数据输出至广域网中；
本地输出模块106用于接收解串及图像处理模块输出的原始视频数据，并将原始视频数据转换成标准格式图像进行输出。
具体的，本申请中的输入可以是通过高带宽的多路视频信号作为输入，即可以同时接收多路串行视频信号，同时画面对应的音频数据也可以随视频信号一起作为输入；输入的信号首先进入到解串及图像处理模块102，在解串及图像处理模块102中完成对多路视频信号的解串，并将解串后的多个视频信号恢复至原始视频数据，并且还能够对原始视频数据进行图像叠加和/或缩放等操作；经过解串及图像处理模块102处理后的视频信号可以经过本地输出模块106转换成适合于本地输出的标准格式视频，用于在本地进行输出，例如可以在本地的视频墙设备上输出多路视频数据；经过 解串及图像处理模块102处理后的视频信号还可以经过视频编码模块103，对视频信号进行压缩编码，压缩后的视频码流数据可以保存至本地，也可以传输至广域网中供其他用户使用；具体的，传输至广域网中的视频码流数据可以先经过第一转协议模块104，用于将视频码流数据进行协议转换，以便于能够在广域网中传播；协议转换后的数据可以通过交换机模块，使得视频数据与广域网进行交互。另外，本申请中还包括控制模块，通过控制解串及图像处理模块102、视频编码模块103及交换机模块105相连，完成对视频解串、图像处理、视频编码及网络交互等过程的控制，从而实现对视频编码系统的启动及运行状态的监控以及对视频流的调度。
本申请通过针对灵活调度场景中的音视频输入，采用解串及图像处理模块对音视频信号进行快速解串和恢复，恢复后的视频音频数据可以分别用于输出至本地或者输出至广域网；恢复后的原始视频数据还可以通过编码器单元进行编码用于输出码流至本地存储或者输出至广域网中供更多用户使用；控制模块用于控制解串及图像处理模块、视频编码模块及及交换机模块，使得能够实时监测系统的运行状态，从而实时做出反应。本申请通过控制模块对解串及图像处理模块、视频编码模块及及交换机模块的联合调度，能够实时处理多路信号的输入，并能够很好的控制多路的视频信道的同时调度。
在一种具体的实施方式中，控制模块101还包括报警模块；报警模块用于当检测到运行状态出现异常时，发出报警信号。
需要说明的是，当系统中出现解串及图像处理模块、视频编码模块以及交换机模块出现运行状态异常时，控制模块可以实时监测异常信号，并发出报警信号。
在一种具体的实施方式中，解串及图像处理模块102包括FPGA芯片；用于对输入视频编码系统的高带宽串行视频信号进行解串，并在行场同步时钟下将解串后的视频信号恢复原始视频数据。
需要说明的是，本申请中FPGA芯片可以直接接收输入的高带宽串行视频信号，并在FPGA内部将高带宽串行视频信号完成解串化，之后在行场同步时钟下将视频信号恢复成原始视频数据；另外还可以在FPGA内部完成图像处理，包括但不限于图像叠加和缩放等。
在一种具体的实施方式中，本地输出模块包括HDMI接口芯片；用于接收解串及图像处理模块输出的原始视频数据，并将原始视频数据转换成标准HDMI图像进行输出。
需要说明的是，HDMI接口芯片可以将FPGA芯片输出的处理后的视频数据装换成标准HDMI图像进行输出，并输出至本地的播放设备。
在一种具体的实施方式中，HDMI接口芯片的数目为多个；多个HDMI接口芯片用于将多路标准HDMI图像在本地进行输出。
需要说明的是，多个HDMI接口芯片可以将FPGA芯片输出的多个视频数据全都转换成标准的HDMI图像进行输出，例如可以输出至本地的拼接墙上。
在一种具体的实施方式中，视频编码模块103包括H.265编码器；用于将原始视频数据进行视频编码，输出H.265编码格式的码流。
需要说明的是，采用H.265编码器来编码FPGA芯片输出的视频数据，可以提高视频压缩效率，并能够用来播放超高清视频数据。
在一种具体的实施方式中，还包括与视频编码模块103相连的本地码流输出模块；用于将视频码流输出至本地设备。
需要说明的是，本地码流输出模块可以用于将H.265编码器编码之后的视频码流数据输出到本地进行保存储。
在一种具体的实施方式中，还包括与交换机模块105相连的网口模块；网口模块用于连接广域网中的网络设备，交换机模块105输出的数据经过网口模块输入广域网中。
在一种具体的实施方式中，还包括与交换机模块相连的第二转协议模块；第二转协议模块用于将交换机模块输出的数据进行协议转换，转换成光纤网络中传输的数据。
在一种具体的实施方式中，还包括与第二转协议模块相连的光口模块；光口模块用于连接至光纤网络中，第二转协议模块输出的数据经过光口模块输入至光纤网络中。
需要说明的是，经过H.265编码器编码之后的视频码流数据经过协议转换之后，可以通过交换机模块105，经过网口流入到广域网中；或者再经过协议转换，转换成适合于在光网络中传输的协议格式，使得协议转换 后的数据能够通过光口进入到光网络中传输。
本申请还提供了一种视频编码系统的另一个实施例的系统架构图，如图2所示，图2中包括：
依次连接的FPGA模块、H.265编码模块、物理层芯片模块、千兆交换机模块以及千兆网口模块；其中FPGA模块分别与两个HDMI接口芯片相连；H.265编码模块与HDMI输出接口相连；千兆交换机模块、物理芯片层以及千兆光口依次相连；并且还包括分别与FPGA模块、H.265编码模块以及千兆交换机模块相连的控制模块。
当输入为一对高速SERDES串行视频信号后，串行视频信号在FPGA模块完成高速视频信号的解串化以及图像处理，并输出至HDMI接口芯片，用于本地输出两路视频图像，经过处理的视频数据还会发送至H.265编码器进行视频压缩编码，而H.265编码器经过物理层芯片的协议转换后接入到千兆交换机的局域网络，通过用户选择的网口或光口在接入到广域网，接入网络的H.265编码器即可为其他用户提供压缩编码后的视频数据；另外，视频编码系统中还有控制模块，用于控制系统中各模块的启动与状态监控等功能。
在该系统中FPGA直接接收输入的高带宽串行视频信号，在FPGA内部完成解串化，并在行场同步时钟下恢复原始视频数据，同时在FPGA内部完成图像处理，包括但不限于图像叠加和缩放等。而处理后的视频图像信息会分别传输至HDMI接口芯片和H.265编码器处，HDMI接口芯片接收到视频图像信息后在本地输出标准的HDMI图像，H.265编码器接收到视频图像数据后则实现H.265编码，并接入以太网完成IP视频流的输出。在硬件电路上还有一个控制模块用于管理单板启动及运行状态，当单板上器件运行异常时可以实时监测并发出警告。
其中使用FPGA作为视频输入接口，可使得输入的视频数据通过一对高带宽的差分SERDES信号进行传输。多对SERDES信号接收多幅画面，每对SERDES信号高达6Gbps的带宽，同时画面对应的音频也在该SERDES通道被一起传输。音视频均在FPGA内部完成解析处理，无需另外添加处理器件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述 描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
本申请的说明书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列模块的系统不必限于清楚地列出的模块，而是可包括没有清楚地列出的或对于这些模块固有的其它模块。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种视频编码系统，其特征在于，包括：控制模块，以及依次相连的解串及图像处理模块、视频编码模块、第一转协议模块及交换机模块；
    所述控制模块分别与所述解串及图像处理模块、所述视频编码模块及所述交换机模块相连；
    还包括与所述解串及图像处理模块相连的本地输出模块；
    所述控制模块用于管理视频编码系统的启动及运行状态；
    所述解串及图像处理模块用于对输入视频编码系统的串行视频信号进行解串，及将解串后的视频信号恢复至原始视频数据；
    所述视频编码模块用于将所述原始视频数据进行视频编码，输出视频码流；
    所述第一转协议模块用于将所述视频码流进行协议转换，并将协议转换后的数据输入至所述交换机模块；
    所述交换机模块用于将协议转换后的数据输出至广域网中；
    所述本地输出模块用于接收所述解串及图像处理模块输出的所述原始视频数据，并将所述原始视频数据转换成标准格式图像进行输出。
  2. 根据权利要求1所述的视频编码系统，其特征在于，所述控制模块还包括报警模块；
    所述报警模块用于当检测到运行状态出现异常时，发出报警信号。
  3. 根据权利要求1所述的视频编码系统，其特征在于，所述解串及图像处理模块包括FPGA芯片；
    用于对输入视频编码系统的高带宽串行视频信号进行解串，并在行场同步时钟下将解串后的视频信号恢复原始视频数据。
  4. 根据权利要求1所述的视频编码系统，其特征在于，所述本地输出模块包括HDMI接口芯片；
    用于接收所述解串及图像处理模块输出的所述原始视频数据，并将所述原始视频数据转换成标准HDMI图像进行输出。
  5. 根据权利要求4所述的视频编码系统，其特征在于，所述HDMI接口芯片的数目为多个；
    多个所述HDMI接口芯片用于将多路标准HDMI图像在本地进行输出。
  6. 根据权利要求1所述的视频编码系统，其特征在于，所述视频编码模块包括H.265编码器；
    用于将所述原始视频数据进行视频编码，输出H.265编码格式的码流。
  7. 根据权利要求1所述的视频编码系统，其特征在于，还包括：与所述视频编码模块相连的本地码流输出模块；
    用于将所述视频码流输出至本地设备。
  8. 根据权利要求1所述的视频编码系统，其特征在于，还包括与所述交换机模块相连的网口模块；
    所述网口模块用于连接广域网中的网络设备，所述交换机模块输出的数据经过所述网口模块输入广域网中。
  9. 根据权利要求1所述的视频编码系统，其特征在于，还包括与所述交换机模块相连的第二转协议模块；
    所述第二转协议模块用于将所述交换机模块输出的数据进行协议转换，转换成光纤网络中传输的数据。
  10. 根据权利要求9所述的视频编码系统，其特征在于，还包括与所述第二转协议模块相连的光口模块；
    所述光口模块用于连接至光纤网络中，所述第二转协议模块输出的数据经过所述光口模块输入至光纤网络中。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114760478A (zh) * 2022-03-08 2022-07-15 江苏泽汇泓智能科技有限公司 一种低码流高清视频处理终端及视频监控系统
CN114866733A (zh) * 2022-03-22 2022-08-05 感知信息科技(浙江)有限责任公司 一种低延迟视频处理方法、系统及装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111757128B (zh) * 2020-07-16 2021-12-07 威创集团股份有限公司 一种视频编码系统
CN115550569B (zh) * 2022-11-24 2023-03-10 基石酷联微电子技术（北京）有限公司 一种音视频收发器及矩阵系统

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102630000A (zh) * 2012-04-18 2012-08-08 天津天地伟业数码科技有限公司 8路sdi嵌入式硬盘录像机
CN104320615A (zh) * 2014-10-17 2015-01-28 智擎信息系统（上海）有限公司 一种智能视频安防系统及其信号处理方法
US10097818B1 (en) * 2016-12-27 2018-10-09 Advanced Testing Technologies, Inc. Video processor with digital video signal processing capabilities
CN108924477A (zh) * 2018-06-01 2018-11-30 北京图森未来科技有限公司 一种远距离视频处理方法和系统、视频处理设备
CN209692943U (zh) * 2019-06-27 2019-11-26 北京多铁克数字技术有限公司 高标清视频兼容的视音频编码器
CN111757128A (zh) * 2020-07-16 2020-10-09 威创集团股份有限公司 一种视频编码系统

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101001118A (zh) * 2007-01-09 2007-07-18 深圳洪迪实业有限公司 多路级联光端机系统
US7656323B2 (en) * 2007-05-31 2010-02-02 Altera Corporation Apparatus for all-digital serializer-de-serializer and associated methods
CN101500169B (zh) * 2009-03-10 2013-03-13 武汉大学 多路音视频压缩传输服务器
CN101577598A (zh) * 2009-06-03 2009-11-11 深圳华为通信技术有限公司 多路信号复用、解复用的方法、装置和系统
CN101799550B (zh) * 2010-03-19 2013-08-14 北京东方联星科技有限公司 基于数字中频信号串行传输的卫星导航接收机和方法
TW201406159A (zh) * 2012-07-18 2014-02-01 Terawins Inc 監控系統、影像壓縮串行器以及影像解壓縮解串行器
CN203120054U (zh) * 2013-01-31 2013-08-07 深圳洪迪实业有限公司 一种可远距离监控的摄像机
EP3412027B1 (en) * 2016-02-12 2024-04-24 Huawei Technologies Co., Ltd. Method and apparatus for scan order selection
CN208836229U (zh) * 2018-12-03 2019-05-07 重庆哆来目科技有限公司 一种基于车载摄像头判断车辆行驶方向和速度的装置
CN111147828A (zh) * 2019-12-23 2020-05-12 威创集团股份有限公司 一种低延时视频光纤传输装置
CN110896431B (zh) * 2019-12-23 2023-12-29 中国电子科技集团公司第三十四研究所 一种无压缩高清视频传输方法和系统

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102630000A (zh) * 2012-04-18 2012-08-08 天津天地伟业数码科技有限公司 8路sdi嵌入式硬盘录像机
CN104320615A (zh) * 2014-10-17 2015-01-28 智擎信息系统（上海）有限公司 一种智能视频安防系统及其信号处理方法
US10097818B1 (en) * 2016-12-27 2018-10-09 Advanced Testing Technologies, Inc. Video processor with digital video signal processing capabilities
CN108924477A (zh) * 2018-06-01 2018-11-30 北京图森未来科技有限公司 一种远距离视频处理方法和系统、视频处理设备
CN209692943U (zh) * 2019-06-27 2019-11-26 北京多铁克数字技术有限公司 高标清视频兼容的视音频编码器
CN111757128A (zh) * 2020-07-16 2020-10-09 威创集团股份有限公司 一种视频编码系统

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114760478A (zh) * 2022-03-08 2022-07-15 江苏泽汇泓智能科技有限公司 一种低码流高清视频处理终端及视频监控系统
CN114866733A (zh) * 2022-03-22 2022-08-05 感知信息科技(浙江)有限责任公司 一种低延迟视频处理方法、系统及装置

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