WO2022001130A1 - 一种用于硬盘端口号灵活分配的硬件架构及其实现方法 - Google Patents

一种用于硬盘端口号灵活分配的硬件架构及其实现方法 Download PDF

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Publication number
WO2022001130A1
WO2022001130A1 PCT/CN2021/076923 CN2021076923W WO2022001130A1 WO 2022001130 A1 WO2022001130 A1 WO 2022001130A1 CN 2021076923 W CN2021076923 W CN 2021076923W WO 2022001130 A1 WO2022001130 A1 WO 2022001130A1
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Prior art keywords
hard disk
phy
card
port numbers
expander
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PCT/CN2021/076923
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English (en)
French (fr)
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王海波
葛志华
龚诗悦
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苏州浪潮智能科技有限公司
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Publication of WO2022001130A1 publication Critical patent/WO2022001130A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device

Definitions

  • the invention relates to the technical field of computers, in particular to a hardware architecture for flexible allocation of hard disk port numbers and an implementation method thereof.
  • some Internet users may not want to adjust the upper-layer software architecture as the underlying hardware architecture becomes increasingly complex; this requires that the server's operating system OS (operational system) be adjusted without adjusting the upper-layer software architecture. system) to read and write hard disk data from a fixed port on the hard disk; alternatively, the port numbers assigned to all hard disks in the operating system OS of all hard disks can be flexibly configured according to user needs, that is, a set of application layer software should be adapted to all hard disks.
  • the server that stores the architecture.
  • the hardware design of the storage server in the prior art is shown in Figure 1, and the platform control center PCH (Platform Controller Hub) of the storage server directly connects to the hard disk on the backplane of the HDD (Hard Disk Drive, hard disk drive) through the serial hard disk SATA interface.
  • HDD Hard Disk Drive, hard disk drive
  • this hardware design architecture cannot meet the above-mentioned needs of users at all.
  • the port number of the hard disk is randomly assigned under the operating system OS, so the port number of the hard disk is uncontrollable.
  • some specific Internet users use some hard disk ports as fixed use in order to not modify the upper-layer software architecture.
  • the present invention provides a hardware architecture for flexibly assigning hard disk port numbers and an implementation method thereof, aiming to solve the problem in the prior art that the port numbers assigned by the operating system OS to all hard disks cannot be flexibly set according to user requirements.
  • the present invention proposes a hardware architecture for flexible allocation of hard disk port numbers, including:
  • the server motherboard is connected to the hard disk backplane through the Raid card and the Expander card, and is used to assign hard disk port numbers to multiple hard disks according to the logical phy stored in the Expander card;
  • Expander card includes: Expander chip and port physical layer phy write module;
  • the Expander chip is connected between the Raid card and the hard disk backplane, and includes a rewritable memory.
  • the rewritable memory stores the corresponding relationship between logical phy and physical phy, wherein physical phy corresponds to multiple hard disks.
  • the phy writing module is electrically connected to the rewritable memory, and is used for erasing the correspondence between the logical phy and the physical phy in the rewritable memory.
  • the hard disk backplane includes:
  • Multiple disk HDDs and/or multiple solid-state disk SSDs and SAS and SATA dual-purpose interfaces respectively connected to the multiple HDDs or SSDs, and the SAS and SATA dual-purpose interfaces are used to connect the Expander card.
  • the server motherboard includes:
  • Central processing unit CPU wherein, the CPU and the Raid card are electrically connected through a high-speed serial computer expansion bus PCIE link; the Raid card is provided with a serially connected small computer system SAS interface, and the SAS interface is used to connect the Expander card.
  • the hardware architecture for flexible allocation of hard disk port numbers further includes a power-on sequence control circuit; the power-on sequence of the power-on sequence control circuit is the hard disk backplane, the Expander card, the Raid card and the server motherboard in sequence.
  • the power-on sequence control circuit includes:
  • CPLD complex programmable logic device
  • baseboard management controller and a power-on control power supply arranged in the server motherboard
  • the second CPLD, the first voltage regulator and the first on-board power supply are arranged in the Raid card and connected in sequence;
  • the third CPLD, the second voltage regulator and the second in-board power supply are arranged in the Expander card and connected in sequence;
  • a fourth CPLD, a third voltage regulator and a third in-board power supply that are arranged in the hard disk backplane and are connected in sequence;
  • the power-on control power supply is respectively electrically connected with the first voltage regulator, the second voltage regulator and the third voltage regulator;
  • the baseboard management controller is respectively electrically connected with the first CPLD, the second CPLD, the third CPLD and the fourth CPLD through an integrated circuit bus.
  • the plurality of hard disks include a plurality of hard disk drives (HDDs) and/or solid-state hard disks (SSDs);
  • HDDs hard disk drives
  • SSDs solid-state hard disks
  • the hard disk backplane includes SAS and SATA dual-purpose interfaces respectively connected to the plurality of HDDs or SSDs, and the SAS and SATA dual-purpose interfaces are used to connect the Expander card.
  • the Expander card is respectively connected to the Raid card and the hard disk backplane through a high-speed cable.
  • the present invention also provides an implementation method for flexible allocation of hard disk port numbers, and the implementation method is used in the hardware architecture for flexible allocation of hard disk port numbers described in any of the above technical solutions ;
  • the implementation method for flexible allocation of hard disk port numbers includes:
  • the hard disk port numbers are sequentially allocated to the multiple hard disks corresponding to the physical phy.
  • the step of setting the correspondence of the logical phy in the rewritable memory and the physical phy includes:
  • the implementation method further includes:
  • the implementation method further includes: controlling the server motherboard, The power-on sequence of the Raid card, the Expander card and the hard disk backplane; the steps to control the power-on sequence of the server motherboard, the Raid card, the Expander card and the hard disk backplane, including:
  • the power-on control power supply in the server motherboard sends electrical signals of predetermined voltages to the first voltage regulator in the Raid card, the second voltage regulator in the Expander card, and the third voltage regulator in the hard disk backplane respectively;
  • the baseboard management controller in the server motherboard sends power-on sequence control signals to the second CPLD in the Raid card, the third CPLD in the Expander card, and the fourth CPLD in the hard disk backplane, respectively, to control the hard disk backplane, Expander card and Raid cards are powered on in sequence;
  • the baseboard management controller determines that the hard disk backplane, the Expander card and the Raid card are powered on in sequence, it sends a power-on sequence control signal to the first CPLD in the server mainboard to power on the server mainboard.
  • the implementation method for flexible allocation of hardware port numbers after the step of controlling the power-on sequence of the server motherboard, the Raid card, the Expander card and the hard disk backplane, the implementation method for flexible allocation of hardware port numbers also includes:
  • the virtual logical phy is used to discover the SAS link topology, and to discover the SAS and SATA dual-purpose link topology.
  • the hardware architecture for flexible allocation of hard disk port numbers and its implementation method provided by the present application, by setting up a Raid card and expanding an Expander card, as a link between the hard disk backplane and the server motherboard, the rewritable memory of the Expander card stores the The correspondence between logical phy and physical phy. Physical phy corresponds to multiple hard disks in the hard disk backplane. After the logical phy is reported to the server motherboard, the operating system in the server motherboard will assign the hard disk port numbers in the order of logical phy.
  • the writing module is electrically connected to the rewritable memory, and the corresponding relationship between the logical phy and the physical phy in the rewritable memory is set, so that the operating system can flexibly assign the hard disk port number to the hard disk, thereby solving the problem of assigning the operating system to the hard disk in the prior art.
  • the hard disk port number is uncontrollable.
  • FIG. 1 is a schematic structural diagram of a hardware design of a storage server provided by the prior art
  • FIG. 2 is a schematic structural diagram of a hardware architecture for flexible allocation of hard disk port numbers provided by an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a power-on sequence control circuit provided by the embodiment shown in FIG. 2;
  • FIG. 4 is a schematic flowchart of a first implementation method for flexible allocation of hard disk port numbers provided by an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a method for setting a corresponding relationship between a logical phy and a physical phy provided by the embodiment shown in FIG. 4;
  • FIG. 6 is a schematic flowchart of a second implementation method for flexible allocation of hard disk port numbers provided by an embodiment of the present invention.
  • FIG. 7 is a schematic flowchart of a power-on sequence control method provided by the embodiment shown in FIG. 6;
  • FIG. 8 is a schematic diagram of an effect of hard disk port number allocation provided by an embodiment of the present invention.
  • the main problem solved by the embodiments of the present invention is: the prior art solution ignores the problem of hard disk port number allocation under the operating system, and this design causes the hard disk port number allocation under the operating system to be random, and with the development of big data technology Development and Internet users have higher requirements for storage product capacity. Under the circumstance that the underlying storage hardware architecture is becoming more and more complex, after the product designed by the traditional design scheme is delivered to the user, the user needs to modify the huge and complex application layer software. It can meet its own special needs, and this modification of application layer software has certain costs and risks.
  • FIG. 2 is a schematic structural diagram of a hardware architecture for flexible allocation of hard disk port numbers according to an embodiment of the present invention.
  • the hardware architecture for flexible allocation of hard disk port numbers includes:
  • the hard disk backplane 3 is connected with a plurality of hard disks 301; the hard disks 301 can be set as a hard disk HDD, and can also be set as a solid state disk SSD (Solid State Disk).
  • the hard disks 301 can be set as a hard disk HDD, and can also be set as a solid state disk SSD (Solid State Disk).
  • the server mainboard 1 is connected to the hard disk backplane 3 through the Raid card 102 and the Expander card 2 , and is used for allocating hard disk port numbers to the multiple hard disks 301 according to the logical phy (Physical, port physical layer) stored in the Expander card 2 .
  • the Expander card 2 is connected to the server mainboard 1 and the hard disk backplane 3 respectively through the high-speed cable5.
  • Server motherboard 1 is a motherboard with x86 architecture, ARM (Advanced RISC Machines) architecture, MIPS (MIPS architecture) architecture or other architectures, and a PCIE (peripheral component interconnect express) slot is reserved on server motherboard 1, and the server motherboard passes through 1 The PCIE slot is inserted into the Raid card 102 .
  • Expander card 2 includes: Expander chip 201 and port physical layer phy writing module 202; the selection of Expander chip 201 can be determined according to the performance requirements of the specific product on the storage medium and other factors, and the interconnection between the boards depends on the specific product. Sure. Wherein, the selection of the Expander chip 201 depends on the product architecture or product performance.
  • the Expander card 2 can be designed on the above-mentioned server motherboard 1, or can be set independently.
  • the expander chip 201 is connected between the Raid card 102 and the hard disk backplane 3, and includes a rewritable memory 2011.
  • the rewritable memory 2011 stores the correspondence between logical phy and physical phy, wherein the physical phy corresponds to multiple hard disks 301 ;Because the operating system OS on the server motherboard 1 will sequentially assign the hard disk port numbers according to the order of the logical phy, and the physical phy corresponds to the hard disk 301, so by setting the corresponding relationship between the logical phy and the physical phy, the operating system OS can flexibly allocate each The port number of the hard disk 301.
  • the phy writing module 202 is electrically connected to the rewritable and rewritable memory 2011 , and is used for erasing and rewriting the correspondence between the logical phy and the physical phy in the rewritable and rewritable memory 2011 .
  • the phy writing module 202 can set the corresponding relationship between the logical phy and the physical phy in the rewritable memory 2011 according to the instruction of the user or the host computer.
  • the hardware architecture for flexibly assigning hard disk port numbers provided by the present application, by setting up an expander card 2, as a link between the hard disk backplane 3 and the server motherboard 1, the rewritable memory 2011 of the expander card 2 stores a logical phy
  • the corresponding relationship with the physical phy, the physical phy corresponds to multiple hard disks 301 in the hard disk backplane 3, and after the logical phy is reported to the server motherboard 1, the operating system in the server motherboard 1 will assign the hard disk port numbers in the order of the logical phy, so that
  • the phy writing module 202 is electrically connected to the rewritable memory 2011, and the corresponding relationship between the logical phy and the physical phy in the rewritable memory 2011 is set, so that the operating system can flexibly assign the hard disk port number to the hard disk 301, thereby solving the problem of the prior art.
  • the problem that the hard disk port number assigned to the hard disk 301 by the operating system is uncontrollable.
  • the hard disk 301 includes: a plurality of magnetic disk HDDs and/or solid-state hard disks SSD (not marked in the figure);
  • the hard disk backplane 3 includes: SAS and SATA dual-purpose interfaces 302 respectively connected to a plurality of HDDs or SSDs, and the SAS and SATA dual-purpose interfaces 302 are used to connect the Expander card 2 .
  • the Expander card 2 also has a SAS and SATA dual-purpose interface 302 to transmit SAS signals or SATA signals through the SAS/SATA link.
  • the bandwidth from the Expander card 2 to the hard disk backplane 3 may be SAS/SATA x4 (4*12G), or SAS/SATA x8 (8*12G) and other bandwidths.
  • the bandwidth between the server motherboard 1 and the Raid card 102, between the Raid card 102 and the Expander card 2, and between the Expander card 2 and the hard disk backplane 3 depends on specific products.
  • SAS full name Serial Attached SCSI, Serial Attached Small Computer System Interface
  • SAS uses serial technology to achieve higher transmission speed and improve internal space by shortening the connection line.
  • SATA Serial Advanced Technology Attachment hard disk, serial hard disk
  • SATA adopts serial connection mode
  • SATA bus uses embedded clock signal, which has stronger error correction ability.
  • the hard disk backplane 3 is an HDD backplane or SAS backplane, and the backplane can be plugged with SAS/SATA HDD hard disks or SAS/SATA SSDs, depending on product requirements. .
  • the server motherboard 1 includes:
  • Central processing unit CPU (central processing unit) 101, the CPU101 and the Raid card 102 are electrically connected through a high-speed serial computer expansion bus PCIE link 103; the Raid card 102 is provided with a serially connected small computer system SAS interface 104, and the SAS interface 104 is used for Connect Expander Card 2.
  • the Raid card 102 can be directly embedded in the mainboard, or can be set apart from the mainboard.
  • the CPU 101 on the motherboard is connected to the disk array Raid card 102 through the high-speed serial computer expansion bus PCIE link 103, and the Raid card 102 can convert the high-speed serial computer expansion bus PCIE signal into a SAS signal.
  • the signal is passed to the Expander card 2.
  • the Raid card 102 can be directly plugged into the server motherboard 1, and at the same time, the Raid card 102 and the Expander card 2 can be interconnected by using a high-speed cable 5, that is, the Expander card 2 and the hard disk backplane 3 can be interconnected by using a high-speed cable. Selection depends on product performance and other factors.
  • the power-on sequence of each board that is, the server motherboard 1, the raid card 102, the Expander card 2 and the hard disk backplane 3
  • the above-mentioned hardware architecture for the flexible allocation of hard disk port numbers also includes a power-on sequence control circuit 4; the power-on sequence control circuit
  • the power-on sequence is the hard disk backplane, Expander card, Raid card, and server motherboard.
  • the power-on sequence control circuit 4 includes:
  • CPLD Complex Programming logic device
  • baseboard management controller and a power-on control power supply 403 arranged in the server motherboard 1;
  • the second CPLD 404, the first voltage regulator 405 and the first on-board power supply 406 are arranged in the Raid card 102 and connected in sequence;
  • the third CPLD 407, the second voltage regulator 408 and the second in-board power supply 409 are arranged in the Expander card 2 and connected in sequence;
  • the power-on control power supply 403 is respectively electrically connected to the first voltage regulator 405, the second voltage regulator 408 and the third voltage regulator 411; the power-on control power supply 403 is set on the server motherboard 1, so that the power-on control power supply 403 Able to provide 12V electrical signal.
  • the baseboard management controller is electrically connected to the first CPLD 401 , the second CPLD 404 , the third CPLD 407 and the fourth CPLD 410 through the integrated circuit bus 413 , respectively.
  • the baseboard management controller BMC (Baseboard Management Controller) 402 can be arranged in the server main board 1, and the baseboard management controller is connected to the first CPLD 401 and the Raid card 102 in the server main board 1 respectively through the integrated circuit bus IIC (Inter-Integrated Circuit) link.
  • the second CPLD404 in the inside and the third CPLD407 in the Expander card 2 are connected to the fourth CPLD410 in the hard disk backplane 3, and can monitor and control the power supply sequence of each board card.
  • the power-on control power supply 403 of the server motherboard 1 provides P12V to the disk array Raid card 102 , the expansion expander card 2 and the voltage regulator VR chip of the hard disk backplane 3 . 2 and HDD backplane board, using complex programmable logic device CPLD for delay sequence control.
  • the hard disk backplane 3 is powered on first, and then the expansion Expander card 2 and the disk array RAID card 102 are powered on.
  • the power completion flag bit, the complex programmable logic device CPLD of the main board polls the power-on completion status of each board card in the Raid card 102, the Expander card 2 and the hard disk backplane 3 respectively through the integrated circuit bus IIC link, and then the baseboard management
  • the controller BMC402 communicates the power-on completion status to the first CPLD 401 of the server motherboard through the integrated circuit bus IIC link, and the first CPLD 401 controls the power-on sequence of the motherboard to complete the power-on operation of all boards.
  • the power-on sequence of the system is as follows: the hard disk backplane 3 is powered on first, then the Expander card 2 is powered on, then the Raid card 102 is powered on, and finally the server motherboard 1 is powered on.
  • the embodiments of the present invention also provide an implementation method for flexible allocation of hard disk port numbers;
  • the structures are similar, so at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments are provided, which will not be repeated here.
  • FIG. 4 is a schematic flowchart of an implementation method for flexible allocation of hard disk port numbers according to an embodiment of the present invention. As shown in FIG. 4 , the implementation method is used in the hardware architecture for flexible allocation of hard disk port numbers according to any one of the foregoing embodiments;
  • the implementation method for flexible allocation of hard disk port numbers includes:
  • the phy writing module in the Expander card is the firmware FW (FrimWare) in the Expander card.
  • the firmware FW FullWare
  • the corresponding relationship between the logical phy and the physical phy in the rewritable memory can be set, and the hard disk port can be realized according to user requirements. Flexible allocation of numbers.
  • the set logical phy (ie, Logical column) and physical phy (ie, Physical column) are shown in the following table.
  • the Physical column indicates the physical phy ports in the Expander card
  • the Logical column indicates the logical phy ports in the Expander card.
  • the step of setting the correspondence between the logical phy and the physical phy in the rewritable memory specifically includes:
  • S111 According to the number of multiple hard disks and the number of hard disk ports reserved by the server, set a starting point logical phy and an end point logical phy.
  • S112 Set the address of the physical phy corresponding to each logical phy between the starting point logical phy and the end point logical phy.
  • the server Before setting the starting logical phy, the server needs to set the logical phy corresponding to the above reserved hard disk ports.
  • the number of the logical phy corresponds to the number of reserved hard disk ports on the server.
  • the starting logical phy of the operating system reported by the Expander card to the operating system of the server motherboard is from 4 in the Logical column. Start, until the end logical phy corresponding to the number of multiple hard disks on the hard disk backplane.
  • the Index column in the above table is the physical phy pointed to by the logical phy column.
  • FIG. 8 a schematic diagram of the allocation of hard disk port port numbers corresponding to the above table is shown in FIG. 8 .
  • the Port number to be allocated to 32 of the logical physical phy required by the user is Port0, that is, the port- 1:0:0, so when modifying the firmware FW in the Expander card, 0x20 in the Physical column corresponds to 4 in the Logical column, that is, the physical phy32 port corresponds to the logical phy4, so the Port number assigned to the physical phy32 is Port0, so modify After that, it can be aligned with the user's upper-layer software, and other port number assignments can be pushed as an example, so that the special needs of the user can be met.
  • the implementation method for flexible allocation of hard disk port numbers is to set up an expansion Expander card as a link between the hard disk backplane and the server motherboard, and the rewritable memory of the Expander card stores logical phy and physical phy
  • the physical phy corresponds to multiple hard disks in the hard disk backplane. After the logical phy is reported to the server motherboard, the operating system in the server motherboard will assign the hard disk port numbers in the order of the logical phy.
  • the rewritable memory is electrically connected, and the corresponding relationship between the logical phy and the physical phy in the rewritable memory is set, so that the operating system can flexibly assign the hard disk port number to the hard disk, thereby solving the problem that the hard disk port number assigned by the operating system to the hard disk in the prior art is not possible. control issues.
  • the above step S120 according to the arrangement order of logical phy, before the step of allocating hard disk port numbers to multiple hard disks corresponding to physical phy in sequence
  • the implementation method for flexibly assigning hard disk port numbers further includes: S130: Control the power-on sequence of the server motherboard, the Expander card and the hard disk backplane.
  • the step of controlling the power-on sequence of the server motherboard, the Expander card and the hard disk backplane is shown in FIG. 7 , and the method for controlling the power-on sequence includes:
  • the power-on control power supply in the server motherboard sends electrical signals of predetermined voltages to the first voltage regulator in the Raid card, the second voltage regulator in the Expander card, and the third voltage regulator in the hard disk backplane, respectively.
  • the baseboard management controller in the server motherboard sends power-on sequence control signals to the second CPLD in the Raid card, the third CPLD in the Expander card, and the fourth CPLD in the hard disk backplane, respectively, to control the hard disk backplane, Expander The card and the Raid card are powered on in sequence.
  • the server AC after the server AC is powered on, after the hard disk backplane is powered on, then after the Expander card is powered on and the firmware FW is completed, then the disk array card Raid card firmware FW runs ok .
  • the BIOS Basic Input Output System, Basic Input Output System
  • the BIOS runs to initialize the high-speed serial computer expansion bus PCIE device, and then starts to load the disk array Raid card driver, so that the power-on procedure is strictly controllable , to avoid the allocation of hard disk ports due to inconsistent power-on timing.
  • the Allocation implementations also include:
  • S140 Create multiple virtual logical phys in the Expander chip; the virtual logical phy is used to discover the SAS link topology, and to discover the SAS and SATA dual-purpose link topology.
  • the virtual phy of the expansion expander chip is preferentially created to discover the SAS topology of the serial connection of the small computer system interface, and the kernel of the operating system OS is based on the logic set in the firmware FW.
  • the order of phy is to assign the port number under the operating system OS in turn. So far, according to the needs of customers, the flexible allocation of hard disk port numbers under the operating system OS has been completed. Specifically, the final port number assignment in this embodiment of the present application is shown in FIG. 8 . In FIG.
  • phy-1:0:0 to phy-1:0:35 are logical phy ports
  • phy-1:0:36, phy -1:0:37, phy-1:0:38 is the virtual phy inside the expander chip, used to discover the SAS/SATA link topology.
  • embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
  • computer-usable storage media including, but not limited to, disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory result in an article of manufacture comprising instruction means, the instructions
  • the apparatus implements the functions specified in the flow or flow of the flowcharts and/or the block or blocks of the block diagrams.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
  • the word “a” or “an” preceding an element does not preclude the presence of a plurality of such elements.
  • the invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware.
  • the use of the words first, second, and third, etc. do not denote any order. These words can be interpreted as names.

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Abstract

一种用于硬盘端口号灵活分配的硬件架构及其实现方法，其中，该用于硬盘端口号灵活分配的硬件架构包括：服务器主板（1）、Raid卡（102）、Expander卡（2）和硬盘背板（3）；硬盘背板（3）连接有多个硬盘（301）；服务器主板（1）通过Raid卡（102）和Expander卡（2）与硬盘背板（3）相连，用于根据Expander卡（2）存储的逻辑phy，为多个硬盘（301）分配硬盘端口号；Expander卡（2）包括：Expander芯片（201）和端口物理层phy写入模块；Expander芯片（201）包括有可擦写存储器（2011），可擦写存储器（2011）存储有逻辑phy和物理phy的对应关系，其中物理phy与多个硬盘（301）相对应，phy写入模块与可擦写存储器（2011）电连接，用于擦写可擦写存储器（2011）中的逻辑phy和物理phy的对应关系。本方法能解决现有技术中操作系统分配给硬盘端口号不可控的问题。

Description

一种用于硬盘端口号灵活分配的硬件架构及其实现方法
本申请要求于2020年6月29日提交中国专利局、申请号为202010605266.4、发明名称为“一种用于硬盘端口号灵活分配的硬件架构及其实现方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及计算机技术领域，特别涉及一种用于硬盘端口号灵活分配的硬件架构及其实现方法。
背景技术
伴随着数据链、大数据和云计算技术的发展，存储服务器，尤其海量存储服务器已经成为各大互联网公司竞相应用的计算存储设备。另外，用户对于数据的存储、加工和服务的需求日益增长，也造成存储服务器的底层硬件架构的日益复杂；为了适应存储服务器底层硬件架构的复杂化，上层应用层软件架构也日趋庞大和复杂。
为解决上述矛盾，在底层硬件架构日益复杂化的今天，某些互联网用户可能不希望对上层软件架构进行调整；这样就要求在上层软件架构不做调整的情况下，服务器的操作系统OS(operation system)从硬盘上固定的端口Port对硬盘数据进行读写；或者，所有硬盘在操作系统OS对所有硬盘分配的端口号可按照用户的需求进行灵活配置，即一套应用层软件要适配所有存储架构的服务器。
现有技术中的存储服务器的硬件设计如图1所示，存储服务器的平台控制中心PCH(Platform Controller Hub)直出串口硬盘SATA接口连到HDD(Hard Disk Drive，硬盘驱动器)背板上的硬盘HDD，这种硬件设计架构根本无法满足用户的上述需求。在这种架构的设计中，硬盘的端口号在操作系统OS下是随机分配的，因此硬盘的端口号是不可控的。而一些特定的互联网用户为了在上层软件架构不做修改的情况下，将一些硬盘端口作为固定使用。
因此，如何根据用户的需求，在用户应用层软件不做架构调整的情况下，满足用户对应用层软件数据端口号灵活分配的机制是相关技术人员亟待解决的技术难题。
发明内容
本发明提供一种用于硬盘端口号灵活分配的硬件架构及其实现方法，旨在解决现有技术中操作系统OS对所有硬盘分配的端口号随机分配，无法根据用户需求灵活设置的问题。
为实现上述目的，根据本发明的第一方面，本发明提出了一种用于硬盘端口号灵活分配的硬件架构包括：
服务器主板、磁盘阵列Raid卡、扩展Expander卡和硬盘背板；其中，
硬盘背板连接有多个硬盘；
服务器主板通过Raid卡和Expander卡与硬盘背板相连，用于根据Expander卡存储的逻辑phy，为多个硬盘分配硬盘端口号；
Expander卡包括：Expander芯片和端口物理层phy写入模块；
Expander芯片连接于Raid卡和硬盘背板之间，包括有可擦写存储器，可擦写存储器存储有逻辑phy和物理phy的对应关系，其中物理phy与多个硬盘相对应，
phy写入模块与可擦写存储器电连接，用于擦写可擦写存储器中的逻辑phy和物理phy的对应关系。
优选地，所述用于硬盘端口号灵活分配的硬件架构中，硬盘背板包括：
多个磁盘HDD和/或多个固态硬盘SSD；以及，与多个HDD或SSD分别相连的SAS和SATA两用接口，SAS和SATA两用接口用于连接Expander卡。
优选地，所述用于硬盘端口号灵活分配的硬件架构中，服务器主板包括：
中央处理器CPU；其中，CPU与Raid卡通过高速串行计算机扩展总线PCIE链路电连接；Raid卡设置有串行连接小型计算机系统SAS接口，SAS接口用于连接Expander卡。
优选地，所述用于硬盘端口号灵活分配的硬件架构，还包括上电时序控制电路；所述上电时序控制电路的上电时序依次为硬盘背板、Expander卡、Raid卡和服务器主板。
优选地，所述上电时序控制电路包括：
设置于服务器主板内的第一复杂可编程逻辑器CPLD、基板管理控制器和上电控制电源；
设置于Raid卡内、且依次相连的第二CPLD、第一电压调节器和第一板内电源；
设置于Expander卡内、且依次相连的第三CPLD、第二电压调节器和第二板内电源；
以及，设置于硬盘背板内、且依次相连的第四CPLD、第三电压调节器和第三板内电源；
其中，上电控制电源分别与第一电压调节器、第二电压调节器和第三电压调节器电连接；
基板管理控制器分别与第一CPLD、第二CPLD、第三CPLD和第四CPLD通过集成电路总线电连接。
优选地，所述多个硬盘包括多个硬盘驱动器HDD和/或固态硬盘SSD；
所述硬盘背板包括与所述多个HDD或SSD分别相连的SAS和SATA两用接口，所述SAS和SATA两用接口用于连接所述Expander卡。
优选地，所述用于硬盘端口号灵活分配的硬件架构中，Expander卡通过高速cable分别与Raid卡和硬盘背板相连。
根据本发明的第二方面，本发明还提供了一种用于硬盘端口号灵活分配的实现方法，该实现方法用于上述任一项技术方案所述的用于硬盘端口号灵活分配的硬件架构；该用于硬盘端口号灵活分配的实现方法包括：
控制Expander卡内的phy写入模块根据硬盘端口分配指令，设置可擦写存储器中的逻辑phy和物理phy的对应关系；
根据逻辑phy和物理phy的对应关系，按照逻辑phy的排列顺序，依次为物理phy对应的多个硬盘分配硬盘端口号。
优选地，所述用于硬盘端口号灵活分配的实现方法中，设置可擦写存 储器中的逻辑phy和物理phy的对应关系的步骤包括：
根据多个硬盘的数量和服务器预留硬盘端口的数量，设置起点逻辑phy和终点逻辑phy；
设置起点逻辑phy至终点逻辑phy之间每个逻辑phy对应的物理phy的地址。
优选地，所述设置可擦写存储器中的逻辑phy和物理phy的对应关系的步骤之前，所述实现方法还包括：
根据服务器预留硬盘端口的数量，设置与预留硬盘端口数量对应的逻辑phy。
优选地，所述用于硬盘端口号灵活分配的实现方法中，按照逻辑phy的排列顺序，依次为物理phy对应的多个硬盘分配硬盘端口号的步骤之前，实现方法还包括：控制服务器主板、Raid卡、Expander卡和硬盘背板的上电时序；控制服务器主板、Raid卡、Expander卡和硬盘背板的上电时序的步骤，包括：
服务器主板内的上电控制电源分别向Raid卡内的第一电压调节器、Expander卡内的第二电压调节器、硬盘背板内的第三电压调节器发送预定电压的电信号；
服务器主板内的基板管理控制器分别向Raid卡内的第二CPLD、Expander卡内的第三CPLD和硬盘背板内的第四CPLD发送上电时序控制信号，以控制硬盘背板、Expander卡和Raid卡依次上电；
基板管理控制器判定硬盘背板、Expander卡和Raid卡依次上电时，向服务器主板中的第一CPLD发送上电时序控制信号，以使服务器主板上电。
优选地，所述用于硬盘端口号灵活分配的实现方法中，在控制服务器主板、Raid卡、Expander卡和硬盘背板的上电时序的步骤之后，该用于硬件端口号灵活分配的实现方法还包括：
创建Expander芯片中的多个虚拟逻辑phy；虚拟逻辑phy用于发现SAS链路拓扑，以及发现SAS和SATA两用链路拓扑。
本申请提供的用于硬盘端口号灵活分配的硬件架构及其实现方法，通过架设Raid卡、扩展Expander卡，作为硬盘背板和服务器主板之间的纽 带，该Expander卡的可擦写存储器存储有逻辑phy和物理phy的对应关系，物理phy与硬盘背板中的多个硬盘对应，逻辑phy上报给服务器主板后，服务器主板内的操作系统会按照逻辑phy的顺序分配硬盘端口号，这样通过phy写入模块与可擦写存储器电连接，设置可擦写存储器中逻辑phy和物理phy的对应关系，就能够使得操作系统对硬盘灵活分配硬盘端口号，从而解决现有技术中操作系统分配给硬盘的硬盘端口号不可控的问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1是现有技术提供的一种存储服务器的硬件设计的结构示意图；
图2是本发明实施例提供的一种用于硬盘端口号灵活分配的硬件架构的结构示意图；
图3是图2所示实施例提供的一种上电时序控制电路的结构示意图；
图4是本发明实施例提供的第一种用于硬盘端口号灵活分配的实现方法的流程示意图；
图5是图4所示实施例提供的一种逻辑phy和物理phy对应关系设置方法的流程示意图；
图6是本发明实施例提供的第二种用于硬盘端口号灵活分配的实现方法的流程示意图；
图7是图6所示实施例提供的一种上电时序控制方法的流程示意图；
图8是本发明实施例提供的一种硬盘端口号分配效果的示意图。
本发明目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
标号 名称 标号 名称
1 服务器主板 2 Expander卡
3 硬盘背板 4 上电时序控制电路
5 高速cable 101 CPU
102 Raid卡 103 PCIE链路
104 SAS接口 201 Expander芯片
202 phy写入模块 2011 可擦写存储器
301 硬盘 302 SAS和SATA两用接口
401 第一CPLD 402 基板管理控制器BMC
403 上电控制电源 404 第二CPLD
405 第一电压调节器 406 第一板内电源
407 第三CPLD 408 第二电压调节器
409 第二板内电源 410 第四CPLD
411 第三电压调节器 412 第三板内电源
413 集成电路总线 001 平台控制中心PCH
002 HDD背板 003 HDD
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例的主要解决问题是：现有技术方案中忽略了操作系统下硬盘端口号分配的问题，这种设计导致操作系统下硬盘端口号的分配是随机的，而随着大数据技术的发展和互联网用户对存储产品容量的更高要求的需求，底层存储硬件架构越来越复杂的情况下，传统设计方案设计出来的产品在给到用户后，需要用户修改庞大复杂的应用层软件后方可满足自身的特殊需求，而这种对应用层软件的修改是有一定的成本和风险的问题。
为了解决上述问题，参见图2，图2是本发明实施例提供的一种用于硬盘端口号灵活分配的硬件架构的结构示意图。如图2所示，该用于硬盘端口号灵活分配的硬件架构包括：
服务器主板1、Raid(Redundant Arrays of Independent Disks)卡102、扩展Expander卡2和硬盘背板3；其中，
硬盘背板3连接有多个硬盘301；该硬盘301能够设为硬盘HDD，也能 够设为固态硬盘SSD(Solid State Disk)。
服务器主板1通过Raid卡102、Expander卡2与硬盘背板3相连，用于根据Expander卡2存储的逻辑phy(Physical，端口物理层)，为多个硬盘301分配硬盘端口号。其中，Expander卡2通过高速cable5分别与服务器主板1和硬盘背板3相连。服务器主板1是x86架构、ARM(Advanced RISC Machines)架构、MIPS(MIPS architecture)架构或者其他架构的主板，并且服务器主板1上预留有PCIE(peripheral component interconnect express)插槽，服务器主板通过1通过该PCIE插槽与Raid卡102相插接。
Expander卡2包括：Expander芯片201和端口物理层phy写入模块202；Expander芯片201的选型可根据具体产品对存储介质性能的要求及其他因素确定，同时各个板卡之间的互联视具体产品确定。其中，Expander芯片201的选型具体视产品架构或产品性能而定，Expander卡2可以设计到上述服务器主板1上，也可以独立设置。
Expander芯片201连接于Raid卡102和硬盘背板3之间，包括有可擦写存储器2011，可擦写存储器2011存储有逻辑phy和物理phy的对应关系，其中物理phy与多个硬盘301相对应；因为服务器主板1上的操作系统OS会根据逻辑phy的顺序依次分配硬盘端口号，而物理phy与硬盘301对应，因此通过设置逻辑phy和物理phy的对应关系，能够使得操作系统OS灵活分配每个硬盘301的端口号。
phy写入模块202与可擦写存储器2011电连接，用于擦写可擦写存储器2011中的逻辑phy和物理phy的对应关系。phy写入模块202可根据用户或上位机的指令设置可擦写存储器2011中的逻辑phy和物理phy的对应关系。
本申请提供的用于硬盘端口号灵活分配的硬件架构，通过架设扩展Expander卡2，作为硬盘背板3和服务器主板1之间的纽带，该Expander卡2的可擦写存储器2011存储有逻辑phy和物理phy的对应关系，物理phy与硬盘背板3中的多个硬盘301对应，逻辑phy上报给服务器主板1后，服务器主板1内的操作系统会按照逻辑phy的顺序分配硬盘端口号，这样通过phy写入模块202与可擦写存储器2011电连接，设置可擦写存储器2011中逻辑phy和物理phy的对应关系，就能够使得操作系统对硬盘301灵活分配硬盘端口号， 从而解决现有技术中操作系统分配给硬盘301的硬盘端口号不可控的问题。
其中，如图2所示，上述用于硬盘端口号灵活分配的硬件架构中，硬盘301包括：多个磁盘HDD和/或固态硬盘SSD(图中未标记)；
硬盘背板3包括：与多个HDD或SSD分别相连的SAS和SATA两用接口302，SAS和SATA两用接口302用于连接Expander卡2。
对应地，Expander卡2也存在SAS和SATA两用接口302，以通过SAS/SATA链路传输SAS信号或SATA信号。本申请实施例中，Expander卡2下行到硬盘背板3的带宽可以为SAS/SATA x4(4*12G)，或者SAS/SATA x8(8*12G)等带宽。上述服务器主板1与Raid卡102之间、Raid卡102和Expander卡2之间、Expander卡2和硬盘背板3之间的带宽视具体产品而定。
SAS(全称Serial Attached SCSI，串行连接小型计算机系统接口)，SAS采用串行技术，能够获得更高的传输速度，并通过缩短连结线改善内部空间。SATA(Serial Advanced Technology Attachment hard disk，串口硬盘)，SATA采用串行连接方式，SATA总线使用嵌入式时钟信号，具备了更强的纠错能力。这两者都是硬盘301常用的接口，因此通过设置SAS和SATA两用接口302能够更好第实现硬盘背板3和服务器主板1的接口兼容性。
与上述硬盘HDD或固态硬盘SSD对应，该硬盘背板3为HDD背板或SAS背板，背板上能够插接SAS/SATA HDD硬盘，或者插接SAS/SATA SSD，具体视产品需求而定。
另外，如图2所示，作为一种优选的实施例，上述用于硬盘端口号灵活分配的硬件架构中，服务器主板1包括：
中央处理器CPU(central processing unit)101，CPU101与Raid卡102通过高速串行计算机扩展总线PCIE链路103电连接；Raid卡102设置有串行连接小型计算机系统SAS接口104，SAS接口104用于连接Expander卡2。其中，Raid卡102可以直接嵌入到主板中，也能够与主板分离设置。
主板上的CPU101通过高速串行计算机扩展总线PCIE链路103连接到磁盘阵列Raid卡102上，Raid卡102能够将高速串行计算机扩展总线PCIE信号转换为SAS信号，从而通过上述SAS接口104将SAS信号传递至Expander卡2上。本申请中能够直接将Raid卡102插接在服务器主板1上，同时使用高 速cable5将Raid卡102与Expander卡2互联，即使用高速cable将Expander卡2和硬盘背板3互联，Raid卡102的选型视产品性能和其他因素确定。
因为各个板卡，即服务器主板1、Raid卡102、Expander卡2和硬盘背板3的上电先后顺序对操作系统下的硬盘端口号的分配也会产生影响，为了保证服务器主板1、磁盘Raid卡102、Expander卡2和硬盘背板3的时序可控，因此，如图3所示，上述用于硬盘端口号灵活分配的硬件架构还包括上电时序控制电路4；该上电时序控制电路的上电时序依次为硬盘背板、Expander卡、Raid卡和服务器主板。
如图3所示，该上电时序控制电路4包括：
设置于服务器主板1内的第一复杂可编程逻辑器CPLD(Complex Programming logic device)、基板管理控制器和上电控制电源403；
设置于Raid卡102内、且依次相连的第二CPLD404、第一电压调节器405和第一板内电源406；
设置于Expander卡2内、且依次相连的第三CPLD407、第二电压调节器408和第二板内电源409；
以及，设置于硬盘背板3内、且依次相连的第四CPLD410、第三电压调节器411和第三板内电源412；
其中，上电控制电源403分别与第一电压调节器405、第二电压调节器408和第三电压调节器411电连接；上电控制电源403设置于服务器主板1上，这样上电控制电源403能够提供12V的电信号。
基板管理控制器分别与第一CPLD401、第二CPLD404、第三CPLD407和第四CPLD410通过集成电路总线413电连接。
基板管理控制器BMC(Baseboard Management Controller)402可设置于服务器主板1内，基板管理控制器通过集成电路总线IIC(Inter-Integrated Circuit)链路分别与服务器主板1内的第一CPLD401、Raid卡102内的第二CPLD404、Expander卡2内的第三CPLD407和硬盘背板3内的第四CPLD410相连，能够监测并控制各个板卡的供电时序。
具体地，如图3所示，服务器主板1的上电控制电源403提供P12V给磁盘阵列Raid卡102、扩展Expander卡2和硬盘背板3的电压调节器VR芯片， 在Raid卡102、Expander卡2和HDD背板的板内，使用复杂可编程逻辑器CPLD进行延时时序控制。在这种设计下，硬盘背板3先完成上电，然后依次是扩展Expander卡2和磁盘阵列Raid卡102完成上电，同时这三个板卡的复杂可编程逻辑器CPLD的寄存器中保存上电完成标志bit位，主板的复杂可编程逻辑器CPLD通过集成电路总线IIC链路分别轮询Raid卡102、Expander卡2和硬盘背板3中每个板卡的上电完成情况，接着基板管理控制器BMC402通过集成电路总线IIC链路将上电完成情况传达给服务器主板的第一CPLD401，第一CPLD401再控制主板上电时序，从而完成所有板卡的上电操作。综上，通过上述严格的硬件时序设计，本系统的上电先后顺序依次是：硬盘背板3先上电、接着Expander卡2上电、接着Raid卡102上电，最后服务器主板1上电。
另外，基于上述用于硬盘端口号灵活分配的硬件架构实施例的同一构思，本发明实施例还提供了用于硬盘端口号灵活分配的实现方法；由于该方法实施例解决问题的原理与上述硬件架构相似，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
参见图4，图4为本发明实施例提供的一种用于硬盘端口号灵活分配的实现方法的流程示意图。如图4所示，该实现方法用于上述实施例中任一项所述的用于硬盘端口号灵活分配的硬件架构；
具体地，该用于硬盘端口号灵活分配的实现方法包括：
S110：控制Expander卡内的phy写入模块根据硬盘端口分配指令，设置可擦写存储器中的逻辑phy和物理phy的对应关系。
Phy(Port Physical Layer，物理层端口)，PCS(process control systems，过程控制系统)对被发送和接收的信息加码和解码，目的是使接收器更容易恢复信号。Expander卡内的phy写入模块即Expander卡内的固件FW(FrimWare)，通过该phy写入模块FW，设置可擦写存储器中的逻辑phy和物理phy的对应关系，能够根据用户需求实现硬盘端口号的灵活分配。
作为一种优选的实施例，在本申请实施例中，设置的逻辑phy(即Logical列)和物理phy(即Physical列)如下表所示。
Figure PCTCN2021076923-appb-000001
Figure PCTCN2021076923-appb-000002
Figure PCTCN2021076923-appb-000003
Physical列表示Expander卡中物理phy端口，Logical列表示Expander卡中逻辑phy端口，通过修改逻辑phy和物理phy端口的对应关系，能够实现操作系统下硬盘端口号的分离可控。
其中，如图5所示，该设置可擦写存储器中的逻辑phy和物理phy的对应关系的步骤具体包括：
S111：根据多个硬盘的数量和服务器预留硬盘端口的数量，设置起点逻辑phy和终点逻辑phy。
S112：设置起点逻辑phy至终点逻辑phy之间每个逻辑phy对应的物理phy的地址。
服务器在设置起点逻辑phy之前，需要设置与上述预留硬盘端口对应的逻辑phy，该逻辑phy的数量与服务器预留硬盘端口的数量相对应。
参见上表和图5所示实施例，上表中Logical列的逻辑phy地址0，1，2，3；Physical列的物理phy 0，1，2，3，这4个物理phy接存储服务器预留的4块硬盘端口，也就是说着4个物理phy并未接硬盘背板的硬盘。由于这4个物理phy未接硬盘，这样服务器主板的操作系统不会给上述几个逻辑phy分配硬盘端口号，Expander卡上报给服务器主板的操作系统的起点逻辑phy即从逻辑列Logical列的4开始，直至硬盘背板的多个硬盘的数量对应的终点逻辑phy为止。另外上表中Index列即是逻辑phy列所指向的物理phy。
S120：根据逻辑phy和物理phy的对应关系，按照逻辑phy的排列顺序，依次为物理phy对应的多个硬盘分配硬盘端口号。
具体地，对应于上表的硬盘端口port号的分配示意图如图8所示，本申请实施例中，用户要求逻辑物理phy的32要分配到的Port号是Port0，即图8中的port-1:0:0，因此在修改Expander卡中的固件FW时，将Physical列的0x20和Logical列的4对应，即物理phy32端口对应逻辑phy4，这样物理phy32分配到的Port号就是Port0，这样修改后，就可以和用户的上层软件对齐，其他port号分配以此例推，这样就可以满足用户的这种特殊需求。
本申请实施例提供的用于硬盘端口号灵活分配的实现方法，通过架设扩展Expander卡，作为硬盘背板和服务器主板之间的纽带，该Expander卡的可擦写存储器存储有逻辑phy和物理phy的对应关系，物理phy与硬盘背板中的多个硬盘对应，逻辑phy上报给服务器主板后，服务器主板内的操作系统会按照逻辑phy的顺序分配硬盘端口号，这样通过phy写入模块与可擦写存储器电连接，设置可擦写存储器中逻辑phy和物理phy的对应关系，就能够使得操作系统对硬盘灵活分配硬盘端口号，从而解决现有技术中操作系统分配给硬盘的硬盘端口号不可控的问题。
另外，作为一种优选的实施例，如图6所示，在本实施例中，上述步骤S120：按照逻辑phy的排列顺序，依次为物理phy对应的多个硬盘分配硬盘端口号的步骤之前，该用于硬盘端口号灵活分配的实现方法还包括：S130：控制服务器主板、Expander卡和硬盘背板的上电时序。
具体地，该控制服务器主板、Expander卡和硬盘背板的上电时序的步骤参见图7，该控制上电时序的方法包括：
S131：服务器主板内的上电控制电源分别向Raid卡内的第一电压调节器、Expander卡内的第二电压调节器、硬盘背板内的第三电压调节器发送预定电压的电信号。
S132：服务器主板内的基板管理控制器分别向Raid卡内的第二CPLD、Expander卡内的第三CPLD和硬盘背板内的第四CPLD发送上电时序控制信号，以控制硬盘背板、Expander卡和Raid卡依次上电。
S133：当基板管理控制器判定硬盘背板、Expander卡和Raid卡依次上电时，向服务器主板中的第一CPLD发送上电时序控制信号，以使服务器主板上电。
本申请实施例中，按照上述时序设计方法，在服务器交流上电后，硬盘背板上电后，接着Expander卡上电完成并且固件FW运行完成后，接下来磁盘阵列卡Raid卡固件FW运行ok，最后服务器主板上电后，BIOS(Basic Input Output System，基本输入输出系统)运行初始化高速串行计算机扩展总线PCIE设备，之后开始加载磁盘阵列Raid卡驱动程序，从而使得使得上电程序严格可控，避免因上电时序不一致影响硬盘端口的分配。
另外，如图6所示，上述用于硬盘端口号灵活分配的实现方法中，在步骤S130：控制服务器主板、Expander卡和硬盘背板的上电时序的步骤之后，该用于硬件端口号灵活分配的实现方法还包括：
S140：创建Expander芯片中的多个虚拟逻辑phy；该虚拟逻辑phy用于发现SAS链路拓扑，以及发现SAS和SATA两用链路拓扑。
本申请实施例中，磁盘阵列Raid卡的驱动程序初始化时，优先创建扩展expander芯片的虚拟phy，以发现串行连接小型计算机系统接口SAS拓扑，同时操作系统OS的内核根据固件FW中设置的逻辑phy的顺序，依次分配操 作系统OS下的Port号。至此，根据客户的需求，完成了操作系统OS下硬盘Port号的灵活分配。具体地，本申请实施例最终的Port号分配如图8所示，图8中phy-1:0:0到phy-1:0:35是逻辑phy端口，phy-1:0:36、phy-1:0:37、phy-1:0:38是expander芯片内部的虚拟phy，用来discover SAS/SATA链路拓扑。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
应当注意的是，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的部件或步骤。位于部件之前的单词“一”或“一个”不排除存在多个这样的部件。本发明可以借助于包括有若干不同部件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

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  1. 一种用于硬盘端口号灵活分配的硬件架构，其特征在于，包括：
    服务器主板、磁盘阵列Raid卡、扩展Expander卡和硬盘背板；其中，
    所述硬盘背板连接有多个硬盘；
    所述服务器主板通过所述Raid卡和Expander卡与所述硬盘背板相连，用于根据所述Expander卡存储的逻辑phy，为所述多个硬盘分配硬盘端口号；
    所述Expander卡包括：Expander芯片和端口物理层phy写入模块；
    所述Expander芯片连接于所述Raid卡和所述硬盘背板之间，包括有可擦写存储器，所述可擦写存储器存储有所述逻辑phy和物理phy的对应关系，其中所述物理phy与所述多个硬盘相对应；
    所述phy写入模块与所述可擦写存储器电连接，用于擦写所述可擦写存储器中的逻辑phy和物理phy的对应关系。
  2. 根据权利要求1所述的用于硬盘端口号灵活分配的硬件架构，其特征在于，所述服务器主板包括：中央处理器CPU；所述CPU与所述Raid卡通过高速串行计算机扩展总线PCIE链路电连接；
    所述Raid卡设置有串行连接小型计算机系统SAS接口，所述SAS接口用于连接所述Expander卡。
  3. 根据权利要求2所述的用于硬盘端口号灵活分配的硬件架构，其特征在于，还包括上电时序控制电路，所述上电时序控制电路的上电时序依次为硬盘背板、Expander卡、Raid卡和服务器主板。
  4. 根据权利要求1所述的用于硬盘端口号灵活分配的硬件架构，其特征在于，所述多个硬盘包括多个磁盘驱动器HDD和/或固态硬盘SSD；
    所述硬盘背板包括与所述多个HDD或SSD分别相连的SAS和SATA两用接口，所述SAS和SATA两用接口用于连接所述Expander卡。
  5. 根据权利要求1所述的用于硬盘端口号灵活分配的硬件架构，其特征在于，所述Expander卡通过高速cable分别与所述Raid卡和硬盘背板相连。
  6. 一种用于硬盘端口号灵活分配的实现方法，其特征在于，所述用于 硬盘端口号灵活分配的实现方法，用于权利要求1-5所述的用于硬盘端口号灵活分配的硬件架构；所述实现方法包括：
    控制Expander卡内的phy写入模块根据硬盘端口分配指令，设置可擦写存储器中的逻辑phy和物理phy的对应关系；
    根据所述逻辑phy和物理phy的对应关系，按照逻辑phy的排列顺序，依次为所述物理phy对应的多个硬盘分配硬盘端口号。
  7. 根据权利要求6所述的用于硬盘端口号灵活分配的实现方法，其特征在于，所述设置可擦写存储器中的逻辑phy和物理phy的对应关系的步骤，包括：
    根据所述多个硬盘的数量和服务器预留硬盘端口的数量，设置起点逻辑phy和终点逻辑phy；
    设置所述起点逻辑phy至终点逻辑phy之间每个逻辑phy对应的物理phy的地址。
  8. 根据权利要求7所述的用于硬盘端口号灵活分配的实现方法，其特征在于，所述设置可擦写存储器中的逻辑phy和物理phy的对应关系的步骤之前，所述实现方法还包括：
    根据所述服务器预留硬盘端口的数量，设置与所述预留硬盘端口数量对应的逻辑phy。
  9. 根据权利要求6所述的用于硬盘端口号灵活分配的实现方法，其特征在于，所述按照逻辑phy的排列顺序，依次为所述物理phy对应的多个硬盘分配硬盘端口号的步骤之前，所述实现方法还包括：
    控制服务器主板、Expander卡和硬盘背板的上电时序；
    其中，所述上电时序依次为硬盘背板、Expander卡、Raid卡和服务器主板。
  10. 根据权利要求8所述的用于硬盘端口号灵活分配的实现方法，其特征在于，在所述控制服务器主板、Expander卡和硬盘背板的上电时序的步骤之后，所述方法还包括：
    创建所述Expander芯片中的多个虚拟逻辑phy；所述虚拟逻辑phy用于发现SAS链路拓扑，以及发现SAS和SATA两用链路拓扑。
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CN116643636A (zh) * 2023-05-29 2023-08-25 合芯科技有限公司 一种硬盘背板随机上电的方法、装置、设备及介质

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CN113360437B (zh) * 2021-04-21 2023-03-03 山东英信计算机技术有限公司 一种硬盘的盘序调整装置、方法、设备及存储介质
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CN114385253A (zh) * 2021-12-23 2022-04-22 新华三云计算技术有限公司 服务器上电管理方法、装置、设备及机器可读存储介质
CN115562738B (zh) * 2022-11-14 2023-03-10 苏州浪潮智能科技有限公司 一种端口配置方法、组件及硬盘扩展装置
CN115904251A (zh) * 2023-01-03 2023-04-04 苏州浪潮智能科技有限公司 硬盘顺序调整方法及装置、系统、电子设备、存储介质

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140122798A1 (en) * 2012-10-31 2014-05-01 Lsi Corporation Methods and structure establishing nested redundant array of independent disks volumes with an expander
CN108762667A (zh) * 2018-04-20 2018-11-06 烽火通信科技股份有限公司 可动态分配磁盘的多节点服务器及动态分配磁盘的方法
CN109614035A (zh) * 2018-11-01 2019-04-12 郑州云海信息技术有限公司 一种支持解决服务器存储介质序列灵活配置的方法与系统
CN111880727A (zh) * 2020-06-29 2020-11-03 苏州浪潮智能科技有限公司 一种用于硬盘端口号灵活分配的硬件架构及其实现方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108984331A (zh) * 2018-06-22 2018-12-11 郑州云海信息技术有限公司 一种服务器硬盘编号按顺序显示装置、方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140122798A1 (en) * 2012-10-31 2014-05-01 Lsi Corporation Methods and structure establishing nested redundant array of independent disks volumes with an expander
CN108762667A (zh) * 2018-04-20 2018-11-06 烽火通信科技股份有限公司 可动态分配磁盘的多节点服务器及动态分配磁盘的方法
CN109614035A (zh) * 2018-11-01 2019-04-12 郑州云海信息技术有限公司 一种支持解决服务器存储介质序列灵活配置的方法与系统
CN111880727A (zh) * 2020-06-29 2020-11-03 苏州浪潮智能科技有限公司 一种用于硬盘端口号灵活分配的硬件架构及其实现方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116643636A (zh) * 2023-05-29 2023-08-25 合芯科技有限公司 一种硬盘背板随机上电的方法、装置、设备及介质
CN116643636B (zh) * 2023-05-29 2024-02-23 合芯科技有限公司 一种硬盘背板随机上电的方法、装置、设备及介质

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