WO2021258748A1 - I2c总线通信控制方法、装置、系统及可读存储介质 - Google Patents

I2c总线通信控制方法、装置、系统及可读存储介质 Download PDF

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WO2021258748A1
WO2021258748A1 PCT/CN2021/076839 CN2021076839W WO2021258748A1 WO 2021258748 A1 WO2021258748 A1 WO 2021258748A1 CN 2021076839 W CN2021076839 W CN 2021076839W WO 2021258748 A1 WO2021258748 A1 WO 2021258748A1
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Prior art keywords
polling
bus
read
communication control
bus communication
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PCT/CN2021/076839
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English (en)
French (fr)
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林宁亚
童元满
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浪潮(北京)电子信息产业有限公司
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Priority to US17/795,255 priority Critical patent/US11726946B2/en
Publication of WO2021258748A1 publication Critical patent/WO2021258748A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the present invention relates to the field of communication technology, in particular to an I2C bus communication control method, device, system and readable storage medium.
  • I2C (Inter-Integrated Circuit) bus is a two-wire serial bus used to connect microcontrollers and their peripheral devices. It is a bus standard widely used in the field of microelectronics communication control.
  • I2C transfers information between devices connected to the bus through serial data (SDA) lines and serial clock (SCL) lines.
  • SDA serial data
  • SCL serial clock
  • Each device has a unique address identification, and can be used as a transmitter or receiver (determined by the function of the device).
  • the host is a device (ie, the master device) that initiates data transmission on the bus and generates a clock signal that allows the transmission.
  • any addressed device (slave device) is considered a slave.
  • the polling method requires the developer to design the polling program specifically. Whenever there is a hardware change, the polling program must also change accordingly, and when the bus is in a busy congestion state, the upper layer will frequently obtain the bus. Status information occupies system resources, and management efficiency is extremely low. In other words, the problem of low I2C access efficiency is still not well resolved.
  • the purpose of the present invention is to provide an I2C bus communication control method, device, system and readable storage medium.
  • the upper layer application and the lower layer hardware can accurately obtain the communication status of the bus based on the polling table, which can avoid frequently obtaining the communication status of the bus.
  • the polling table is used to control the communication control of the I2C bus, which can avoid the risk of congestion and improve the access efficiency in the application scenarios of multiple master devices.
  • the present invention provides the following technical solutions:
  • An I2C bus communication control method including:
  • it also includes:
  • the polling table is updated by using the configuration modification information.
  • the configuration information is parsed to obtain multiple polling parameters, including:
  • the operation type, the master device, the slave device, the number of bytes, the polling time, the remaining time, and the priority level corresponding to one of the read and write operations are regarded as one item Polling parameters.
  • using the number of bytes and the polling period corresponding to each of the read and write operations to calculate the remaining time corresponding to the read and write operations includes:
  • the bottom layer clock is used in combination with the execution time and the polling period to obtain the remaining time.
  • controlling the I2C bus and executing corresponding read and write operations according to the polling table includes:
  • the read and write operations of the I2C bus are verified, and the read and write operations that fail the verification are intercepted.
  • it also includes:
  • the end signal of the target read and write operation is generated; the target read and write operation is the read and write operation currently performed by the I2C bus.
  • it also includes:
  • the priority corresponding to the target slave device in the polling table is lowered.
  • An I2C bus communication control device including:
  • the configuration information acquisition module is used to receive the configuration information of the I2C bus sent by the upper application;
  • the parsing module is used to parse the configuration information to obtain each polling parameter
  • a polling table maintenance module configured to write the polling parameters into the polling table
  • the read and write operation execution module is used to control the I2C bus and execute corresponding read and write operations according to the polling table.
  • An I2C bus communication control system including:
  • I2C bus communication control equipment connected to I2C bus, I2C master device and I2C slave device;
  • the upper layer application accesses the I2C bus communication control device through the AXI bus;
  • the I2C bus communication control device includes a register, a counter and a polling table
  • the I2C bus communication control device is used to execute the steps of the above-mentioned I2C bus communication control method.
  • An I2C bus communication control device including:
  • Memory used to store computer programs
  • the processor is used to implement the steps of the I2C bus communication control method when the computer program is executed.
  • the configuration information sent by the upper-layer application is written into the polling table, and then multiple polling parameters are obtained. Then, control the I2C bus to perform read and write operations corresponding to the polling read operation parameters. It can be seen that in this method, since the read and write operations performed on the I2C bus are performed in accordance with the polling table, there is no need to poll the access bus status, and the accurate I2C bus communication status can be obtained directly based on the polling table. It is precisely because the read and write operations performed on the I2C bus are performed in accordance with the polling table, which can greatly reduce the risk of congestion. When there are multiple master devices, the access efficiency of a single master device can also be achieved. It is convenient for management and maintenance; if there is a hardware or function change, only the polling table needs to be updated without modifying the program, which can quickly adapt to the function update or hardware replacement.
  • the embodiments of the present invention also provide an I2C bus communication control device, system, and readable storage medium corresponding to the above I2C bus communication control method, which have the above technical effects, and will not be repeated here.
  • Figure 1 is an implementation flow chart of an I2C bus communication control method in an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an I2C bus communication control device in an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an I2C bus communication control system in an embodiment of the present invention.
  • FIG. 1 is a flowchart of an I2C bus communication control method in an embodiment of the present invention. The method includes the following steps:
  • S101 Receive configuration information of the I2C bus sent by an upper-layer application.
  • upper-layer applications such as applications running on mobile phones and tablet computers, may be specific personal user applications or enterprise-level applications.
  • the upper-layer application is not specifically limited.
  • the upper-layer application can send the configuration information corresponding to the I2C bus by writing, so as to perform data transfer processing based on the I2C bus.
  • the configuration information can specifically specify which master device needs to access which slave device in which way, when and what is the access method, how many bytes are accessed, and so on.
  • the configuration information may include the master device, operation type, slave device, number of bytes, polling period, and priority.
  • the operation type can be divided into read operation and write operation, the number of bytes is the number of bits read or the number of bits written; the polling period is the length of the access interval period, which corresponds to the polling time; the priority is when an access conflict occurs At the time, determine which master device's access demand is to be executed first.
  • the configuration information can be parsed to obtain multiple polling parameters.
  • a polling parameter specifically corresponds to a read and write operation
  • the polling parameters can specifically include: operation type, master device, slave device, number of bytes, polling time, remaining time, and priority.
  • the process of obtaining polling parameters includes:
  • Step 1 Analyze the configuration information to obtain the operation type, master device, slave device, number of bytes, polling cycle, and priority corresponding to each read and write operation;
  • Step 2 Use the number of bytes and polling time corresponding to each read and write operation to calculate the remaining time corresponding to the read and write operation;
  • Step 3 Use the operation type, master device, slave device, number of bytes, polling time, remaining time, and priority corresponding to a read and write operation as a polling parameter.
  • step two may specifically include:
  • Step 2.1 Calculate the execution time of a read and write operation by using the number of bytes and the bus frequency
  • Step 2.2 use the bottom layer clock, and combine the execution time and the polling period to obtain the remaining time.
  • each serial number in the polling table represents an I2C read and write operation, which can be represented by an 8-bit binary number, (8-bit binary numbers can represent 256 operations in total, which is much larger than an I2C bus
  • the normal operand of ) the main device is distinguished by the numerical value of the designated bit in the serial number.
  • each I2C is determined by the address of the SLAVE device (slave device) and the offset address of the internal register of the slave.
  • the number of bytes represents the number of bytes that need to be occupied by a read operation or a write operation. There is no need to distinguish between read operations and write operations at the number of bytes in the polling table.
  • the execution time of the read/write operation can be calculated.
  • the polling time indicates the interval of periodically obtaining information, and the remaining time indicates the remaining time until the next read/write operation. This time can be determined from the bottom-level clock, that is, the upper-level application performs a countdown operation synchronously after obtaining data once. .
  • a more accurate timing time can be obtained by increasing the number of visits.
  • the priority is to define which operation is given priority when a conflict is about to occur, and the remaining time of the other operation will be adjusted and delayed.
  • the polling parameters can be written into the polling table.
  • a table header including sequence number, operation type, slave device, number of bytes, polling time, remaining time, and priority type table can be set; correspondingly, the configuration information includes operation type, Slave device, number of bytes, polling period, and priority.
  • Figure 2 is a schematic diagram of the main structure of an I2C bus communication control system in an embodiment of the present invention.
  • the configuration information includes:
  • Master device 1 and A device offset0x01 have an operation of writing 0x88, and the polling cycle is two seconds;
  • the master device 1 has an operation to read 2bytes to the offset0x2 of the B device, and the polling cycle is three seconds;
  • Master device 2 and A device offset0x01 have an operation of writing 0x88, and the polling cycle is two seconds;
  • the master device 2 has an operation to read 3bytes to the offset0x3 of the B device, and the polling cycle is three seconds;
  • polling parameters can be obtained by analyzing the configuration information, and the polling parameters are written into the polling table to obtain the polling table as shown below:
  • Serial number Slave Offset Byte number When polling Remaining time (10us) priority 00000001 00110011 00000001 00000001 0111110100 00001110101001100000 01 00000010 00110100 00000010 00000002 1011101110 00001110101001011101 01 10000011 00110011 00000001 00000001 0111110100 00011101010011000000 01 10000100 00110100 00000011 00000003 1011101110 00101011111100100000 10 To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To To
  • the highest bit of the serial number distinguishes the master device, 0 identifies the master device 1; 1 identifies the master device 2.
  • the remaining time can be set as read-only data, and the remaining time can be automatically generated after analyzing all operations. Analyze all data in the normal mode, take the maximum number of polling cycles as the total number of cycles, and evenly distribute each task in each time period in the cycle to ensure the sparsity of communications.
  • S104 Control the I2C bus, and execute corresponding read and write operations according to the polling table.
  • the specific polling read and write reference parameters corresponding to a read and write operation for each record in the polling table the specific read and write operations performed by the I2C bus and the specific time are determined.
  • the specific implementation process includes:
  • Step 1 Determine each read and write operation to be performed according to the corresponding operation type, master device, slave device, and number of bytes;
  • Step 2 Determine the execution time of each read and write operation to be executed according to the priority and the remaining time
  • Step 3 Perform each read and write operation to be executed according to the execution time
  • Step 4 Verify the read and write operations of the I2C bus, and intercept the read and write operations that fail the verification.
  • the polling table can determine the specific polling cycle of each read and write operation, the master device, slave device, access type, access time, etc. of the operation. There is no need to query the status register every time the I2C bus is accessed. That is, all the master devices in the system access the slave devices through the I2C bus according to the polling table. It can analyze the data from the I2C bus and correlate it with the data in the internal register to update the polling table related information. In order to ensure the safety of the system, in practical applications, when controlling the I2C bus to perform read and write operations, the I2C bus read and write operations can be verified, and the read and write operations that fail the verification can be intercepted. The verification function can be set, and read and write operations that do not meet the verification conditions will be intercepted to protect the security of the system.
  • the following steps can also be performed to complete the I2C adaptation:
  • Step 1 Receive configuration modification information sent by upper-layer applications
  • Step 2 Use configuration modification information to update the polling table.
  • the configuration modification information may specifically be a change in the polling time, access address, or access mode of a specific read and write operation, and modify a record in the polling table, or it may be a brand new one. Configure information to replace all records in the entire polling table.
  • the communication interruption request sent by the upper-layer application can also be received; the end signal of the target read and write operation is generated; the target read and write operation is the read and write operation currently performed by the I2C bus. That is, it can generate an end signal for the current I2C bus operation in the emergent situation of emergency communication, and shorten the time delay of burst communication.
  • the faulty slave device can also be marked to reduce the number of times of accessing the faulty slave device.
  • it can also be executed: if the number of failed accesses of the target slave device reaches the degrading threshold, the priority corresponding to the target slave device in the polling table is reduced. If the slave device of a certain address fails to access continuously (for example, if the degrading threshold is 3, that is, the continuous access fails 3 times, it is regarded as the continuous access failure), the slave device is considered to be faulty, and the slave device is lowered in the polling table, such as The priority is reduced to the lowest, further reducing the frequency of accessing faulty slave devices.
  • the configuration information sent by the upper-layer application is written into the polling table, and then multiple polling parameters are obtained. Then, control the I2C bus to perform read and write operations corresponding to the polling read operation parameters. It can be seen that in this method, since the read and write operations performed on the I2C bus are performed in accordance with the polling table, there is no need to poll the access bus status, and the accurate I2C bus communication status can be obtained directly based on the polling table. It is precisely because the read and write operations performed on the I2C bus are performed in accordance with the polling table, which can greatly reduce the risk of congestion. When there are multiple master devices, the access efficiency of a single master device can also be achieved. It is convenient for management and maintenance; if there is a hardware or function change, only the polling table needs to be updated without modifying the program, which can quickly adapt to function updates or hardware replacements.
  • the embodiment of the present invention also provides an I2C bus communication control device.
  • the I2C bus communication control device described below and the I2C bus communication control method described above can be referenced correspondingly.
  • the device includes:
  • the configuration information acquisition module 101 is used to receive the configuration information of the I2C bus sent by the upper application;
  • the parsing module 102 is used for parsing configuration information to obtain each polling parameter
  • the polling table maintenance module 103 is used to write polling parameters into the polling table
  • the read and write operation execution module 104 is used to control the I2C bus and execute corresponding read and write operations according to the polling table.
  • the configuration information sent by the upper-layer application is written into the polling table, and then multiple polling parameters are obtained. Then, control the I2C bus to perform read and write operations corresponding to the polling read operation parameters. It can be seen that in this device, since the read and write operations performed on the I2C bus are performed in accordance with the polling table, there is no need to poll the access bus status, and the accurate I2C bus communication status can be obtained directly based on the polling table. It is precisely because the read and write operations performed on the I2C bus are performed in accordance with the polling table, which can greatly reduce the risk of congestion. When there are multiple master devices, the access efficiency of a single master device can also be achieved. It is convenient for management and maintenance; if there is a hardware or function change, only the polling table needs to be updated without modifying the program, which can quickly adapt to the function update or hardware replacement.
  • the polling table update module is used to receive the configuration modification information sent by the upper application; use the configuration modification information to update the polling table.
  • the analysis module 102 is specifically used to analyze configuration information to obtain the operation type, master device, slave device, byte number, polling period, and priority corresponding to each read and write operation; Use the number of bytes corresponding to each read and write operation and the polling time to calculate the remaining time corresponding to the read and write operations; the operation type, master device, slave device, number of bytes, and polling corresponding to a read and write operation Time, remaining time and priority are used as a polling parameter.
  • the parsing module 102 is specifically configured to use the number of bytes and the bus frequency to calculate the execution time for a read and write operation; use the underlying clock, and combine the execution time and the polling cycle, Get the remaining time.
  • the read and write operation execution module 104 is configured to determine each read and write operation to be executed according to the corresponding operation type, master device, slave device, and number of bytes; according to priority and remaining time Determine the execution time of each read and write operation to be executed; execute each read and write operation to be executed according to the execution time; verify the read and write operations of the I2C bus, and intercept the read and write operations that fail the verification.
  • the communication interrupt control module is used to receive the communication interrupt request sent by the upper application; generate the end signal of the target read and write operation; the target read and write operation is the read and write operation currently performed by the I2C bus.
  • the fault processing module is used to reduce the priority corresponding to the target slave device in the polling table if the number of access failures of the target slave device reaches the degrading threshold.
  • the embodiment of the present invention also provides an I2C bus communication control system.
  • the I2C bus communication control system described below and the I2C bus communication control method described above can be referenced correspondingly.
  • the system includes:
  • I2C bus communication control equipment connected to I2C bus, I2C master device and I2C slave device;
  • the upper application accesses the I2C bus communication control device through the AXI bus;
  • I2C bus communication control equipment includes registers, counters and polling tables
  • the I2C bus communication control device is used to execute the steps of the I2C bus communication control method described in the above method embodiment.
  • the I2C bus communication control device mainly includes four functional modules (of course, other combination types of functional modules can also be divided, subject to the I2C bus communication control provided by the method embodiment):
  • Proxy unit responsible for generating an end signal for the current I2C bus operation in the event of a sudden emergency in emergency communication, and shortening the time delay of burst communication. For example, when the CPU temperature is too high, it is necessary to immediately interrupt the read and write operations performed by the existing I2C bus in order to perform the I2C bus write operation to urgently control the fan speed.
  • Analysis module responsible for analyzing the data from the I2C bus, associating with the data in the internal configuration register, and updating the relevant information of the polling table. In addition, if the verification function is enabled, read and write operations that do not meet the verification conditions will be intercepted to protect the security of the system.
  • Polling table Contains polling table information, which can be accessed by I2C bus and AXI bus.
  • Internal configuration register It can include various detailed configurations, such as: safety check switch, automatic reread function, faulty device mark, etc.
  • the specific instructions are as follows:
  • Security check switch After it is turned on, operations that are not the highest priority, slave device address, and offset address will be refused to initiate;
  • Faulty device mark After opening, if the slave device of a certain address fails to access continuously, the device is considered to be faulty, and the priority of the device is reduced to the lowest in the polling table to reduce the access frequency.
  • the timer is responsible for recording the bus timing and ensuring that the upper and lower clock frequencies are consistent.
  • the resource usage of the entire I2C bus is redistributed, and in the case of multiple master devices, there is a better anti-collision mechanism, which greatly improves the bus utilization, avoids the occurrence of congestion, and saves upper-level resources .
  • the safety check and fault marking function greatly improve the safety and stability of the bus.
  • the embodiment of the present invention also provides a readable storage medium, and a readable storage medium described below and an I2C bus communication control method described above may correspond to each other and refer to each other.
  • a readable storage medium in which a computer program is stored, and when the computer program is executed by a processor, the steps of the I2C bus communication control method in the foregoing method embodiment are implemented.
  • the readable storage medium can specifically be a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk, or an optical disk that can store program codes. Readable storage medium.

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Abstract

一种I2C总线通信控制方法、装置、系统及可读存储介质，该方法包括：接收上层应用发送的I2C总线的配置信息；解析所述配置信息，得到多条轮询参数；将多条所述轮询参数写入轮询表中；控制所述I2C总线，按照所述轮询表执行对应的读写操作。该方法中，I2C总线上执行的读写操作是按照轮询表进行的，因而无需轮询访问总线状态，便可直接基于轮询表得到精准的I2C总线的通信情况；可降低拥塞风险，存在多个主器件时，也可达到单个主器件的访问效率。对于管理维护方便；若发生硬件或功能变化，仅需对轮询表进行更新即可，而无需修改程序，能够快速适应功能更新或硬件更替。

Description

I2C总线通信控制方法、装置、系统及可读存储介质
本申请要求于2020年6月24日提交至中国专利局、申请号为202010589296.0、发明名称为“I2C总线通信控制方法、装置、系统及可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，特别是涉及一种I2C总线通信控制方法、装置、系统及可读存储介质。
背景技术
I2C(Inter－Integrated Circuit)总线是一种两线式串行总线，用于连接微控制器及其外围设备。是微电子通信控制领域广泛采用的一种总线标准。
I2C通过串行数据(SDA)线和串行时钟(SCL)线在连接到总线的器件间传递信息。每个器件都有一个唯一的地址识别，而且都可以作为一个发送器或接收器(由器件的功能决定)。主机是初始化总线的数据传输并产生允许传输的时钟信号的器件(即主器件)。相应地，任何被寻址的器件(从器件)都被认为是从机。
在现有的I2C控制器访问方案中，提出在访问I2C控制器获取总线状态时，采用轮询方式，来解决现有I2C访问标准流程效率不高的问题。但是，在此类方案中，轮询方式需要开发人员专门设计轮询程序，每当有硬件改动，轮询程序也必须随之发生变化，而且当总线处于繁忙拥塞状态时，上层会频繁获取总线状态信息，占用系统资源，管理效率极低。也就是说，I2C访问效率低这个问题仍然没有被很好的解决。
综上所述，如何有效地提高I2C访问效率等问题，是目前本领域技术人员急需解决的技术问题。
发明内容
本发明的目的是提供一种I2C总线通信控制方法、装置、系统及可读存储介质，上层应用和底层硬件可以基于轮询表精准的得到总线的通信情况， 可避免频繁获取总线通信情况，按照轮询表来控制I2C总线的通信控制，可避免出现拥塞风险，可提高多个主器件应用场景下的访问效率。
为解决上述技术问题，本发明提供如下技术方案：
一种I2C总线通信控制方法，包括：
接收上层应用发送的I2C总线的配置信息；
解析所述配置信息，得到多条轮询参数；
将多条所述轮询参数写入轮询表中；
控制所述I2C总线，按照所述轮询表执行对应的读写操作。
优选地，还包括：
接收所述上层应用发送的配置修改信息；
利用所述配置修改信息对所述轮询表进行更新。
优选地，解析所述配置信息，得到多条轮询参数，包括：
解析所述配置信息，得到各个所述读写操作分别对应的操作类型、主器件、从器件、字节数、轮询时间和优先级；
利用每一种所述读写操作对应的所述字节数和所述轮询周期，计算出所述读写操作对应的剩余时间；
将一种所述读写操作对应的所述操作类型、所述主器件、所述从器件、所述字节数、所述轮询时间、所述剩余时间和所述优先级作为一条所述轮询参数。
优选地，利用每一种所述读写操作对应的所述字节数和所述轮询周期，计算出所述读写操作对应的剩余时间，包括：
利用所述字节数以及总线频率，计算出执行一次所述读写操作的执行用时；
利用底层时钟，并结合所述执行用时和所述轮询周期，得到所述剩余时间。
优选地，控制所述I2C总线，按照所述轮询表执行对应的读写操作，包括：
按照对应的所述操作类型、所述主器件、所述从器件和所述字节数确定出各个待执行读写操作；
按照所述优先级和所述剩余时间确定出各个所述待执行读写操作的执 行时间；
按照所述执行时间执行各个所述待执行读写操作；
对所述I2C总线的读写操作进行校验，并拦截校验失败的读写操作。
优选地，还包括：
接收所述上层应用发送的通信中断请求；
生成目标读写操作的结束信号；所述目标读写操作为所述I2C总线当前执行的读写操作。
优选地，还包括：
若目标从器件访问失败次数达到降级阈值，则降低所述轮询表中所述目标从器件对应的优先级。
一种I2C总线通信控制装置，包括：
配置信息获取模块，用于接收上层应用发送的I2C总线的配置信息；
解析模块，用于解析所述配置信息，得到每一条轮询参数；
轮询表维护模块，用于将所述轮询参数写入轮询表中；
读写操作执行模块，用于控制所述I2C总线，按照所述轮询表执行对应的读写操作。
一种I2C总线通信控制系统，包括：
上层应用，以及与I2C总线相连接的I2C总线通信控制设备、I2C主器件和I2C从器件；
其中，所述上层应用通过AXI总线访问所述I2C总线通信控制设备；
所述I2C总线通信控制设备包括寄存器、计数器和轮询表；
所述I2C总线通信控制设备，用于执行如上述的I2C总线通信控制方法的步骤。
一种I2C总线通信控制设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现上述I2C总线通信控制方法的步骤。
一种可读存储介质，所述可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述I2C总线通信控制方法的步骤。
应用本发明实施例所提供的方法，接收上层应用发送的I2C总线的配置 信息；解析配置信息，得到多条轮询参数；将多条轮询参数写入轮询表中；控制I2C总线，按照轮询表执行对应的读写操作。
在本方法中，将上层应用发送的配置信息写入到轮询表中，进而得到多条轮询参数。然后，控制I2C总线执行与轮询读取操作参数对应的读写操作即可。可见，在本方法中，由于I2C总线上执行的读写操作是按照轮询表进行的，因而无需轮询访问总线状态，便可直接基于轮询表得到精准的I2C总线的通信情况。也正是因为I2C总线上执行的读写操作是按照轮询表进行的，可大大降低拥塞风险，当存在多个主器件时，也可达到单个主器件的访问效率。对于管理维护方便；若发生硬件或功能变化，仅需对轮询表进行更新即可，而无需修改程序，能够快速适应功能更新或硬件更替。
相应地，本发明实施例还提供了与上述I2C总线通信控制方法相对应的I2C总线通信控制装置、系统和可读存储介质，具有上述技术效果，在此不再赘述。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中一种I2C总线通信控制方法的实施流程图；
图2为本发明实施例中一种I2C总线通信控制装置的结构示意图；
图3为本发明实施例中一种I2C总线通信控制系统的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1，图1为本发明实施例中一种I2C总线通信控制方法的流程图，该方法包括以下步骤：
S101、接收上层应用发送的I2C总线的配置信息。
其中，上层应用(APPLY)，例如运行在手机、平板电脑的应用，该上层应用可具体为个人用户应用，也可以为企业级应用。在本实施例中对上层应用并不做具体限定。
在本实施例中，该上层应用可通过写入的方式，发送I2C总线对应的配置信息，以便基于I2C总线进行数据传递处理。
其中，配置信息可具体为指明哪个主器件需要在何时才有何种方式访问哪个从器件，访问方式是什么，访问字节数多少等。具体的，配置信息可包括主器件、操作类型、从器件、字节数、轮询周期和优先级。
其中，操作类型可分读操作和写操作，字节数即读的位数或写的位数；轮询周期即多长的访问间隔周期，与轮询时间对应；优先级即当出现访问冲突时，确定优先执行哪个主器件的访问需求。
S102、解析配置信息，得到多条轮询参数。
得到配置信息之后，便可对配置信息进行解析，得到多条轮询参数。
其中，一条轮询参数具体对应一种读写操作，在轮询参数可具体包括：操作类型、主器件、从器件、字节数、轮询时间、剩余时间和优先级。
得到轮询参数的过程，包括：
步骤一、解析配置信息，得到各个读写操作分别对应的操作类型、主器件、从器件、字节数、轮询周期和优先级；
步骤二、利用每一种读写操作对应的字节数和轮询时间，计算出读写操作对应的剩余时间；
步骤三、将一种读写操作对应的操作类型、主器件、从器件、字节数、轮询时间、剩余时间和优先级作为一条轮询参数。
其中，步骤二可具体包括：
步骤2.1、利用字节数以及总线频率，计算出执行一次读写操作的执行用时；
步骤2.2、利用底层时钟，并结合执行用时和轮询周期，得到剩余时间。
具体来说，在轮询表中每个序号代表一种I2C读写操作，可采用8位2进制数表示，(8位2进制数共计可表示256种操作，远远大于一条I2C总线的常规操作数)，在序号中通过指定位的数值来区分主器件。
具体的，若有2个主器件，则可采用1位(如最高位)来区别主器件，例如，0标识主器件1，而1标识主器件2；若有3个或4个主器件，则采用2位来区别主器件；若有5-8个主器件，则采用3位来区别主器件；以此类推。每种I2C的操作由SLAVE器件(从器件)的地址，以及slave内部寄存器的偏移地址决定。
字节数(Byte数)表示读操作或者写操作需要占用的字节数，在轮询表的字节数处不需要区分读操作还是写操作。
通过字节数以及系统内部默认的总线频率，可以计算出该次读/写操作的执行用时。而轮询时间则表示周期性获取信息的间隔，剩余时间表示的是距离下一次读/写操作的剩余时间，该时间可从底层时钟确定，即上层应用在获取一次数据后，同步进行倒计时操作。
优选地，可以通过增加访问次数，获得更精确的计时时间。
而优先级则是定义当有冲突将要出现时，优先进行哪一个操作，另一个操作的剩余时间将进行调整延后。
S103、将多条轮询参数写入轮询表中。
得到轮询参数之后，可将轮询参数写入到轮询表。
具体的，在本实施例中，可设置一个表头包括序号、操作类型、从器件、字节数、轮询时间、剩余时间和优先级的类型表；相应地，该配置信息包括操作类型、从器件、字节数、轮询周期和优先级。
举例说明：请参考图2，图2为本发明实施例中一种I2C总线通信控制系统的主要结构示意图。假设I2C总线上有两个主器件，两个从器件AB，其中A、B从器件的地址为0X33、0X34。若配置信息包括：
主器件1与A器件offset0x01有写0x88的操作，轮询周期两秒；
主器件1对B器件offset0x2有读2byte的操作，轮询周期三秒；
主器件2与A器件offset0x01有写0x88的操作，轮询周期两秒；
主器件2对B器件offset0x3有读3byte的操作，轮询周期三秒；
相应的，解析配置信息可得到四条轮询参数，将轮询参数写入轮询表， 得到如下所示的轮询表：
序号 Slave Offset Byte数 轮询时 剩余时间(10us) 优先级
00000001 00110011 00000001 00000001 0111110100 00001110101001100000 01
00000010 00110100 00000010 00000002 1011101110 00001110101001011101 01
10000011 00110011 00000001 00000001 0111110100 00011101010011000000 01
10000100 00110100 00000011 00000003 1011101110 00101011111100100000 10
             
其中，序号的最高位区别主器件，0标识主器件1；1标识主器件2。
可将剩余时间设置为只读数据，剩余时间可在对所有操作分析后自动生成。在常规模式下分析所有数据，以最大轮询周期数为总周期数，将每个任务平均分配在该周期内的各个时间段，保证通信之间的稀疏性。
S104、控制I2C总线，按照轮询表执行对应的读写操作。
即按照轮询表中每一条记录对应一个读写操作的具体轮询读写参照参数，确定出I2C总线所执行的具体读写操作以及具体时间。
具体执行过程，包括：
步骤一、按照对应的操作类型、主器件、从器件和字节数确定出各个待执行读写操作；
步骤二、按照优先级和剩余时间确定出各个待执行读写操作的执行时间；
步骤三、按照执行时间执行各个待执行读写操作；
步骤四、对I2C总线的读写操作进行校验，并拦截校验失败的读写操作。
也就是说，通过轮询表可确定出每个读写操作的具体轮询周期，操作的主器件、从器件、访问类型、访问时间等。而无需每次访问I2C总线都查询一次状态寄存器。即，系统内的全部主器件均按照轮询表通过I2C总线访问从器件。可分析I2C总线传来的数据，并与内部寄存器中的数据进行关联，更新轮询表相关信息。为了保障系统安全，在实际应用，在控制I2C总线执行读写操作时，可以对I2C总线的读写操作进行校验，并拦截校验失败的读写操作。可设置校验功能，即将会拦截不满足校验条件的读 写操作，保护系统安全。
优选地，当系统硬件发生更替，或上层用于功能更新后，还可执行以下步骤来完成I2C适配：
步骤一、接收上层应用发送的配置修改信息；
步骤二、利用配置修改信息对轮询表进行更新。
通过对轮询表进行更新，便可完成I2C适配，无需修改底层访问控制程序。具体的，该配置修改信息可具体为某一种具体的读写操作的轮询时间、访问地址或访问方式的变化，并针对轮询表中的某一条记录进行修改，也可以是对全新的配置信息，对整个轮询表中的全部记录进行更替。
优选地，为了缩短突发通信时延，还可接收上层应用发送的通信中断请求；生成目标读写操作的结束信号；目标读写操作为I2C总线当前执行的读写操作。即能够在紧急通信出现的突发情况下，对当前的I2C总线操作产生结束信号，缩短突发通信时延。
优选地，还可对故障从器件进行标记，减少故障从器件访问次数。也就是说，还可执行：若目标从器件访问失败次数达到降级阈值，则降低轮询表中目标从器件对应的优先级。如果某个地址的从器件持续访问失败(如降级阈值为3，即连续访问失败3次，即视为连续访问失败)，认为该从器件故障，在轮询表中将该从器件降低，如优先级降为最低，进一步降低访问故障从器件的频率。
应用本发明实施例所提供的方法，接收上层应用发送的I2C总线的配置信息；解析配置信息，得到多条轮询参数；将多条轮询参数写入轮询表中；控制I2C总线，按照轮询表执行对应的读写操作。
在本方法中，将上层应用发送的配置信息写入到轮询表中，进而得到多条轮询参数。然后，控制I2C总线执行与轮询读取操作参数对应的读写操作即可。可见，在本方法中，由于I2C总线上执行的读写操作是按照轮询表进行的，因而无需轮询访问总线状态，便可直接基于轮询表得到精准的I2C总线的通信情况。也正是因为I2C总线上执行的读写操作是按照轮询表进行的，可大大降低拥塞风险，当存在多个主器件时，也可达到单个主器件的访问效率。对于管理维护方便；若发生硬件或功能变化，仅需对轮询表进行更新即可，而无需修改程序，能够快速适应功能更新或硬件更 替。
相应于上面的方法实施例，本发明实施例还提供了一种I2C总线通信控制装置，下文描述的I2C总线通信控制装置与上文描述的I2C总线通信控制方法可相互对应参照。
请参考图2，该装置包括：
配置信息获取模块101，用于接收上层应用发送的I2C总线的配置信息；
解析模块102，用于解析配置信息，得到每一条轮询参数；
轮询表维护模块103，用于将轮询参数写入轮询表中；
读写操作执行模块104，用于控制I2C总线，按照轮询表执行对应的读写操作。
应用本发明实施例所提供的装置，接收上层应用发送的I2C总线的配置信息；解析配置信息，得到多条轮询参数；将多条轮询参数写入轮询表中；控制I2C总线，按照轮询表执行对应的读写操作。
在本装置中，将上层应用发送的配置信息写入到轮询表中，进而得到多条轮询参数。然后，控制I2C总线执行与轮询读取操作参数对应的读写操作即可。可见，在本装置中，由于I2C总线上执行的读写操作是按照轮询表进行的，因而无需轮询访问总线状态，便可直接基于轮询表得到精准的I2C总线的通信情况。也正是因为I2C总线上执行的读写操作是按照轮询表进行的，可大大降低拥塞风险，当存在多个主器件时，也可达到单个主器件的访问效率。对于管理维护方便；若发生硬件或功能变化，仅需对轮询表进行更新即可，而无需修改程序，能够快速适应功能更新或硬件更替。
在本发明的一种具体实施方式中，还包括：
轮询表更新模块，用于接收上层应用发送的配置修改信息；利用配置修改信息对轮询表进行更新。
在本发明的一种具体实施方式中，解析模块102，具体用于解析配置信息，得到各个读写操作分别对应的操作类型、主器件、从器件、字节数、轮询周期和优先级；利用每一种读写操作对应的字节数和轮询时间，计算 出读写操作对应的剩余时间；将一种读写操作对应的操作类型、主器件、从器件、字节数、轮询时间、剩余时间和优先级作为一条轮询参数。
在本发明的一种具体实施方式中，解析模块102，具体用于利用字节数以及总线频率，计算出执行一次读写操作的执行用时；利用底层时钟，并结合执行用时和轮询周期，得到剩余时间。
在本发明的一种具体实施方式中，读写操作执行模块104，用于按照对应的操作类型、主器件、从器件和字节数确定出各个待执行读写操作；按照优先级和剩余时间确定出各个待执行读写操作的执行时间；按照执行时间执行各个待执行读写操作；对I2C总线的读写操作进行校验，并拦截校验失败的读写操作。
在本发明的一种具体实施方式中，还包括：
通信中断控制模块，用于接收上层应用发送的通信中断请求；生成目标读写操作的结束信号；目标读写操作为I2C总线当前执行的读写操作。
在本发明的一种具体实施方式中，还包括：
故障处理模块，用于若目标从器件访问失败次数达到降级阈值，则降低轮询表中目标从器件对应的优先级。
相应于上面的方法实施例，本发明实施例还提供了一种I2C总线通信控制系统，下文描述的I2C总线通信控制系统与上文描述的I2C总线通信控制方法可相互对应参照。
请参见图3所示，该系统包括：
上层应用，以及与I2C总线相连接的I2C总线通信控制设备、I2C主器件和I2C从器件；
其中，上层应用通过AXI总线访问I2C总线通信控制设备；
I2C总线通信控制设备包括寄存器、计数器和轮询表；
I2C总线通信控制设备，用于执行如上述方法实施例所描述的I2C总线通信控制方法的步骤。
其中，I2C总线通信控制设备的具体结构可参照图3所示。I2C总线通信控制设备内部主要包括四个功能模块(当然，也可划分出其他组合类型的功能模块，以能够实现方法实施例所提供的I2C总线通信控制为准)：
1、代理单元：负责在紧急通信出现的突发情况下，对当前的I2C总线操作产生结束信号，缩短突发通信时延。例如，在CPU温度过高时，需要马上中断现有的I2C总线所执行的读写操作，以便进行I2C总线的写操作来紧急控制风扇提速。
2、分析模块：负责分析I2C总线传来的数据，并与内部的配置寄存器中的数据进行关联，更新轮询表相关信息。此外，如果开启校验功能，将会拦截不满足校验条件的读写操作，保护系统安全。
3、轮询表：包含轮询表信息，可供I2C总线与AXI总线访问。
4、内部的配置寄存器：可包括各项详细配置，如：安全校验开关、自动重读功能、故障器件标记等。具体说明如下：
安全校验开关：开启后，非最高优先级、从器件地址以及offset地址不符的操作将会被拒绝发起；
自动重读功能：开启后，当一次读或写操作失败后，不需要上层修改，自动将下一次的通信改为本次失败的通信；
故障器件标记：开启后，如果某个地址的从器件持续访问失败，认为该器件故障，在轮询表中将该器件优先级降为最低，降低访问频率。
5、计时器，负责记录总线时序，保证上下时钟频率一致。
基于底层轮询表，对整个I2C总线的资源使用进行重新分配，而且多主器件的情况下有更好的防冲突机制，大大提高了总线利用率，避免了拥塞情况的发生，节省了上层资源。同时安全校验以及故障标记功能极大的提高了总线安全性与稳定性。
相应于上面的方法实施例，本发明实施例还提供了一种可读存储介质，下文描述的一种可读存储介质与上文描述的一种I2C总线通信控制方法可相互对应参照。
一种可读存储介质，可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述方法实施例的I2C总线通信控制方法的步骤。
该可读存储介质具体可以为U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可存储程序代码的可读存储介质。
本领域技术人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。

Claims (10)

  1. 一种I2C总线通信控制方法，其特征在于，包括：
    接收上层应用发送的I2C总线的配置信息；
    解析所述配置信息，得到多条轮询参数；
    将多条所述轮询参数写入轮询表中；
    控制所述I2C总线，按照所述轮询表执行对应的读写操作。
  2. 根据权利要求1所述的I2C总线通信控制方法，其特征在于，还包括：
    接收所述上层应用发送的配置修改信息；
    利用所述配置修改信息对所述轮询表进行更新。
  3. 根据权利要求1所述的I2C总线通信控制方法，其特征在于，解析所述配置信息，得到多条轮询参数，包括：
    解析所述配置信息，得到各个所述读写操作分别对应的操作类型、主器件、从器件、字节数、轮询时间和优先级；
    利用每一种所述读写操作对应的所述字节数和所述轮询周期，计算出所述读写操作对应的剩余时间；
    将一种所述读写操作对应的所述操作类型、所述主器件、所述从器件、所述字节数、所述轮询时间、所述剩余时间和所述优先级作为一条所述轮询参数。
  4. 根据权利要求3所述的I2C总线通信控制方法，其特征在于，利用每一种所述读写操作对应的所述字节数和所述轮询周期，计算出所述读写操作对应的剩余时间，包括：
    利用所述字节数以及总线频率，计算出执行一次所述读写操作的执行用时；
    利用底层时钟，并结合所述执行用时和所述轮询周期，得到所述剩余时间。
  5. 根据权利要求3所述的I2C总线通信控制方法，其特征在于，控制所述I2C总线，按照所述轮询表执行对应的读写操作，包括：
    按照对应的所述操作类型、所述主器件、所述从器件和所述字节数确定出各个待执行读写操作；
    按照所述优先级和所述剩余时间确定出各个所述待执行读写操作的执行时间；
    按照所述执行时间执行各个所述待执行读写操作；
    对所述I2C总线的读写操作进行校验，并拦截校验失败的读写操作。
  6. 根据权利要求1所述的I2C总线通信控制方法，其特征在于，还包括：
    接收所述上层应用发送的通信中断请求；
    生成目标读写操作的结束信号；所述目标读写操作为所述I2C总线当前执行的读写操作。
  7. 根据权利要求1所述的I2C总线通信控制方法，其特征在于，还包括：
    若目标从器件访问失败次数达到降级阈值，则降低所述轮询表中所述目标从器件对应的优先级。
  8. 一种I2C总线通信控制装置，其特征在于，包括：
    配置信息获取模块，用于接收上层应用发送的I2C总线的配置信息；
    解析模块，用于解析所述配置信息，得到每一条轮询参数；
    轮询表维护模块，用于将所述轮询参数写入轮询表中；
    读写操作执行模块，用于控制所述I2C总线，按照所述轮询表执行对应的读写操作。
  9. 一种I2C总线通信控制系统，其特征在于，包括：
    上层应用，以及与I2C总线相连接的I2C总线通信控制设备、I2C主器件和I2C从器件；
    其中，所述上层应用通过AXI总线访问所述I2C总线通信控制设备；
    所述I2C总线通信控制设备包括寄存器、计数器和轮询表；
    所述I2C总线通信控制设备，用于执行如权利要求1至7任一项所述的I2C总线通信控制方法的步骤。
  10. 一种可读存储介质，其特征在于，所述可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述I2C总线通信控制方法的步骤。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115220675A (zh) * 2022-05-20 2022-10-21 广东逸动科技有限公司 显示设备的控制方法、显示设备及计算机存储介质
CN117240651A (zh) * 2023-11-14 2023-12-15 广东宝莱特医用科技股份有限公司 查询设备上线的方法、遥测系统、电子设备和存储介质

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111737173B (zh) 2020-06-24 2022-03-22 浪潮(北京)电子信息产业有限公司 I2c总线通信控制方法、装置、系统及可读存储介质
CN112463662B (zh) * 2020-12-16 2024-04-05 福州创实讯联信息技术有限公司 一种用户态控制i2c设备的方法与终端
CN113641618B (zh) * 2021-08-12 2024-06-18 海信空调有限公司 Iic通讯控制方法、用电设备和计算机可读存储介质
CN113986803B (zh) * 2021-10-21 2024-05-28 山东云海国创云计算装备产业创新中心有限公司 一种i2c总线控制方法、装置、器件及存储介质
TWI845154B (zh) * 2023-02-09 2024-06-11 大陸商北京集創北方科技股份有限公司 數據傳輸電路、電子晶片及資訊處理裝置
CN116132383B (zh) * 2023-04-13 2023-07-18 苏州浪潮智能科技有限公司 信息传输装置、系统及方法
CN116185915B (zh) * 2023-04-21 2023-08-04 山东云海国创云计算装备产业创新中心有限公司 总线调度方法、装置及设备、介质和基板管理控制芯片

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7188202B1 (en) * 2003-09-29 2007-03-06 Emc Corporation Techniques for accessing devices through a set of serial buses
US20100318693A1 (en) * 2009-06-11 2010-12-16 Espig Michael J Delegating A Poll Operation To Another Device
CN105279133A (zh) * 2015-10-20 2016-01-27 电子科技大学 基于SoC在线重构的VPX并行DSP信号处理板卡
CN111090600A (zh) * 2019-12-09 2020-05-01 苏州浪潮智能科技有限公司 一种总线共享的方法
CN111737173A (zh) * 2020-06-24 2020-10-02 浪潮(北京)电子信息产业有限公司 I2c总线通信控制方法、装置、系统及可读存储介质

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6938103B2 (en) * 2001-10-19 2005-08-30 Dell Products L.L.P. Universal serial bus transaction processing tasks scheduling method for computer system, involves assigning transaction to periodic queue head list with faster polling interval
WO2009012810A1 (en) * 2007-07-23 2009-01-29 Telefonaktiebolaget Lm Ericsson (Pub) Database system with multiple layer distribution
US8024499B1 (en) * 2008-01-17 2011-09-20 Juniper Networks, Inc. Systems and methods for automated sensor polling
US10019546B1 (en) * 2015-10-30 2018-07-10 Amazon Technologies, Inc. Modular system on chip configuration system
US10467890B2 (en) * 2016-05-13 2019-11-05 Microsoft Technology Licensing, Llc Secured sensor interface
US10348834B2 (en) * 2016-10-24 2019-07-09 Graywolf Sensing Solutions, Llc Self configuring smart probe
CN107066413B (zh) * 2016-12-30 2023-11-24 幻境(珠海)科技有限公司 一种用于处理多个总线设备数据的方法及其总线系统
CN106936647B (zh) * 2017-04-26 2020-02-14 成都成电光信科技股份有限公司 一种新型gjb289a总线的配置方法
TWI662410B (zh) * 2017-12-18 2019-06-11 慧榮科技股份有限公司 資料儲存裝置與記憶體裝置之資料處理方法
US10860509B1 (en) * 2019-07-23 2020-12-08 Texas Instruments Incorporated Multi-device burst update method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7188202B1 (en) * 2003-09-29 2007-03-06 Emc Corporation Techniques for accessing devices through a set of serial buses
US20100318693A1 (en) * 2009-06-11 2010-12-16 Espig Michael J Delegating A Poll Operation To Another Device
CN105279133A (zh) * 2015-10-20 2016-01-27 电子科技大学 基于SoC在线重构的VPX并行DSP信号处理板卡
CN111090600A (zh) * 2019-12-09 2020-05-01 苏州浪潮智能科技有限公司 一种总线共享的方法
CN111737173A (zh) * 2020-06-24 2020-10-02 浪潮(北京)电子信息产业有限公司 I2c总线通信控制方法、装置、系统及可读存储介质

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115220675A (zh) * 2022-05-20 2022-10-21 广东逸动科技有限公司 显示设备的控制方法、显示设备及计算机存储介质
CN115220675B (zh) * 2022-05-20 2024-04-09 广东逸动科技有限公司 显示设备的控制方法、显示设备及计算机存储介质
CN117240651A (zh) * 2023-11-14 2023-12-15 广东宝莱特医用科技股份有限公司 查询设备上线的方法、遥测系统、电子设备和存储介质
CN117240651B (zh) * 2023-11-14 2024-03-22 广东宝莱特医用科技股份有限公司 查询设备上线的方法、遥测系统、电子设备和存储介质

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