WO2021249097A1 - 驱动电路和驱动方法，以及显示装置 - Google Patents

驱动电路和驱动方法，以及显示装置 Download PDF

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Publication number
WO2021249097A1
WO2021249097A1 PCT/CN2021/093411 CN2021093411W WO2021249097A1 WO 2021249097 A1 WO2021249097 A1 WO 2021249097A1 CN 2021093411 W CN2021093411 W CN 2021093411W WO 2021249097 A1 WO2021249097 A1 WO 2021249097A1
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WIPO (PCT)
Prior art keywords
pixel
unit
sub
polarity
multiplexing unit
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PCT/CN2021/093411
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English (en)
French (fr)
Inventor
孙建
王珍
许梦兴
山岳
秦文文
杨小艳
王继国
张寒
王德帅
闫伟
张健
张亚东
张洁
刘建涛
Original Assignee
京东方科技集团股份有限公司
华为技术有限公司
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Publication of WO2021249097A1 publication Critical patent/WO2021249097A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements

Definitions

  • This application relates to the field of display, in particular, to a driving circuit and a driving method, and a display device.
  • liquid crystal display devices In order to increase the transmittance of the panel, liquid crystal display devices, especially those designed based on RGB pixels, can replace half of the B pixels with W pixels on the basis of the original RGB pixels, so as to increase the overall transmittance of the panel and reduce The effect of backlight power consumption.
  • the RGBW pixel design and the multiplexing circuit (MUX) connection design are not appropriate, the crosstalk will be poor.
  • liquid crystal display devices especially drive circuits and drive methods based on RGBW pixel designs, and display devices still need to be improved.
  • the liquid crystal display panel has a plurality of pixel units arranged in an array.
  • the pixel unit includes 6 sub-pixels.
  • the 6 sub-pixels are arranged into two pixel rows and three pixel columns.
  • the first pixel column has two first sub-pixels.
  • Pixel, the second pixel column has two second sub-pixels
  • the third pixel column has a third sub-pixel and a fourth sub-pixel, and two adjacent pixel units along the extending direction of the pixel row
  • the arrangement order of the third sub-pixels and the fourth sub-pixels of the third pixel column in the third pixel column is opposite, and the driving circuit includes a driving chip, a gate driving unit, and a plurality of multiplexing units.
  • the driving chip is configured to provide a gate driving signal to the gate driving unit and to provide a source driving signal to the multiplexing unit through a data bus.
  • the driving circuit includes a first polarity data bus and a second polarity data bus. Polar data bus, each of the multiplexing unit is connected to a data bus, and the source driving signal is output to a plurality of data lines, each of the data lines is connected to a pixel column, located in the same row A part of the plurality of third sub-pixels is connected to the first polarity data bus, and the other part is connected to the second polarity data bus; One part is connected to the first polarity data bus, and the other part is connected to the second polarity data bus.
  • the sub-pixels of the same color in each pixel row can have opposite polarities, which can alleviate or even solve the problem of common electrode (VCOM) ) Coupling, thereby alleviating the cross-color problem caused by the change of the voltage difference between the common electrode and the pixel electrode.
  • VCOM common electrode
  • the first sub-pixel is red
  • the second sub-pixel is green
  • the third sub-pixel is blue
  • the fourth sub-pixel is white
  • the first sub-pixel is The opening area and the opening area of the second sub-pixel are the same
  • the ratio of the opening area of the fourth sub-pixel to the opening area of the first sub-pixel is 0.3-0.6
  • the opening area of the third sub-pixel is the same as the opening area of the third sub-pixel.
  • the opening area of a sub-pixel is 1.5-2.5 times. As a result, the transmittance can be increased while keeping the PPI from falling.
  • the widths of the third sub-pixel and the fourth sub-pixel are the same, the length of the third sub-pixel is 1.5-2.5 times the length of the fourth sub-pixel, and the third sub-pixel
  • the width of the pixel is greater than the width of the first sub-pixel, and the length of the third sub-pixel is greater than the length of the first sub-pixel.
  • the multiplexing unit includes: an input terminal connected to the data bus for receiving the source drive signal; three control terminals and three output terminals, the The control terminal receives a control signal, each of the control terminals is used to control the output of one output terminal, and the three output terminals are respectively connected to different data lines.
  • one source driving signal can be used to source the three columns of sub-pixels, so that the size of the driving chip can be reduced, and the cost can be reduced.
  • the driving circuit includes a plurality of multiplexing unit groups, and the multiplexing unit group has a first multiplexing unit, a second multiplexing unit, and a third multiplexing unit.
  • the source driving signal output by the first multiplexing unit and the third multiplexing unit has a first polarity
  • the second multiplexing unit The source drive signals output by the multiplexing unit and the fourth multiplexing unit both have the second polarity, and the drive circuit can utilize the first multiplexing unit and the second multiplexing unit.
  • the use unit, the third multiplexing unit, and the fourth multiplexing unit apply voltage to the data line with every 12 sub-pixel columns as a cycle.
  • the sub-pixels of multiple colors in each pixel row can have opposite polarities.
  • the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are arranged in sequence, and the first multiplexing unit is connected to one of the first pixel units.
  • One-polarity data bus connection has a first polarity
  • the first output end of the first multiplexing unit is connected to the first pixel column of the first pixel unit, and the second output end is connected to the first pixel
  • the third pixel column of the unit is connected, and the third output terminal is connected to the second pixel column of the second pixel unit;
  • the second multiplexing unit is connected to one of the second polarity data buses and has a second polarity.
  • the first output terminal of the second multiplexing unit is connected to the second pixel column of the first pixel unit, the second output terminal is connected to the first pixel column of the second pixel unit, and the third output terminal is connected to the first pixel column of the second pixel unit.
  • the output terminal is connected to the third pixel column of the second pixel unit; the third multiplexing unit is connected to another data bus of the first polarity having the first polarity, and the third multiplexing unit is connected to another data bus of the first polarity.
  • the first output terminal of the multiplexing unit is connected to the first pixel column of the third pixel unit, the second output terminal is connected to the second pixel column of the fourth pixel unit, and the third output terminal is connected to the fourth pixel unit.
  • the third pixel column of the pixel unit is connected; the fourth multiplexing unit is connected to another data bus of the second polarity having the second polarity, and the first of the fourth multiplexing unit
  • the output terminal is connected to the second pixel column of the third pixel unit, the second output terminal is connected to the third pixel column of the third pixel unit, and the third output terminal is connected to the first pixel column of the fourth pixel unit.
  • the first pixel column has a plurality of red sub-pixels
  • the second pixel column has a plurality of green sub-pixel columns
  • the third pixel column has a plurality of white and blue sub-pixels. Therefore, it is easy to make the sub-pixels of different colors in the same pixel row have opposite polarities.
  • the driving circuit includes a plurality of cascaded gate driving units, and the gate driving unit includes a gate input terminal for receiving the gate driving signal, a clock input terminal, and a reset input.
  • Terminal and output terminal the four gate driving units include a first-stage gate driving unit, a second-stage gate driving unit, a third-stage gate driving unit and a fourth-stage gate driving unit, the third The output terminal of the gate driving unit is connected to the reset input terminal of the first gate driving unit, and the output terminal of the first gate driving unit is connected to the reset input terminal of the third gate driving unit.
  • the gate input terminal is connected, and the clock input terminals of the first-stage gate driving unit and the third-stage gate driving unit are both connected to the first gate clock signal and the third gate clock signal, so The clock input terminals of the second-stage gate driving unit and the fourth-stage gate driving unit are both connected to a second gate clock signal and a fourth gate clock signal.
  • the performance of the drive circuit can be further improved.
  • this application proposes a method for driving the aforementioned driving circuit.
  • the method includes: using a driving chip to provide a gate driving signal to a gate driving unit to scan a plurality of pixel rows row by row, using the driving chip to provide a source driving signal to the multiplexing unit through a data bus and A voltage is applied to the data line so that the multiple sub-pixels located in the same column have the same polarity, and the multiple sub-pixels located in the same row and the same color may have opposite polarities.
  • VCOM common electrode
  • a voltage is applied to the data line in a period of every 12 adjacent pixel columns, and a first multiplexing unit connected to a first polarity data bus is used to transfer a voltage to the first pixel unit.
  • the data lines of the first pixel column, the third pixel column, and the second pixel column of the second pixel unit output a first polarity voltage signal, and a second multiplexing unit connected to a second polarity data bus is used
  • the second-polarity voltage signal is output to the second pixel column of the first pixel unit, the first pixel column of the second pixel unit, and the data line of the third pixel column.
  • the third multiplexing unit connected to the polarity data bus outputs the first pixel column to the data line of the first pixel column of the third pixel unit and the second pixel column and the third pixel column of the fourth pixel unit.
  • the polarity voltage signal is transmitted to the second pixel column, the third pixel column and the fourth pixel unit of the third pixel unit by using the fourth multiplexing unit connected to the other second polarity data bus
  • the data line of the first pixel column outputs the second polarity voltage signal
  • the first pixel column has a plurality of red sub-pixels
  • the second pixel column has a plurality of green sub-pixel columns
  • the first pixel column has a plurality of green sub-pixel columns.
  • the three-pixel column has multiple white and blue sub-pixels. Thus, multiple sub-pixels in the same row and of the same color can be easily made to have opposite polarities.
  • control signals are applied to the multiple control terminals of the multiplexing unit in order to make the multiple output terminals of the multiplexing unit follow the order from the first pixel column and the first pixel column.
  • the sequence from the second pixel column to the third pixel column is opened.
  • the source drive signal sent by the drive chip to the input ends of the first multiplexing unit and the fourth multiplexing unit adopts a first set of clock signals to transmit
  • the source drive signals sent by the input ends of the second multiplexing unit and the third multiplexing unit use a second set of clock signals, and the first set of clock signals and the second set of clocks The signal does not turn on at the same time.
  • a plurality of sub-pixels that are located in the same row and have the same color can have opposite polarities easily.
  • the polarity of each pixel column is reversed every predetermined time interval. As a result, fatigue caused by long-term deflection of liquid crystal molecules to the same side can be prevented.
  • this application proposes a display panel.
  • the display panel includes the aforementioned driving circuit. Therefore, the display panel can make the coupling of sub-pixels (such as B pixels) in the same pixel row to VCOM cancel each other, thereby improving the crosstalk.
  • Fig. 1 shows a schematic structural diagram of a driving circuit according to an example of the present application
  • Fig. 2 shows a schematic structural diagram of a pixel structure according to an example of the present application
  • Fig. 3 shows a partial structural diagram of a pixel structure according to an example of the present application
  • Fig. 4 shows a schematic structural diagram of a driving circuit according to an example of the present application
  • Fig. 5 shows a block diagram of a multiplexing circuit according to an example of the present application
  • FIG. 6 shows a schematic diagram of a part of the driving circuit and the pixel structure according to Comparative Example 1 of the present application;
  • FIG. 7 shows a schematic diagram of part of the driving circuit and the pixel structure according to an example of the present application.
  • FIG. 8 shows a schematic diagram of the voltage of each line under the crosstalk screen of the blue screen according to Comparative Example 1 of the present application;
  • FIG. 9 shows a schematic diagram of the voltage of each line in the blue screen according to an example of the present application.
  • Fig. 10 shows a schematic circuit diagram of a gate driving unit according to an example of the present application
  • FIG. 11 shows a schematic circuit diagram of multiple cascaded gate driving units according to an example of the present application.
  • FIG. 12 shows a timing diagram of a driving method according to an example of the present application.
  • Figure 13 shows a result diagram of an example of a lighting test in the related art
  • Fig. 14 shows a result diagram of a lighting test according to an example of the present application.
  • the driving circuit includes a driving chip, a gate driving unit, and multiple multiplexing units, which can make multiple sub-pixels of the same color in the same pixel row have different polarities during display, thereby alleviating or even solving the aforementioned problems.
  • the coupling to the common electrode (VCOM) caused by the same polarity of the sub-pixels of the same color in the same row can alleviate the cross-color problem caused by the change of the voltage difference between the common electrode and the pixel electrode.
  • the pixel structure of the display panel includes a plurality of pixel units 100 arranged in an array (100A and 100B as shown in the figure).
  • the pixel unit 100 includes 6 sub-pixels and 6 sub-pixels. Arranged into two pixel rows and three pixel columns, the first pixel column has two first sub-pixels 1, the second pixel column has two second sub-pixels 2, and the third pixel column has a third sub-pixel 3 and For a fourth sub-pixel 4, the arrangement order of the third sub-pixel 3 and the fourth sub-pixel 4 in the third pixel column of the two adjacent pixel units in the direction in which the pixel row extends is opposite.
  • the sub-pixels in the third column of two adjacent pixel units in the pixel structure are not the third sub-pixel 3 at the same time, and they are not the fourth sub-pixel 4 at the same time.
  • Multiple sub-pixels in each pixel column are connected to the same data line 11 (11A-11F as shown in the figure). .
  • the driving circuit includes a first polarity data bus and a second polarity data bus (not shown in the figure), each multiplexing unit is connected to a data bus, and the source driving signal is output to a plurality of data lines , Each data line is connected to a pixel column, a part of the plurality of third sub-pixels in the same row is connected to the first polarity data bus, and the other part is connected to the second polarity data bus. A part of the fourth sub-pixels is connected to the first polarity data bus, and the other part is connected to the second polarity data bus.
  • RGBW pixel arrangement There is a known RGBW pixel arrangement.
  • the first sub-pixel is red and the second sub-pixel is green, as described above, in order to increase the transmittance of the panel, half of the B pixels are replaced with W pixels.
  • one pixel column is used to connect to the same MUX (multiplexing unit)
  • the output end of each MUX is connected to three data lines and the source driving signals of two adjacent MUXs have opposite polarities (one is positive, When the other is negative), the sub-pixels of the same color in the same row may have the same polarity.
  • the first multiplexing circuit can provide positive source drive signals to the data lines 11A, 11C, and 11E, and the second multiplexing circuit can provide negative electricity to the data lines 11B, 11D, and 11F.
  • the source drive signal At this time, for the first sub-pixel 1, the polarities of the first sub-pixel 1 (connected to the data line 11A) in the pixel unit 100A and the first sub-pixel 1 (connected to the data line 11D) in the second pixel unit 100B The opposite is true.
  • the third sub-pixel 3 (connected to the data line 11C) in the pixel unit 100A is connected to the fourth sub-pixel 4 (the first pixel row of the pixel unit 100B) connected to the data line 11F.
  • the connection of the data line, the third sub-pixel and the fourth sub-pixel in the same row can have two different polarities, so that the data line can be eliminated in the direction of the pixel row. Coupling to the common electrode. Therefore, it is possible to prevent poor cross-color due to the coupling effect to the common electrode when displaying a picture of a certain color.
  • the color of the aforementioned sub-pixels is not particularly limited, as long as the sub-pixels of two colors in adjacent pixel units are interchanged in a certain pixel column.
  • the first sub-pixel may be red
  • the second sub-pixel may be green
  • the third sub-pixel may be blue
  • the fourth sub-pixel may be white.
  • the white fourth sub-pixel can be used to increase the transmittance of the panel using the pixel structure.
  • the opening areas of the two first sub-pixels in the same pixel unit are the same, and the opening areas of the two second sub-pixels are the same.
  • the opening area of the first sub-pixel and the second sub-pixel may be the same, and the opening area of the third sub-pixel is 1.5-2.5 times the opening area of the first sub-pixel, for example, it may be twice.
  • the ratio of the opening area of the fourth sub-pixel to the opening area of the first sub-pixel may be 0.3-0.6, for example, 0.5.
  • the “width” of the sub-pixel refers to the size of the sub-pixel in the direction along the pixel row
  • the “length” refers to the size of the sub-pixel along the pixel column. The size in the direction.
  • the terms “equal”, “same”, “identical”, etc. should be understood in a broad sense, that is, there is no difference in the area, length, width and other dimensions of the two, and they are not strictly equal. Tolerance within the allowable range.
  • the width of the third sub-pixel and the fourth sub-pixel may be the same, and the length of the third sub-pixel is twice the length of the fourth sub-pixel.
  • the width of the third sub-pixel may be greater than the width of the first sub-pixel, and the length of the third sub-pixel may be greater than the length of the first sub-pixel.
  • the first and second sub-pixels can be made slightly narrower, and the third and fourth sub-pixels can have the same width and be larger than the width of the first sub-pixel, thereby increasing the opening area of the third sub-pixel.
  • the total area of the pixel unit in the pixel structure remains unchanged.
  • the pixel unit with 6 sub-pixels shown in Table 1 below is taken as an example.
  • the 6 sub-pixels are 2 R, 2 G, and 2 B sub-pixels arranged in three columns (that is, the W sub-pixel is not used)
  • the size of the 6 sub-pixels can all be 21 ⁇ m ⁇ 63 ⁇ m.
  • the B pixel in the RGBW pixel unit (the structure shown in FIG.
  • the pixel structure does not cause a decrease in PPI.
  • the driving circuit includes a driving chip 400, a gate driving unit 300 and a multiplexing unit 200.
  • the driving chip is configured to provide a gate driving signal to the gate driving unit and to provide a source driving signal to the multiplexing unit.
  • the driving circuit may have multiple data buses.
  • the first polarity data bus has a first polarity, such as positive; the second polarity data bus has a second polarity, such as negative.
  • Each multiplexing unit is connected to a data bus and outputs source driving signals to a plurality of data lines, and each data line is connected to a pixel column.
  • a part of the plurality of third sub-pixels in the same row is connected to the first polarity data bus, and the other part is connected to the second polarity data bus; a part of the plurality of fourth sub-pixels in the same row is connected to the first polarity The other part is connected to the second polarity data bus.
  • the multiple first sub-pixels located in the same row also have the first and second polarities
  • the multiple second sub-pixels located in the same row also have the first and second polarities.
  • the sub-pixels of the same color in each pixel row can have opposite polarities, which can alleviate or even solve the problem of common electrode (VCOM) ) Coupling, thereby alleviating the cross-color problem caused by the change of the voltage difference between the common electrode and the pixel electrode.
  • VCOM common electrode
  • the type of the driver chip is not particularly limited.
  • TED technology can be used, that is, a method in which TCON and Driver are integrated into a single IC for processing.
  • the driver chip (IC) can be bound on a flexible circuit board (FPC) and integrated on the display panel by means including but not limited to COF.
  • FPC flexible circuit board
  • COF organic compound
  • an oxide thin film transistor since it can have a higher on-state current (I on ) compared to a polysilicon thin film transistor, it can be fully charged in a shorter time, thereby realizing a higher data line multiplexing method.
  • I on on-state current
  • FIG. 1 on-state current
  • the multiplexing unit may include an input terminal 210 to receive a source driving signal, and the input terminal 210 is connected to a data bus.
  • Three control terminals (221, 222, and 223) and three output terminals (231, 232, 233) correspond one to one.
  • the control terminals receive control signals, and each control terminal is used to control the output of one output terminal.
  • the three output terminals are respectively Connect with different data lines.
  • the three control terminals can respectively correspond to the pixel columns in the aforementioned pixel structure.
  • the control terminal 221 can correspond to the pixel column where the red sub-pixel is located (MUXR)
  • the control terminal 222 can correspond to the pixel column where the green sub-pixel is located (MUXG).
  • the control terminal 223 can correspond to the pixel column (MUXB) where the blue and white sub-pixels are located, so that one source driving signal can be used to source the three columns of sub-pixels, thereby reducing the size of the driver chip and reducing the cost.
  • MUXB pixel column
  • the driving circuit may have multiple multiplexing unit groups, and each multiplexing unit group specifically includes a first multiplexing unit, a second multiplexing unit, and a third multiplexing unit. Multiplexing unit and fourth multiplexing unit.
  • the input terminal received by the first multiplexing unit receives the source driving signal of the first polarity data bus S1
  • the input terminal received by the third multiplexing unit receives the source driving signal of the second polarity data bus S3.
  • the input terminal received by the second multiplexing unit receives the source driving signal of another data bus S2 of the first polarity
  • the fourth multiplexing unit receives the source driving signal of another second-polarity data bus S4 and all have the second polarity (negative electricity is taken as an example in the figure).
  • the polarity of the source driving signal output from the output terminal of the multiplexing unit to the data line (11A, 11D, etc. as shown in the figure) is the same as the polarity of the source driving signal it receives.
  • the driving circuit can use the first multiplexing unit, the second multiplexing unit, the third multiplexing unit and the fourth multiplexing unit to apply every 12 sub-pixel columns as a cycle to the data line Voltage.
  • the multiple multiplexing units cooperate to apply voltage to the data lines in the display panel to realize display.
  • the sub-pixels of multiple colors in each pixel row can have opposite polarities.
  • the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are arranged in sequence, and each pixel unit has 3 pixel columns, that is, a period of 12 sub-pixel columns is formed.
  • the first output terminal of the first multiplexing unit is connected to the first pixel column of the first pixel unit, the second output terminal is connected to the third pixel column of the first pixel unit, and the third output terminal is connected to the second pixel unit.
  • the second pixel column is connected; the first output terminal of the second multiplexing unit is connected to the second pixel column of the first pixel unit, the second output terminal is connected to the first pixel column of the second pixel unit, and the third output terminal Connected to the third pixel column of the second pixel unit;
  • the first output terminal of the third multiplexing unit is connected to the first pixel column of the third pixel unit, and the second output terminal is connected to the second pixel column of the fourth pixel unit Connected, the third output terminal is connected to the third pixel column of the fourth pixel unit;
  • the first output terminal of the fourth multiplexing unit is connected to the second pixel column of the third pixel unit, and the second output terminal is connected to the third pixel
  • the sub-pixels of different colors in the same pixel row can all have opposite polarities.
  • the data lines connected to the output ends of the first multiplexing unit and the second multiplexing voltage may be spaced apart from each other.
  • the polarities of the first 6 sub-pixels in the first pixel row are positive and negative intervals.
  • the second and third output ends of the third multiplexing unit are connected to the last two of the 12 sub-pixels, and the data line connected to the first output end and the data line connected to the second output end are multiplexed by the fourth multiplexing unit. Separate with the data lines connected to the 3 output terminals of the unit.
  • the first six sub-pixels of the 12 sub-pixels have the first polarity (positive polarity), the middle three have the second polarity (negative polarity), and the last two have the first polarity (positive polarity). ). Since the arrangement order of the third sub-pixel (B) and the fourth sub-pixel (W) in the third sub-pixel column in the aforementioned pixel structure will be exchanged in the next pixel unit, a period of 12 sub-pixels is used.
  • the connection mode of the driving circuit can ensure that all color sub-pixels in the same row can have opposite polarities.
  • the specific type and number of the gate driving unit are not particularly limited, as long as the gate driving can be realized.
  • the driving circuit includes a plurality of cascaded gate driving units. 10 and 11, multiple gate driving units may have multiple input terminals, such as gate input terminals, clock input terminals, reset input terminals, etc., for receiving gate drive signals (STV) and timing signals Wait.
  • the circuit structure of the gate driving unit may be as shown in FIG. 11, that is, it may include a plurality of thin film transistors and capacitors, and specifically may have a plurality of thin film transistors connected in parallel, thereby further improving the performance of the driving circuit.
  • CN and CNB in the gate drive unit are signals for controlling positive and negative sweeps, CN is high level, when CNB is low, it is forward sweep, and vice versa, it is reverse sweep, which can prevent long-term maintenance of a certain power.
  • the life of the device is shortened due to the nature.
  • VGH_G and VGL_G provide high and low level signals for gate drive.
  • RESET is a reset signal, and it is low level during normal display.
  • EN_Touch is a signal related to the touch module (Touch). At the time of Touch, EN_Touch is high level, and when it is displayed, it is low level.
  • the cascade of multiple gate driving units may be as shown in FIG. 11, and the four gate driving units may include a first-level gate driving unit, a second-level gate driving unit, and a third-level gate driving unit.
  • the fourth-stage gate drive unit the output terminal of the third gate drive unit (Gate_N+2 as shown in the figure) and the reset input of the first gate drive unit (Gate_N as shown in the figure)
  • the output terminal of the first gate driving unit is connected to the gate input terminal of the third gate driving unit.
  • the output (OUT) of the first gate driving unit can control the opening of Gate_N (that is, the gate line of the Nth row, as shown in the structure perpendicular to the data line in Figure 7), and at the same time connect and control the gate line Gate_N+2 that is separated from it by one row.
  • the output (OUT) of the gate line Gate_N+2 separated by one row can be connected to the reset input terminal (RST) of the gate line Gate_N separated by one row at the same time. In this way, the progressive scan of the gate line is realized.
  • the clock input terminals of the first-stage gate driving unit and the third-stage gate driving unit are both connected to the first gate clock signal and the third gate clock signal (CK1 and CK3 as shown in the figure), and the second The clock input terminals of the second gate driving unit and the fourth gate driving unit (Gate_N+3 as shown in the figure) are both connected to the second gate clock signal and the fourth gate clock signal (as shown in the figure).
  • CK1 and CK3 are connected.
  • Still other examples of this application propose a method of driving the previous driving circuit.
  • the method includes: using a driving chip to provide a gate driving signal to a gate driving unit to scan a plurality of pixel rows row by row, and using a driving chip to provide a source driving signal to a multiplexing unit through a data bus and apply it to a data line Voltage so that multiple sub-pixels located in the same column have the same polarity, and multiple sub-pixels located in the same row and the same color can have opposite polarities.
  • VCOM common electrode
  • a voltage is applied to the data line in a period of every 12 adjacent pixel columns.
  • the first pixel unit, the second pixel unit, the third pixel unit, and the fourth pixel unit are arranged in sequence in the direction extending along the pixel row, and the first multiplexing unit (input terminal connected Figure 7 shows S1) so that the first pixel column, the third pixel column of the first pixel unit, and the second pixel column of the second pixel unit (the fifth column from the left in the figure) have the first polarity ( If it is positive), the second multiplexing unit (input terminal connected to S2 shown in Figure 8) is used to make the second pixel column of the first pixel unit, the first pixel column of the second pixel unit, and the third pixel The column has the second polarity (if negative), and the third multiplexing unit (the input terminal is connected to S3 shown in FIG.
  • the second pixel column and the third pixel column have the first polarity (if positive), and the fourth multiplexing unit (the input terminal is connected to S4 shown in FIG. 7) is used to make the second pixel column of the third pixel unit ,
  • the third pixel column and the first pixel column of the fourth pixel unit have the second polarity (for example, negative). In this way, a plurality of sub-pixels located in the same row and of the same color can have opposite polarities.
  • control signals are sequentially applied to the multiple control terminals of the multiplexing unit, so that the multiple output terminals of the multiplexing unit are arranged from the first pixel column, the second pixel column to the third pixel column.
  • the order of opening As a result, the display effect of the driving method can be further improved.
  • the driver chip can use the first set of clock signals to send source drive signals to the input ends of the first multiplexing unit and the fourth multiplexing unit to the second multiplexing unit and the third multiplexing unit.
  • the source driving signal sent by the input end of the multiplexing unit adopts the second set of clock signals, and the first set of clock signals and the second set of clock signals are not turned on at the same time. In this way, a plurality of sub-pixels that are located in the same row and have the same color can have opposite polarities easily.
  • timing signals to the gate driving unit can make the gate driving unit control a plurality of gate lines to turn on sequentially to realize progressive scanning.
  • Figure 12 is a timing diagram of gate drive and MUX coordination.
  • the control terminal of the multiplexing circuit is turned on in the order of the first pixel column (MUXB), the second pixel column (MUXG) to the third pixel column (MUXR).
  • the screen needs to output different signals.
  • the blue screen is shown in the figure as an example.
  • the cascading situation of the gate driving units is as described above, and will not be repeated here. Take Gate_N-2 in FIG. 12 (the structure of the gate drive unit is similar to Gate_N+2 shown in FIG.
  • Gate_N-1 when Gate_N-1 outputs the first pulse signal, the first set of clock signals of S1 and S4 are turned off, the second set of clock signals of S2 and S3 are turned on, and S2 and S3 output the second pulse signal when MUXB is turned on.
  • a voltage is applied to the data line of the negative pixel column shown in FIG. 7 to realize a blue screen display.
  • the polarity of each pixel column can be reversed every predetermined time interval.
  • the predetermined time may be the time for displaying one frame of picture, that is, when displaying the first frame of picture, S1 and S4 are set to positive polarity, S2 and S3 are set to negative polarity, and when the next frame of picture is displayed, S1 and S4 are set to negative polarity. , S2 and S3 are positive polarity.
  • the data lines 11C and 11F are located through the blue lighted area shown in FIG. The area shown by the frame), the data line 11A is located in the white picture area on the left side of the blue lighted area.
  • the period t1-t3 is a positive frame display, and the subsequent period is a negative frame display.
  • the grayscale display is displayed at t1.
  • the positions of the three data lines are all grayscale images.
  • the data lines will not be inverted and maintain a level (2.5V).
  • 11C and 11F display blue images.
  • the data lines It will continue to flip between the high level (5V) and 0V, and the data line 11A is still a gray-scale image, and it still maintains 2.5V.
  • the polarity of 11C is opposite to that of 11F, so there is no coupling capacitor between the data line and the common electrode VCOM when the data line is inverted, and the pixel electrode voltage (Pixel E) is not affected. Therefore, the blue screen has no crosstalk.
  • the connection relationship shown in FIG. 6 since the data lines 11C and 11F are both positive, there is a coupling capacitor between the data line and VCOM, and VCOM will be affected by the coupling capacitor. Referring to Figure 8, when the data line jumps upwards, VCOM is coupled upwards.
  • VCOM When the data line jumps downwards, VCOM is coupled downwards, and the voltage jumps upwards or downwards, although VCOM will slowly return to Set value, but the VCOM recovery time is longer than the data line flip time, VCOM cannot be recovered to the set value (0V), so the voltage difference between the pixel electrode and the common electrode changes, and the crosstalk phenomenon shown in Figure 13 appears.
  • the area shown by the dashed frame is the blue lit area.
  • the display panel includes the front driving circuit. Therefore, the display panel can make the coupling of sub-pixels (such as B pixels) in the same pixel row to VCOM cancel each other, thereby improving the crosstalk.
  • sub-pixels such as B pixels

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Abstract

提出了驱动电路和驱动方法，以及显示装置。驱动电路的驱动芯片被配置为向所述栅极驱动单元提供栅极驱动信号，并通过数据总线向所述多路复用单元提供源极驱动信号，所述驱动电路包括第一极性数据总线和第二极性数据总线，每个所述多路复用单元与一个数据总线相连，并将所述源极驱动信号输出至多个数据线上，每个所述数据线与一个像素列相连，位于同一行的多个所述第三子像素中的一部分与所述第一极性数据总线相连，另一部分和所述第二极性数据总线相连；位于同一行的多个所述第四子像素中的一部分与所述第一极性数据总线相连，另一部分和所述第二极性数据总线相连。

Description

驱动电路和驱动方法，以及显示装置 技术领域
本申请涉及显示领域，具体地，涉及驱动电路和驱动方法，以及显示装置。
背景技术
液晶显示装置，特别是基于RGB像素设计的液晶显示装置为了提高面板的透过率，可在原有RGB像素的基础上将一半的B像素替换成W像素，以实现提高面板整体透过率，降低背光功耗的效果。但当RGBW像素设计与多路复用电路(MUX)连接设计不恰当时，将出现串扰不良。
因此，液晶显示装置，特别是基于RGBW像素设计的驱动电路和驱动方法，以及显示装置仍有待改进。
发明内容
本申请提出了一种基于液晶显示面板的驱动电路。液晶显示面板具有多个阵列排布的像素单元，所述像素单元包括6个子像素，6个所述子像素排列成两个像素行以及三个像素列，第一像素列具有两个第一子像素，第二像素列具有两个第二子像素，第三像素列具有一个第三子像素和一个第四子像素，沿着所述像素行延伸的方向上相邻的两个所述像素单元中的所述第三像素列的所述第三子像素和所述第四子像素的排列顺序相反，所述驱动电路包括驱动芯片、栅极驱动单元和多个多路复用单元，所述驱动芯片被配置为向所述栅极驱动单元提供栅极驱动信号，并通过数据总线向所述多路复用单元提供源极驱动信号，所述驱动电路包括第一极性数据总线和第二极性数据总线，每个所述多路复用单元与一个数据总线相连，并将所述源极驱动信号输出至多个数据线上，每个所述数据线与一个像素列相连，位于同一行的多个所述第三子像素中的一部分与所述第一极性数据总线相连，另一部分和所述第二极性数据总线相连；位于同一行的多个所述第四子像素中的一部分与所述第一极性数据总线相连，另一部分和所述第二极性数据总线相连。由此，可令每一像素行中颜色相同的子像素均具有相反的极性，从而可以缓解甚至解决由于同一行相同颜色子像素极性一致，而导致的在进行显示时对公共电极(VCOM)的耦合，进而可缓解由于公共电极和像素电极之间的压差改变而导致的串色问题。
根据本申请的示例，所述第一子像素为红色，所述第二子像素为绿色，所述第三子像素为蓝色，所述第四子像素为白色，所述第一子像素的开口面积以及所述第二子像素的开口面积相同，所述第四子像素的开口面积和第一子像素的开口面积比例为0.3-0.6，所述第 三子像素的开口面积为所述第一子像素的开口面积的1.5-2.5倍。由此，可在提升透过率的同时保持PPI不致下降。
根据本申请的示例，所述第三子像素和所述第四子像素的宽度一致，所述第三子像素的长度为所述第四子像素长度的1.5-2.5倍，所述第三子像素的宽度大于所述第一子像素的宽度，所述第三子像素的长度大于所述第一子像素的长度。由此，可在提升透过率的同时保持PPI不致下降。
根据本申请的示例，所述多路复用单元包括：输入端，所述输入端与所述数据总线相连用于接收所述源极驱动信号；三个控制端以及三个输出端，所述控制端接收控制信号，每个所述控制端用于控制一个所述输出端的输出，所述三个输出端分别与不同的所述数据线相连。由此，可利用一个源极驱动信号对3列子像素进行源极驱动，从而可降低驱动芯片的尺寸，降低成本。
根据本申请的示例，所述驱动电路包括多个多路复用单元组，所述多路复用单元组具有第一多路复用单元、第二多路复用单元、第三多路复用单元以及第四多路复用单元，所述第一多路复用单元和所述第三多路复用单元输出的所述源极驱动信号均具有第一极性，所述第二多路复用单元和所述第四多路复用单元输出的所述源极驱动信号均具有第二极性，所述驱动电路可利用所述第一多路复用单元、第二多路复用单元、第三多路复用单元以及第四多路复用单元，以每12个子像素列为一周期对所述数据线施加电压。由此，可实现每一个像素行中的多个颜色的子像素均可具有相反的极性。
根据本申请的示例，沿着像素行延伸的方向，第一像素单元、第二像素单元、第三像素单元和第四像素单元依次排列，所述第一多路复用单元与一个所述第一极性数据总线相连具有第一极性，所述第一多路复用单元的第一输出端和所述第一像素单元的第一像素列相连，第二输出端和所述第一像素单元的第三像素列相连，第三输出端和所述第二像素单元的第二像素列相连；所述第二多路复用单元与一个所述第二极性数据总线相连具有第二极性，所述第二多路复用单元的第一输出端和所述第一像素单元的第二像素列相连，第二输出端和所述第二像素单元的第一像素列相连，第三输出端和所述第二像素单元的第三像素列相连；所述第三多路复用单元与另一个所述第一极性数据总线相连具有所述第一极性，所述第三多路复用单元的第一输出端和所述第三像素单元的第一像素列相连，第二输出端和所述第四像素单元的第二像素列相连，第三输出端和所述第四像素单元的第三像素列相连；所述第四多路复用单元与另一个所述第二极性数据总线相连具有所述第二极性，所述第四多路复用单元的第一输出端和所述第三像素单元的第二像素列相连，第二输出端和所述第三像素单元的第三像素列相连，第三输出端和所述第四像素单元的第一像素列相连，所述第一像素列具有多个红色子像素，所述第二像素列具有多个绿色子像素列，所述第三 像素列具有多个白色和蓝色子像素。由此，可简便地令同一像素行中不同颜色的子像素均具有相反的极性。
根据本申请的示例，该驱动电路包括多个级联的所述栅极驱动单元，所述栅极驱动单元包括用于接收所述栅极驱动信号的栅极输入端、时钟输入端、复位输入端以及输出端，四个所述栅极驱动单元包括第一级栅极驱动单元，第二级栅极驱动单元，第三级栅极驱动单元和第四级栅极驱动单元，所述第三栅极驱动单元的所述输出端和所述第一栅极驱动单元的所述复位输入端相连，所述第一栅极驱动单元的所述输出端和所述第三栅极驱动单元的所述栅极输入端相连，所述第一级栅极驱动单元和所述第三级栅极驱动单元的所述时钟输入端均与第一栅极时钟信号和第三栅极时钟信号相连，所述第二级栅极驱动单元和所述第四级栅极驱动单元的所述时钟输入端均与第二栅极时钟信号和第四栅极时钟信号相连。由此，可进一步提高该驱动电路的性能。
在本申请的又一方面，本申请提出了一种驱动前面所述的驱动电路的方法。该方法包括：利用驱动芯片向栅极驱动单元提供栅极驱动信号以对多个像素行进行逐行扫描，利用所述驱动芯片通过数据总线向所述多路复用单元提供源极驱动信号并向数据线施加电压，以使得位于同一列的多个子像素具有相同极性，并使得位于同一行且颜色相同的多个子像素可具有相反的极性。由此，可缓解甚至解决由于同一行相同颜色子像素极性一致，而导致的在进行显示时对公共电极(VCOM)的耦合，进而可缓解由于公共电极和像素电极之间的压差改变而导致的串色问题。
根据本申请的示例，以每相邻的12个像素列为以周期向所述数据线施加电压，利用与一个第一极性数据总线相连的第一多路复用单元向第一像素单元的第一像素列、第三像素列和第二像素单元的第二像素列的所述数据线输出第一极性电压信号，利用与一个第二极性数据总线相连的第二多路复用单元向所述第一像素单元的第二像素列、所述第二像素单元的第一像素列和第三像素列的所述数据线输出第二极性电压信号，利用与另一个所述第一极性数据总线相连的第三多路复用单元向第三像素单元的第一像素列和所述第四像素单元的第二像素列、第三像素列的所述数据线输出所述第一极性电压信号，利用与另一个所述第二极性数据总线相连的第四多路复用单元向所述第三像素单元的第二像素列、第三像素列和所述第四像素单元的第一像素列的所述数据线输出所述第二极性电压信号，所述第一像素列具有多个红色子像素，所述第二像素列具有多个绿色子像素列，所述第三像素列具有多个白色和蓝色子像素由此，可简便地令位于同一行且颜色相同的多个子像素可具有相反的极性。
根据本申请的示例，依次对所述多路复用单元的多个控制端施加控制信号，以令所述多路复用单元的多个输出端按照自所述第一像素列、所述第二像素列至所述第三像素列的 顺序打开。由此，可进一步提高利用该驱动方法进行显示的效果。
根据本申请的示例，所述驱动芯片向所述第一多路复用单元和所述第四多路复用单元的输入端发送的所述源极驱动信号采用第一套时钟信号，向所述第二多路复用单元和所述第三多路复用单元的输入端发送的所述源极驱动信号采用第二套时钟信号，所述第一套时钟信号和所述第二套时钟信号不同时打开。由此，可简便地令位于同一行且颜色相同的多个子像素可具有相反的极性。
根据本申请的示例，每间隔一预定时间令每一个所述像素列的极性均发生翻转。由此，可防止液晶分子长期向同侧偏转导致的疲劳。
在本申请的又一方面，本申请提出了一种显示面板。该显示面板包括前面所述的驱动电路。由此，该显示面板可令同一像素行内的子像素(如B像素)对VCOM的耦合相互抵消，进而改善了串扰不良。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对示例的描述中将变得明显和容易理解，其中：
图1显示了根据本申请一个示例的驱动电路的结构示意图；
图2显示了根据本申请一个示例的像素结构的结构示意图；
图3显示了根据本申请一个示例的的像素结构的部分结构示意图；
图4显示了根据本申请一个示例的驱动电路的结构示意图；
图5显示了根据本申请一个示例的多路复用电路的方框示意图；
图6显示了根据本申请对比例1的部分驱动电路以及像素结构的示意图；
图7显示了根据本申请一个示例的部分驱动电路以及像素结构的示意图；
图8显示了根据本申请对比例1蓝色画面的串扰画面下各线路的电压示意图；
图9显示了根据本申请一个示例的蓝色画面各线路的电压示意图；
图10显示了根据本申请一个示例的栅极驱动单元的电路示意图；
图11显示了根据本申请一个示例的多个级联的栅极驱动单元的电路示意图；
图12显示了根据本申请一个示例的驱动方法的时序图；
图13显示了相关技术中一个示例的点灯测试的结果图；
图14显示了根据本申请一个示例的点灯测试的结果图。
具体实施方式
下面详细描述本申请的示例，所述示例的示例在附图中示出，其中自始至终相同或类 似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的示例是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
本申请的一些示例提出了一种液晶显示面板的驱动电路。该驱动电路包括驱动芯片、栅极驱动单元和多个多路复用单元，可令位于同一像素行中颜色相同的多个子像素在进行显示时具有不同的极性，从而可以缓解甚至解决前述的由于同一行相同颜色子像素极性一致而导致的对公共电极(VCOM)的耦合，进而可缓解由于公共电极和像素电极之间的压差改变而导致的串色问题。
具体地，参考图1、图2，该显示面板的像素结构包括多个阵列排布的像素单元100(如图中所示出的100A和100B)，像素单元100包括6个子像素，6个子像素排列成两个像素行以及三个像素列，第一像素列具有两个第一子像素1，第二像素列具有两个第二子像素2，第三像素列具有一个第三子像素3和一个第四子像素4，沿着像素行延伸的方向上相邻的两个像素单元中的第三像素列的第三子像素3和第四子像素4的排列顺序相反。即在像素行延伸的方向上，该像素结构中相邻的两个像素单元中第三列的子像素不同时为第三子像素3，也不同时为第四子像素4。每个像素列中的多个子像素均和同一个数据线11相连(如图中所示出的11A-11F)。。该驱动电路包括第一极性数据总线和第二极性数据总线(图中未示出)，每个多路复用单元与一个数据总线相连，并将源极驱动信号输出至多个数据线上，每个数据线与一个像素列相连，位于同一行的多个第三子像素中的一部分与第一极性数据总线相连，另一部分和第二极性数据总线相连，同时位于同一行的多个第四子像素中的一部分与第一极性数据总线相连，另一部分和第二极性数据总线相连。为了方便理解，下面首先对该驱动电路可实现该有益效果的原理进行简单说明：
已知一种RGBW像素设，当第一子像素为红色，第二子像素为绿色时，如前所述，为了提高面板的透过率，将一半的B像素替换成W像素。如采用间隔一个像素列和同一个MUX(多路复用单元)相连，每个MUX的输出端连接三个数据线且相邻的两个MUX的源极驱动信号极性相反(一为正，另一个为负)的方案时，则可能会出现位于同一行颜色相同的子像素均为同一极性的情况。例如，采用第一个多路复用电路可向数据线11A、11C和11E提供正电性的源极驱动信号，第二个多路复用电路可向数据线11B、11D和11F提供负电性的源极驱动信号。此时对于第一子像素1而言，像素单元100A中的第一子像素1(与数据线11A相连)和第二像素单元100B中的第一子像素1(与数据线11D相连)的极性相反。对于第一像素行而言，像素单元100A中的第三子像素3(与数据线11C相连)虽然和与数据线11F相连的第四子像素4(像素单元100B的第一像素行)极性相反，但二者颜色不相同。因此当该像素结构以阵列方式进行排布时，和像素单元100B相邻的下一个像素单元在第一像素行的第三列子像素仍旧为电性为正的第三子像素。参考图7，也即是说，该种 连接方式将导致位于同一像素行中的第三子像素的极性全部相同，位于同一行中的第四子像素的极性也完全相同。因此在显示第三子像素(B)或是第四子像素(W)的颜色的画面时，该像素行数据线对于公共电极(VCOM)的耦合作用将无法抵消。
根据本申请的示例，通过对数据线的连接进行设计，令位于同一行的第三子像素和第四子像素均可具有两种不同的极性，从而可以在像素行的方向上消除数据线对公共电极的耦合作用。由此可防止在显示某一颜色的画面时，由于对公共电极的耦合作用而产生的串色不良。本领域技术人员能够理解的是，上述子像素的颜色不受特别限制，只要在某一像素列中，相邻的像素单元有两种颜色的子像素出现了互换即可。
例如，根据本申请的具体示例，第一子像素可为红色，第二子像素为绿色，第三子像素为蓝色，第四子像素为白色。由此，可利用白色的第四子像素提高利用该像素结构的面板的透过率。具体地，参考图3，同一像素单元中的2个第一子像素的开口面积相等，2个第二子像素的开口面积相等。第一子像素、第二子像素的开口面积可一致，第三子像素的开口面积为第一子像素的开口面积的1.5-2.5倍，例如可以为2倍。第四子像素的开口面积和第一子像素的开口面积比例可以为0.3-0.6，例如可以为0.5。由此，可在提高利用该像素结构的显示面板的透过率的同时，维持该显示面板的PPI不下降。
需要特别说明的是，在本申请的示例中，如无特殊说明，则子像素的“宽度”为该子像素在沿着像素行方向上的尺寸，“长度”为该子像素在沿着像素列方向上的尺寸。且如无特殊说明，术语“相等”、“相同”、“一致”等均应做广义理解，即二者的面积或是长度、宽度等尺寸无差别，而非严格相等，可具有本领域所允许的范围内的公差。
具体地，参考图3，适当增大第三子像素(即蓝色子像素)的面积可缓解由于引入了白色子像素而导致的画面发黄的问题。具体地，第三子像素和第四子像素的宽度可以一致，第三子像素的长度为第四子像素长度的2倍。并且，为了不额外增加像素单元的面积导致显示面板的PPI下降，可令第三子像素的宽度大于第一子像素的宽度，第三子像素的长度大于第一子像素的长度。也即是说，可以令第一、第二子像素略窄，令第三、第四子像素具有相同的宽度且较第一子像素的宽度大，从而在增大第三子像素开口面积的同时，维持该像素结构中像素单元的总面积保持不变。具体地，以下表1所示出的含6个子像素的像素单元为例，当6个子像素为排列为三列的2个R、2个G和2个B子像素(即未采用W子像素替换B子像素)时，6个子像素的大小可均为21μm×63μm。根据本申请示例的RGBW像素单元(结构如图3中所示出的)中的B像素面积最大，从而可缓解引入了W像素导致的发黄现象。但通过对每个子像素的长度和宽度进行调节，该像素单元的子像素平均值与RGB像素单元的子像素平均值一致。因此，该像素结构不会导致PPI的降低。
表1
子像素大小 RGB RGBW
R像素 21μm×63μm 18μm×63μm
G像素 21μm×63μm 18μm×63μm
B像素 21μm×63μm 27μm×84μm
W像素 无 27μm×42μm
子像素平均值 21μm×63μm 21μm×63μm
参考图1，驱动电路包括驱动芯片400、栅极驱动单元300和多路复用单元200。驱动芯片被配置为向栅极驱动单元提供栅极驱动信号，并向多路复用单元提供源极驱动信号。该驱动电路可具有多个数据总线，第一极性数据总线具有第一极性，如可以为正极；第二极性数据总线具有第二极性，如可以为负极。每个多路复用单元与一个数据总线相连，并将源极驱动信号输出至多个数据线上，每个数据线与一个像素列相连。位于同一行的多个第三子像素中的一部分与第一极性数据总线相连，另一部分和第二极性数据总线相连；位于同一行的多个第四子像素中的一部分与第一极性数据总线相连，另一部分和第二极性数据总线相连。类似地，位于同一行的多个第一子像素也具有第一和第二两种极性，位于同一行的多个第二子像素也具有第一和第二两种极性。由此，可令每一像素行中颜色相同的子像素均具有相反的极性，从而可以缓解甚至解决由于同一行相同颜色子像素极性一致，而导致的在进行显示时对公共电极(VCOM)的耦合，进而可缓解由于公共电极和像素电极之间的压差改变而导致的串色问题。
根据本申请的示例，参考图4，驱动芯片的类型不受特别限制，例如可以采用TED技术，即将TCON和Driver集成在一颗IC进行处理的方式。驱动芯片(IC)可绑定在柔性线路板(FPC)上，并通过包括但不限于COF的方式集成在显示面板上。当采用氧化物薄膜晶体管时，由于相对于基于多晶硅薄膜晶体管可具有更高的开态电流(I on)，因此可在较短时间内充满，进而可实现较高的数据线复用方式。具体而言，根据本申请的示例，参考图5，该多路复用单元可包括输入端210以接收源极驱动信号，输入端210与数据总线相连。三个控制端(221、222和223)以及三个输出端(231、232、233)一一对应，控制端接收控制信号，每个控制端用于控制一个输出端的输出，三个输出端分别与不同的数据线相连。例如，三个控制端可分别对应前述的像素结构中的像素列，例如控制端221可以与红色子像素所在像素列对应(MUXR)，控制端222可以与绿色子像素所在像素列对应(MUXG)，控制端223可以与蓝色和白色子像素所在像素列对应(MUXB)，由此，可利用一个源极驱动信号对3列子像素进行源极驱动，从而可降低驱动芯片的尺寸，降低成本。
具体地，参考图7，该驱动电路可以具有多个多路复用单元组，每个多路复用单元组具 体包括第一多路复用单元、第二多路复用单元、第三多路复用单元以及第四多路复用单元。第一多路复用单元接收的输入端接收第一极性数据总线S1的源极驱动信号，第三多路复用单元接收的输入端接收第二极性数据总线S3的源极驱动信号均具有第一极性(图中以正电性为例)，第二多路复用单元接收的输入端接收另一个第一极性数据总线S2的源极驱动信号，第四多路复用单元接收的输入端接收另一个第二极性数据总线S4的源极驱动信号均具有第二极性(图中以负电性为例)。多路复用单元输出端输出至数据线(如图中所示出的11A、11D等)的源极驱动信号极性和其接收的源极驱动信号极性一致。该驱动电路可利用第一多路复用单元、第二多路复用单元、第三多路复用单元以及第四多路复用单元，以每12个子像素列为一周期对数据线施加电压。多个多路复用单元配合以对显示面板中的数据线施加电压，实现显示。由此，可实现每一个像素行中的多个颜色的子像素均可具有相反的极性。具体地，第一像素单元、第二像素单元、第三像素单元和第四像素单元依次排列，每个像素单元具有3个像素列，即构成12个子像素列的一个周期。第一多路复用单元的第一输出端和第一像素单元的第一像素列相连，第二输出端和第一像素单元的第三像素列相连，第三输出端和第二像素单元的第二像素列相连；第二多路复用单元的第一输出端和第一像素单元的第二像素列相连，第二输出端和第二像素单元的第一像素列相连，第三输出端和第二像素单元的第三像素列相连；第三多路复用单元的第一输出端和第三像素单元的第一像素列相连，第二输出端和第四像素单元的第二像素列相连，第三输出端和第四像素单元的第三像素列相连；第四多路复用单元的第一输出端和第三像素单元的第二像素列相连，第二输出端和第三像素单元的第三像素列相连，第三输出端和第四像素单元的第一像素列相连。由此，可令同一像素行中不同颜色的子像素均具有相反的极性。具体地，第一多路复用单元和第二多路复用电压的输出端连接的数据线可以是彼此间隔的，此时第一像素行中前6个子像素的极性为正负间隔。第三多路复用单元的第二、第三输出端连接12个子像素中的最后两个，第一输出端连接的数据线和第二输出端连接的数据线之间被第四多路复用单元的3个输出端连接的数据线间隔开。由此，12个子像素中的后6个子像素的第一个为第一极性(正极性)，中间三个为第二极性(负极性)，最后两个为第一极性(正极性)。由于前述的像素结构中的第三子像素列中第三子像素(B)和第四子像素(W)的排列顺序会在下一个像素单元中发生互换，因此以12个子像素为一个周期，利用该驱动电路的连接方式可以保证位于同一行中的所有颜色子像素均可具有相反的极性。
根据本申请的示例，栅极驱动单元的具体类型和数量均不受特别限制，只要能够实现栅极驱动即可。具体地，该驱动电路包括多个级联的栅极驱动单元。参考图10和图11，多个栅极驱动单元可具有多个输入端，如可包括栅极输入端、时钟输入端、复位输入端等，用于接收栅极驱动信号(STV)以及时序信号等。栅极驱动单元的电路结构可以如图11所 示出的，即可包括多个薄膜晶体管和电容等结构，具体可具有多个并联的薄膜晶体管，由此，可进一步提高该驱动电路的性能。例如具体地，栅极驱动单元中的CN、CNB为控制正反扫的信号，CN为高电平，CNB为低电平时为正扫，反之为反扫，由此可防止长期保持某一电性而引起器件寿命缩短。VGH_G和VGL_G为栅极驱动中提供高低电平的信号。RESET为复位信号，正常显示时为低电平。EN_Touch为触控模组(Touch)相关的信号，Touch时刻，EN_Touch为高电平，显示时为低电平。
多个栅极驱动单元的级联情况可以如图11所示出的，四个栅极驱动单元可包括第一级栅极驱动单元，第二级栅极驱动单元，第三级栅极驱动单元和第四级栅极驱动单元，第三栅极驱动单元(如图中所示出的Gate_N+2)的输出端和第一栅极驱动单元(如图中所示出的Gate_N)的复位输入端相连，第一栅极驱动单元的输出端和第三栅极驱动单元的栅极输入端相连。即第一个栅极驱动单元的输出(OUT)可控制Gate_N的打开(即第N行栅线，如图7中与数据线垂直的结构)，同时连接控制与其相隔一行的栅线Gate_N+2的输入端(STV)。与其相隔一行的栅线Gate_N+2的输出(OUT)可同时对其上间隔一行的栅线Gate_N的复位输入端(RST)相连。由此，以实现栅线的逐行扫描。第一级栅极驱动单元和第三级栅极驱动单元的时钟输入端均与第一栅极时钟信号和第三栅极时钟信号相连(如图中所示出的CK1和CK3)，第二级栅极驱动单元和第四级栅极驱动单元(如图中所示出的Gate_N+3)的时钟输入端均与第二栅极时钟信号和第四栅极时钟信号(如图中所示出的CK1和CK3)相连。由此，多个级联的栅极驱动单元可一次控制每一行的栅线依次打开。
本申请的又一些示例提出了一种驱动前面的驱动电路的方法。该方法包括：利用驱动芯片向栅极驱动单元提供栅极驱动信号以对多个像素行进行逐行扫描，利用驱动芯片通过数据总线向多路复用单元提供源极驱动信号并向数据线施加电压，以使得位于同一列的多个子像素具有相同极性，并使得位于同一行且颜色相同的多个子像素可具有相反的极性。由此，可缓解甚至解决由于同一行相同颜色子像素极性一致，而导致的在进行显示时对公共电极(VCOM)的耦合，进而可缓解由于公共电极和像素电极之间的压差改变而导致的串色问题。
根据本申请的示例，以每相邻的12个像素列为以周期向数据线施加电压。参考图7以及图11，第一像素单元、第二像素单元、第三像素单元和第四像素单元在沿着像素行延伸的方向上依次排列，利用第一多路复用单元(输入端连接图7所示出的S1)以令第一像素单元的第一像素列、第三像素列和第二像素单元的第二像素列(图中自左起第5列)具有第一极性(如为正)，利用第二多路复用单元(输入端连接图8所示出的S2)以令第一像素单元的第二像素列、第二像素单元的第一像素列和第三像素列具有第二极性(如为负)，利用第三多路复用单元(输入端连接图7所示出的S3)以令第三像素单元的第一像素列和第 四像素单元的第二像素列、第三像素列具有第一极性(如为正)，利用第四多路复用单元(输入端连接图7所示出的S4)以令第三像素单元的第二像素列、第三像素列和第四像素单元的第一像素列具有第二极性(如为负)。由此，可令位于同一行且颜色相同的多个子像素可具有相反的极性。
根据本申请的示例，依次对多路复用单元的多个控制端施加控制信号，以令多路复用单元的多个输出端按照自第一像素列、第二像素列至第三像素列的顺序打开。由此，可进一步提高利用该驱动方法进行显示的效果。此外，驱动芯片可向第一多路复用单元和第四多路复用单元的输入端发送的源极驱动信号采用第一套时钟信号，向第二多路复用单元和第三多路复用单元的输入端发送的源极驱动信号采用第二套时钟信号，第一套时钟信号和第二套时钟信号不同时打开。由此，可简便地令位于同一行且颜色相同的多个子像素可具有相反的极性。
具体地，参考图12，可向栅极驱动单元的时序信号(如图中示出的CK1-CK4)令栅极驱动单元控制多个栅线依次打开，实现逐行扫描。图12为栅极驱动、MUX配合的时序图，多路复用电路的控制端以第一像素列(MUXB)、第二像素列(MUXG)至第三像素列(MUXR)的顺序打开，不同画面需输出不同的信号，图中以显示蓝色画面为例。栅极驱动单元的级联情况如前所述，在此不再赘述。以图12中的Gate_N-2(栅极驱动单元结构和图11中示出的Gate_N+2类似)为例，当CK3输出第一个脉冲信号时，Gate_N-2的输出端向Gate_N-2栅线输出第一个脉冲信号。此时每行栅线打开时同时多个MUX的输入端均按照前述的顺序依次打开，MUXB输出第三个脉冲信号。此时S1和S4的第一套时钟信号打开，S2和S3的第二套时钟信号关闭，S1和S4在MUXB打开时输出第二个脉冲信号，向图7中示出的正极性像素列的数据线施加电压。类似地，Gate_N-1输出第一个脉冲信号时，S1和S4的第一套时钟信号关闭，S2和S3的第二套时钟信号打开，S2和S3在MUXB打开时输出第二个脉冲信号，向图7中示出的负极性像素列的数据线施加电压，实现蓝色画面显示。
根据本申请的示例，可每间隔一预定时间令每一个像素列的极性均发生翻转。由此，可防止液晶分子长期向同侧偏转导致的疲劳。该预定的时间可以为显示一帧画面的时间，即在显示第一帧画面时令S1和S4为正极性，S2和S3为负极性，在显示下一帧画面时，令S1和S4为负极性，S2和S3为正极性。由此，可以延长器件寿命，并缓解液晶分子长时间向同一方向偏转导致的疲劳。
具体地，以利用该方法在显示面板的中央显示蓝色画面为例，参考图9以及图7，数据线11C和11F位于穿过图14所示出的蓝色点亮区域(如图中虚线框所示出的区域)，数据线11A位于蓝色点亮区域左侧的白画面区域。参考图9，t1-t3时段内为正帧显示，后续时 段为负帧显示。t1时刻为灰阶显示，三条数据线所在位置均为灰阶画面，数据线不会发生反转，一直保持一个电平(2.5V)，t2时刻11C和11F显示蓝色画面，此时数据线会在高电平(5V)与0V间不断翻转，数据线11A仍为灰阶画面，仍保持2.5V。11C极性和11F相反，因此数据线翻转时和公共电极VCOM之间没有耦合电容，不影响像素电极电压(Pixel E)。由此蓝色画面无串扰。当采用如图6中所示出的连接关系时，由于数据线11C和11F均为正电性，因此数据线和VCOM之间有耦合电容，VCOM会受到耦合电容的影响。参考图8，数据线向上跳变时，VCOM受到向上的耦合，数据线向下跳变时，VCOM受到向下的耦合，电压发生向上或向下的跳变，之后虽然VCOM会慢慢恢复至设定值，但VCOM恢复时间长于数据线翻转的时间，VCOM不能恢复至设定值(0V)，因此像素电极和公共电极之间的压差改变，出现如图13所示的串扰现象，其中虚线框所示出的区域为蓝色点亮区域。
本申请的另一些示例提出了一种显示面板。该显示面板包括前面的驱动电路。由此，该显示面板可令同一像素行内的子像素(如B像素)对VCOM的耦合相互抵消，进而改善了串扰不良。
在本说明书的描述中，参考术语“一个示例”、“另一个示例”等的描述意指结合该示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的示例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个示例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同示例或示例以及不同示例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的示例，可以理解的是，上述示例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述示例进行变化、修改、替换和变型。

Claims (13)

  1. 一种液晶显示面板的驱动电路，所述液晶显示面板具有多个阵列排布的像素单元，所述像素单元包括6个子像素，6个所述子像素排列成两个像素行以及三个像素列，第一像素列具有两个第一子像素，第二像素列具有两个第二子像素，第三像素列具有一个第三子像素和一个第四子像素，沿着所述像素行延伸的方向上相邻的两个所述像素单元中的所述第三像素列的所述第三子像素和所述第四子像素的排列顺序相反，所述驱动电路包括驱动芯片、栅极驱动单元和多个多路复用单元，
    所述驱动芯片被配置为向所述栅极驱动单元提供栅极驱动信号，并通过数据总线向所述多路复用单元提供源极驱动信号，
    所述驱动电路包括第一极性数据总线和第二极性数据总线，每个所述多路复用单元与一个数据总线相连，并将所述源极驱动信号输出至多个数据线上，每个所述数据线与一个像素列相连，
    位于同一行的多个所述第三子像素中的一部分与所述第一极性数据总线相连，另一部分和所述第二极性数据总线相连；
    位于同一行的多个所述第四子像素中的一部分与所述第一极性数据总线相连，另一部分和所述第二极性数据总线相连。
  2. 根据权利要求1所述的驱动电路，所述第一子像素为红色，所述第二子像素为绿色，所述第三子像素为蓝色，所述第四子像素为白色，
    所述第一子像素的开口面积以及所述第二子像素的开口面积相同，所述第四子像素的开口面积和第一子像素的开口面积比例为0.3-0.6，所述第三子像素的开口面积为所述第一子像素的开口面积的1.5-2.5倍。
  3. 根据权利要求2所述的驱动电路，所述第三子像素和所述第四子像素的宽度一致，所述第三子像素的长度为所述第四子像素长度的1.5-2.5倍，
    所述第三子像素的宽度大于所述第一子像素的宽度，所述第三子像素的长度大于所述第一子像素的长度。
  4. 根据权利要求1-3任一项所述的驱动电路，所述多路复用单元包括：
    输入端，所述输入端与所述数据总线相连用于接收所述源极驱动信号；
    三个控制端以及三个输出端，所述控制端接收控制信号，每个所述控制端用于控制一个所述输出端的输出，所述三个输出端分别与不同的所述数据线相连。
  5. 根据权利要求4所述的驱动电路，所述驱动电路包括多个多路复用单元组，所述多 路复用单元组具有第一多路复用单元、第二多路复用单元、第三多路复用单元以及第四多路复用单元，
    所述第一多路复用单元和所述第三多路复用单元输出的所述源极驱动信号均具有第一极性，所述第二多路复用单元和所述第四多路复用单元输出的所述源极驱动信号均具有第二极性，所述驱动电路可利用所述第一多路复用单元、第二多路复用单元、第三多路复用单元以及第四多路复用单元，以每12个子像素列为一周期对所述数据线施加电压。
  6. 根据权利要求5所述的驱动电路，沿着像素行延伸的方向，第一像素单元、第二像素单元、第三像素单元和第四像素单元依次排列，
    所述第一多路复用单元与一个所述第一极性数据总线相连具有第一极性，所述第一多路复用单元的第一输出端和所述第一像素单元的第一像素列相连，第二输出端和所述第一像素单元的第三像素列相连，第三输出端和所述第二像素单元的第二像素列相连；
    所述第二多路复用单元与一个所述第二极性数据总线相连具有第二极性，所述第二多路复用单元的第一输出端和所述第一像素单元的第二像素列相连，第二输出端和所述第二像素单元的第一像素列相连，第三输出端和所述第二像素单元的第三像素列相连；
    所述第三多路复用单元与另一个所述第一极性数据总线相连具有所述第一极性，所述第三多路复用单元的第一输出端和所述第三像素单元的第一像素列相连，第二输出端和所述第四像素单元的第二像素列相连，第三输出端和所述第四像素单元的第三像素列相连；
    所述第四多路复用单元与另一个所述第二极性数据总线相连具有所述第二极性，所述第四多路复用单元的第一输出端和所述第三像素单元的第二像素列相连，第二输出端和所述第三像素单元的第三像素列相连，第三输出端和所述第四像素单元的第一像素列相连，
    所述第一像素列具有多个红色子像素，所述第二像素列具有多个绿色子像素列，所述第三像素列具有多个白色和蓝色子像素。
  7. 根据权利要求1-6任一项所述的驱动电路，包括多个级联的所述栅极驱动单元，所述栅极驱动单元包括用于接收所述栅极驱动信号的栅极输入端、时钟输入端、复位输入端以及输出端，
    四个所述栅极驱动单元包括第一级栅极驱动单元，第二级栅极驱动单元，第三级栅极驱动单元和第四级栅极驱动单元，
    所述第三栅极驱动单元的所述输出端和所述第一栅极驱动单元的所述复位输入端相连，所述第一栅极驱动单元的所述输出端和所述第三栅极驱动单元的所述栅极输入端相连，
    所述第一级栅极驱动单元和所述第三级栅极驱动单元的所述时钟输入端均与第一栅极时钟信号和第三栅极时钟信号相连，所述第二级栅极驱动单元和所述第四级栅极驱动单元的所述时钟输入端均与第二栅极时钟信号和第四栅极时钟信号相连。
  8. 一种驱动权利要求1-7任一项所述的驱动电路的方法，包括：
    利用驱动芯片向栅极驱动单元提供栅极驱动信号以对多个像素行进行逐行扫描，利用所述驱动芯片通过数据总线向所述多路复用单元提供源极驱动信号并向数据线施加电压，以使得位于同一列的多个子像素具有相同极性，并使得位于同一行且颜色相同的多个子像素可具有相反的极性。
  9. 根据权利要求8所述的方法，以每相邻的12个像素列为以周期向所述数据线施加电压，
    利用与一个第一极性数据总线相连的第一多路复用单元向第一像素单元的第一像素列、第三像素列和第二像素单元的第二像素列的所述数据线输出第一极性电压信号，
    利用与一个第二极性数据总线相连的第二多路复用单元向所述第一像素单元的第二像素列、所述第二像素单元的第一像素列和第三像素列的所述数据线输出第二极性电压信号，
    利用与另一个所述第一极性数据总线相连的第三多路复用单元向第三像素单元的第一像素列和所述第四像素单元的第二像素列、第三像素列的所述数据线输出所述第一极性电压信号，
    利用与另一个所述第二极性数据总线相连的第四多路复用单元向所述第三像素单元的第二像素列、第三像素列和所述第四像素单元的第一像素列的所述数据线输出所述第二极性电压信号，
    所述第一像素列具有多个红色子像素，所述第二像素列具有多个绿色子像素列，所述第三像素列具有多个白色和蓝色子像素。
  10. 根据权利要求9所述的方法，依次对所述多路复用单元的多个控制端施加控制信号，以令所述多路复用单元的多个输出端按照自所述第一像素列、所述第二像素列至所述第三像素列的顺序打开。
  11. 根据权利要求10所述的方法，所述驱动芯片向所述第一多路复用单元和所述第四多路复用单元的输入端发送的所述源极驱动信号采用第一套时钟信号，向所述第二多路复用单元和所述第三多路复用单元的输入端发送的所述源极驱动信号采用第二套时钟信号，所述第一套时钟信号和所述第二套时钟信号不同时打开。
  12. 根据权利要求8-11任一项所述的方法，每间隔一预定时间令每一个所述像素列的极性均发生翻转。
  13. 一种显示面板，其特征在于，包括：权利要求1-7任一项所述的驱动电路。
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