WO2021244065A1 - 一种均衡训练方法、装置及系统 - Google Patents

一种均衡训练方法、装置及系统 Download PDF

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Publication number
WO2021244065A1
WO2021244065A1 PCT/CN2021/076554 CN2021076554W WO2021244065A1 WO 2021244065 A1 WO2021244065 A1 WO 2021244065A1 CN 2021076554 W CN2021076554 W CN 2021076554W WO 2021244065 A1 WO2021244065 A1 WO 2021244065A1
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Prior art keywords
equalization
training
chip
target
stage
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PCT/CN2021/076554
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English (en)
French (fr)
Inventor
李永耀
罗飞
朱江
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华为技术有限公司
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Priority to EP21818880.3A priority Critical patent/EP4152170A4/en
Priority to CA3213458A priority patent/CA3213458A1/en
Publication of WO2021244065A1 publication Critical patent/WO2021244065A1/zh
Priority to US18/070,986 priority patent/US20230091617A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • This application relates to the field of chip technology, and in particular to an equalization training method, device and system.
  • the high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) is a computer expansion bus standard.
  • the PCIe bus is often used in computer systems, servers, memories, mobile phones, and other processors that require high-speed data transmission to connect peripheral devices.
  • the PCIe stipulates that the communication system (for example, the link negotiation between the master chip and the slave chip) performs link negotiation first after power-on, and only after successful negotiation, a high-speed link is established to send and receive service data.
  • the communication system for example, the link negotiation between the master chip and the slave chip
  • link negotiation performs link negotiation first after power-on, and only after successful negotiation, a high-speed link is established to send and receive service data.
  • an equalization training mechanism is provided to compensate for signal quality problems caused by link loss.
  • the balance training mechanism includes a balance training stage one to a balance training stage four (phase0 ⁇ phase3), a total of 4 stages.
  • each stage of equalization training specifies a fixed equalization timeout time.
  • the maximum time limit of the equalization timeout time specified in Phase2 and Phase3 is usually 32ms.
  • the communication system requires a more complex equalization circuit structure and a huge number of equalization parameters when performing communication transmission in a higher-speed link. This means that in this case, in the equalization training stage, it takes longer to determine the equalization parameters, which even far exceeds the maximum equalization timeout time of 32 ms currently specified by the PCIe protocol. Therefore, when communicating and transmitting in a higher-speed link, the link negotiation success rate is lower.
  • the current method of equalization training is not flexible enough to be suitable for higher-speed link negotiation.
  • This application provides an equalization training method to perform equalization training more flexibly and improve the success rate of high-speed link negotiation. Further, this application also provides a device and system for executing the method, and a chip used in executing the method.
  • an embodiment of the present application provides an equalization training method, which includes the following steps:
  • the target stage refers to the third or fourth stage; determine the target rate threshold interval in which the training rate of the target stage is located, according to N+1
  • the corresponding relationship between the rate threshold interval and N+1 equalization timeout periods, the target equalization timeout period corresponding to the target rate threshold interval is determined, and the target equalization timeout period is configured as the equalization timeout period of the target phase, N
  • the rate threshold is predetermined, and N is an integer greater than or equal to 0. The larger the rate threshold interval, the greater the corresponding equalization timeout time; the master chip and the slave chip are in the same position. Perform the equalization training of the target phase within the equalization timeout period of the target phase.
  • the embodiment of the present application can flexibly configure the equalization timeout time for equalization training for each equalization training stage, so that the configured equalization timeout time is more in line with the current training rate used for negotiation. It is known that in each stage of the equalization, if the equalization operation of the chip cannot be completed within the equalization timeout period, the chip will exit the equalization, which will cause the link negotiation between the chip and the opposite chip to fail.
  • the equalization timeout period configured in the equalization training phase is determined according to the training rate of the equalization training phase. Therefore, the equalization timeout time configured in the equalization training phase is relatively sufficient, which can better ensure the smooth completion of the operations of the equalization training phase, and will not exit due to insufficient time. Therefore, the method provided in this application can improve the link negotiation success rate to a certain extent.
  • the opposite chip is the slave chip.
  • the opposite chip is the master chip.
  • the master chip and the slave chip are connected through a PCIe bus or a CCIX bus. It can be seen that the equalization training method provided in this embodiment is applied in a processor system using PCIe bus or CCIX bus.
  • the master chip is a root component (RC, Root Complex) or a switch chip
  • the slave chip is an endpoint device (Endpoint) independent of the master chip.
  • the switching chip can be the master chip in some cases and the slave chip in other cases.
  • the target equalization timeout time is forward compatible Balance timeout period.
  • the target equalization timeout time is set to the forward compatible equalization timeout time, and there is no need to follow
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout time searches for the equalization timeout time corresponding to the training rate of the target stage, which saves system overhead better.
  • the forward compatible equalization timeout period of PCIe3.0 to PCIe5.0 is 32ms.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout time is pre-stored in the register of the master chip or the slave Inside the chip's registers.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the master chip or the register of the slave chip, so that it is in use
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout time is reached, it can be directly read in the register of the corresponding chip, which saves time.
  • the fast equalization training mode refers to In the previous round of equalizing the sending parameters and the receiving parameters of the training target stage, respectively configure the mode of the initial parameter of the master chip and the slave chip in the current round of equalizing the training target stage.
  • the embodiment of the application also provides a fast equalization training mode, that is, if the fast equalization training mode is selected before the current round of equalization training target stage, the sending parameters of the previous round of equalization training stage and The receiving parameters are respectively configured as initial parameters of the master chip and the slave chip in the current round of equalization training target nodes.
  • a fast equalization training mode that is, if the fast equalization training mode is selected before the current round of equalization training target stage, the sending parameters of the previous round of equalization training stage and The receiving parameters are respectively configured as initial parameters of the master chip and the slave chip in the current round of equalization training target nodes.
  • the equalization parameters of the main chip in the current round of equalization training target stage are stored in the main chip And store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, the master chip and the slave chip are equalized in the current round
  • the equalization parameters of the training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the register of the slave chip.
  • the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage According to the corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode, it is determined that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the embodiment of the present application provides a method for determining whether to use the equalization training mode, that is, determining according to the specified bit value in the negotiation sequence used for the equalization training target stage, which enriches the equalization training mode.
  • an embodiment of the present application also provides an equalization training method, which includes the following steps:
  • the equalization training target stage refers to the third or fourth stage of the equalization training, to obtain the forward compatible equalization timeout time of the equalization training target stage, And configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target phase; within the equalization timeout time of the current round of equalization training target phase, use the master chip and the slave chip to Perform equalization training on the initial parameters of the current round of equalization training target stage.
  • the embodiment of the present application obtains the sending and receiving parameters of the master chip and the slave chip in the previous round of the equalization training target stage during the current equalization training target stage, and combines the sending parameters and the receiving parameters They are respectively configured as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage. Enriching the methods of equalization training helps to obtain the equalization parameters of this equalization training stage faster, with stronger applicability and higher efficiency. At the same time, due to the fast equalization training mode, the complexity of obtaining equalization parameters can be effectively reduced and the time for obtaining equalization parameters can be effectively shortened, thereby better ensuring that the operation of the equalization training stage is completed successfully, and will not be caused by insufficient time. Withdrawal, to a certain extent, improve the success rate of link negotiation.
  • the opposite chip is the slave chip.
  • the opposite chip is the master chip.
  • the master chip and the slave chip are connected through a PCIe bus or a CCIX bus. It can be seen that the equalization training method provided in this embodiment is applied in a processor system using PCIe bus or CCIX bus.
  • the master chip is a root component (RC, Root Complex) or a switch chip
  • the slave chip is an endpoint device (Endpoint) independent of the master chip.
  • the switching chip can be the master chip in some cases and the slave chip in other cases.
  • the fast equalization training mode refers to configuring the master chip and the slave chip in the current stage according to the sending and receiving parameters of the target stage of the previous equalization training.
  • the embodiment of the application also provides a fast equalization training mode, that is, after confirming that the fast equalization training mode is adopted, the main chip is configured according to the sending and receiving parameters of the target stage of the previous equalization training. And the initial parameters of the slave chip in the current round of equalizing the training target stage. Enriched methods for equalization training, which helps to obtain the equalization parameters of this equalization training stage faster.
  • the equalization parameters of the main chip in the current round of equalization training target stage in the main chip
  • store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip or, the master chip and the slave chip are equalized in the current round
  • the equalization parameters of the training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the register of the slave chip.
  • the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage before the determination to adopt the fast equalization training mode, obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; according to the The corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode is determined, and it is determined that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the embodiment of the present application provides a method for determining whether to use the equalization training mode, that is, determining according to the specified bit value in the negotiation sequence used for the equalization training target stage, which enriches the equalization training mode.
  • the present application provides an equalization training device, which is used to perform the method described in the foregoing first aspect or any one of the implementation manners of the first aspect.
  • the device includes a transceiver and a manager.
  • the transceiver is used to obtain the training rate of the master chip and the slave chip in the target stage of equalization training, and the target stage refers to the third stage or the fourth stage.
  • the manager is used to determine the target rate threshold interval where the training rate of the target stage is located, and determine the target rate threshold interval corresponding to the corresponding relationship between the N+1 rate threshold intervals and the N+1 equalization timeout periods Target equalization timeout time, and configure the target equalization timeout time as the equalization timeout time of the target stage, N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein the rate threshold interval The larger the value, the larger the corresponding equalization timeout time. ; Then the master chip and the slave chip perform the equalization training of the target phase within the equalization timeout time of the target phase.
  • the equalization training method described in the first aspect or any one of the possible implementation manners of the first aspect can be implemented. It can be seen that the use of the device provided in this embodiment can make the equalization timeout time of the main chip in the third stage of equalization sufficient, and correspondingly, the equalization operation of the main chip in the third stage will not exit due to insufficient time. ; And, the equalization timeout time of the slave chip in the fourth stage of equalization is also sufficient, and correspondingly, the equalization operation of the slave chip in the fourth stage will not exit due to insufficient time. Therefore, using the device provided in this embodiment can reduce to a certain extent the chip exiting the equalization operation due to insufficient equalization timeout, and effectively improve the link negotiation success rate.
  • the target equalization timeout time is forward compatible Balance timeout period.
  • the forward compatible equalization timeout time of PCIe3.0 to PCIe5.0 is 32ms.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the master chip or the slave Inside the chip's registers.
  • the manager before the acquiring the training rate of the master chip and the slave chip in the target phase of the equalization training, the manager is further configured to determine not to use the fast equalization training mode;
  • the fast equalization training mode refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending parameters and the receiving parameters of the previous round of equalization training target stage.
  • the manager is also used to adjust the balance of the main chip in the current round of equalization training target stage
  • the parameters are stored in the register of the master chip, and the equalization parameters of the slave chip in the current round of equalization training target stage are stored in the register of the slave chip; or, the master chip and the slave chip
  • the equalization parameters of the chip in the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in all
  • the description is from the register of the chip.
  • the transceiver is further configured to obtain a negotiation sequence used by the master chip and the slave chip to perform the equalization training target phase; and specify according to the negotiation sequence The corresponding relationship between the bit value of and the equalization training mode is determined, and the specified bit value in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the present application provides a balance training device, which is used to execute the method described in the foregoing second aspect or any implementation manner of the second aspect.
  • the device includes a transceiver and a manager.
  • the manager is used to judge whether to adopt the fast balance mode
  • the transceiver is used to obtain the sending and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage when the fast equalization mode is determined to be adopted;
  • the manager is further configured to configure the sending parameter and the receiving parameter as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the equalization training target stage refers to the third stage of equalization training. Or the fourth stage;
  • the transceiver is also used to obtain the forward compatible equalization timeout time of the equalization training target stage;
  • the manager is further configured to configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target stage;
  • the manager is further configured to use the initial parameters of the master chip and the slave chip in the current round of equalization training target stage to perform equalization training within the equalization timeout period of the current round of equalization training target stage.
  • the equalization training method described in the second aspect or any one of the possible implementation manners of the second aspect can be implemented. It can be seen that the device provided by this embodiment can configure the initial parameters of the current round of equalization training target stage for the master chip and the slave chip more quickly, enriching the methods for performing equalization training, and helping to obtain the cost more quickly.
  • the equalization parameters of the secondary equalization training stage have stronger applicability and higher efficiency. In addition, it effectively reduces the probability of exiting due to insufficient time during the equalization training target stage, and improves the link negotiation success rate.
  • the manager is also used to adjust the balance of the main chip in the current round of equalization training target stage
  • the parameters are stored in the register of the master chip, and the equalization parameters of the slave chip in the current round of equalization training target stage are stored in the register of the slave chip; or, the master chip and the slave chip
  • the equalization parameters of the chip in the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in all
  • the description is from the register of the chip.
  • the transceiver before the fast equalization training mode is determined to be adopted, the transceiver is also used to obtain that the master chip and the slave chip are used to negotiate the equalization training target stage Sequence; the manager is further configured to determine that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode according to the corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode.
  • the present application provides another equalization training device, which is also used to execute the equalization training method described in the foregoing first aspect or any implementation manner of the first aspect.
  • the device includes an acquisition unit, a determination unit, and a configuration unit.
  • the acquiring unit is configured to acquire the training rate of the master chip and the slave chip in a target stage of balanced training, and the target stage refers to the third stage or the fourth stage;
  • the determining unit is configured to determine the target rate threshold interval in which the training rate of the target phase is located, and determine the target rate threshold interval corresponding to the corresponding relationship between N+1 rate threshold intervals and N+1 equalization timeout periods The target equalization timeout time;
  • the configuration unit is configured to configure the target equalization timeout time as the equalization timeout time of the target phase
  • N rate thresholds are predetermined, and N is an integer greater than or equal to 0.
  • the master chip and the slave chip perform the equalization training of the target phase within the equalization timeout time of the target phase.
  • the device provided in this embodiment is used to execute the method described in the first aspect or any one of the possible implementation manners of the first aspect.
  • the equalization timeout time of the main chip in the third stage of equalization can be sufficient, and accordingly, the equalization operation of the main chip in the third stage will not quit due to insufficient time; and , So that the equalization timeout time of the slave chip in the fourth stage of equalization is also sufficient.
  • the equalization operation of the slave chip in the fourth stage will not exit due to insufficient time. Therefore, using the device provided in this embodiment can reduce to a certain extent the chip exiting the equalization operation due to insufficient equalization timeout, and effectively improve the link negotiation success rate.
  • the determining unit is specifically configured to: when the target rate threshold interval is the threshold interval with the smallest rate among the N+1 rate threshold intervals, the target equalization The timeout period is the equalization timeout period for forward compatibility.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the master chip or the slave Inside the chip's registers.
  • the determining unit before the acquiring the training rate of the master chip and the slave chip in the target phase of the equalization training, the determining unit is further configured to determine not to adopt the fast equalization training mode;
  • the fast equalization training mode refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending parameters and the receiving parameters of the previous round of equalization training target stage.
  • the acquiring unit is further configured to perform the equalization of the master chip in the current round of equalization training target stage after completing the equalization training of the current round of equalization training target stage.
  • the parameters are stored in the register of the master chip, and the equalization parameters of the slave chip in the current round of equalization training target stage are stored in the register of the slave chip; or, the master chip and the slave chip
  • the equalization parameters of the chip in the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in all
  • the description is from the register of the chip.
  • the acquiring unit is further configured to acquire the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; the determining unit also uses According to the corresponding relationship between the bit value specified in the negotiation sequence and the equalization training mode, it is determined that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the present application provides another equalization training device, which is also used to execute the equalization training method described in the foregoing second aspect or any implementation manner of the second aspect.
  • the device includes an acquisition unit, a determination unit, and a configuration unit.
  • the determining unit is used to determine whether to adopt a fast equalization mode
  • the acquiring unit is configured to acquire the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage when the fast equalization mode is determined to be adopted;
  • the configuration unit is configured to configure the sending parameter and the receiving parameter as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage, and the equalization training target stage refers to the first equalization training stage. Stage three or stage four;
  • the obtaining unit is also used to obtain the forward compatible equalization timeout time of the equalization training target stage;
  • the configuration unit is further configured to configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target phase; then, within the equalization timeout time of the current round of equalization training target phase, use the master The chip and the slave chip perform equalization training on the initial parameters of the current round of equalization training target stage.
  • the device provided in this embodiment is used to execute the method described in the second aspect or any one of the possible implementation manners of the second aspect.
  • the master chip and the slave chip can be configured with the initial parameters of the current round of equalization training target stage faster, which enriches the methods for performing equalization training and helps to obtain the current equalization faster.
  • the equalization parameters in the training phase have stronger applicability and higher efficiency. In addition, it effectively reduces the probability of exiting due to insufficient time during the equalization training target stage, and improves the link negotiation success rate.
  • the acquisition unit is further configured to perform the equalization of the master chip in the current round of equalization training target stage after completing the equalization training of the current round of equalization training target stage.
  • the parameters are stored in the register of the master chip, and the equalization parameters of the slave chip in the current round of equalization training target stage are stored in the register of the slave chip; or, the master chip and the slave chip
  • the equalization parameters of the chip in the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in all
  • the description is from the register of the chip.
  • the obtaining unit is further configured to obtain that the master chip and the slave chip are used to negotiate the equalization training target stage Sequence; the determining unit is further configured to determine, according to the corresponding relationship between the bit value specified in the negotiation sequence and the equalization training mode, that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • this application provides yet another equalization training device, which is also used to perform the equalization training method described in the foregoing first aspect or any one of the first aspects.
  • the device includes a central processing unit (CPU, Central Processor Unit) and a memory, and the CPU is used to execute codes stored in the memory to perform the functions of the device described in this embodiment.
  • CPU Central Processor Unit
  • the memory is used to store the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods.
  • the CPU is used to obtain the training rate of the master chip and the slave chip in the target stage of the balanced training, and the target stage refers to the third stage or the fourth stage.
  • the CPU is also used to determine the target rate threshold interval where the training rate of the target stage is located, and determine the target equalization corresponding to the target rate threshold interval according to the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods Timeout time, and the target equalization timeout time is configured as the equalization timeout time of the target stage, N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein the greater the rate threshold interval , The corresponding equalization timeout time is greater; then the master chip and the slave chip perform equalization training in the target phase within the equalization timeout time of the target phase.
  • the device described in this embodiment can reduce the risk of the system exiting the balancing operation due to insufficient balancing timeout time to a certain extent, thereby causing link negotiation failure.
  • the present application provides yet another equalization training device, which is also used to execute the equalization training method described in the foregoing second aspect or any implementation manner of the second aspect.
  • the device includes a central processing unit (CPU, Central Processor Unit) and a memory, and the CPU is used to execute codes stored in the memory to perform the functions of the device described in this embodiment.
  • the memory is used to store the equalization parameters of the previous round of equalization training target stage.
  • the CPU is used to determine whether to adopt the fast equalization mode, and when the fast equalization mode is determined to be adopted, it obtains the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage, and compares the sending parameters with all the parameters.
  • the receiving parameters are respectively configured as initial parameters of the master chip and the slave chip in the current round of equalization training target stage, and the equalization training target stage refers to the third stage or the fourth stage of the equalization training.
  • the CPU is also used to obtain the forward compatible equalization timeout time of the equalization training target phase, and configure the forward compatible equalization timeout time to the equalization timeout time of the current round of equalization training target phase; in the current round of equalization training target phase During the equalization timeout period, the initial parameters of the master chip and the slave chip in the target stage of the current round of equalization training are used to perform equalization training.
  • the device described in this embodiment can reduce the risk of the system exiting the balancing operation due to insufficient balancing timeout time to a certain extent, thereby causing link negotiation failure.
  • this application provides a chip, which may be the foregoing first aspect or any of its implementations, or the third aspect or any of its implementations, or the fifth aspect or its implementations
  • the chip includes registers, transceivers and managers.
  • the transceiver is used to obtain the training rate of the master chip and the slave chip in the target stage of equalization training, and the target stage refers to the third stage or the fourth stage;
  • the manager is used to determine the target rate threshold interval where the training rate of the target phase is located, and determine the target corresponding to the target rate threshold interval according to the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods Equalize timeout time, and configure the target equalization timeout time as the equalization timeout time of the target stage, N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein the rate threshold interval is higher Larger, the corresponding equalization timeout time is larger;
  • the master chip and the slave chip perform the equalization training of the target phase within the equalization timeout time of the target phase.
  • the method described in the first aspect or any one of the possible implementations of the first aspect can be implemented, thereby reducing the system exiting the balance operation due to insufficient balance timeout time, which in turn leads to the link The risk of negotiation failure.
  • the register is also used to store the forward compatible equalization timeout time.
  • the register is also used to store the equalization parameters of the current round of equalization training target stage.
  • the chip has the function of turning on and off part of the equalizing circuit, and turning off the part of the equalizing circuit when a fast equalization process is required, such as turning off DFE or part of CTLE, so as to shorten the equalization time.
  • the chip described in the embodiment of the present application comes with its own management software, or is a state machine that meets the standard.
  • this application provides a chip, which may be the foregoing second aspect or any of its implementations, or the fourth aspect or any of its implementations, or the sixth aspect or its implementations
  • the chip includes registers, transceivers and managers.
  • the manager is used to determine whether to adopt the fast balance mode
  • the transceiver is used to obtain the sending and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage when the fast equalization mode is determined to be adopted;
  • the manager is further configured to configure the sending parameter and the receiving parameter as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the equalization training target stage refers to the third stage of equalization training. Or the fourth stage;
  • the transceiver is also used to obtain the forward compatible equalization timeout time of the equalization training target stage;
  • the manager is further configured to configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target phase; and within the equalization timeout time of the current round of equalization training target phase, using the main chip and The slave chip performs equalization training on the initial parameters of the current round of equalization training target stage.
  • the method described in the second aspect or any one of the possible implementations of the second aspect can be implemented, thereby reducing the system exiting the balance operation due to insufficient balance timeout time, which in turn leads to the link The risk of negotiation failure.
  • the register is also used to store the equalization parameters of the current round of equalization training target stage.
  • the register is also used to store the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods.
  • the chip has the function of turning on and off part of the equalizing circuit, and turning off the part of the equalizing circuit when a fast equalization process is required, such as turning off DFE or part of CTLE, so as to shorten the equalization time.
  • the chip described in the embodiment of the present application comes with its own management software, or is a state machine that meets the standard.
  • this application also provides a communication system, which includes system software, a master chip, and a slave chip.
  • the master chip and the slave chip are connected through a bus or a CCIX bus.
  • the system software is used to obtain the training rate of the master chip and the slave chip in the target stage of balanced training, the target stage refers to the third stage or the fourth stage; determine the target rate threshold interval in which the training rate of the target stage is located , According to the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period, determine the target equalization timeout time corresponding to the target rate threshold interval, and configure the target equalization timeout time as the target stage
  • N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein, the larger the rate threshold interval, the larger the corresponding equalization timeout time; then the main chip and The slave chip performs the equalization training of the target phase within the equalization timeout time of the target phase.
  • the equalization training method described in the first aspect or any one of the possible implementation manners of the first aspect can be implemented. It can be seen that the use of the device provided in this embodiment can make the balance timeout time of the main chip in the third stage of equalization sufficient, and correspondingly, the balance operation of the main chip in the third stage will not quit due to insufficient time. ; And, the equalization timeout time of the slave chip in the fourth stage of equalization is also sufficient, and correspondingly, the equalization operation of the slave chip in the fourth stage will not exit due to insufficient time. Therefore, using the device provided in this embodiment can reduce to a certain extent the chip exiting the equalization operation due to insufficient equalization timeout time, and effectively improve the link negotiation success rate.
  • the system software is further configured to: when the target rate threshold interval is the threshold interval with the smallest rate among the N+1 rate threshold intervals, the target rate The equalization timeout is the forward compatible equalization timeout.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the main chip or in the register of the main chip. From the register of the chip.
  • the system software before the acquisition of the training rate of the master chip and the slave chip in the target phase of the equalization training, the system software is also used to determine not to adopt the fast equalization training mode;
  • the fast equalization training mode refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending and receiving parameters of the previous round of equalization training target stage.
  • the system software is also used to set the main chip to the current round of equalization training target stage.
  • the equalization parameter is stored in the register of the master chip, and the equalization parameter of the slave chip in the current round of equalization training target stage is stored in the register of the slave chip; or, the master chip and the The equalization parameters of the slave chip in the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the register of the master chip. In the register of the slave chip.
  • the system software is also used to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; according to the negotiation sequence The corresponding relationship between the designated bit value and the equalization training mode is determined, and the designated bit value in the negotiation sequence corresponds to the non-fast equalization training mode.
  • this application also provides a communication system, which includes system software, a master chip, and a slave chip.
  • the master chip and the slave chip are connected through a bus or a CCIX bus.
  • the system software is used to determine whether to adopt the fast equalization mode.
  • the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage are obtained, and the sending parameters and all the parameters are combined.
  • the receiving parameters are respectively configured as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the equalization training target stage refers to the third or fourth stage of the equalization training, and the forward direction of the equalization training target stage is obtained.
  • the equalization training method described in the second aspect or any one of the possible implementation manners of the second aspect can be implemented. It can be seen that using the device provided in this embodiment can configure the master chip and the slave chip with the initial parameters of the current round of equalization training target phases, enriching the methods for performing equalization training, and helping to obtain the cost more quickly.
  • the equalization parameters of the secondary equalization training stage have stronger applicability and higher efficiency. In addition, it effectively reduces the probability of exiting due to insufficient time during the equalization training target stage, and improves the link negotiation success rate.
  • the system software is also used to set the main chip in the current round of equalization training target stage.
  • the equalization parameter is stored in the register of the master chip, and the equalization parameter of the slave chip in the current round of equalization training target stage is stored in the register of the slave chip; or, the master chip and the The equalization parameters of the slave chip in the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the register of the master chip. In the register of the slave chip.
  • the system software is also used to obtain the information used by the master chip and the slave chip to perform the equalization training target stage.
  • negotiation sequence and according to the corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode, it is determined that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the embodiments of the present application provide a computer program product
  • the computer program product includes: computer program code, when the computer program code is run by the unit module or transceiver of the equalization training device, the device is executed Any one of the foregoing first aspect or second aspect; or any method in any possible implementation manner of the first aspect to the second aspect.
  • an embodiment of the present application provides a computer-readable storage medium, and the computer-readable storage medium stores a program, and the program makes the equalization timeout time training device (for example, the master chip; another example, the slave chip) execute the above-mentioned first One aspect or any one of the second aspect; or any one of the possible implementations of the first aspect to the second aspect.
  • the equalization timeout time training device for example, the master chip; another example, the slave chip
  • Figure 1 is a schematic diagram of the variable speed balance training provided by this application.
  • FIG. 2 is a schematic diagram of the equalization circuit provided by this application.
  • FIG. 3 is a schematic diagram of a system architecture provided by an embodiment of the application.
  • Figure 4 is a schematic diagram of the signal channel between the RC and the graphics card provided by this application.
  • Figure 5 is a flow chart of the chain establishment stipulated by the PCIe standard
  • FIG. 6 is a schematic diagram of a scenario provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a first scenario for determining a first equalization timeout period provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a second scenario for determining a first equalization timeout period provided by an embodiment of the application.
  • FIG. 9 is a schematic flowchart of a first balance training method provided by an embodiment of this application.
  • FIG. 10 is a schematic diagram of a second balance training method provided by an embodiment of this application.
  • FIG. 11 is a schematic diagram of a third balance training method provided by an embodiment of the application.
  • FIG. 12 is a schematic diagram of the first balance training device provided by this application.
  • FIG. 13 is a schematic diagram of the second balance training device provided by this application.
  • FIG. 14 is a schematic diagram of still another balance training device provided by this application.
  • FIG. 15 is a schematic structural diagram of a chip provided by this application.
  • FIG. 16 is a schematic structural diagram of a communication system provided by this application.
  • PCIe is a computer expansion bus standard.
  • the PCIe bus is often used in computer systems, servers, storage, mobile phones, and other processors that require high-speed data transmission to connect peripheral devices.
  • PCIe3.0 PCIe uses transmit and receive equalization circuits to solve signal quality problems, and also defines an equalization training mechanism.
  • the equalization training mechanism includes 4 phases phase0 to phase3.
  • the Phase2 is mainly used by the master chip to adjust the sending parameters of the slave chips, and the master chip correspondingly adjusts its own receiving parameters, in order to expect the link to achieve a stable state where the bit error rate required by the protocol is less than 10E-12;
  • the Phase3 mainly It is the slave chip that adjusts the sending parameters of the main chip and its own receiving parameters.
  • the Phase2 and the Phase3 are mainly used for parameter training of the equalizing circuit at the transmitting end and the receiving end, respectively, so as to ensure that suitable equalizing circuit parameters are found.
  • the value of the equalization parameter may be expressed as a value of C-1/C0/C+1.
  • each stage of current equalization training specifies a fixed equalization timeout time.
  • the maximum time limit of the equalization timeout time specified in Phase2 and Phase3 is usually 32ms, and if If the equalization training is not completed within the specified equalization timeout period, a timeout will be triggered and the link equalization failure will be announced.
  • PCIe rate Due to the continuous improvement of PCIe rate, the transfer rate of PCIe has been increased from 2.5G in PCIe1.0 version to 64Gbps in PCIe6.0 version. With the advancement of technology, higher rates will be used in the future in higher-speed transmission. , The sending end and receiving end of the chip require a more complex equalization circuit structure and a huge number of equalization parameters.
  • the equalization timeout according to the link loss, that is, divide the link loss into different loss types such as long reach (LR) and short reach (SR).
  • LR long reach
  • SR short reach
  • the determination of the link loss type itself is a more complicated issue, and the equalization timeout time is configured according to the link loss type.
  • the constraint range is wide, and it is impossible to make more flexible adjustments for equalization training with the same loss type but different rates. .
  • the embodiment of the present application provides an equalization training method, and the technical solution of the embodiment of the present application can be applied to various bus processing systems.
  • a processor system using the PCIe bus also referred to as "PCIe system”
  • a processor system using the CCIX bus also referred to as "CCIX system”
  • FIG. 3 it shows a processor system using PCIe bus.
  • the system includes root complex (RC), switch and PCIe-to-PCI bridge.
  • RC root complex
  • switch switch
  • PCIe-to-PCI bridge PCIe-to-PCI bridge
  • RC is also called the root controller of the system, and is usually integrated on a central processor unit (CPU).
  • CPU central processor unit
  • RC usually has multiple ports. Through each of the multiple ports, the RC can communicate with a component.
  • the multiple ports may include multiple ports (PCIe ports for short) for connecting to a PCIe bus.
  • PCIe ports for short
  • the RC can be connected to an endpoint.
  • the Endpoint can be a graphics card, a network card, an optical channel card, a Switch, or an application specific integrated circuit (ASIC), etc.
  • ASIC application specific integrated circuit
  • the RC and DDR are connected through the DDR bus, so the port connected to the DDR on the RC is not a PCIe port. Therefore, the multiple ports of the RC may all be PCIe ports, or part of them may be PCIe ports.
  • Switch is used to expand the link of this RC.
  • the Switch and the RC are connected through the PCIe bus;
  • the Switch has multiple ports, and through one port, the Switch can communicate with an EP through the PCIe bus. Therefore, based on the Switch, the RC can communicate with multiple Endpoints through one port.
  • the Switch has 3 ports, and the Switch can communicate with an ASIC through any one of the 3 ports through the PCIe bus.
  • the role of the PCIe-to-PCI bridge is to bridge, which is used to realize the conversion between the PCIe bus and the PCI bus, so that it can be compatible with the original Endpoint that supports the PCI bus.
  • one end of the PCIe-to-PCI bridge is connected to the Switch through the PCIe bus, and the other end is connected to the PCI bus.
  • FIG. 3 also shows a plurality of PCI slots that support the PCI bus standard, and the chip or card inserted in the PCI slot can be connected to the PCIe-to-PCI bridge through the PCI bus, and then connected through the Switch To the CPU.
  • the RC and Endpoint can be directly connected through the PCIe bus, or through the PCIe bus and the connector. As shown in Figure 4, the RC and the graphics card are connected through the PCIe bus, the connector, the PCIe bus, the connector, and the PCIe bus in sequence. It should be known that the lengths of the multiple PCIe buses located between the RC and the Endpoint may be the same or different.
  • the PCIe/CCIX system may include a central processing unit CPU and its peripheral devices, wherein at least one of the channels between the CPU and its peripheral devices uses the PCIe/CCIX bus.
  • the PCIe/CCIX system may also include multiple CPUs and their peripheral devices, wherein at least one of the channels between the multiple CPUs uses the PCIe/CCIX bus, or one of the channels between the CPU and the peripheral device At least one of the channels uses the PCIe/CCIX bus.
  • FIG. 5 shows a flowchart of the PCIe system from power-on to establishment of a communication connection.
  • the link state machine in the main chip will control the link sequentially: detection-polling (polling)-configuration (configuration)-connection (linkup)-recovery .
  • the master chip detects whether the slave chip is in place. After detecting that the slave chip is in place, it enters the Polling stage to perform bit lock and training rate determination, or bit lock and training mode determination (that is, determine whether to use the fast equalization mode). Then enter the configuration stage to determine the link bandwidth and link number, and perform channel-to-channel phase compensation.
  • the link After completing the configuration, enter the Linkup phase, the link runs to Linkup at low speed, that is, the master chip and the slave chip establish a connection. Then, the system enters the recovery phase, performs equalization timeout time and speed change, after the speed change is completed and the speed is increased to high speed, it returns to the connected state to realize the business data transmission.
  • the main chip mentioned in this application refers to a chip including a downstream port (DSP). Sometimes, the main chip is also referred to as the downstream port for short.
  • the slave chip mentioned in this application refers to a chip including an upstream port (USP). Sometimes, the slave chip is also referred to as the uplink port for short.
  • the main chip may be an RC or a switch chip (switch).
  • the slave chip can be an endpoint device (endpoint) or a switch chip (switch).
  • the master chip is a switching chip
  • the slave chip may be an endpoint device.
  • the endpoint device may be a graphics card, a network card, an optical channel card, a memory card, or a switching chip.
  • the embodiment of the present application selects that the sending terminal device and the receiving terminal device are chips with processing functions as an example, and a specific scenario of the embodiment of the present application is introduced in detail.
  • this scenario includes PCIe link and chips at both ends of the link.
  • One end of the chip includes a downstream port (downstream port, DSP), and the other end of the chip includes an upstream port (upstream port, USP).
  • DSP downstream port
  • upstream port upstream port
  • the chip containing DSP can be CPU (including the root complex part), switch chip (switch) and Retimer
  • the chip containing USP can be PCIe node (FC card, IB, etc.), switch chip (switch) And Retimer, etc.
  • the operation on the equalization timeout period occurs between the master chip and the slave chip.
  • the master chip and the slave chip may be located in the same processor system or in different processor systems, wherein the master chip and the slave chip are connected through a PCIe/CCIX bus.
  • RC in Figure 3 corresponds to the master chip
  • Endpoint corresponds to the slave chip.
  • the operation of configuring the equalization timeout in the embodiment of the present application can be implemented in different stages, not only in the recovery stage, but also after the chip is powered on and before the PCIe/CCIX state machine is started.
  • the power-on chip calibration phase is completed by the system software by configuring the chip function module registers at both ends of the two channels, such as I2C, Jtag, and other interfaces; or during the link negotiation phase, the chips at both ends are negotiated through TS sequence; or Start to complete the link initialization at a lower rate (such as 2.5G), complete the configuration through in-band, and then negotiate to a high rate.
  • a lower rate such as 2.5G
  • FIGS. 3 to 6 are only simplified schematic diagrams illustrating examples for ease of understanding, and the system may also include other devices or other structures, which are not shown in FIGS. 3 to 6.
  • PCIe bus in the embodiments of this application is a high-speed serial computer expansion bus standard.
  • PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission.
  • the connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliable transmission, hot plugging and quality of service (QOS) and other functions. Compared with the PCI bus, it has a faster transfer rate.
  • PCIe bus described in the embodiment of the present application can not only be applied to internal interconnection, but also can be applied to external interconnection.
  • the "CCIX bus" in the embodiments of the application is based on the same physical architecture as the PCIe bus, which includes an electrical sub-block and a logical sub-block, and the CCIX bus supports PCIe1. 0, PCIe2.0, PCIe3.0 and PCIe4.0 transfer rate.
  • the CCIX bus described in the embodiments of the present application can not only be applied to internal interconnection, but also can be applied to external interconnection.
  • the "state machine” in the embodiments of the present application is composed of a state register and a combinational logic circuit, which can perform state transition according to a preset state according to a control signal, and is a control center that coordinates related signal actions and completes specific operations.
  • Equalization training in the embodiments of this application means that in the communication system, due to the existence of various noises and interferences, the transmission signal in the communication system is distorted, that is, the channel is a non-ideal channel.
  • the "equalization timeout period” refers to the maximum time limit of the equalization training phase, that is, if the equalization training is not completed within the specified equalization timeout period, the timeout will be triggered and the link equalization failure will be declared.
  • the term "at least one" in the embodiments of the present application refers to one or more, and “multiple” refers to two or more than two.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A , B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an "or” relationship.
  • the following at least one item (item) or similar expressions refer to any combination of these items, including any combination of single item (item) or plural items (item).
  • at least one item (a) of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple .
  • the target stage of the equalization training in the equalization training method provided in the embodiment of this application refers to the third stage or the fourth stage, that is, the equalization training method provided in the embodiment of the present application is configured with two stages Phase 2 and/or Phase 3.
  • the required target equalization timeout time is configured with two stages Phase 2 and/or Phase 3.
  • the PCIe system needs to be configured as follows.
  • the equalization training phase is equalization training phase three
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the main chip
  • the equalization training phase is equalization training phase four
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the slave chip.
  • the system will not be powered on, powered off, or reset. As a result, the correspondence between the N+1 rate threshold interval and the N+1 equalization timeout period is lost.
  • the corresponding relationship between the N+1 rate threshold intervals and the N+1 equalization timeout periods is stored in a memory in the PCIe system.
  • the specific steps of the first equalization training method can refer to the steps described in FIG. 9.
  • S900 Obtain the training rate of the master chip and the slave chip in the target phase of the balanced training.
  • the training rate of the balanced training target stage is obtained in the following manner:
  • the negotiation sequence between the master chip and the slave chip for performing the equalization training target stage is obtained, and according to the first specific bit value in the negotiation sequence, it is determined to be in the equalization training target stage The training rate of, wherein the first specific bit indicates that training rate information is required.
  • the training rate at which the equalization training target phase will be performed is determined, for example, The training rate is V.
  • the training rate for equalization training is 16 GT/s.
  • the corresponding relationship between the bit value and the training rate shown in Table 1 is pre-stored in the memory of the PCIe/CCIX system.
  • the memory may be a flash memory or an electronic erasable programmable read-only memory EEPROM or the like.
  • S901 Determine a target equalization timeout period corresponding to the training rate.
  • the target equalization timeout time represents the maximum time limit for obtaining equalization parameters in the equalization training target stage.
  • the target rate threshold interval where the training rate of the target phase is located is determined, and the corresponding relationship between N+1 rate threshold intervals and N+1 equalization timeout periods is determined.
  • the N rate thresholds are predetermined, and N is an integer greater than or equal to 0, and the larger the rate threshold interval is, the larger the corresponding equalization timeout time is.
  • the embodiment of the present application separately introduces the search target equalization timeout time in detail according to the value of N.
  • N 2, that is, the current rate threshold is one, and the rate threshold interval is two.
  • the rate threshold interval in which the training rate is located is determined.
  • the rate threshold is one, for example, the rate threshold is Va.
  • the corresponding target equalization timeout time is determined according to the rate threshold interval where the training rate V is obtained.
  • rate threshold interval 1 used to indicate that the training rate is less than the rate threshold Va
  • rate threshold interval 2 used to indicate that the training rate is greater than or equal to the rate threshold Va.
  • the target equalization timeout time corresponding to the rate threshold interval 1 is 32 ms
  • the target equalization timeout time corresponding to the rate threshold interval 2 is 50 ms.
  • the obtained training rate V is compared with the rate threshold Va to determine which rate threshold interval the training rate is located in.
  • the target equalization timeout time corresponding to the training rate is 50 ms.
  • the target equalization timeout time corresponding to the training rate is 32 ms.
  • the obtained training rate and the setting The minimum threshold rate for comparison.
  • the minimum rate threshold is used to determine whether to continue to use the forward compatible equalization timeout time as the configured equalization timeout time.
  • the S901 is executed. Conversely, if it is determined that the training rate is less than or equal to the minimum rate threshold; or it is determined that the training rate is less than the minimum rate threshold, then the target equalization timeout time is determined to be a forward compatible equalization timeout time, for example, directly according to the forward Compatible equalization timeout time is 32ms for equalization training.
  • the forward compatible equalization timeout time should not be used as the target equalization timeout time
  • it is necessary to reselect the equalization timeout time that is, when the target equalization timeout time, Then in the scenario of the value case 1.
  • the rate threshold Va is the minimum rate threshold. At this time, it can be directly determined that the training rate V is in the rate threshold interval 2, and the corresponding first duration is 50 ms.
  • Value case 2 N>2, that is, there are at least two current rate thresholds and at least three rate threshold intervals.
  • the rate threshold interval in which the training rate is located is determined.
  • the corresponding target equalization timeout time is determined according to the rate threshold interval in which the acquired training rate value V is located.
  • rate threshold interval 1 used to indicate that the training rate is less than the rate threshold Va
  • rate threshold interval 2 used to indicate that the training rate is greater than or equal to the rate threshold Va and less than the rate threshold Vb
  • ... Used to indicate the rate threshold interval Vn where the training rate is greater than or equal to the rate threshold Vn-2 and less than the rate threshold Vn-1.
  • the target equalization timeout time corresponding to the rate threshold interval 1 is 32ms
  • the target equalization timeout time corresponding to the rate threshold interval 2 is 50ms
  • the target equalization timeout time corresponding to the rate threshold interval N is 100ms.
  • the acquired training rate V it is determined in which rate threshold interval the training rate is located.
  • the target equalization timeout time corresponding to the training rate is 50 ms.
  • V ⁇ Va the training rate is within the rate threshold interval 1.
  • the target equalization timeout time corresponding to the training rate is 32 ms.
  • Vn-1 ⁇ V the training rate is located in the rate threshold interval N. At this time, the target equalization timeout time corresponding to the training rate is 100 ms.
  • the obtained training rate and the setting The minimum threshold rate for comparison.
  • the minimum rate threshold is used to determine whether to continue to use the forward compatible equalization timeout time as the configured equalization timeout time.
  • the equalization timeout time needs to be reselected, that is, when the target equalization timeout time , Then in the scenario of the value case 2.
  • the rate threshold Va is the minimum rate threshold. At this time, when determining the target equalization timeout time, there is no need to perform a comparison between the training rate V and the rate threshold Va.
  • S902 Configure the equalization timeout time of the master chip and the slave chip in the equalization training phase according to the target equalization timeout time.
  • an equalization parameter for satisfying link stability is found, it is determined that this equalization training is successful, and communication is performed according to the training rate; otherwise, it is determined that this equalization training has failed.
  • the link state opportunity completes the link establishment according to the process shown in FIG. 5.
  • the equalization parameters of the master chip in the current round of equalization training target stage are stored in the register of the slave chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in all In the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the register of the slave chip.
  • the sending parameters and receiving parameters of the previous round of equalization training target stage are stored in the PCIe system, the power on, power off, and reset of the system will not cause the previous round of equalization training target
  • the sending and receiving parameters of the stage are lost.
  • the sending parameters and receiving parameters of the previous round of equalization training target stage are stored in the memory in the PCIe system.
  • the specific steps of the first equalization training method can refer to the steps described in FIG. 10.
  • the fast equalization training mode refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending parameters and the receiving parameters of the previous round of equalization training target stage.
  • the equalization parameters obtained in the previous round of equalization training target stage are recorded, for example, the The equalization parameter obtained in the previous round is the second equalization parameter, so that the second equalization parameter can be directly called to determine the target equalization parameter of the current round during the equalization training target stage of this round.
  • S1002 Configure the sending parameter and the receiving parameter as initial parameters of the master chip and the slave chip in the current round of equalization training target stage, respectively.
  • the target equalization parameter of the current round of equalization training target stage in the embodiment of the present application is the initial parameter, or is further determined according to the initial parameter.
  • the target equalization parameters of the last round of equalization training target stage and the target equalization parameters of this round of equalization training target stage will not be very different, therefore, when performing the current round of equalization training target stage, use it directly
  • the target equalization parameters of the previous round are used as the target equalization parameters of this round, which can effectively save the time to determine the target equalization parameters; or, to determine the target equalization parameters of the current round according to the target equalization parameters of the previous round, you can better understand the cost
  • the approximate range of the target equalization parameters is helpful to quickly determine the target equalization parameters of this round and save the time to determine the target equalization parameters.
  • S1003 Obtain the forward compatible equalization timeout time of the equalization training target phase, and configure the forward compatible equalization timeout time of the equalization timeout time of the current round of equalization training target phase.
  • the first equalization parameter is found within the equalization timeout period configured in this equalization training stage, it is determined that the current equalization training is successful; otherwise, it is determined that the current equalization training has failed.
  • whether to adopt the fast equalization training mode is determined in the following manner:
  • the negotiation sequence between the master chip and the slave chip for the target stage of equalization training is obtained, and according to the second specific bit value in the negotiation sequence, it is determined whether to adopt the fast equalization training mode, where: The second specific bit indicates whether to adopt the fast equalization training mode.
  • the second specific bit used to indicate whether to adopt the fast equalization training mode is the first bit in the negotiation sequence, where the corresponding relationship between the bit value and the equalization training mode is shown in Table 2 .
  • the embodiment of this application can also be represented by multiple bits, for example, 2bit is used to indicate whether to use the fast equalization mode, and the bits used to indicate whether to use the fast equalization training mode are the first two bits in the negotiation sequence. . Among them, optional, 00 means Disenable; 01 means enable.
  • S1101 Obtain the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage, and continue to execute S1103.
  • S1102 Obtain the training rate of the master chip and the slave chip in the equalization training phase, and continue to execute S1104.
  • S1103 Configure the sending parameter and the receiving parameter as initial parameters of the master chip and the slave chip in the current round of equalization training target stage, respectively, and continue to execute S1106.
  • S1104 Determine the target equalization timeout time corresponding to the training rate, and continue to perform S1105.
  • S1106 Obtain the forward compatible equalization timeout time of the equalization training target phase, and configure the forward compatible equalization timeout time of the equalization timeout time of the current round of equalization training target phase.
  • S1107 during the equalization timeout period of the current round of equalization training target stage, perform equalization training using the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the target equalization timeout period can be determined according to the training rate used for the equalization training target stage, so that equalization training is performed according to the target equalization timeout period and the obtained initial parameters.
  • the default configuration is restored after the equalization training is completed through any one of the above-mentioned methods in FIG. 9 to FIG. 11.
  • This application also provides a balance training device, which can be used to execute the first balance training method and/or the second balance training method provided above. Therefore, the device described in this embodiment can refer to the foregoing method For the relevant definitions and descriptions of the embodiments, in order to save space, the same or similar parts will not be repeated in this embodiment. It should be noted that the device described in this embodiment may be a system management chip.
  • the device 1200 includes a transceiver 1201 and a manager 1202;
  • the transceiver 1201 is used to obtain the training rate of the master chip and the slave chip in the target stage of equalization training, and the target stage refers to the third stage or the fourth stage.
  • the manager 1202 is used to determine the target rate threshold interval where the training rate of the target phase is located, and determine the target rate threshold according to the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods
  • the target equalization timeout time corresponding to the interval, and the target equalization timeout time is configured as the equalization timeout time of the target stage
  • the N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein the The larger the rate threshold interval, the larger the corresponding equalization timeout time. ;
  • the master chip and the slave chip perform the equalization training of the target phase within the equalization timeout time of the target phase.
  • the manager 1202 determines that the target equalization timeout time is forward compatible Balance timeout period.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the master chip or the register of the slave chip.
  • the manager 1202 before the acquiring the training rate of the master chip and the slave chip in the target phase of the equalization training, the manager 1202 is further configured to determine not to use the fast equalization training mode; the fast equalization training The mode refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending parameters and the receiving parameters of the previous round of equalization training target stage.
  • the manager 1202 is further configured to store the equalization parameters of the main chip in the current round of equalization training target stage in In the register of the master chip, and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the register of the slave chip.
  • the equalization parameters of the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the slave chip In the register.
  • the manager 1202 is further configured to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; according to the bit position specified by the negotiation sequence The corresponding relationship between the value and the equalization training mode determines that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the manager 1202 is used to determine whether to adopt the fast equalization mode.
  • the transceiver 1201 is used to obtain the sending and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage when the fast equalization mode is determined to be adopted.
  • the manager is further configured to configure the sending parameter and the receiving parameter as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the equalization training target stage refers to the third stage of equalization training. Or the fourth stage; the transceiver is also used to obtain the forward compatible equalization timeout time of the equalization training target stage; the manager is also used to configure the forward compatible equalization timeout time of the equalization timeout time of the current round of equalization training target stage And, the manager is further configured to perform equalization training using the initial parameters of the master chip and the slave chip in the current round of equalization training target stage within the equalization timeout period of the current round of equalization training target stage .
  • the manager 1202 is further configured to store the equalization parameters of the main chip in the current round of equalization training target stage in the In the register of the master chip, and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the local
  • the equalization parameters of the round equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round equalization training target stage are stored in the register of the slave chip Inside.
  • the transceiver 1201 before the fast equalization training mode is determined to be adopted, the transceiver 1201 is further configured to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; the management The device 1202 is further configured to determine that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode according to the correspondence between the bit value specified by the negotiation sequence and the equalization training mode.
  • This application also provides a second equalization training device, which can also be used to execute the first equalization training method for configuring an equalization timeout period and/or the second equalization training method provided in the foregoing. Therefore, this embodiment
  • a second equalization training device which can also be used to execute the first equalization training method for configuring an equalization timeout period and/or the second equalization training method provided in the foregoing. Therefore, this embodiment
  • the device described in this embodiment may be a BIOS.
  • a balance training device 1300 provided in this embodiment includes an acquiring unit 1301, a determining unit 1302, and a configuration unit 1303.
  • the acquiring unit 1301 is configured to acquire the training rate of the master chip and the slave chip in a target stage of balanced training, and the target stage refers to the third stage or the fourth stage;
  • the determining unit 1302 is configured to determine the target rate threshold interval where the training rate of the target phase is located, and determine the target according to the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods The target equalization timeout time corresponding to the rate threshold interval;
  • the configuration unit 1303 is configured to configure the target equalization timeout time as the equalization timeout time of the target phase; wherein, N rate thresholds are predetermined, and N is an integer greater than or equal to 0, The larger the rate threshold interval is, the larger the corresponding equalization timeout period is; then, the master chip and the slave chip perform equalization training in the target phase within the equalization timeout period of the target phase.
  • the determining unit 1302 is specifically configured to: when the target rate threshold interval is the threshold interval with the smallest rate among the N+1 rate threshold intervals, the target equalization timeout time is Forward compatible equalization timeout time.
  • the determining unit 1302 before the acquiring the training rate of the master chip and the slave chip in the target phase of the equalization training, the determining unit 1302 is further configured to determine not to use the fast equalization training mode; the fast equalization training The mode refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending parameters and the receiving parameters of the previous round of equalization training target stage.
  • the acquiring unit 1301 is further configured to store the equalization parameters of the main chip in the current round of equalization training target stage after the completion of the equalization training of the current round of equalization training target stage in In the register of the master chip, and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the register of the slave chip.
  • the equalization parameters of the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the slave chip In the register.
  • the acquiring unit 1301 is further configured to acquire the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; the determining unit is also configured to According to the corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode, it is determined that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the determining unit 1302 is configured to determine whether to adopt the fast equalization mode
  • the obtaining unit 1301 is configured to obtain the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage when the fast equalization mode is determined to be adopted;
  • the configuration unit 1303 is configured to configure the sending parameters and the receiving parameters to be the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the equalization training target stage refers to the equalization training stage.
  • the obtaining unit 1301 is also configured to obtain the forward compatible equalization timeout time of the equalization training target stage;
  • the configuration unit 1303 is further configured to configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target stage; then, within the equalization timeout time of the current round of equalization training target stage, use the The master chip and the slave chip perform equalization training on the initial parameters of the current round of equalization training target stage.
  • the acquiring unit 1301 is further configured to store the equalization parameters of the main chip in the current round of equalization training target stage after the completion of the equalization training of the current round of equalization training target stage in In the register of the master chip, and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the register of the slave chip.
  • the equalization parameters of the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the slave chip In the register.
  • the obtaining unit 1301 is further configured to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage;
  • the determining unit 1302 is further configured to determine that the bit value specified in the negotiation sequence corresponds to the non-rapid equalization training mode according to the corresponding relationship between the bit value specified in the negotiation sequence and the equalization training mode.
  • This application also provides a third type of balance training device, which can also be used to execute the first type of balance training method for configuring the balance timeout period and/or the second type of balance training method provided above, correspondingly, the For the device, reference may also be made to the relevant limitation of the foregoing method embodiment, and the same or similar parts are not repeated in this embodiment.
  • the apparatus 1400 for equalization training provided in this embodiment.
  • the apparatus 1400 includes a central processing unit 1401 and a memory 1402.
  • the memory 1402 is used to store codes
  • the CPU 1401 is used to execute the codes stored in the memory 1402 to implement the functions of the device described in this embodiment. It should be known that the CPU is the CPU of the processor system using the PCIe bus.
  • the memory 1402 is also used to store the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods.
  • the CPU 1401 is used to obtain the training rate of the master chip and the slave chip in the target stage of equalization training, and the target stage refers to the third stage or the fourth stage.
  • the CPU1401 is also used to determine the target rate threshold interval where the training rate of the target stage is located, and determine the target equalization corresponding to the target rate threshold interval according to the correspondence between the N+1 rate threshold intervals and the N+1 equalization timeout periods Timeout time, and the target equalization timeout time is configured as the equalization timeout time of the target stage, N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein the greater the rate threshold interval , The corresponding equalization timeout time is greater; then the master chip and the slave chip perform equalization training in the target phase within the equalization timeout time of the target phase.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the master chip or the register of the slave chip.
  • the CPU 1401 before the acquiring the training rate of the master chip and the slave chip in the target phase of the equalization training, the CPU 1401 is also used to determine not to use the fast equalization training mode; the fast equalization training mode is Refers to a mode for configuring the initial parameters of the master chip and the slave chip in the current round of equalization training target stage according to the sending parameters and receiving parameters of the previous round of equalization training target stage.
  • the CPU 1401 is further configured to store the equalization parameters of the main chip in the current round of equalization training target stage in the In the register of the master chip, and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the local
  • the equalization parameters of the round equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round equalization training target stage are stored in the register of the slave chip Inside.
  • the CPU 1401 is further configured to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; according to the bit value specified by the negotiation sequence and The corresponding relationship of the equalization training mode is determined, and the specified bit value in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the memory 1402 is also used to store the equalization parameters of the previous round of equalization training target stage.
  • the CPU1401 is used to determine whether to adopt the fast equalization mode. When determining to adopt the fast equalization mode, obtain the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage, and combine the sending parameters and the receiving parameters They are respectively configured as the initial parameters of the master chip and the slave chip in the current round of equalization training target stage, and the equalization training target stage refers to the third stage or the fourth stage of the equalization training.
  • the CPU1401 is also used to obtain the forward compatible equalization timeout time of the equalization training target stage, and configure the forward compatible equalization timeout time to the equalization timeout time of the current round of equalization training target stage; in the current round of the equalization training target stage During the equalization timeout period, the initial parameters of the master chip and the slave chip in the target stage of the current round of equalization training are used to perform equalization training.
  • the CPU 1401 is further configured to store the equalization parameters of the main chip in the current round of equalization training target stage in the main In the register of the chip, and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the current round
  • the equalization parameters of the equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of the equalization training target stage are stored in the register of the slave chip .
  • the CPU 1401 before the fast equalization training mode is determined to be adopted, the CPU 1401 is further configured to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; and according to the The corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode is determined, and it is determined that the bit value specified in the negotiation sequence corresponds to the non-fast equalization training mode.
  • This application also provides a chip, which is the master chip or the slave chip described in the foregoing embodiment. Please refer to FIG. 15, a chip 1500 provided for this application.
  • the chip 1500 includes a register 1501, a transceiver 1502 and a manager 1503.
  • the register 1501 is used to store the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods;
  • the transceiver 1502 is configured to obtain the training rate of the master chip and the slave chip in the target stage of equalization training, and the target stage refers to the third stage or the fourth stage;
  • the manager 1503 is configured to determine the target rate threshold interval in which the training rate of the target phase is located, and determine the target rate threshold interval corresponding to the corresponding relationship between N+1 rate threshold intervals and N+1 equalization timeout periods Target equalization timeout time, and configure the target equalization timeout time as the equalization timeout time of the target stage, N rate thresholds are predetermined, and N is an integer greater than or equal to 0, wherein the rate threshold interval The larger the value, the larger the corresponding equalization timeout time;
  • the master chip and the slave chip perform the equalization training of the target phase within the equalization timeout time of the target phase.
  • the register 1501 is used to store the equalization parameters of the current round of equalization training target stage of the chip
  • the manager 1503 is used for judging whether to adopt the fast equalization mode
  • the transceiver 1502 is used to obtain the sending parameters and receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage when the fast equalization mode is determined to be adopted;
  • the manager 1503 is further configured to configure the sending parameters and the receiving parameters to be the initial parameters of the master chip and the slave chip in the current round of equalization training target stage.
  • the equalization training target stage refers to the third stage of equalization training. Stage or fourth stage;
  • the transceiver 1502 is also used to obtain the forward compatible equalization timeout time of the equalization training target stage;
  • the manager 1503 is further configured to configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target phase; and use the main chip within the equalization timeout time of the current round of equalization training target phase Perform equalization training with the initial parameters of the slave chip in the current round of equalization training target stage.
  • the chip has the function of turning on and off part of the equalizing circuit, and turning off the part of the equalizing circuit when a fast equalization process is required, such as turning off DFE or part of CTLE, so as to shorten the equalization time.
  • the chip described in the embodiment of the present application comes with its own management software, or is a state machine that meets the standard.
  • the communication system 1600 includes system software 1601, a master chip 1603, and a slave chip 1604. Among them, the master chip 1603 and the slave chip 1604 are connected through the PCIe/CCIX bus. It should be noted that the system software 1601 may be BIOS.
  • the system software 1601 obtains the training rate of the master chip and the slave chip in the target stage of the balanced training, the target stage refers to the third stage or the fourth stage; determines the target rate threshold interval in which the training rate of the target stage is located , According to the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period, determine the target equalization timeout time corresponding to the target rate threshold interval, and configure the target equalization timeout time as the target stage
  • N rate thresholds are predetermined, and N is an integer greater than or equal to 0. The larger the rate threshold interval is, the larger the corresponding equalization timeout time is; then the main chip and The slave chip performs the equalization training of the target phase within the equalization timeout time of the target phase.
  • the communication system may further include a memory 1602.
  • the memory 1602 is used to store the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods.
  • the memory 1602 is also used to store the equalization parameters of the current round of equalization training target stage.
  • the system software 1601 is also used for when the target rate threshold interval is the threshold interval of the smallest rate among the N+1 rate threshold intervals, the target equalization timeout time is the previous Compatible equalization timeout time.
  • the corresponding relationship between the N+1 rate threshold interval and the N+1 equalization timeout period is pre-stored in the register of the master chip or the register of the slave chip.
  • the system software 1601 before the acquisition of the training rate of the master chip and the slave chip in the target phase of the equalization training, the system software 1601 is also used to determine not to use the fast equalization training mode; the fast equalization training mode It refers to a mode in which the initial parameters of the master chip and the slave chip in the current round of equalization training target stage are respectively configured according to the sending parameters and the receiving parameters of the previous round of equalization training target stage.
  • the system software 1601 is also used to store the equalization parameters of the main chip in the current round of equalization training target stage in the current round of equalization training target stage.
  • the register of the master chip and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the register of the slave chip.
  • the equalization parameters of the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the slave chip’s In the register.
  • the system software 1601 is also used to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; according to the bit value specified by the negotiation sequence Corresponding relationship with the equalization training mode, determining that the specified bit value in the negotiation sequence corresponds to the non-fast equalization training mode.
  • the system software 1601 is used to determine whether to adopt the fast equalization mode.
  • the fast equalization mode is determined to be adopted, the sending parameters and the receiving parameters of the master chip and the slave chip in the previous round of equalization training target stage are obtained, and the sending parameters And the receiving parameters are respectively configured as the initial parameters of the master chip and the slave chip in the current round of the equalization training target stage, the equalization training target stage refers to the third or fourth stage of the equalization training, and the equalization training target stage is obtained Forward compatible equalization timeout time, and configure the forward compatible equalization timeout time as the equalization timeout time of the current round of equalization training target stage; within the equalization timeout time of the current round of equalization training target stage, use the The master chip and the slave chip perform equalization training on the initial parameters of the current round of equalization training target stage.
  • the communication system may further include a memory 1602.
  • the memory 1602 is used to store the equalization parameters of the previous round of equalization training target stage.
  • the memory 1602 is also used to store the equalization parameters of the current round of equalization training target stage.
  • the memory 1602 is used to store the correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods.
  • the system software 1601 is also used to store the equalization parameters of the main chip in the current round of equalization training target stage in the current round of equalization training target stage.
  • the register of the master chip and store the equalization parameters of the slave chip in the target stage of the current round of equalization training in the register of the slave chip; or, store the master chip and the slave chip in the register of the slave chip.
  • the equalization parameters of the current round of equalization training target stage are stored in the register of the master chip; or, the equalization parameters of the master chip and the slave chip in the current round of equalization training target stage are stored in the slave chip’s In the register.
  • the system software 1601 is also used to obtain the negotiation sequence used by the master chip and the slave chip to perform the equalization training target stage; and according to The corresponding relationship between the bit value specified by the negotiation sequence and the equalization training mode is determined, and the bit value specified in the negotiation sequence is determined to correspond to the non-fast equalization training mode.
  • various aspects of the equalization training method provided in the embodiments of the present application can also be implemented in the form of a program product, which includes program code.
  • program code runs on a computer device
  • the program code is used to make the computer device execute the steps in the equalization training method according to various exemplary embodiments of the present application described in this specification.
  • the program product can use any combination of one or more readable media.
  • the readable medium may be a readable signal medium or a readable storage medium.
  • the readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or a combination of any of the above.
  • An example (non-exhaustive list) of an implementation of the embodiments of this application includes: electrical connection with one or more wires, portable disk, hard disk, random access memory (RAM), read-only Memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.
  • RAM random access memory
  • ROM read-only Memory
  • EPROM or flash memory erasable programmable read-only memory
  • CD-ROM compact disk read-only memory
  • magnetic storage device magnetic storage device, or any suitable combination of the above.
  • the program product for equalization training may adopt a portable compact disk read-only memory (CD-ROM) and include program code, and may run on a server device.
  • CD-ROM portable compact disk read-only memory
  • the program product of this application is not limited to this.
  • the readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with message transmission, devices, or devices.
  • the readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, and readable program code is carried therein. This propagated data signal can take many forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • the readable signal medium may also be any readable medium other than a readable storage medium, and the readable medium may send, propagate, or transmit a program for use by or in combination with a periodic network action system, apparatus, or device.
  • the program code contained on the readable medium can be transmitted by any suitable medium, including, but not limited to, wireless, wired, optical cable, RF, etc., or any suitable combination of the above.
  • the program code used to perform the operations of this application can be written in any combination of one or more programming languages.
  • the programming languages include object-oriented programming languages—such as Java, C++, etc., as well as conventional procedural programming languages. Programming language-such as "C" language or similar programming language.
  • the program code can be executed entirely on the user's computing device, partly on the user's device, executed as an independent software package, partly on the user's computing device and partly executed on the remote computing device, or entirely on the remote computing device or server Executed on.
  • the remote computing device may be connected to a user computing device through any kind of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device.
  • LAN local area network
  • WAN wide area network
  • the embodiment of the present application also provides a computing device readable storage medium for the equalization training method, that is, the content is not lost after the power is off.
  • the storage medium stores a software program, including program code, and when the program code runs on a computing device, the software program can implement any of the above embodiments of the present application when the software program is read and executed by one or more processors A scheme for equalizing overtime training.
  • this application may take the form of a computer program product on a computer-usable or computer-readable storage medium, which has a computer-usable or computer-readable program code implemented in the medium to be used or used by the instruction execution system. Used in conjunction with the instruction execution system.
  • a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, transmit, or transmit a program for use by an instruction execution system, apparatus, or device, or in combination with an instruction execution system, Device or equipment use.

Abstract

一种均衡训练方法、装置及系统，包括：获取主芯片与从芯片在均衡训练的目标阶段的训练速率（900）；确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。该方法能够针对每次均衡训练过程，灵活的配置用于均衡训练的均衡超时时间，从而使配置的均衡超时时间更符合当前用于链路协商的训练速率，更好的保证了在配置的均衡超时时间内，找到均衡参数，提升了均衡训练成功率。

Description

一种均衡训练方法、装置及系统
相关申请的交叉引用
本申请要求在2020年05月30日提交中国专利局、申请号为202010480695.3、申请名称为“一种均衡训练方法、装置及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片技术领域，尤其涉及一种均衡训练方法、装置及系统。
背景技术
高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe)是一种计算机扩展总线标准，PCIe总线常用于计算机系统、服务器、存储器、手机等需要高速传输数据的处理器中，来连接外围设备。所述PCIe规定，通信系统(例如，主芯片与从芯片之间的链路协商)上电后先进行链路协商，成功协商后，才建立高速链路进行业务数据的收发。其中，从PCIe3.0开始，在进行链路协商时，提供了用以补偿因链路损耗引起信号质量问题的均衡训练机制。
所述均衡训练机制包括均衡训练阶段一至均衡训练阶段四(phase0～phase3)，共4个阶段。当前，均衡训练的每一阶段都规定了固定的均衡超时时间，例如，Phase2和Phase3阶段规定的均衡超时时间的最大时限通常为32ms。其中，所述通信系统如果在规定的均衡超时时间内均衡训练未完成，便会触发超时，并宣布链路均衡失败。
而随着通信速率的飞速提升，在更高速的链路中进行通信传输时，所述通信系统需要更为复杂的均衡电路结构以及数量庞大的均衡参数。也就意味着，该种情况下，在均衡训练阶段中，确定均衡参数需要花费更长的时间，甚至远远超出所述PCIe协议目前规定的最大时限32ms的均衡超时时间。因此，在更高速的链路中进行通信传输时，链路协商成功率较低。
综上，目前进行均衡训练的方式不够灵活，无法适用更高速的链路协商。
发明内容
本申请提供一种均衡训练方法，用以更灵活的进行均衡训练，提升高速链路协商的成功率。进一步的，本申请还提供了执行该方法的装置及系统，以及在执行该方法中用到的一种芯片。
第一方面，本申请实施例提供一种均衡训练方法，该方法包括下述步骤：
获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行 所述目标阶段的均衡训练。
基于该方案，本申请实施例能够针对每次均衡训练阶段，灵活的配置用于均衡训练的均衡超时时间，从而使配置的均衡超时时间更符合当前用于协商的训练速率。已知的，在均衡的各个阶段，如果芯片的均衡操作不能在均衡超时时间内完成，则该芯片将会退出均衡，进而导致该芯片和对端芯片之间的链路协商失败。而本申请中，均衡训练阶段中配置的均衡超时时间是根据所述均衡训练阶段的训练速率确定的。因此，所述均衡训练阶段配置的均衡超时时间较为充足，能够更好的保证所述均衡训练阶段的操作顺利完成，不会由于时间不充裕而退出。因此，本申请提供的方法能够在一定程度上提升链路协商成功率。
需要说明的是，在该芯片为主芯片时，所述对端芯片为从芯片。在该芯片为从芯片时，所述对端芯片为主芯片。
可选的，该主芯片和该从芯片之间通过PCIe总线或CCIX总线连通。可知，本实施例提供的均衡训练方法应用在使用PCIe总线或CCIX总线的处理器系统内。
可选的，在应用PCIe总线的处理器系统中，该主芯片为根组件(RC，Root Complex)或交换芯片，该从芯片是独立于该主芯片的端点设备(Endpoint)。应当知道的是，交换芯片在一些情况下可以为主芯片，在另一些情况下可以为从芯片。
结合第一方面，在一种可能的实现方式中，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
基于该方案，本申请实施例在确定所述目标阶段的训练速率所在的目标速率阈值区间为最小的阈值区间时，将所述目标均衡超时时间设置为前向兼容的均衡超时时间，无需再根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系查找所述目标阶段的训练速率对应的均衡超时时间时间，更好的节省了系统开销。
例如，所述PCIe3.0～PCIe5.0的前向兼容的均衡超时时间为32ms。
结合第一方面，在一种可能的实现方式中，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
基于该方案，将所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储到所述主芯片的寄存器内，或者所述从芯片的寄存器内，从而在用到所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系时，可以直接到对应芯片的寄存器中读取，节约时间。
结合第一方面，在一种可能的实现方式中，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
基于该方案，本申请实施例中还提供了一种快速均衡训练模式，即如果在进行本轮均衡训练目标阶段之前，选择了快速均衡训练模式，则将前一轮均衡训练阶段的发送参数和接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标节点的初始参数。丰富了进行均衡训练的方法，同时，因采用快速均衡训练模式，能够有效降低获取均衡参数的复杂度以及有效缩短获取均衡参数的时间，从而，更好的保证所述均衡训练阶段的操作顺利完成，不会由于时间不充裕而退出，一定程度上提升链路协商成功率。
结合第一方面，在一种可能的实现方式中，在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内， 并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
基于该方案，在完成本轮均衡训练目标阶段的均衡训练后，存储所述主芯片在所述本轮均衡训练目标阶段的均衡参数，以及存储所述从芯片在所述本轮均衡训练目标阶段的均衡参数。从而在进行下一轮均衡训练目标阶段时，可以直接获取主芯片与从芯片事先存储的发送参数和接收参数，用于确定初始参数，节约时间。
结合第一方面，在一种可能的实现方式中，所述确定不采用快速均衡训练模式之前，获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
基于该方案，本申请实施例提供了一种如何确定是否采用均衡训练模式的方法，即根据用于进行所述均衡训练目标阶段的协商序列中指定比特位值来确定，丰富了均衡训练方式。
第二方面，本申请实施例还提供一种均衡训练方法，该方法包括下述步骤：
判断是否采用快速均衡模式，在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段，获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
基于该方案，本申请实施例在进行本次均衡训练目标阶段中，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数。丰富了进行均衡训练的方法，有助于更快获取本次均衡训练阶段的均衡参数，适用性更强，效率更高。同时，因采用快速均衡训练模式，能够有效降低获取均衡参数的复杂度以及有效缩短获取均衡参数的时间，从而，更好的保证所述均衡训练阶段的操作顺利完成，不会由于时间不充裕而退出，一定程度上提升链路协商成功率。
需要说明的是，在该芯片为主芯片时，所述对端芯片为从芯片。在该芯片为从芯片时，所述对端芯片为主芯片。
可选的，该主芯片和该从芯片之间通过PCIe总线或CCIX总线连通。可知，本实施例提供的均衡训练方法应用在使用PCIe总线或CCIX总线的处理器系统内。
可选的，在应用PCIe总线的处理器系统中，该主芯片为根组件(RC，Root Complex)或交换芯片，该从芯片是独立于该主芯片的端点设备(Endpoint)。应当知道的是，交换芯片在一些情况下可以为主芯片，在另一些情况下可以为从芯片。
结合第二方面，在一种可能的实现方式中，所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训 练目标阶段的初始参数的模式。基于该方案，本申请实施例中还提供了一种快速均衡训练模式，即在确认采用快速均衡训练模式后，根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数。丰富了进行均衡训练的方法，有助于更快获取本次均衡训练阶段的均衡参数。
结合第二方面，在一种可能的实现方式中，在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
基于该方案，在完成本轮均衡训练目标阶段的均衡训练后，存储所述主芯片在所述本轮均衡训练目标阶段的均衡参数，以及存储所述从芯片在所述本轮均衡训练目标阶段的均衡参数。从而在进行下一轮均衡训练目标阶段时，可以直接获取主芯片与从芯片事先存储的发送参数和接收参数，用于确定初始参数，节约时间。
结合第二方面，在一种可能的实现方式中，所述确定采用快速均衡训练模式之前，获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
基于该方案，本申请实施例提供了一种如何确定是否采用均衡训练模式的方法，即根据用于进行所述均衡训练目标阶段的协商序列中指定比特位值来确定，丰富了均衡训练方式。
第三方面，本申请提供一种均衡训练装置，该装置用于执行前述第一方面或第一方面任一实现方式所述的方法。该装置包括收发器和管理器。
收发器用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段。对应的，管理器用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大。；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
采用本实施例提供的装置，能够实现第一方面或第一方面任一种可能的实现方式所述的均衡训练方法。可知，采用本实施例提供的装置，能够使得该主芯片在均衡的第三阶段的均衡超时时间是充足的，相应的，该主芯片在该第三阶段的均衡操作不会因为时间不够而退出；以及，使得该从芯片在均衡的第四阶段的均衡超时时间也是充足的，相应的，该从芯片在该第四阶段的均衡操作也不会因为时间不够而退出。因此，采用本实施例提供的装置，能够在一定程度上降低因为均衡超时时间不够而导致芯片退出均衡操作，有效提升链路协商成功率。
结合第三方面，在一种可能的实现方式下，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
该方案的有益效果可以参见第一方面的相关实现方式对应的有益效果，此处不再赘述。
如前文所述，所述PCIe3.0～PCIe5.0的前向兼容的均衡超时时间为32ms。
结合第三方面，在一种可能的实现方式下，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
结合第三方面，在一种可能的实现方式下，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述管理器还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
该方案的有益效果可以参见第一方面的相关实现方式对应的有益效果，此处不再赘述。
结合第三方面，在一种可能的实现方式下，在完成本轮均衡训练目标阶段的均衡训练后，所述管理器还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
结合第三方面，在一种可能的实现方式下，所述收发器还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
该方案的有益效果可以参见第一方面的相关实现方式对应的有益效果，此处不再赘述。
第四方面，本申请提供一种均衡训练装置，该装置用于执行前述第二方面或第二方面任一实现方式所述的方法。该装置包括收发器和管理器。
管理器，用于判断是否采用快速均衡模式；
收发器，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
管理器还用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
收发器还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
管理器还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；
以及，所述管理器还用于在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
采用本实施例提供的装置，能够实现第二方面或第二方面任一种可能的实现方式所述的均衡训练方法。可知，采用本实施例提供的装置，能够更快的为所述主芯片和所述从芯片配置本轮均衡训练目标阶段的初始参数，丰富了进行均衡训练的方法，有助于更快获取本次均衡训练阶段的均衡参数，适用性更强，效率更高。此外，有效降低了在进行均衡训练目标阶段过程中因时间不够而退出的概率，提升链路协商成功率。
结合第四方面，在一种可能的实现方式下，在完成本轮均衡训练目标阶段的均衡训练后，所述管理器还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述 主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
该方案的有益效果可以参见第二方面的相关实现方式对应的有益效果，此处不再赘述。
结合第四方面，在一种可能的实现方式下，确定采用快速均衡训练模式之前，所述收发器还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；所述管理器还用于根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
该方案的有益效果可以参见第二方面的相关实现方式对应的有益效果，此处不再赘述。
第五方面，本申请提供另一种均衡训练装置，该装置也用于执行前述第一方面或第一方面任一实现方式所述的均衡训练方法。该装置包括获取单元、确定单元和配置单元。
所述获取单元，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
所述确定单元，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间；
所述配置单元，用于将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间；
其中，N个速率阈值是预先确定的，且N是大于或等于0的整数，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
本实施例提供的装置用于执行第一方面或第一方面任一种可能的实现方式所述的方法。采用本实施例提供的装置，能够使得该主芯片在均衡的第三阶段的均衡超时时间是充足的，相应的，该主芯片在该第三阶段的均衡操作不会因为时间不够而退出；以及，使得该从芯片在均衡的第四阶段的均衡超时时间也是充足的，相应的，该从芯片在该第四阶段的均衡操作也不会因为时间不够而退出。因此，采用本实施例提供的装置，能够在一定程度上降低因为均衡超时时间不够而导致芯片退出均衡操作，有效提升链路协商成功率。
结合第五方面，在一种可能的实现方式下，所述确定单元具体用于在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
结合第五方面，在一种可能的实现方式下，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
结合第五方面，在一种可能的实现方式下，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述确定单元还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
结合第五方面，在一种可能的实现方式下，所述获取单元还用于在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所 述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
结合第五方面，在一种可能的实现方式下，所述获取单元还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；所述确定单元还用于根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
第六方面，本申请提供另一种均衡训练装置，该装置也用于执行前述第二方面或第二方面任一实现方式所述的均衡训练方法。该装置包括获取单元、确定单元和配置单元。
所述确定单元，用于判断是否采用快速均衡模式；
所述获取单元，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
所述配置单元，用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
所述获取单元还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
所述配置单元还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；则在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
本实施例提供的装置用于执行第二方面或第二方面任一种可能的实现方式所述的方法。采用本实施例提供的装置，能够更快的为所述主芯片和所述从芯片配置本轮均衡训练目标阶段的初始参数，丰富了进行均衡训练的方法，有助于更快获取本次均衡训练阶段的均衡参数，适用性更强，效率更高。此外，有效降低了在进行均衡训练目标阶段过程中因时间不够而退出的概率，提升链路协商成功率。
结合第六方面，在一种可能的实现方式下，所述获取单元还用于在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
结合第六方面，在一种可能的实现方式下，确定采用快速均衡训练模式之前，所述获取单元还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；所述确定单元还用于根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
第七方面，本申请提供了再一种均衡训练装置，该装置也用于执行前述第一方面或第一方面任一实现方式所述的均衡训练方法。该装置包括中央处理器(CPU，Central Processor Unit)和存储器，CPU用于执行存储在存储器内的代码以本实施例所述的装置的功能。
存储器用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系。对应的，CPU用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段。
CPU还用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
与前述各个实现方式所述的装置类似，采用本实施例所述的装置，能够在一定程度上降低由于均衡超时时间不够而导致系统退出均衡操作，进而导致链路协商失败的风险。
第八方面，本申请提供了再一种均衡训练装置，该装置也用于执行前述第二方面或第二方面任一实现方式所述的均衡训练方法。该装置包括中央处理器(CPU，Central Processor Unit)和存储器，CPU用于执行存储在存储器内的代码以本实施例所述的装置的功能。
存储器用于存储前一轮均衡训练目标阶段的均衡参数。对应的，CPU用于判断是否采用快速均衡模式，在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段。
CPU还用于获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
与前述各个实现方式所述的装置类似，采用本实施例所述的装置，能够在一定程度上降低由于均衡超时时间不够而导致系统退出均衡操作，进而导致链路协商失败的风险。
第九方面，本申请提供了一种芯片，该芯片可以为前述第一方面或其任一种实现方式、或第三方面或其任一种实现方式、或第五方面或其任一种实现方式提及的主芯片或从芯片。该芯片包括寄存器、收发器和管理器。
寄存器，用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系；
收发器，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
管理器，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
应用本实施例所述的芯片，能够实现第一方面或第一方面的任一种可能的实现方式所述的方法，进而实现降低因均衡超时时间不够而导致系统退出均衡操作，进而导致链路协商失败的风险。
结合第九方面，在第一种可能的实现方式下，所述寄存器还用于存储前向兼容的均衡超时时间。
结合第九方面，在第一种可能的实现方式下，所述寄存器还用于存储本轮均衡训练目标阶段的均衡参数。
进一步的，本申请实施例中，所述芯片具有打开和关闭部分均衡电路，在需要快速均衡过程的情况下关闭部分均衡电路的功能，比如关闭DFE或者部分CTLE，实现缩短均衡时间。其中，本申请实施例所述芯片自带管理软件，或者是符合标准的状态机。
第十方面，本申请提供了一种芯片，该芯片可以为前述第二方面或其任一种实现方式、或第四方面或其任一种实现方式、或第六方面或其任一种实现方式提及的主芯片或从芯片。该芯片包括寄存器、收发器和管理器。
寄存器，用于存储所述芯片本轮均衡训练目标阶段的均衡参数；
管理器，用于判断是否采用快速均衡模式；
收发器，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
管理器还用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
收发器还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
管理器还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；以及在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
应用本实施例所述的芯片，能够实现第二方面或第二方面的任一种可能的实现方式所述的方法，进而实现降低因均衡超时时间不够而导致系统退出均衡操作，进而导致链路协商失败的风险。
结合第十方面，在第一种可能的实现方式下，所述寄存器还用于存储本轮均衡训练目标阶段的均衡参数。
结合第十方面，在第一种可能的实现方式下，所述寄存器还用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系。
进一步的，本申请实施例中，所述芯片具有打开和关闭部分均衡电路，在需要快速均衡过程的情况下关闭部分均衡电路的功能，比如关闭DFE或者部分CTLE，实现缩短均衡时间。其中，本申请实施例所述芯片自带管理软件，或者是符合标准的状态机。
第十一方面，本申请还提供一种通信系统，该通信系统包括系统软件、主芯片和从芯片。所述主芯片和所述从芯片之间通过总线或CCIX总线连通。
所述系统软件用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时 时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
采用本实施例提供的装置，能够实现第一方面或第一方面任一种可能的实现方式所述的均衡训练方法。可知，采用本实施例提供的装置，能够使得该主芯片在均衡的第三阶段的均衡超时时间是充足的，相应的，该主芯片在该第三阶段的均衡操作不会因为时间不够而退出；以及，使得该从芯片在均衡的第四阶段的均衡超时时间也是充足的，相应的，该从芯片在该第四阶段的均衡操作也不会因为时间不够而退出。因此，采用本实施例提供的装置，能够在一定程度上降低因为均衡超时时间不够而导致芯片退出均衡操作，有效提升链路协商成功率。
结合第十一方面，在一种可能的实现方式下，所述系统软件还用于在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
结合第十一方面，在一种可能的实现方式下，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
结合第十一方面，在一种可能的实现方式下，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述系统软件还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
结合第十一方面，在一种可能的实现方式下，在完成本轮均衡训练目标阶段的均衡训练后，所述系统软件还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
结合第十一方面，在一种可能的实现方式下，所述系统软件还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
需要说明的是，第十一方面或其各个可能实现方式的有益效果可以参见前述各个关联实施例的有益效果，由于高度类似，因此不再赘述。
第十二方面，本申请还提供一种通信系统，该通信系统包括系统软件、主芯片和从芯片。所述主芯片和所述从芯片之间通过总线或CCIX总线连通。
所述系统软件用于判断是否采用快速均衡模式，在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段，获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片 在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
采用本实施例提供的装置，能够实现第二方面或第二方面任一种可能的实现方式所述的均衡训练方法。可知，采用本实施例提供的装置，能够更快的为所述主芯片和所述从芯片配置本轮均衡训练目标阶段的初始参数，丰富了进行均衡训练的方法，有助于更快获取本次均衡训练阶段的均衡参数，适用性更强，效率更高。此外，有效降低了在进行均衡训练目标阶段过程中因时间不够而退出的概率，提升链路协商成功率。
结合第十二方面，在一种可能的实现方式下，在完成本轮均衡训练目标阶段的均衡训练后，所述系统软件还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
结合第十二方面，在一种可能的实现方式下，确定采用快速均衡训练模式之前，所述系统软件还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；以及根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
需要说明的是，第十二方面或其各个可能实现方式的有益效果可以参见前述各个关联实施例的有益效果，由于高度类似，因此不再赘述。
第十三方面，本申请实施例提供了一种计算机程序产品，计算机程序产品包括：计算机程序代码，当计算机程序代码被均衡训练装置的单元模块或收发器、管理器运行时，使得该装置执行上述第一方面或第二方面中的任意一面；或第一方面至第二方面中的任意可能的实现方式中的任一方法。
第十四方面，本申请实施例提供了一种计算机可读存储介质，计算机可读存储介质存储有程序，程序使得均衡超时时间训练装置(例如，主芯片；再例如，从芯片)执行上述第一方面或第二方面中的任意一面；或第一方面至第二方面中的任意可能的实现方式中的任一方法。
附图说明
图1为本申请提供的变速均衡训练示意图；
图2为本申请提供的均衡电路示意图；
图3为本申请实施例提供的一种系统架构示意图；
图4为本申请提供的位于RC和显卡之间的信号通道的示意图；
图5为PCIe标准规定的建链流程图；
图6为本申请实施例提供的一种场景示意图；
图7为本申请实施例提供的第一种确定第一均衡超时时间的场景示意图；
图8为本申请实施例提供的第二种确定第一均衡超时时间的场景示意图；
图9为本申请实施例提供的第一种均衡训练方法流程示意图；
图10为本申请实施例提供的第二种均衡训练方法示意图；
图11为本申请实施例提供的第三种均衡训练方法示意图；
图12为本申请提供的第一种均衡训练装置示意图；
图13为本申请提供的第二种均衡训练装置示意图；
图14为本申请提供的再一种均衡训练装置的示意图；
图15为本申请提供的一种芯片的结构示意图；
图16为本申请提供的一种通信系统的结构示意图。
具体实施方式
下面结合说明书附图对本申请进行具体说明。
PCIe是一种计算机扩展总线标准，PCIe总线常用于计算机系统、服务器、存储器、手机等需要高速传输数据的处理器中，来连接外围设备。从PCIe3.0开始，PCIe采用发送和接收均衡电路来解决信号质量问题，同时也定义了均衡训练机制。如图1所示，所述均衡训练机制包括phase0～phase3共4个阶段。其中，所述Phase2主要是主芯片调整从芯片的发送参数，同时主芯片对应的调整自己的接收参数，以期望链路达到协议要求的误码率小于10E-12的稳定状态；所述Phase3主要是从芯片调整主芯片的发送参数和自己接收参数。也就是说，所述Phase2与所述Phase3主要分别用于进行发送端和接收端均衡电路的参数训练，以保证寻找到合适的均衡电路参数。示例性的，如图2所示的均衡电路框图，所述均衡参数的值可以表示为C-1/C0/C+1值。
此外，在PCIe均衡训练中，当前均衡训练的每一阶段都规定了固定的均衡超时时间，例如，上述图1所示，Phase2和Phase3阶段规定的均衡超时时间的最大时限通常为32ms，而如果在规定的均衡超时时间内均衡训练未完成，便会触发超时，并宣布链路均衡失败。
由于PCIe速率不断提升，PCIe的传输速率已经从PCIe1.0版本的2.5G提升到PCIe6.0版本的64Gbps，并且随着科技的进步，后续还会使用更高的速率，在更高速的传输中，芯片的发送端与接收端需要更为复杂的均衡电路结构以及数量庞大的均衡参数。
因此，在均衡训练阶段中，确定均衡参数需要花费更长的时间，甚至从ms级别到s级别，远远超出PCIe协议目前要求的最大32ms的时间要求。而这种情况，会导致在更高速的链路中进行通信传输时，链路协商成功率较低。
目前针对上述问题提供的解决方案如下：
根据链路损耗配置均衡超时时间，即把链路损耗分为长距(long reach，LR)和短距(short reach，SR)等不同损耗类型，在进行均衡训练时，确定链路损耗类型，根据不同链路损耗类型对均衡超时时间的需求，配置均衡训练Phase2和Phase3阶段的均衡超时时间为不同值。
但是，链路损耗类型的确定本身就是一个较为复杂的问题，并且根据链路损耗类型来配置均衡超时时间，约束范围较宽泛，无法针对损耗类型相同，但速率不同的均衡训练进行更加灵活的调整。
为解决上述问题，本申请实施例提供一种均衡训练方法，本申请实施例的技术方案可以应用于各种总线处理系统。例如，应用PCIe总线的处理器系统(也可以简称为“PCIe系统”)，以及应用CCIX总线的处理器系统(也可以简称为“CCIX系统”)。
为便于理解本申请实施例，下面仅以PCIe系统为例详细说明本申请涉及的方案。应当知道的是，应用CCIX系统也具有相同或相似的特征，具体参见下文关于应用PCIe系统的描述就能够理解应用CCIX系统了，因此不再重复赘述。
如图3所示，它示出了一个应用PCIe总线的处理器系统。该系统包括根组件(root complex，RC)、交换芯片(switch)和PCIe-to-PCI桥等。
具体的，RC也被称为该系统的根控制器，通常被集成在中央处理器(central processor unit，CPU)上。RC通常具有多个端口。通过该多个端口中的每一个端口，该RC可以和一个部件连通。该多个端口可以包括多个用于连接PCIe总线的端口(简称PCIe端口)。通过一个PCIe端口，该RC可以连接一个端点(endpoint)，自然，该RC和该Endpoint之间是通过PCIe总线实现连接的。需要说明的是，如图3所示，该Endpoint可以为显卡、网卡、光通道卡、Switch或准用集成电路(application specific integrated circuit，ASIC)等。在图1所示的处理器系统中，RC和DDR之间通过DDR总线连通，所以RC上与DDR连接的端口不是PCIe端口。因此，该RC的多个端口可以全是PCIe端口，也可以部分是PCIe端口。
Switch用于对该RC进行链路扩展。具体的，一方面，该Switch和RC之间通过PCIe总线实现连通；另一方面，该Switch具有多个端口，通过一个端口，该Switch可以和一个EP通过PCIe总线连通。因此，基于该Switch，该RC可以通过一个端口和多个Endpoint实现连通。如图3所示，该Switch具有3个端口，该Switch通过该3个端口中的任意一个端口可以和一个ASIC，通过PCIe总线连通。
PCIe-to-PCI桥的作用是桥接，用于实现PCIe总线和PCI总线的转换，从而能够兼容原来的支持PCI总线的Endpoint。如图3所示，PCIe-to-PCI桥的一端通过PCIe总线连接到Switch，另一端连接到PCI总线上。进一步地，图3中还示出了多个支持PCI总线标准的PCI插槽，插在该PCI插槽内的芯片或卡能够通过PCI总线连接到该PCIe-to-PCI桥，进而通过Switch连接到CPU。
需要说明的是，RC和Endpoint之间可以通过PCIe总线直接连通，也可以通过PCIe总线和连接器后实现连通。如图4所示，RC和显卡之间依次通过PCIe总线、连接器、PCIe总线、连接器和PCIe总线后实现连通。应当知道的是，位于RC和Endpoint之间的多条PCIe总线的长度可以是相同，也可以是不同。
为了便于理解，此处对本申请中多次提及的“系统”进行说明。本申请所述的系统是指应用PCIe/CCIX总线的系统(简称为“PCIe/CCIX系统”)。该PCIe/CCIX系统可以包括一个中央处理器CPU和其外围设备，其中，该CPU和其外围设备之间的通道中至少有一个通道使用的是PCIe/CCIX总线。该PCIe/CCIX系统还可以包括多个CPU和其外围设备，其中，该多个CPU之间的通道中至少有一个通道使用的是PCIe/CCIX总线，或其中一个CPU和外围设备之间的通道中至少有一个通道使用的是PCIe/CCIX总线。
参见附图5，它示出了PCIe系统从上电到建立通信连接的流程图。根据PCIe标准的规定，当开机或复位后，主芯片中的链路状态机将控制链路依次进入：检测——轮询(polling)——配置(configuration)——连接(linkup)——恢复。具体的，在检测阶段，主芯片检测从芯片是否在位。当检测到从芯片在位后，进入到Polling阶段，进行比特锁定以及训练速率确定，或者进行比特锁定以及训练模式确定(即确定是否采用快速均衡模式)。然后进入到配置阶段，进行链路带宽和链路号的确定，执行通道到通道的相位补偿等。完成配 置后，进入Linkup阶段，链路以低速运行到Linkup，也即主芯片和从芯片建立连接。然后，系统进入到恢复阶段，进行均衡超时时间以及变速，完成变速且速率提升到高速后，返回到连接状态，以实现业务数据传输。
需要说明的是，本申请中所述的主芯片是指包含下行口(downstream port，DSP)的芯片。有时，该主芯片也被简称为下行口。本申请中所述的从芯片是指包含上行口(upstream port，USP)的芯片。有时，该从芯片也被简称为上行口。
进一步地，结合图3可知，在本申请中，所述主芯片可以为RC，也可以为交换芯片(switch)。在该主芯片为RC时，该从芯片可以为端点设备(endpoint)，也可以为交换芯片(switch)。在该主芯片为交换芯片时，该从芯片可以为端点设备。其中，该端点设备可以为显卡、网卡、光通道卡、存储卡或交换芯片等。
示例性的，本申请实施例选取所述发送终端设备与所述接收终端设备为具有处理功能的芯片为例，对本申请实施例的具体场景进行详细介绍。其中，该场景中包括PCIe link以及link两端的芯片，其中一端芯片包括下行口(downstream port，DSP)，另一端芯片包括上行口(upstream port，USP)。如下如图6所示，包含DSP的芯片可以是CPU(包含root complex部分)、交换芯片(switch)和Retimer，包含USP的芯片可以是PCIe节点(FC card、IB等)、交换芯片(switch)以及Retimer等。
值得注意的是，关于均衡超时时间的操作发生在主芯片和从芯片之间。在本申请中，该主芯片和从芯片可以位于同一处理器系统中，也可以位于不同的处理器系统中，其中，该主芯片和从芯片之间通过PCIe/CCIX总线连通。例如，图3中的RC对应于主芯片，Endpoint对应于从芯片。
需要说明的是，本申请实施例中关于配置均衡超时时间的操作可以在不同阶段实现，不仅可以发生在恢复阶段，也可以发生在芯片上电之后以及PCIe/CCIX状态机启动之前。
示例性的，上电芯片校准阶段由系统软件通过配置两路两端的芯片功能模块寄存器完成，比如I2C、Jtag等接口；或者在链路协商阶段由两端芯片通过TS序列协商完成；或者链路开始以较低速率(比如2.5G)完成链路初始化，通过带内完成配置，再协商到高速率。
本申请实施例描述的系统架构以及业务场景是为了更加清楚的说明本申请实施例的技术方案，并不构成对于本申请实施例提供的技术方案的限定，本领域普通技术人员可知，随着系统架构的演变和新业务场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。应理解，图3至图6仅为便于理解而示例的简化示意图，该系统中还可以包括其他装置或者其他构造等，图3至图6中未予以画出。
以下再对本申请实施例中涉及的部分用语进行解释说明，以便于理解。
1)本申请实施例中“PCIe总线”，是一种高速串行计算机扩展总线标准。
PCIe属于高速串行点对点双通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，主要支持主动电源管理，错误报告，端对端的可靠性传输，热插拔以及服务质量(QOS)等功能。相对于PCI总线来说具有更快的传输速率。
其中，需要说明的是，本申请实施例中所述PCIe总线不仅可以应用于内部互连，也可以应用于外部互连。
2)本申请实施例中“CCIX总线”基于与PCIe总线相同的物理架构，该物理架构包括电气子层(electrical sub-block)和逻辑子层(logical sub-block)，且CCIX总线支持PCIe1.0、 PCIe2.0、PCIe3.0和PCIe4.0的传输速率。
其中，需要说明的是，本申请实施例中所述CCIX总线不仅可以应用于内部互连，也可以应用于外部互连。
3)本申请实施例中“状态机”是由状态寄存器和组合逻辑电路构成，能够根据控制信号按照预先设定的状态进行状态转移，是协调相关信号动作、完成特定操作的控制中心。
4)本申请实施例中“均衡训练”是指在通信系统中，由于各种噪声和干扰的存在，使得通信系统中的传输信号发生失真的变化，也就是信道是非理想信道，对信道中这些特性进行补偿和校正的技术。
5)本申请实施例中“均衡超时时间”是指均衡训练阶段的的最大时限，即如果在规定的均衡超时时间内均衡训练未完成，便会触发超时，并宣布链路均衡失败。
其中，本申请实施例中的术语“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中，A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。以下至少一项(个)下或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b，或c中的至少一项(个)，可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。
除非有相反的说明，本申请实施例提及“第一”、“第二”等序数词是用于对多个对象进行区分，不用于限定多个对象的顺序、时序、优先级或者重要程度。
此外，本申请实施例和权利要求书及附图中的术语“包括”和“具有”不是排他的。例如，包括了一系列步骤或模块的过程、方法、系统、产品或设备，不限定于已列出的步骤或模块，还可以包括没有列出的步骤或模块。
一、通过上述应用场景等内容的介绍，本申请实施例提供的第一种均衡训练方法。
其中，本申请实施例提供的均衡训练方法中均衡训练的目标阶段是指第三阶段或第四阶段，即本申请实施例提供的均衡训练方法配置的是Phase 2和/或Phase 3两个阶段所需要的目标均衡超时时间。
此外，在执行本申请所述的第一种均衡训练方法之前，还需要对该PCIe系统做如下的配置。
首先，需要在该PCIe系统内建立并存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系，如图7或者图8所示。
可选的，所述均衡训练阶段为均衡训练阶段三时，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系被预先存储在所述主芯片的寄存器内；所述均衡训练阶段为均衡训练阶段四时，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系被预先存储在所述从芯片的寄存器内。
需要说明的是，该所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系被存储在该PCIe系统中之后，该系统上电、下电以及复位，均不会造成所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系丢失。可选的，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系被存储在该PCIe系统内的存储器中。
进一步的，所述第一种均衡训练方法具体步骤可参图9所述步骤。
S900，获取主芯片与从芯片在均衡训练的目标阶段的训练速率。
本申请实施例一种可选的方式，通过下列方式获取所述均衡训练目标阶段的训练速率：
本申请实施例中，获取主芯片和从芯片之间用于进行所述均衡训练目标阶段的协商序列，并根据所述协商序列中第一特定的bit位值，确定在所述均衡训练目标阶段的训练速率，其中，所述第一特定的bit位指示需要进行训练速率信息。
具体的，获取到所述第一特定的bit位数值后，根据所述第一特定的bit位数值与进行训练速率的对应关系，确定将要进行所述均衡训练目标阶段的训练速率，例如，所述训练速率为V。
示例性的，以PCIe5.0为例，假设，用于表示训练速率的所述第一特定的bit位为协商序列中的最后两位，其中，bit位数值与训练速率对应关系如表1所示。
例如，所述第一特定的bit位值为01，则确定要进行均衡训练的训练速率为16GT/s。
bit位数值 训练速率
00b 8.0GT/s
10b 16.0GT/s
01b 32.0GT/s
11b Reserved
表1 bit位数值与训练速率对应关系
其中，所述表1所示的bit位数值与训练速率的对应关系被预先存储在PCIe/CCIX系统的存储器内。具体的，该存储器可以为闪存或电子可擦可编程序只读存储器EEPROM等。
S901，确定所述训练速率对应的目标均衡超时时间。
所述目标均衡超时时间表示在所述均衡训练目标阶段获取到均衡参数的最大时限。
本申请实施例中一种可选的方式，确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间。其中，所述N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大。
进一步的，本申请实施例根据N的取值情况，分别对查找目标均衡超时时间进行详细介绍。
取值情况1：N＝2的情况，即当前的速率阈值是一个，速率阈值区间为两个。
具体的，根据获取到的所述训练速率，例如，所述训练速率为V，判断所述训练速率所处的速率阈值区间。当速率阈值是一个，例如所述速率阈值为Va。则根据获取的所述训练速率V所在的速率阈值区间确定对应的目标均衡超时时间。
示例性的，如上述图7所示，因当前速率阈值是一个，即Va。因此，当前存在两个速率阈值区间，即用于表示训练速率小于速率阈值Va的速率阈值区间1，以及用于表示训练速率大于等于速率阈值Va的速率阈值区间2。
其中，假设，速率阈值区间1对应的目标均衡超时时间为32ms，速率阈值区间2对应的目标均衡超时时间为50ms。
进一步的，将获取到的所述训练速率V，与所述速率阈值Va进行比较，确定所述训练速率位于哪个速率阈值区间。
假设，若V>＝Va，则所述训练速率位于所述速率阈值区间2，此时，所述训练速率对应的目标均衡超时时间为50ms。同理，若V<Va，则所述训练速率位于所述速率阈值区间1，此时，所述训练速率对应的目标均衡超时时间为32ms。
此外，本申请实施例中一种可选的方式，为了节省在不必要情况下查找目标均衡超时时间造成的系统开销，在执行所述S901之前，还会将获取到的所述训练速率与设置的最小阈值速率进行比较。其中，所述最小速率阈值用于确定是否继续使用前向兼容的均衡超时时间作为配置的均衡超时时间。
具体的，若确定所述训练速率大于等于最小速率阈值；或确定所述训练速率大于所述最小速率阈值，则执行所述S901。反之，若确定所述训练速率小于等于最小速率阈值；或确定所述训练速率小于所述最小速率阈值，则确定所述目标均衡超时时间为前向兼容的均衡超时时间，例如，直接根据前向兼容的均衡超时时间32ms进行均衡训练。
进一步的，若本申请实施例中，在执行所述S901之前，已经确定了不继续使用前向兼容的均衡超时时间作为目标均衡超时时间，需要重新选取均衡超时时间，即目标均衡超时时间时，则在取值情况1的场景下。所述速率阈值Va即为所述最小速率阈值。此时，可以直接确定所述训练速率V处于所述速率阈值区间2，对应的第一时长为50ms。
取值情况2：N>2的情况，即当前的速率阈值至少有两个，速率阈值区间至少有三个。
具体的，根据获取到的所述训练速率，例如，所述训练速率为V，判断所述训练速率所处的速率阈值区间。当速率阈值至少两个时，根据获取的所述训练速率值V所在的速率阈值区间确定对应的目标均衡超时时间。
示例性的，如上述图8所示，因当前速率阈值至少两个，例如第一速率阈值Va，第二速率阈值Vb，……，第N-1速率阈值Vn-1。因此，当前存在至少三个速率阈值区间，即用于表示训练速率小于速率阈值Va的速率阈值区间1；用于表示训练速率大于等于速率阈值Va，小于速率阈值Vb的速率阈值区间2；……；用于表示训练速率大于等于速率阈值Vn-2，小于速率阈值Vn-1的速率阈值区间Vn。
其中，假设，速率阈值区间1对应的目标均衡超时时间为32ms，速率阈值区间2对应的目标均衡超时时间为50ms，……，速率阈值区间N对应的目标均衡超时时间为100ms。
进一步的，根据获取到的所述训练速率V，确定所述训练速率位于哪个速率阈值区间。
假设，若Va＝<V<Vb，则所述训练速率位于所述速率阈值区间2，此时，所述训练速率对应的目标均衡超时时间为50ms。同理，若V<Va，则所述训练速率位于所述速率阈值区间1，此时，所述训练速率对应的目标均衡超时时间为32ms。若Vn-1<V，则所述训练速率位于所述速率阈值区间N，此时，所述训练速率对应的目标均衡超时时间为100ms。
此外，本申请实施例中一种可选的方式，为了节省在不必要情况下查找目标均衡超时时间造成的系统开销，在执行所述S901之前，还会将获取到的所述训练速率与设置的最小阈值速率进行比较。其中，所述最小速率阈值用于确定是否继续使用前向兼容的均衡超时时间作为配置的均衡超时时间。
进一步的，若本申请实施例中，在执行所述S901之前，已经确定了不继续使用前向兼容的均衡超时时间作为配置的均衡超时时间，需要重新选取均衡超时时间，即目标均衡超时时间时，则在取值情况2的场景下。所述速率阈值Va即为所述最小速率阈值。此时，在确定所述目标均衡超时时间时，无需在进行所述训练速率V与所述速率阈值Va的比较。
S902，根据所述目标均衡超时时间，配置所述主芯片以及所述从芯片在所述均衡训练阶段的均衡超时时间。
进一步的，若在所述目标均衡超时时间内，找到用于满足链路稳定性的均衡参数，确定本次均衡训练成功，并根据所述训练速率，进行通信；反之确定本次均衡训练失败。
应当知道的是，在完成前述均衡超时时间的配置之后，按照PCIe总线标准规定的协商流程，链路状态机会按照图5所示的过程完成建链。
二、通过上述应用场景等内容的介绍，本申请实施例提供的第二种均衡训练方法。
其中，在执行本申请所述的第二种均衡训练方法之前，还需要对该PCIe系统做如下的配置。
首先，需要在该PCIe系统内建立并存储前一轮均衡训练目标阶段的发送参数和接收参数。
可选的，在完成前一轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
需要说明的是，所述前一轮均衡训练目标阶段的发送参数和接收参数被存储在该PCIe系统中之后，该系统上电、下电以及复位，均不会造成该前一轮均衡训练目标阶段的发送参数和接收参数丢失。具体的，该前一轮均衡训练目标阶段的发送参数和接收参数被存储在该PCIe系统内的存储器中。
进一步的，所述第一种均衡训练方法具体步骤可参图10所述步骤。
S1000，确定本轮均衡训练目标阶段采用快速均衡训练模式。
其中，所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
S1001，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数。
其中，本申请实施例中，成功进行前一轮均衡训练目标阶段后，记录所述前一轮均衡训练目标阶段得到的均衡参数(即所述发送参数和所述接收参数)，例如，所述前一轮得到的均衡参数为第二均衡参数，以备在本轮进行均衡训练目标阶段中直接调用所述第二均衡参数确定本轮的目标均衡参数。
S1002，将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数。
其中，本申请实施例中本轮均衡训练目标阶段的目标均衡参数为所述初始参数，或者是根据所述初始参数进一步确定的。
因为，在相同的运行环境下，上一轮均衡训练目标阶段的目标均衡参数与本轮均衡训练目标阶段的目标均衡参数相差不会很大，因此，进行本轮均衡训练目标阶段时，直接使用上一轮的目标均衡参数作为本轮的目标均衡参数，能够有效节省确定目标均衡参数的时间；或者，根据上一轮的目标均衡参数来确定本轮的目标均衡参数，能够更好的知晓本轮目标均衡参数的大致范围，有助于快速的确定本轮目标均衡参数，节省确定目标均衡参数 的时间。
S1003，获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间。
S1004，在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
进一步的，若在本次均衡训练阶段配置的均衡超时时间内，找到所述第一均衡参数，则确定本次均衡训练成功；反之则确定本次均衡训练失败。
三、进一步的，本申请实施例中所述图9所述方案，与所述图10所述方案，在实际均衡训练过程中可以进行结合使用，即在执行所述图9中的S900之前，确定是否开启快速训练模式，具体参见图11所述步骤。其中，为简洁描述，该部分的配置内容以及执行过程中的细节参见上述内容的介绍，在此不进行赘述。
S1100，在本次均衡训练过程中，确定是否采用快速均衡训练模式，若是，执行S1101，若否，执行S1102。
本申请实施例一种可选的方式，通过下列方式确定是否采用快速均衡训练模式：
本申请实施例中，获取主芯片和从芯片之间用于进行均衡训练目标阶段的协商序列，并根据所述协商序列中第二特定的bit位值，确定是否采用快速均衡训练模式，其中，所述第二特定的bit位指示是否采用快速均衡训练模式。
示例性的，假设，用于表示是否采用快速均衡训练模式的所述第二特定的bit位为协商序列中的第一位，其中，bit位数值与均衡训练模式的对应关系如表2所示。
例如，所述第一特定的bit位值为0时，表示不能采用(disenable)，为1时表示可以采用(enable)。
bit位数值 均衡训练模式
0b 不采用快速均衡训练模式
1b 采用快速均衡训练模式
表2 bit位数值与均衡训练模式对应关系
需要说明的是，本申请实施例中也可以用多bit表示，例如，用2bit表示是否使采用快速均衡模式，且用于表示是否采用快速均衡训练模式的bit位为协商序列中的前两位。其中，可选的，00表示Disenable；01表示enable。
S1101，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，继续执行S1103。
S1102，获取主芯片与从芯片在均衡训练阶段的训练速率，继续执行S1104。
S1103，将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，继续执行S1106。
S1104，确定所述训练速率对应的目标均衡超时时间，继续执行S1105。
S1105，将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
S1106，获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡 超时时间配置为本轮均衡训练目标阶段的均衡超时时间。
S1107，在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
需要说明的是，本申请实施例中所述图9与所述图10的结合方式并不限于上述图11所述方式，可以根据实际应用进行灵活调整，例如，确定采用快速均衡模式后，依旧可以根据用于进行均衡训练目标阶段的训练速率确定目标均衡超时时间，从而根据所述目标均衡超时时间以及得到的初始参数进行均衡训练。
进一步的，本申请实施例中在通过上述图9～图11任一种方式完成均衡训练后，恢复默认配置。
四、本申请还提供了一种均衡训练装置，该装置可以用来执行前述提供的第一种均衡训练方法和/或第二种均衡训练方法，因此本实施例所述的装置可以参见前述方法实施例的相关限定和描述，为了节约篇幅，相同或者相似部分，本实施例不再赘述。需要说明的是，本实施例所述的装置可以为系统的管理芯片。
如图12所示，为本实施例提供的一种均衡训练装置1200。该装置1200包括收发器1201和管理器1202；
当所述均衡训练装置用来执行前述提供的第一种均衡训练方法时：
具体的，该收发器1201用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段。对应的，该管理器1202用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大。；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
作为本申请的一个实施例，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述管理器1202确定所述目标均衡超时时间为前向兼容的均衡超时时间。
作为本申请的另一个实施例，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
作为本申请的再一种实施例，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述管理器1202还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
作为本申请的再一种实施例，在完成本轮均衡训练目标阶段的均衡训练后，所述管理器1202还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的再一种实施例，所述管理器1202还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训 练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
当所述均衡训练装置用来执行前述提供的第二种均衡训练方法时：
具体的，该管理器1202用于判断是否采用快速均衡模式。对应的，该收发器1201用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数。
管理器还用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；收发器还用于获取均衡训练目标阶段前向兼容的均衡超时时间；管理器还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；以及，所述管理器还用于在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
作为本申请的一个实施例，在完成本轮均衡训练目标阶段的均衡训练后，所述管理器1202还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的一个实施例，确定采用快速均衡训练模式之前，所述收发器1201还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；所述管理器1202还用于根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
五、本申请还提供了第二种均衡训练装置，该装置也可以用来执行前述提供的第一种的配置均衡超时时间的均衡训练方法和/或第二种均衡训练方法，因此本实施例所述的装置也可以参见前述方法实施例的相关限定和描述。需要说明的是，本实施例所述的装置可以为BIOS。
如图13所示，为本实施例提供的一种均衡训练装置1300，该装置包括获取单元1301，确定单元1302和配置单元1303。
其中，当所述均衡训练装置用来执行前述提供的第一种均衡训练方法时：
所述获取单元1301，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
相应的，所述确定单元1302，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间；
进一步地，所述配置单元1303，用于将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间；其中，N个速率阈值是预先确定的，且N是大于或等于0的整数，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。作为本申请的再一种实施例，所述确定单元1302具体用于在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最 小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
作为本申请的再一种实施例，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述确定单元1302还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
作为本申请的再一种实施例，所述获取单元1301还用于在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的再一种实施例，所述获取单元1301还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；所述确定单元还用于根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
其中，当所述均衡训练装置用来执行前述提供的第二种均衡训练方法时：
所述确定单元1302，用于判断是否采用快速均衡模式；
相应的，所述获取单元1301，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
所述配置单元1303，用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
进一步地，所述获取单元1301还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
所述配置单元1303还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；则在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
作为本申请的再一种实施例，所述获取单元1301还用于在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的再一种实施例，确定采用快速均衡训练模式之前，所述获取单元1301还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；所述确定单元1302还用于根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
六、本申请还提供了第三种均衡训练装置，该装置也可以用于执行前述提供的第一种 的配置均衡超时时间的均衡训练方法和/或第二种均衡训练方法，相应的，该装置也可以参见前述方法实施例的相关限定，相同或相似部分，本实施例不再赘述。
请参见附图14，为本实施例提供的均衡训练的装置1400，该装置1400包括中央处理器1401和存储器1402。其中，存储器1402用于存储代码，CPU1401用于执行存储器1402存储的代码以实现本实施例所述的装置的功能。应当知道的是，该CPU为应用该PCIe总线的处理器系统的CPU。
其中，当所述均衡训练装置用来执行前述提供的第一种均衡训练方法时：
具体的，存储器1402还用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系。CPU1401用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段。
CPU1401还用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
作为本申请的一种实施例，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
作为本申请的再一种实施例，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述CPU1401还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
作为本申请的再一种实施例，在完成本轮均衡训练目标阶段的均衡训练后，所述CPU1401还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的再一种实施例，所述CPU1401还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
其中，当所述均衡训练装置用来执行前述提供的第二种均衡训练方法时：
具体的，存储器1402还用于存储前一轮均衡训练目标阶段的均衡参数。CPU1401用于判断是否采用快速均衡模式，在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段。
CPU1401还用于获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；在所述本轮均衡训练目标 阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
作为本申请的一种实施例，在完成本轮均衡训练目标阶段的均衡训练后，所述CPU1401还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的一种实施例，确定采用快速均衡训练模式之前，所述CPU1401还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；以及根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
七、本申请还提供了一种芯片，该芯片为前述实施例所述的主芯片或从芯片。请参见附图15，为本申请提供的芯片1500，该芯片1500包括寄存器1501，收发器1502管理器1503。
其中，当所述芯片用来执行前述提供的第一种均衡训练方法时：
寄存器1501，用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系；
收发器1502，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
管理器1503，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
其中，当所述芯片用来执行前述提供的第二种均衡训练方法时：
寄存器1501，用于存储所述芯片本轮均衡训练目标阶段的均衡参数；
管理器1503，用于判断是否采用快速均衡模式；
收发器1502，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
管理器1503还用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
收发器1502还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
管理器1503还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；以及在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
进一步的，本申请实施例中，所述芯片具有打开和关闭部分均衡电路，在需要快速均衡过程的情况下关闭部分均衡电路的功能，比如关闭DFE或者部分CTLE，实现缩短均衡时间。其中，本申请实施例所述芯片自带管理软件，或者是符合标准的状态机。
八、请参阅附图16，为本申请提供的一种通信系统1600。该通信系统1600包括系统软件1601、主芯片1603和从芯片1604。其中，主芯片1603和从芯片1604之间通过PCIe/CCIX总线连通。需要说明的是，该系统软件1601可以为BIOS。
其中，当所述通信系统用来执行前述提供的第一种均衡训练方法时：
具体的，系统软件1601获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
需要说明的是，该通信系统还可以包括存储器1602。该存储器1602用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系。
进一步的，该存储器1602还用于存储本轮均衡训练目标阶段的均衡参数。作为本申请的一种实施例，所述系统软件1601还用于在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
作为本申请的一种实施例，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
作为本申请的一种实施例，所述获取主芯片与从芯片在均衡训练的目标阶段的训练速率之前，所述系统软件1601还用于确定不采用快速均衡训练模式；所述快速均衡训练模式是指根据上一轮均衡训练目标阶段的发送参数和接收参数，分别配置所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数的模式。
作为本申请的一种实施例，在完成本轮均衡训练目标阶段的均衡训练后，所述系统软件1601还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的一种实施例，所述系统软件1601还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
其中，当所述通信系统用来执行前述提供的第二种均衡训练方法时：
具体的，系统软件1601用于判断是否采用快速均衡模式，在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的 初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段，获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
需要说明的是，该通信系统还可以包括存储器1602。该存储器1602用于存储前一轮均衡训练目标阶段的均衡参数。
进一步的，该存储器1602还用于存储本轮均衡训练目标阶段的均衡参数。
进一步的，该存储器1602用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系。
作为本申请的一种实施例，在完成本轮均衡训练目标阶段的均衡训练后，所述系统软件1601还用于将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
作为本申请的一种实施例，确定采用快速均衡训练模式之前，所述系统软件1601还用于获取所述主芯片与所述从芯片用于进行所述均衡训练目标阶段的协商序列；以及根据所述协商序列指定的比特位值与均衡训练模式的对应关系，确定所述协商序列中指定的比特位值对应非快速均衡训练模式。
值得注意的是，上述的装置、芯片以及通信系统均可以参见方法实施例中的有关描述。由于本申请保护的主体之间具有单一性，因此这些主体的描述部分有很多相同或相似的部分，为了节约篇幅，本申请文件中对方法实施例做了全面丰富的描述，其他实施例均比较简约。
在一些可能的实施方式中，本申请实施例提供的均衡训练方法的各个方面还可以实现为一种程序产品的形式，其包括程序代码，当所述程序代码在计算机设备上运行时，所述程序代码用于使所述计算机设备执行本说明书中描述的根据本申请各种示例性实施方式的均衡训练方法中的步骤。
所述程序产品可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更本申请实施例一种实现方式中例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。
根据本申请的实施方式的用于均衡训练的程序产品，其可以采用便携式紧凑盘只读存储器(CD-ROM)并包括程序代码，并可以在服务器设备上运行。然而，本申请的程序产品不限于此，在本文件中，可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被消息传输、装置或者器件使用或者与其结合使用。
可读信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了可 读程序代码。这种传播的数据信号可以采用多种形式，包括——但不限于——电磁信号、光信号或上述的任意合适的组合。可读信号介质还可以是可读存储介质以外的任何可读介质，该可读介质可以发送、传播或者传输用于由周期网络动作系统、装置或者器件使用或者与其结合使用的程序。
可读介质上包含的程序代码可以用任何适当的介质传输，包括——但不限于——无线、有线、光缆、RF等，或者上述的任意合适的组合。
可以以一种或多种程序设计语言的任意组合来编写用于执行本申请操作的程序代码，所述程序设计语言包括面向对象的程序设计语言—诸如Java、C++等，还包括常规的过程式程序设计语言—诸如“C”语言或类似的程序设计语言。程序代码可以完全地在用户计算设备上执行、部分地在用户设备上执行、作为一个独立的软件包执行、部分在用户计算设备上部分在远程计算设备上执行、或者完全在远程计算设备或服务器上执行。在涉及远程计算设备的情形中，远程计算设备可以通过任意种类的网络——包括局域网(LAN)或广域网(WAN)—连接到用户计算设备，或者，可以连接到外部计算设备。
本申请实施例针对均衡训练方法还提供一种计算设备可读存储介质，即断电后内容不丢失。该存储介质中存储软件程序，包括程序代码，当所述程序代码在计算设备上运行时，该软件程序在被一个或多个处理器读取并执行时可实现本申请实施例上面任何一种均衡超时时间训练的方案。
以上参照示出根据本申请实施例的方法、装置(系统)和/或计算机程序产品的框图和/或流程图描述本申请。应理解，可以通过计算机程序指令来实现框图和/或流程图示图的一个块以及框图和/或流程图示图的块的组合。可以将这些计算机程序指令提供给通用计算机、专用计算机的处理器和/或其它可编程数据处理装置，以产生机器，使得经由计算机处理器和/或其它可编程数据处理装置执行的指令创建用于实现框图和/或流程图块中所指定的功能/动作的方法。
相应地，还可以用硬件和/或软件(包括固件、驻留软件、微码等)来实施本申请。更进一步地，本申请可以采取计算机可使用或计算机可读存储介质上的计算机程序产品的形式，其具有在介质中实现的计算机可使用或计算机可读程序代码，以由指令执行系统来使用或结合指令执行系统而使用。在本申请上下文中，计算机可使用或计算机可读介质可以是任意介质，其可以包含、存储、通信、传输、或传送程序，以由指令执行系统、装置或设备使用，或结合指令执行系统、装置或设备使用。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (33)

  1. 一种均衡训练方法，其特征在于，包括：
    获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
    确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
    则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
  2. 如权利要求1所述的方法，其特征在于，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
  3. 如权利要求1所述的方法，其特征在于，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
  4. 如权利要求1～3任一项所述的方法，其特征在于：所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  5. 一种均衡训练方法，其特征在于，包括：
    判断是否采用快速均衡模式，
    在确定采用快速均衡模式时，
    获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段，
    获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；
    在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
  6. 如权利要求5所述的方法，其特征在于，所述方法还包括：
    在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
  7. 如权利要求5或6所述的方法，其特征在于：所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  8. 一种均衡训练装置，其特征在于，包括：
    收发器，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
    管理器，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
  9. 如权利要求8所述的装置，其特征在于，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
  10. 如权利要求8所述的装置，其特征在于，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
  11. 如权利要求8～10任一项所述的装置，其特征在于，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  12. 一种均衡训练装置，其特征在于，包括：
    管理器，用于判断是否采用快速均衡模式；
    收发器，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
    管理器还用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
    收发器还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
    管理器还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；
    以及，所述管理器还用于在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
  13. 如权利要求12所述的装置，其特征在于，所述管理器还用于：
    在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
  14. 如权利要求12或13所述的装置，其特征在于，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  15. 一种均衡训练装置，其特征在于，包括：
    获取单元，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
    确定单元，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间；
    配置单元，用于将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间；
    其中，N个速率阈值是预先确定的，且N是大于或等于0的整数，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
    则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
  16. 如权利要求15所述的装置，其特征在于，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
  17. 如权利要求15所述的装置，其特征在于，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
  18. 如权利要求15～17任一项所述的装置，其特征在于，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  19. 一种均衡训练装置，其特征在于，包括：
    确定单元，用于判断是否采用快速均衡模式；
    获取单元，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
    配置单元，用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
    获取单元还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
    配置单元还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；用于在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
  20. 如权利要求19所述的装置，其特征在于，所述处理单元还用于：
    在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
  21. 如权利要求19或20所述的装置，其特征在于，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通，所述主芯片为根组件或交换芯片，所述从芯片是独立于所述主芯片的端点设备。
  22. 一种芯片，其特征在于，包括：
    寄存器，用于存储N+1个速率阈值区间与N+1个均衡超时时间的对应关系；
    收发器，用于获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
    管理器，用于确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
    则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
  23. 如权利要求22所述的芯片，其特征在于，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
  24. 如权利要求22所述的芯片，其特征在于，所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系预先存储在所述主芯片的寄存器内或所述从芯片的寄存器内。
  25. 一种芯片，其特征在于，包括：
    寄存器，用于存储所述芯片本轮均衡训练目标阶段的均衡参数；
    管理器，用于判断是否采用快速均衡模式；
    收发器，用于在确定采用快速均衡模式时，获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数；
    管理器还用于将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段；
    收发器还用于获取均衡训练目标阶段前向兼容的均衡超时时间；
    管理器还用于将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；以及在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
  26. 如权利要求25所述的芯片，其特征在于，所述管理器还用于：
    在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
  27. 一种通信系统，其特征在于，包括系统软件、主芯片和从芯片，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通；
    所述系统软件用于：
    获取主芯片与从芯片在均衡训练的目标阶段的训练速率，所述目标阶段是指第三阶段或第四阶段；
    确定所述目标阶段的训练速率所在的目标速率阈值区间，根据N+1个速率阈值区间与N+1个均衡超时时间的对应关系，确定所述目标速率阈值区间对应的目标均衡超时时间，并将所述目标均衡超时时间配置为所述目标阶段的均衡超时时间，N个速率阈值是预先确定的，且N是大于或等于0的整数，其中，所述速率阈值区间越大，则对应的所述均衡超时时间越大；
    则所述主芯片与所述从芯片在所述目标阶段的均衡超时时间内进行所述目标阶段的均衡训练。
  28. 如权利要求27所述的通信系统，其特征在于，还包括：
    存储器，用于存储所述N+1个速率阈值区间与所述N+1个均衡超时时间的对应关系。
  29. 如权利要求27或28所述的通信系统，其特征在于，在所述目标速率阈值区间为所述N+1个速率阈值区间中速率最小的阈值区间时，所述目标均衡超时时间为前向兼容的均衡超时时间。
  30. 一种通信系统，其特征在于，包括系统软件、主芯片和从芯片，所述主芯片和所述从芯片之间通过外围组件快速互连PCIe总线或者加速器的高速互连内存一致性CCIX总线连通；
    所述系统软件用于：
    判断是否采用快速均衡模式，
    在确定采用快速均衡模式时，
    获取主芯片与从芯片在前一轮均衡训练目标阶段的发送参数和接收参数，并将所述发送参数和所述接收参数分别配置为所述主芯片和所述从芯片在本轮均衡训练目标阶段的初始参数，均衡训练目标阶段是指均衡训练的第三阶段或第四阶段，
    获取均衡训练目标阶段前向兼容的均衡超时时间，并将所述前向兼容的均衡超时时间配置为本轮均衡训练目标阶段的均衡超时时间；
    在所述本轮均衡训练目标阶段的均衡超时时间内，利用所述主芯片和所述从芯片在所述本轮均衡训练目标阶段的初始参数进行均衡训练。
  31. 如权利要求30所述的通信系统，其特征在于，还包括：
    第一存储器，用于存储主芯片在所述前一轮均衡训练目标阶段的均衡参数；
    第二存储器，用于存储从芯片在所述前一轮均衡训练目标阶段的均衡参数。
  32. 如权利要求30或31所述的通信系统，其特征在于，所述系统软件还用于：
    在完成本轮均衡训练目标阶段的均衡训练后，将所述主芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内，并将所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述主芯片的寄存器内；
    或者，将所述主芯片以及所述从芯片在所述本轮均衡训练目标阶段的均衡参数存储在所述从芯片的寄存器内。
  33. 如权利要求30～32任一项所述的通信系统，其特征在于，还包括：
    第一存储器，用于存储主芯片在所述本轮均衡训练目标阶段的均衡参数； 第二存储器，用于存储从芯片在所述本轮均衡训练目标阶段的均衡参数。
PCT/CN2021/076554 2020-05-30 2021-02-10 一种均衡训练方法、装置及系统 WO2021244065A1 (zh)

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