WO2021242322A1 - Ensemble de puces empilées comprenant des connexions de liaison entre puces double face et ses procédés de formation - Google Patents

Ensemble de puces empilées comprenant des connexions de liaison entre puces double face et ses procédés de formation Download PDF

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Publication number
WO2021242322A1
WO2021242322A1 PCT/US2020/067424 US2020067424W WO2021242322A1 WO 2021242322 A1 WO2021242322 A1 WO 2021242322A1 US 2020067424 W US2020067424 W US 2020067424W WO 2021242322 A1 WO2021242322 A1 WO 2021242322A1
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WIPO (PCT)
Prior art keywords
die
bonding pads
memory
bonded
logic
Prior art date
Application number
PCT/US2020/067424
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English (en)
Inventor
Hardwell Chibvongodze
Zhixin Cui
Rajdeep Gautam
Fei Zhou
Raghuveer S. Makala
Rahul Sharangpani
Adarsh Rajashekhar
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Sandisk Technologies Llc
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Publication date
Priority claimed from US16/886,164 external-priority patent/US11335671B2/en
Priority claimed from US16/886,221 external-priority patent/US11309301B2/en
Application filed by Sandisk Technologies Llc filed Critical Sandisk Technologies Llc
Priority to CN202080081821.6A priority Critical patent/CN114830326A/zh
Publication of WO2021242322A1 publication Critical patent/WO2021242322A1/fr

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    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne de multiples unités liées, comprenant chacune une puce de face avant respective et une puce de face arrière. Les deux puces dans chaque unité liée peuvent être une puce mémoire et une puce logique configurée pour commander le fonctionnement d'éléments de mémoire dans la puce mémoire. En variante, les deux puces peuvent être des puces mémoire. Les multiples unités liées peuvent être fixées de telle sorte que des plots de liaison externes de face avant ont des surfaces physiquement mises à nu qui sont orientées vers le haut et des plots de liaison externes de face arrière de chaque unité liée ont des surfaces physiquement mises à nu qui sont orientées vers le bas. Un premier ensemble de fils de connexion peut connecter une paire respective de plots de connexion externes de face avant, et un second ensemble de fils de connexion peut connecter une paire respective de plots de liaison externes de face arrière.
PCT/US2020/067424 2020-05-28 2020-12-30 Ensemble de puces empilées comprenant des connexions de liaison entre puces double face et ses procédés de formation WO2021242322A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202080081821.6A CN114830326A (zh) 2020-05-28 2020-12-30 包括双面管芯间接合连接的堆叠式管芯组件及其形成方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US16/886,164 US11335671B2 (en) 2020-05-28 2020-05-28 Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same
US16/886,221 US11309301B2 (en) 2020-05-28 2020-05-28 Stacked die assembly including double-sided inter-die bonding connections and methods of forming the same
US16/886,164 2020-05-28
US16/886,221 2020-05-28

Publications (1)

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WO2021242322A1 true WO2021242322A1 (fr) 2021-12-02

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CN (1) CN114830326A (fr)
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190043836A1 (en) * 2018-06-18 2019-02-07 Intel Corporation Three-dimensional (3d) memory with shared control circuitry using wafer-to-wafer bonding
US20190051627A1 (en) * 2016-04-01 2019-02-14 Intel Corporation Wire bond connection with intermediate contact structure
US20190067248A1 (en) * 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190051627A1 (en) * 2016-04-01 2019-02-14 Intel Corporation Wire bond connection with intermediate contact structure
US20190067248A1 (en) * 2017-08-24 2019-02-28 Micron Technology, Inc. Semiconductor device having laterally offset stacked semiconductor dies
US20190043836A1 (en) * 2018-06-18 2019-02-07 Intel Corporation Three-dimensional (3d) memory with shared control circuitry using wafer-to-wafer bonding

Also Published As

Publication number Publication date
CN114830326A (zh) 2022-07-29

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