WO2021240657A1 - Power conversion device, motor drive device, blower, compressor, and air conditioner - Google Patents

Power conversion device, motor drive device, blower, compressor, and air conditioner Download PDF

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Publication number
WO2021240657A1
WO2021240657A1 PCT/JP2020/020782 JP2020020782W WO2021240657A1 WO 2021240657 A1 WO2021240657 A1 WO 2021240657A1 JP 2020020782 W JP2020020782 W JP 2020020782W WO 2021240657 A1 WO2021240657 A1 WO 2021240657A1
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WO
WIPO (PCT)
Prior art keywords
voltage
capacitor
switching
power conversion
duty ratio
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PCT/JP2020/020782
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French (fr)
Japanese (ja)
Inventor
浩一 有澤
基 豊田
貴昭 ▲高▼原
修 森
啓介 植村
貴彦 小林
Original Assignee
三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2022527330A priority Critical patent/JP7297157B2/en
Priority to PCT/JP2020/020782 priority patent/WO2021240657A1/en
Publication of WO2021240657A1 publication Critical patent/WO2021240657A1/en
Priority to JP2023018913A priority patent/JP7399331B2/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention includes a power converter that converts an AC voltage output from an AC power supply into a DC voltage, a motor drive device equipped with a power converter, a blower and a compressor provided with a motor drive device, and a blower or a compressor. Regarding the air conditioner equipped.
  • Patent Document 1 discloses a multi-level power conversion device.
  • the power conversion device described in Patent Document 1 includes a sub-converter composed of four switching elements and one capacitor between the reactor and the main converter.
  • a high power factor is provided while the capacitor voltage of the sub-converter is interposed between the output DC voltage and the input AC voltage. Power control is performed.
  • the applied voltage of the reactor is reduced as compared with the high power factor converter having a general bridgeless configuration, and the capacity and loss of the reactor are reduced as compared with the high power factor converter of the same specifications.
  • the present invention has been made in view of the above, and an object of the present invention is to reduce the switching loss of a switching element and the high frequency loss of a reactor to obtain a highly efficient power conversion device.
  • the power conversion device includes at least one reactor and a plurality of switching elements. Further, the power conversion device includes a first capacitor, a second capacitor provided between the reactor and the first capacitor, and a controller for controlling the conduction of the switching element.
  • the reactor, switching element, first capacitor and second capacitor are provided between the AC power supply and the DC load.
  • the power conversion device performs power conversion between the AC voltage of the AC power supply and the voltage of the first capacitor, which is the voltage of the first capacitor.
  • the controller controls the switching of the switching element by switching the switching element once or more and 20 times or less in a half cycle of the AC voltage.
  • the present invention by reducing the switching loss of the switching element and the high frequency loss of the reactor, it is possible to drive the power conversion device with high efficiency.
  • the block diagram used for explaining the operation of the addition / subtraction determination device shown in FIG. A block diagram showing an internal configuration of the controller according to the second embodiment.
  • FIG. 19 A block diagram showing a detailed configuration of the carrier wave generator shown in FIG. A block diagram showing a detailed configuration of the high power factor controller shown in FIG. A block diagram showing a detailed configuration of the gate signal generator shown in FIG.
  • FIG. 1 is a diagram showing a basic circuit configuration of the power conversion device 100 according to the first embodiment.
  • the power conversion device 100 according to the first embodiment includes a main circuit 110 and a controller 8.
  • the main circuit 110 is a power conversion circuit that converts AC power generated by AC voltage output from AC power source 1 into DC power generated by DC voltage and applies it to the load 7.
  • the load 7 is a DC load.
  • a DC load is a load that operates by being supplied with DC power.
  • a load 7 including an inverter that converts DC power into AC power is also included in the DC load referred to here.
  • the main circuit 110 includes a reactor 2 for limiting current, a subconverter 3, a main converter 5, and a smoothing capacitor 6, which is a first capacitor.
  • the smoothing capacitor 6 is connected in parallel to each of the main converter 5 and the load 7 between the main converter 5 and the load 7.
  • the subconverter 3 includes a first leg in which the switching element 3a and the switching element 3b are connected in series, a second leg in which the switching element 3c and the switching element 3d are connected in series, and a direct current which is a second capacitor. It has a capacitor 4. The first leg, the second leg and the DC capacitor 4 are connected in parallel with each other.
  • Examples of the DC capacitor 4 and the smoothing capacitor 6 are an aluminum electrolytic capacitor and a film capacitor.
  • the main converter 5 includes a third leg in which the diode 5a and the switching element 5b are connected in series, and a fourth leg in which the diode 5c and the switching element 5d are connected in series. Both the third leg and the fourth leg have a configuration in which the anode of each diode is connected to the switching element. The third and fourth legs are connected in parallel with each other.
  • the diodes 5a and 5c may be replaced with switching elements.
  • One end of the reactor 2 is connected to one of the AC power supplies 1, and the other end of the reactor 2 is connected to the midpoint of the first leg.
  • the midpoint of the first leg is the connection point between the switching element 3a and the switching element 3b. Also in other legs, the connection point between the switching elements and the connection point between the diode and the switching element are called "midpoints".
  • the midpoint of the third leg is connected to the midpoint of the second leg of the subconverter 3, and the midpoint of the fourth leg is connected to the other of the AC power supply 1.
  • switching elements 3a, 3b, 3c, 3d (hereinafter, appropriately referred to as “3a to 3d”) and the switching elements 5b, 5d is a metal oxide semiconductor field effect transistor (Metal) in which diodes are connected in antiparallel.
  • Metal Oxide Semiconductor (Field Effect Transistor: MOSFET).
  • the anti-parallel connection means that the drain of the MOSFET and the cathode of the diode are connected, and the source of the MOSFET and the anode of the diode are connected.
  • a parasitic diode contained in the MOSFET itself may be used. Parasitic diodes are also called body diodes.
  • an insulated gate bipolar transistor (IGBT) or a high electron mobility transistor (HEMT) may be used.
  • IGBT insulated gate bipolar transistor
  • HEMT high electron mobility transistor
  • a cascode type GaN (Gallium Nitride) -HEMT is suitable.
  • the smoothing capacitor 6 smoothes and holds the DC voltage converted by the main converter 5.
  • the polarity of the smoothing capacitor voltage Vdc which is the voltage held in the smoothing capacitor 6, is indicated by an arrow.
  • the tip of the arrow is the high potential side, and the opposite side is the low potential side. This definition is the same for the subconverter 3. Further, in the AC power supply 1, the case where the tip of the arrow has a high potential is defined as the positive electrode property, and the case where the opposite side has a high potential is defined as the negative electrode property.
  • the power conversion device 100 further includes voltage detectors 30, 31, 33, and a current detector 32.
  • the voltage detector 30 detects the smoothing capacitor voltage Vdc.
  • the smoothing capacitor voltage may be referred to as “first capacitor voltage”, and the voltage detector 30 may be referred to as “first voltage detector”.
  • the detected value of the smoothing capacitor voltage Vdc detected by the voltage detector 30 is input to the controller 8.
  • the voltage detector 31 detects the DC capacitor voltage Vsub, which is the voltage of the DC capacitor 4.
  • the DC capacitor voltage may be referred to as a "second capacitor voltage”
  • the voltage detector 31 may be referred to as a "second voltage detector”.
  • the detected value of the DC capacitor voltage Vsub detected by the voltage detector 31 is input to the controller 8.
  • the current detector 32 detects the alternating current iac flowing in the reactor 2.
  • the detected value of the alternating current iac detected by the current detector 32 is input to the controller 8.
  • the voltage detector 33 detects the AC voltage vac output by the AC power supply 1.
  • the voltage detector 33 may be referred to as a "third voltage detector”.
  • the detected value of the AC voltage vac detected by the voltage detector 33 is input to the controller 8.
  • the controller 8 has gate signals G3a, G3b, G3c, for controlling conduction of the switching elements 3a to 3d based on the detected values of the smoothing capacitor voltage Vdc, the DC capacitor voltage Vsub, the AC voltage vac, and the AC current iac.
  • G3d (hereinafter, appropriately referred to as “G3a to G3d”) and gate signals G5b and G5d for controlling the conduction of the switching elements 5b and 5d are generated.
  • Each of the sub-converter 3 and the main converter 5 has a gate drive circuit (not shown).
  • Each gate drive circuit of the subconverter 3 generates a drive pulse using the gate signals G3a to G3d output from the controller 8, and applies the generated drive pulse to the gate of the corresponding switching element to control the switching element.
  • Drive Each gate drive circuit of the main converter 5 generates a drive pulse using the gate signals G5b and G5d output from the controller 8, and applies the generated drive pulse to the gate of the corresponding switching element to control the switching element.
  • Drive
  • controller 8 The internal configuration of the controller 8 and the detailed operation of the controller 8 will be described later.
  • the processor 8a is an arithmetic unit such as an arithmetic unit, a microprocessor, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor).
  • arithmetic unit such as an arithmetic unit, a microprocessor, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor).
  • the memory 8b is a non-volatile or volatile semiconductor such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Project ROM), and EEPROM (registered trademark) (Electrically EPROM).
  • RAM Random Access Memory
  • ROM Read Only Memory
  • flash memory EPROM (Erasable Project ROM)
  • EEPROM registered trademark
  • the memory 8b stores a function of the controller 8 described later and a program for executing the function of the controller 8 described later.
  • the processor 8a exchanges necessary information via an interface including an analog-to-digital converter and a digital-to-digital converter (not shown), and the processor 8a executes a program stored in the memory 8b to perform necessary processing.
  • the calculation result by the processor 8a can be stored in the memory 8b.
  • the function of the controller 8 may be realized by using a processing circuit.
  • the processing circuit referred to here corresponds to a single circuit, a composite circuit, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof. Even in a configuration using a processing circuit, some processing in the controller 8 may be performed by the processor 8a.
  • the power conversion device 100 configured as described above performs power conversion between the AC voltage output by the AC power supply 1 and the first capacitor voltage which is the DC voltage held in the smoothing capacitor 6.
  • the function of this power conversion is carried out by the reactor 2, the sub-converter 3, and the main converter 5. Further, the power conversion device 100 controls the conduction of the switching elements 3a to 3d, 5b, 5d so that the second capacitor voltage held in the DC capacitor 4 matches the command voltage.
  • the controller 8 is responsible for this function.
  • FIG. 1 discloses a configuration in which one reactor 2 is connected to one side of the AC power supply 1, but the configuration is not limited to this configuration.
  • One reactor 2 may be connected to the other side of the AC power supply 1.
  • the two divided reactors 2 may be connected to both one side and the other side of the AC power supply 1.
  • the divided reactor 2 may be wound around the same core to form one magnetically coupled reactor, and may be connected to either one side or the other side of the AC power supply 1.
  • FIG. 2 is a diagram used to explain the concept of an operating region when the power conversion device 100 according to the first embodiment operates for boosting.
  • FIG. 3 is a diagram used to explain the concept of an operating region when the power conversion device 100 according to the first embodiment operates in a step-down operation.
  • FIG. 4 is a diagram showing the relationship between the operating region defined in FIGS. 2 and 3 and the operating state of the main circuit 110.
  • FIG. 5 is a diagram showing an example of a current path when the power conversion device 100 according to the first embodiment performs power conversion.
  • FIG. 5 is a diagram showing an example of a current path when the power conversion device 100 according to the first embodiment performs power conversion.
  • FIG. 6 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the first embodiment operates for boosting.
  • FIG. 7 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the first embodiment operates in a step-down operation.
  • FIG. 2 shows the voltage relationship when the smoothing capacitor voltage Vdc is larger than the absolute value
  • AC half cycle the smoothing capacitor voltage Vdc is larger than the absolute value
  • the mode in which the power conversion device 100 is stepped up is referred to as a “boosting operation mode”.
  • FIG. 3 shows the voltage relationship in the case where the smoothing capacitor voltage Vdc is smaller than the absolute value
  • the mode in which the power conversion device 100 is stepped down is referred to as a "stepping down operation mode".
  • . Further, ⁇ 1 and ⁇ 2 are phases in which Vdc
  • the operating region in which the phase ⁇ satisfies 0 ⁇ ⁇ ⁇ 1 and ⁇ 2 ⁇ ⁇ ⁇ is the operating region in which the relationship of
  • This operating area is defined as area 1.
  • the region of ⁇ 1 ⁇ ⁇ ⁇ ⁇ 2 in FIG. 2 and the operating region in FIG. 3 that satisfies ⁇ 1 ⁇ ⁇ ⁇ 1 and ⁇ 2 ⁇ ⁇ ⁇ 2 are operating regions in which Vsub ⁇
  • the operating region satisfying ⁇ 1 ⁇ ⁇ ⁇ ⁇ 2 is the operating region where Vsub ⁇ Vdc ⁇
  • FIG. 4 shows the reactor 2, the operating state of the DC capacitor 4, and the magnitude of the reactor applied voltage, which is the voltage applied to the reactor 2, corresponding to each operating region defined in FIGS. 2 and 3. ..
  • Excitation is an operation of accumulating electromagnetic energy in the reactor 2.
  • Reset is an operation of releasing the electromagnetic energy stored in the reactor 2.
  • FIG. 5 shows the current path when the reactor applied voltage becomes “vac-Vdc + Vsub” in the region 2 of FIG.
  • the arrow in FIG. 5 indicates the current path through which the alternating current iac flows.
  • the controller 8 controls the switching elements 3b, 3c, 5d to be on and the switching elements 3a, 3d, 5b to be off. Be controlled.
  • the current path of the alternating current iac can be shown as in FIG. The explanation here is omitted.
  • the lower part of FIG. 6 shows an example of a switching pattern in the boost operation mode.
  • An example of the switching pattern in the step-down operation mode is shown in the lower part of FIG. 7.
  • the smoothing capacitor voltage Vdc, the smoothing capacitor voltage command Vdc * which is the command value of the smoothing capacitor voltage Vdc, the DC capacitor voltage Vsub, and the DC which is the command value of the DC capacitor voltage Vsub are shown.
  • the switching pattern of the section A in the region 2 is the switching pattern at the time of the operation of FIG. Further, according to the switching pattern of the section B in the region 1 of FIG. 6, the operation in which the DC capacitor 4 shown in the region 1 of FIG. 4 is “through” and the reactor applied voltage is “vac” is performed.
  • FIG. 8 is a block diagram showing an internal configuration of the controller 8 according to the first embodiment.
  • the controller 8 includes an operating area determination device 9, a feed forward (FF) duty (Duty) (hereinafter referred to as “FF_Duty”) arithmetic unit 10, a DC capacitor voltage controller 11, and an addition / subtraction determination device 12. , The adder 12a, and the gate signal generator 13.
  • FF_Duty feed forward
  • FF_Duty feed forward
  • the adder 12a and the gate signal generator 13.
  • the operating area determination device 9 generates the area determination signal Sig_SP based on the detected values of the AC voltage vac, the smoothing capacitor voltage Vdc, and the DC capacitor voltage Vsub.
  • the area determination signal Sig_SP is a signal indicating in which region of FIG. 2 or FIG. 3 the operating state of the power conversion device 100 at the time of determination is.
  • the area determination signal Sig_SP generated by the operation area determination device 9 is input to the FF_Duty calculator 10, the addition / subtraction determination unit 12, and the gate signal generator 13. In each arithmetic unit, an arithmetic operation is performed according to the operating area.
  • the FF_Duty calculator 10 calculates the FF_Duty ratio D_Vdc based on the detected value of the AC voltage vac and the region determination signal Sig_SP.
  • the charging and discharging in the DC capacitor 4 are set to be the same number of times in each AC half cycle in each region shown in FIG. 2 or FIG. For example, in a certain AC half cycle, if the DC capacitor 4 is charged once, the DC capacitor 4 is also discharged once, and if the DC capacitor 4 is charged twice, the DC capacitor 4 is also discharged twice. Will be. In addition, "0" is also included in the charge / discharge count which is the total value of the charge count and the discharge count.
  • Charging and discharging in each operating area are set with reference to FIG. When the number of charge / discharge cycles is "0", "through” in FIG. 4 is selected. It is preferable, but not limited to, the set of “charging” and “discharging” of the same number of times is selected for each operating region. As long as it is within the period of the AC half cycle, the set of "charge” and “discharge” may be selected across the operating region.
  • the number of charge / discharge cycles can be determined based on the capacity of the DC capacitor 4, the withstand voltage of the main circuit component, and the power factor of the main circuit 110.
  • the switching loss can be reduced, but the responsiveness of the control deteriorates, resulting in a decrease in the power factor and an increase in the amount of voltage ripple. Therefore, in order to operate the power conversion device 100 stably, it is necessary to increase the capacity of the capacitor.
  • the capacitor capacity can be small and the responsiveness of control is improved, but the switching loss increases.
  • FIG. 9 is a block diagram showing a detailed configuration of the DC capacitor voltage controller 11 shown in FIG.
  • the DC capacitor voltage controller 11 includes a pretreatment device 11a and a sample hold device 11b.
  • the DC capacitor voltage controller 11 controls the DC capacitor voltage Vsub to follow the DC capacitor voltage command Vsub *, which is a command value of the DC capacitor voltage Vsub, based on the detected value of the DC capacitor voltage Vsub. Generate a command duty ratio D_Vsub.
  • the preprocessing device 11a proportionally controls the deviation between the DC capacitor voltage command Vsub * and the detected value of the DC capacitor voltage Vsub *, and divides the control value by the DC capacitor voltage command Vsub * to obtain a standardized duty ratio. Is calculated.
  • the sample hold device 11b updates the value of the output of the preprocessing device 11a in the sample hold cycle, and outputs the updated value to the addition / subtraction determination device 12 as the DC capacitor voltage command duty ratio D_Vsub.
  • the above-mentioned FF_Duty ratio may be referred to as a "first duty ratio”
  • the above-mentioned DC capacitor voltage command duty ratio may be referred to as a "second duty ratio”.
  • FIG. 10 is a time chart used for explaining the operation of the addition / subtraction determination device 12 shown in FIG.
  • FIG. 11 is a block diagram used for explaining the operation of the addition / subtraction determination device 12 shown in FIG.
  • the waveform in FIG. 10 is an example of the operation of region 2 in the positive half wave of the AC voltage vac.
  • FIG. 10 shows the waveforms of the alternating current iac and the waveforms of the gate signals G3a to G3d, G5b, and G5d for controlling each of the switching elements 3a to 3d, 5b, and 5d in order from the upper stage side. .. Further, the operating state of the DC capacitor 4 is shown in the lower part of FIG. 10. At times t0 to t1 and t2 to t3, the reactor 2 is excited, and at times t1 to t2 and t3 to t4, the excitation of the reactor 2 is reset. Therefore, in the example of FIG. 10, two pairs of switching control with excitation and reset as one pair, that is, four times of switching control are performed.
  • the DC capacitor voltage command duty ratio D_Vsub is input to the addition / subtraction determination device 12.
  • the addition / subtraction determination device 12 multiplies the DC capacitor voltage command duty ratio D_Vsub by a value of "1" or "-1" based on the area determination signal Sig_SP. That is, the addition / subtraction determination device 12 outputs a non-inverted control signal “+ D_Vsub” whose sign is not inverted or a control signal “ ⁇ D_Vsub” whose sign is inverted according to the area determination signal Sig_SP.
  • the upper part of FIG. 11 shows a situation in which a non-inverting control signal “+ D_Vsub” is output.
  • the lower part of FIG. 11 shows a situation in which the inverted control signal “ ⁇ D_Vsub” is output.
  • voltage control is performed by changing the time t1 and the time t3 in FIG.
  • the DC capacitor voltage Vsub becomes lower than the DC capacitor voltage command Vsub * due to disturbance, as shown in the upper part of FIG. 11, at time t1, the DC capacitor voltage with respect to the FF_Duty ratio D_Vdc in the adder 12a.
  • the command duty ratio D_Vsub is positively added.
  • the DC capacitor voltage command duty ratio D_Vsub is negatively added to the FF_Duty ratio D_Vdc in the adder 12a.
  • the DC capacitor voltage command duty ratio D_Vsub is negatively added to the FF_Duty ratio D_Vdc in the adder 12a. Will be done. Further, at time t3, the DC capacitor voltage command duty ratio D_Vsub is positively added to the FF_Duty ratio D_Vdc in the adder 12a. As a result, the operation of the main circuit 110 is such that the amount of charge to the DC capacitor 4 decreases and the amount of discharge increases.
  • the DC capacitor voltage Vsub is controlled according to the DC capacitor voltage command Vsub *.
  • the operation of the region 2 in the positive half wave of the AC voltage vac has been described in FIG. 10, the same operation is performed in the regions 1 and 3 in the positive half wave and the regions 1 to 3 in the negative half wave. It is possible to perform constant voltage control with.
  • the AC voltage vac, the area determination signal Sig_SP, and the total duty ratio D_total output from the adder 12a are input to the gate signal generator 13.
  • the gate signal generator 13 generates gate signals G3a to G3d, G5b, and G5d based on the AC voltage vac, the area determination signal Sig_SP, and the total duty ratio amount D_total output from the adder 12a.
  • the gate signals G3a to G3d, G5b, and G5d are applied to the switching elements 3a to 3d, 5b, and 5d, respectively, and the conduction of the switching elements 3a to 3d, 5b, and 5d is controlled.
  • the required power can be supplied to the load 7 through the control of the first capacitor voltage. Further, it is possible to control the voltage constant so that the second capacitor voltage follows the command value while controlling the first capacitor voltage.
  • the number of switchings in the AC half cycle is at most 20 times. That is, in the first embodiment, switching control is performed for the switching elements 3a to 3d, 5b, and 5d of the main circuit 110 by switching the number of times of switching to a dozen or less times in an AC half cycle.
  • the AC half cycle is 10 [ms].
  • the time required for one switching control is 0.5 [ms]. If 0.5 [ms] is set as one switching cycle, the switching frequency is 5 [kHz], and the switching frequency can be reduced as compared with the conventional case. As a result, the switching loss of the switching element and the high frequency loss of the reactor can be reduced, so that the power conversion device can be driven with higher efficiency than in the conventional case.
  • the DC capacitor 4 is charged and discharged at least once in the AC half cycle, but the present invention is not limited to this.
  • the main circuit 110 In the case of the boosting operation using only the region 1 and the region 2, it is possible to operate the main circuit 110 only by controlling the smoothing capacitor voltage Vdc, with the number of charge / discharge of the DC capacitor 4 in the AC half cycle being 0 times.
  • the FF_Duty calculator 10 only the “through” operation is selected in FIG. 4, and the FF_Duty ratio D_Vdc is calculated. Then, the gate signals G3a to G3d, G5b, and G5d are generated using the calculated FF_Duty ratio D_Vdc. In this case, feedback control of the DC capacitor voltage Vsub becomes unnecessary. Therefore, the number of switching times and the conduction time according to the operating conditions may be stored in the memory 8b of the controller 8 in advance, and the stored information may be read out to operate the main circuit 110.
  • the controller switches a plurality of switching elements once or more and a dozen times or less (less than 20 times) in a half cycle of the AC voltage. Switching control is performed with. As a result, the switching loss of the switching element and the high frequency loss of the reactor can be reduced, and the power conversion device can be driven with high efficiency. Further, in this switching control, the controller controls the charge amount and the discharge amount of the second capacitor in the half cycle of the AC voltage to match the second capacitor voltage with the command value of the second capacitor voltage. Take control. By this control, the power factor of the main circuit operation can be increased while reducing the switching loss of the switching element and the high frequency loss of the reactor. As a result, the power conversion device can be driven with high efficiency.
  • the controller can perform switching control while changing the charging time for charging the second capacitor and the discharging time for discharging the second capacitor. Since this control can be performed without using carrier waves, it is possible to easily carry out high-efficiency driving of the power conversion device.
  • the controller charges and discharges the second capacitor once or more within a half cycle of the AC voltage, and the number of times of charging and the number of times of discharging are within the half cycle of the AC voltage. It is preferable to perform switching control so that they are equal to each other. As a result, constant voltage control that causes the second capacitor voltage to follow the command value can be reliably performed.
  • the controller preferably adds or subtracts the second duty ratio to the first duty ratio so that the total amount of duty ratios in the half cycle of the AC voltage is kept constant. As a result, it is possible to carry out both the control of the first capacitor voltage and the constant voltage control for making the second capacitor voltage follow the command value.
  • FIG. 12 is a block diagram showing an internal configuration of the controller 8A according to the second embodiment.
  • the FF_Duty calculator 10 is replaced with the high power factor controller 17, and the gate signal generator 13 is the gate signal. It has been replaced by the generator 18.
  • a carrier wave generator 16 has been added.
  • the other configurations are the same as or equivalent to the configurations shown in FIG. 8, and the same or equivalent components are designated by the same reference numerals, and duplicate explanations are omitted.
  • the basic circuit configuration is the same as or equivalent to that in FIG.
  • FIG. 13 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the second embodiment operates for boosting.
  • FIG. 14 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the second embodiment operates in a step-down operation.
  • the concept of the operating area described in the first embodiment is the same in the second embodiment.
  • the power conversion device 100 according to the second embodiment performs switching control for the switching elements 3a to 3d, 5b, 5d while changing the carrier frequency for each operating region. When the carrier frequency is changed, so is the switching frequency.
  • the period in which the same switching frequency is maintained is defined as the "first switching period".
  • the DC capacitor 4 is operated so as to be charged and discharged once or more in each operating region.
  • the width of each operating region is determined by the magnitude relationship between the smoothing capacitor voltage Vdc and the DC capacitor voltage Vsub and the AC voltage vac, the width of each operating region varies. Therefore, in a region with a narrow period, power factor control is performed by switching control at a higher frequency, and in a region with a wide period, power factor control is performed by switching control at a lower frequency.
  • the number of switching times is at most 20 times, which is significantly reduced as compared with the conventional method. Therefore, it is possible to significantly reduce the loss as compared with the conventional case, and it is possible to drive the power conversion device with high efficiency.
  • the operating area increases as compared with the case of the step-up operation shown in FIG. Therefore, if the number of switchings for each operating region is the same, the number of switchings in the AC half cycle is larger in the step-down operation. Further, the step-down operation is different from the step-up operation, and it is necessary to operate while charging / discharging the DC capacitor 4. Therefore, in the region 3, switching control for charging / discharging is always performed. This point is the same in the first embodiment. As shown in region 3 of FIG. 4, there is no "through" operation in region 3, and either discharge or charge operation is selected.
  • FIG. 15 is a block diagram showing a detailed configuration of the carrier wave generator 16 shown in FIG.
  • the carrier wave generator 16 includes a switching frequency calculator 20 and a frequency converter 21.
  • the switching frequency calculator 20 calculates the time of each operating region in the AC half cycle based on the AC voltage vac, the DC capacitor voltage Vsub, and the smoothing capacitor voltage Vdc. Further, the switching frequency calculator 20 calculates a switching cycle which is the reciprocal of the switching frequency based on the number of times of charging / discharging of the DC capacitor 4 set by the user.
  • the frequency converter 21 generates a carrier wave based on the switching cycle calculated by the switching frequency calculator 20 and the region determination signal Sig_SP.
  • the carrier wave may be a sawtooth wave or a triangular wave.
  • the switching frequency calculator 20 includes a first time calculator 20a, a second time calculator 20c, a third time calculator 20e, a fourth time calculator 20i, and the like.
  • the dividers 20b, 20d, 20g, 20j and the adder 20h are provided.
  • the first time calculator 20a calculates the time Rt1 in the region 1 by dividing the DC capacitor voltage Vsub by the AC voltage vac, converting it into time by an inverse trigonometric function, and further dividing by the angular frequency 2 ⁇ fac.
  • the time Rt1 is the time corresponding to the phase difference from 0 to ⁇ 1 in FIG. fac is the frequency of the AC voltage vac.
  • the frequency of the AC voltage vac is referred to as "AC voltage frequency”.
  • the switching frequency calculator 20 calculates the switching cycle Tsw_1 of the region 1 by dividing the time Rt1 by the number of charge / discharge cycles in the divider 20b.
  • the second time calculator 20c calculates the time Rt2b of the region 2 by subtracting the double value of the time Rt1 of the region 1 from the value obtained by dividing the value of 1 by the double value of the AC voltage frequency fac.
  • the double value of the time Rt1 is the time corresponding to the phase difference obtained by adding the phase difference from 0 to ⁇ 1 in FIG. 2 and the phase difference from ⁇ 2 to ⁇ .
  • the value obtained by dividing the value of 1 by a double value of the AC voltage frequency fac is the time corresponding to the phase difference from 0 to ⁇ in FIG. Therefore, by the processing of the second time calculator 20c, the time Rt2b of the region 2 corresponding to the phase difference from ⁇ 1 to ⁇ 2 in FIG. 2 is calculated.
  • the switching frequency calculator 20 calculates the switching cycle Tsw_2b of the region 2 in the boost operation mode by dividing the time Rt2b by the number of charges and discharges in the divider 20d.
  • the third time calculator 20e divides the smoothing capacitor voltage Vdc by the AC voltage vac, converts it into time by an inverse trigonometric function, further divides it by the angular frequency 2 ⁇ fac, and further subtracts the time Rt1 in the region 1.
  • the time Rt2s of the region 2 is calculated.
  • the value divided by the angular frequency 2 ⁇ fac is the time corresponding to the phase difference from 0 to ⁇ 1 in FIG. Therefore, the time Rt2s of the region 2 can be calculated by subtracting the time Rt1 of the region 1 from the value divided by the angular frequency 2 ⁇ fac.
  • the switching frequency calculator 20 calculates the switching cycle Tsw_2s of the region 2 in the step-down operation mode by dividing the time Rt2s by the number of charges and discharges in the divider 20g.
  • the adder 20h recalculates the time corresponding to the phase difference from 0 to ⁇ 1 in FIG. 3 by adding the time Rt2s in the region 2 and the time Rt1 in the region 1.
  • the fourth time calculator 20i calculates the time Rt3 in the region 3 by subtracting the double value of the output of the adder 20h from the value obtained by dividing the value of 1 by the double value of the AC voltage frequency fac.
  • the double value of the output of the adder 20h is the time corresponding to the phase difference obtained by adding the phase difference from 0 to ⁇ 1 in FIG. 3 and the phase difference from ⁇ 2 to ⁇ .
  • the value obtained by dividing the value of 1 by a double value of the AC voltage frequency fac is the time corresponding to the phase difference from 0 to ⁇ in FIG. Therefore, by the processing of the fourth time calculator 20i, the time Rt3 of the region 3 corresponding to the phase difference from ⁇ 1 to ⁇ 2 in FIG. 3 is calculated.
  • the switching frequency calculator 20 calculates the switching cycle Tsw_3 of the region 3 in the step-down operation mode by dividing the time Rt3 by the number of charges and discharges in the divider 20j.
  • the switching frequency calculator 20 outputs the calculated switching cycles Tsw_1, Tsw_2b, Tsw_2s, and Tsw_3 to the frequency converter 21, but is not limited to this.
  • the reciprocals of the switching cycles Tsw_1, Tsw_2b, Tsw_2s, and Tsw_3 may be calculated, and each calculated value may be output to the frequency converter 21 as the switching frequency corresponding to the operating region.
  • the switching cycles Tsw_1, Tsw_2b, Tsw_2s, and Tsw_3 are used as switching frequency information
  • the times Rt1, Rt2b, Rt2s, and Rt3 can be regarded as reference switching frequencies for calculating each switching frequency.
  • the switching frequency calculator 20 shown in FIG. 15 the front stage portion calculates the reference switching frequency corresponding to the operating region, and the rear stage portion determines the reference switching frequency and the number of times of charging / discharging of the second capacitor. It is configured to calculate the switching frequency based on it.
  • the frequency converter 21 generates a carrier wave corresponding to the operating region based on the switching cycles Tsw_1, Tsw_2b, Tsw_2s, Tsw_3 calculated by the switching frequency calculator 20 and the region determination signal Sig_SP, and is a gate signal generator. Output to 18.
  • the number of charge / discharge cycles is set by an integer including 0 so as to be 1 or more in an AC half cycle.
  • the number of charge / discharge cycles can be determined based on the capacity of the DC capacitor 4, the withstand voltage of the main circuit component, and the power factor of the main circuit 110.
  • the switching loss can be reduced, but the responsiveness of the control deteriorates, resulting in a decrease in the power factor and an increase in the amount of voltage ripple. Therefore, in order to operate the power conversion device 100 stably, it is necessary to increase the capacity of the capacitor.
  • the capacitor capacity can be small and the responsiveness of control is improved, but the switching loss increases.
  • FIG. 16 is a block diagram showing a detailed configuration of the high power factor controller 17 shown in FIG.
  • the high power factor controller 17 includes a current command calculator 17a, a current controller 17b, an FF_Duty calculator 17c, and an adder 17d.
  • the high power factor controller 17 commands the smoothing capacitor voltage Vdc while controlling the power factor of the main circuit 110 to approach 1 based on the detected values of the AC voltage vac, the smoothing capacitor voltage Vdc, and the AC current iac.
  • a control signal D_PFC that controls to follow the value is generated.
  • the current command calculator 17a calculates the current command amplitude Iac * by controlling the deviation between the smoothing capacitor voltage command Vdc * and the detected value of the smoothing capacitor voltage Vdc by proportional integral (PI).
  • the current command calculator 17a multiplies the current command amplitude Iac * by the AC voltage vac generated by the phase-locked loop (PLL) control and the sinusoidal signal Sin ( ⁇ t) having the same phase, and the AC current command iac. * Is calculated.
  • the current controller 17b performs PI control of the deviation between the AC current command iac * and the AC current iac, and calculates the standardized control duty ratio D_PFC1 by dividing the control value by the DC capacitor voltage command Vsub *.
  • the adder 17d adds the control duty ratio D_PFC1 and the FF_Duty ratio D_PFC_FF calculated by the FF_Duty calculator 17c, and outputs the added value as the FF_Duty ratio D_PFC for high power rate control to the adder 12a in FIG. do.
  • the control duty ratio D_PFC1 is switched according to the operating region. Therefore, by inserting the FF control, the current fluctuation at the time of switching the control can be suppressed.
  • the FF_Duty ratio D_PFC_FF for FF control calculates the theoretical duty ratio so that the amount of increase / decrease in the AC current iac due to the excitation and reset of the reactor 2 becomes equal.
  • the method for calculating the theoretical duty ratio is described in detail in Patent Document 1 described above, so please refer to the description. The contents of the description are incorporated in the present specification and form a part of the present specification. The method for calculating the theoretical duty ratio is not limited to the contents described in the publication, and any method may be used as long as the theoretical duty ratio can be obtained.
  • a set of excitation and reset is selected so that the charging and discharging of the DC capacitor 4 have the same number of times in the AC half cycle.
  • the FF_Duty calculator 17c calculates the theoretical duty ratio based on information about the selected excitation and reset pairs.
  • FIG. 17 is a block diagram showing a detailed configuration of the gate signal generator 18 shown in FIG.
  • the gate signal generator 18 includes a comparison unit 18a and a pulse calculator 18b. Further, the comparison unit 18a includes a first comparator 18a1, a multiplier 18a2, and a second comparator 18a3.
  • the total duty ratio amount D_total is input to the + terminal of the second comparator 18a3 via the multiplier 18a2, and the carrier wave is input to the-terminal of the second comparator 18a3.
  • the total duty ratio D_total and the amplitude value of the carrier wave are compared, and if the total duty ratio D_total is larger than the amplitude value of the carrier wave, an on signal for conducting the switching element is generated. ..
  • the pulse calculator 18b generates gate signals G3a to G3d, G5b, and G5d using the on signal output from the comparison unit 18a and the region determination signal Sig_SP.
  • the gate signals G3a to G3d, G5b, and G5d are applied to the switching elements 3a to 3d, 5b, and 5d, respectively, and the conduction of the switching elements 3a to 3d, 5b, and 5d is controlled.
  • a first comparator 18a1 and a multiplier 18a2 are provided in order to realize control when the number of charge / discharge cycles is 0.
  • the output of the first comparator 18a1 becomes 0 and the output of the multiplier 18a2 also becomes 0. Therefore, the total duty ratio input to the second comparator 18a3 is D_total. Is also 0.
  • the configuration of FIG. 17 is an example and is not limited to these configurations. For example, an on-signal for conducting the switching element may be generated when the total duty ratio D_total is smaller than the amplitude value of the carrier wave.
  • the required power can be supplied to the load 7 through the control of the first capacitor voltage. Further, it is possible to control the voltage constant so that the second capacitor voltage follows the command value while controlling the first capacitor voltage.
  • the number of switchings in the AC half cycle is at most 20 times. Therefore, in the second embodiment, the first capacitor voltage is controlled by the switching control of the switching elements 3a to 3d, 5b, 5d of the main circuit 110 by the number of switchings of 10 or less times in the AC voltage half cycle. It is possible to carry out both constant voltage control that causes the second capacitor voltage to follow the command value.
  • the controller responds to the magnitude relationship between the detected values of the first and second capacitor voltages and the detected values of the AC voltage.
  • the operating region is determined, and switching control is performed while changing the switching frequency for each operating region based on the detected values of the first and second capacitor voltages and the detected value of the AC voltage.
  • the controller charges and discharges the second capacitor once or more in the first switching period, which is the period in which the same switching frequency is maintained, and the number of times of charging. It is preferable to perform switching control so that the number of discharges becomes equal within the first switching period. As a result, constant voltage control that causes the second capacitor voltage to follow the command value can be reliably performed.
  • the controller may add or subtract the second duty ratio to the first duty ratio so that the total amount of duty ratios in the first switching period is kept constant. As a result, it is possible to carry out both the control of the first capacitor voltage and the constant voltage control for making the second capacitor voltage follow the command value.
  • the controller refers from the first phase at which the AC voltage and the second capacitor voltage intersect and the second phase at which the AC voltage and the first capacitor voltage intersect for each operating region. Calculate the switching frequency.
  • the controller may calculate the switching frequency based on the predetermined number of times of charging and discharging of the second capacitor and the reference switching frequency obtained by the calculation.
  • the controller has a theory that the amount of increase / decrease in the alternating current due to the excitation and reset of the reactor becomes equal to the feedback duty ratio for controlling the second capacitor voltage within the first switching period.
  • a duty ratio may be added. This makes it possible to smoothly switch between operating areas.
  • FIG. 18 is a diagram showing a basic circuit configuration of the power conversion device 100A according to the third embodiment.
  • the diode bridge 24 is provided on the AC power supply 1 side of the reactor 2 in the configuration of the power conversion device 100 according to the first embodiment shown in FIG.
  • the switching elements 3a and 3d provided in the subconverter 3 of the main circuit 110 are replaced with the diodes 3a'and 3d', respectively.
  • the switching element 5d provided in the main converter 5 of the main circuit 110 is replaced with the diode 5d'.
  • the other configurations are the same as or equivalent to the configurations shown in FIG. 1, and the same or equivalent components are designated by the same reference numerals, and duplicate explanations are omitted.
  • a voltage waveform rectified by a diode bridge 24 is applied to the subconverter 3. Therefore, the operation of the controller 8 in the third embodiment has no negative half-wave operation and is only a positive half-wave operation. Therefore, the function of the controller 8 in the first embodiment or the second embodiment can be used as it is.
  • the positive half-wave operation is the same as that of the first and second embodiments, and the description thereof is omitted here.
  • the number of switching elements can be reduced as compared with the first embodiment and the second embodiment, so that the switching loss can be reduced. Further, since the diode can be obtained at a lower cost than the switching element, the cost of the device can be reduced.
  • the operation of the controller 8 is only a positive half wave operation. Therefore, the function of the controller 8 can be simplified as compared with the first embodiment and the second embodiment. This makes it possible to reduce the cost of the device.
  • FIG. 19 is a diagram showing a configuration example of the motor drive device 150 according to the fourth embodiment.
  • the inverter 7a and the motor 7b are added to the configuration of the power conversion device 100 shown in FIG.
  • a motor 7b is connected to the output side of the inverter 7a.
  • the motor 7b is an example of a load device.
  • the inverter 7a drives the motor 7b by converting the DC power stored in the smoothing capacitor 6 into AC power and supplying the converted AC power to the motor 7b.
  • the motor drive device 150 shown in FIG. 19 can be applied to products such as blowers, compressors and air conditioners.
  • the power conversion device 100 according to the first embodiment is applied to configure the motor drive device 150, but the present invention is not limited to this.
  • the power conversion device 100 according to the first embodiment the power conversion device 100 according to the second embodiment or the power conversion device 100A according to the third embodiment may be used.
  • FIG. 20 is a diagram showing an example in which the motor drive device 150 shown in FIG. 19 is applied to an air conditioner.
  • a motor 7b is connected to the output side of the motor drive device 150, and the motor 7b is connected to the compression element 504.
  • the compressor 505 includes a motor 7b and a compression element 504.
  • the refrigeration cycle unit 506 is configured to include a four-way valve 506a, an indoor heat exchanger 506b, an expansion valve 506c, and an outdoor heat exchanger 506d.
  • the flow path of the refrigerant circulating inside the air conditioner is from the compression element 504 via the four-way valve 506a, the indoor heat exchanger 506b, the expansion valve 506c, the outdoor heat exchanger 506d, and again via the four-way valve 506a. , It is configured to return to the compression element 504.
  • the motor drive device 150 receives electric power from the AC power supply 1 and rotates the motor 7b.
  • the compression element 504 can execute the compression operation of the refrigerant by rotating the motor 7b, and the refrigerant can be circulated inside the refrigeration cycle unit 506.
  • the motor drive device 150 according to the fourth embodiment is configured to include the power conversion device according to the first to third embodiments. Thereby, in the products such as the blower, the compressor and the air conditioner to which the motor drive device according to the fourth embodiment is applied, the effects described in the first to third embodiments can be obtained.

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Abstract

A power conversion device (100) is provided with: a reactor (2); switching elements (3a-3d, 5b, 5d); a smoothing capacitor (6); a DC capacitor (4) provided between the reactor (2) and the smoothing capacitor (6); and a controller (8) for controlling the conduction of the switching elements (3a-3d, 5b, 5d). The power conversion device (100) performs power conversion between AC voltage and smoothing capacitor voltage. The controller (8) performs switching control of the switching elements (3a-3d, 5b, 5d) with the number of switching times of 1 to 20, inclusive, within a half cycle of the AC voltage.

Description

電力変換装置、モータ駆動装置、送風機、圧縮機及び空気調和機Power converters, motor drives, blowers, compressors and air conditioners
　本発明は、交流電源から出力される交流電圧を直流電圧に変換する電力変換装置、電力変換装置を備えたモータ駆動装置、モータ駆動装置を備えた送風機及び圧縮機、並びに、送風機又は圧縮機を備えた空気調和機に関する。 The present invention includes a power converter that converts an AC voltage output from an AC power supply into a DC voltage, a motor drive device equipped with a power converter, a blower and a compressor provided with a motor drive device, and a blower or a compressor. Regarding the air conditioner equipped.
　交流電源に接続され、力率改善を行いながら交流電力を直流電力に変換する電力変換装置においては、装置の高電力密度化が要望されている。高電力密度化には、装置の低損失化及び小型化が必須である。低損失化及び小型化には、装置の構成要素のうちで、体積割合の高いリアクトルの低損失化及び小型化が重要な課題となる。一般的に、リアクトルの小型化には、回路を高周波化し、必要容量を下げることが考えられる。一方、回路の高周波化には、リアクトル及びスイッチング素子の損失が増加するため、変換効率が低下し、冷却器が大型化するという課題がある。 In a power conversion device that is connected to an AC power supply and converts AC power into DC power while improving the power factor, there is a demand for higher power density of the device. In order to increase the power density, it is essential to reduce the loss and size of the device. In order to reduce the loss and size, it is important to reduce the loss and size of the reactor having a high volume ratio among the components of the device. Generally, in order to reduce the size of the reactor, it is conceivable to increase the frequency of the circuit and reduce the required capacity. On the other hand, increasing the frequency of the circuit increases the loss of the reactor and the switching element, so that there is a problem that the conversion efficiency is lowered and the size of the cooler is increased.
　上記の課題に対して、下記特許文献１には、マルチレベル方式の電力変換装置が開示されている。特許文献１に記載の電力変換装置は、リアクトルとメインコンバータとの間に、４つのスイッチング素子と１つのコンデンサとで構成されたサブコンバータを備えている。特許文献１では、メインコンバータ及びサブコンバータのスイッチング素子をそれぞれ半周期ずれたスイッチング周期で駆動することで、出力直流電圧と入力交流電圧との間にサブコンバータのコンデンサ電圧を介在させながら高力率に電力制御を行う。これにより、一般的なブリッジレス構成の高力率コンバータよりもリアクトルの印加電圧が低減され、同仕様の高力率コンバータに比べて、リアクトルの容量低減と損失低減とを実現している。 For the above problem, Patent Document 1 below discloses a multi-level power conversion device. The power conversion device described in Patent Document 1 includes a sub-converter composed of four switching elements and one capacitor between the reactor and the main converter. In Patent Document 1, by driving the switching elements of the main converter and the sub-converter with switching cycles shifted by half a cycle, a high power factor is provided while the capacitor voltage of the sub-converter is interposed between the output DC voltage and the input AC voltage. Power control is performed. As a result, the applied voltage of the reactor is reduced as compared with the high power factor converter having a general bridgeless configuration, and the capacity and loss of the reactor are reduced as compared with the high power factor converter of the same specifications.
特許第６１２９４５０号公報Japanese Patent No. 6129450
　しかしながら、特許文献１では、回路の駆動周波数は、何れの動作条件においても、常に１０ｋＨｚ以上である。このため、スイッチング素子のスイッチング損失、及びリアクトルの高周波損失が大きく、電力変換装置の変換効率が低くなってしまうという課題がある。 However, in Patent Document 1, the drive frequency of the circuit is always 10 kHz or more under any operating condition. Therefore, there is a problem that the switching loss of the switching element and the high frequency loss of the reactor are large, and the conversion efficiency of the power conversion device is lowered.
　本発明は、上記に鑑みてなされたものであって、スイッチング素子のスイッチング損失、及びリアクトルの高周波損失を低減して、高効率な電力変換装置を得ることを目的とする。 The present invention has been made in view of the above, and an object of the present invention is to reduce the switching loss of a switching element and the high frequency loss of a reactor to obtain a highly efficient power conversion device.
　上述した課題を解決し、目的を達成するため、本発明に係る電力変換装置は、少なくとも１つのリアクトルと、複数のスイッチング素子と、を備える。また、電力変換装置は、第１のコンデンサと、リアクトルと第１のコンデンサとの間に設けられる第２のコンデンサと、スイッチング素子の導通を制御する制御器とを備える。リアクトル、スイッチング素子、第１のコンデンサ及び第２のコンデンサは、交流電源と直流負荷との間に設けられる。電力変換装置は、交流電源の交流電圧と第１のコンデンサの電圧である第１のコンデンサ電圧との間で電力変換を行う。制御器は、スイッチング素子を交流電圧の半周期で１回以上、２０回以下のスイッチング回数でスイッチング制御する。 In order to solve the above-mentioned problems and achieve the object, the power conversion device according to the present invention includes at least one reactor and a plurality of switching elements. Further, the power conversion device includes a first capacitor, a second capacitor provided between the reactor and the first capacitor, and a controller for controlling the conduction of the switching element. The reactor, switching element, first capacitor and second capacitor are provided between the AC power supply and the DC load. The power conversion device performs power conversion between the AC voltage of the AC power supply and the voltage of the first capacitor, which is the voltage of the first capacitor. The controller controls the switching of the switching element by switching the switching element once or more and 20 times or less in a half cycle of the AC voltage.
　本発明によれば、スイッチング素子のスイッチング損失、及びリアクトルの高周波損失を低減することにより、電力変換装置を高効率に駆動することができるという効果を奏する。 According to the present invention, by reducing the switching loss of the switching element and the high frequency loss of the reactor, it is possible to drive the power conversion device with high efficiency.
実施の形態１に係る電力変換装置の基本回路構成を示す図The figure which shows the basic circuit structure of the power conversion apparatus which concerns on Embodiment 1. 実施の形態１に係る電力変換装置が昇圧動作するときの動作領域の概念の説明に使用する図The figure used for explaining the concept of the operating area at the time of the boosting operation of the power conversion apparatus which concerns on Embodiment 1. 実施の形態１に係る電力変換装置が降圧動作するときの動作領域の概念の説明に使用する図The figure used for explaining the concept of the operation area at the time of the step-down operation of the power conversion apparatus which concerns on Embodiment 1. 図２及び図３で定義される動作領域と主回路の動作状態との関係を示す図The figure which shows the relationship between the operation area defined in FIGS. 2 and 3 and the operation state of a main circuit. 実施の形態１に係る電力変換装置が電力変換を行うときの電流経路の例を示す図The figure which shows the example of the current path when the power conversion apparatus which concerns on Embodiment 1 performs power conversion. 実施の形態１に係る電力変換装置が昇圧動作するときのスイッチングパターンの例を示す図The figure which shows the example of the switching pattern when the power conversion apparatus which concerns on Embodiment 1 performs a step-up operation. 実施の形態１に係る電力変換装置が降圧動作するときのスイッチングパターンの例を示す図The figure which shows the example of the switching pattern at the time of the step-down operation of the power conversion apparatus which concerns on Embodiment 1. 実施の形態１における制御器の内部構成を示すブロック図A block diagram showing an internal configuration of a controller according to the first embodiment. 図８に示す直流コンデンサ電圧制御器の詳細構成を示すブロック図A block diagram showing a detailed configuration of the DC capacitor voltage controller shown in FIG. 図８に示す加減算判定器の動作説明に用いるタイムチャートTime chart used to explain the operation of the addition / subtraction judgment device shown in FIG. 図８に示す加減算判定器の動作説明に用いるブロック図The block diagram used for explaining the operation of the addition / subtraction determination device shown in FIG. 実施の形態２における制御器の内部構成を示すブロック図A block diagram showing an internal configuration of the controller according to the second embodiment. 実施の形態２に係る電力変換装置が昇圧動作するときのスイッチングパターンの例を示す図The figure which shows the example of the switching pattern when the power conversion apparatus which concerns on Embodiment 2 performs a step-up operation. 実施の形態２に係る電力変換装置が降圧動作するときのスイッチングパターンの例を示す図The figure which shows the example of the switching pattern at the time of the step-down operation of the power conversion apparatus which concerns on Embodiment 2. 図１２に示すキャリア波生成器の詳細構成を示すブロック図A block diagram showing a detailed configuration of the carrier wave generator shown in FIG. 図１２に示す高力率制御器の詳細構成を示すブロック図A block diagram showing a detailed configuration of the high power factor controller shown in FIG. 図１２に示すゲート信号生成器の詳細構成を示すブロック図A block diagram showing a detailed configuration of the gate signal generator shown in FIG. 実施の形態３に係る電力変換装置の基本回路構成を示す図The figure which shows the basic circuit composition of the power conversion apparatus which concerns on Embodiment 3. 実施の形態４に係るモータ駆動装置の構成例を示す図The figure which shows the structural example of the motor drive device which concerns on Embodiment 4. 図１９に示すモータ駆動装置を空気調和機に適用した例を示す図The figure which shows the example which applied the motor drive device shown in FIG. 19 to an air conditioner.
　以下に添付図面を参照し、本発明の実施の形態に係る電力変換装置、モータ駆動装置、送風機、圧縮機及び空気調和機について説明する。なお、以下に示す実施の形態により本発明が限定されるものではない。また、以下では、電気的な接続を単に「接続」と称して説明する。 The power conversion device, motor drive device, blower, compressor, and air conditioner according to the embodiment of the present invention will be described below with reference to the accompanying drawings. The present invention is not limited to the embodiments shown below. Further, in the following, the electrical connection will be described simply as "connection".
実施の形態１．
　図１は、実施の形態１に係る電力変換装置１００の基本回路構成を示す図である。実施の形態１に係る電力変換装置１００は、主回路１１０と、制御器８とを備える。主回路１１０は、交流電源１から出力される交流電圧による交流電力を直流電圧による直流電力に変換して負荷７に印加する電力変換回路である。負荷７は、直流負荷である。直流負荷は、直流電力の供給を受けて動作する負荷である。負荷７の内部に、直流電力を交流電力に変換するインバータを含むものも、ここで言う直流負荷に含まれる。 Embodiment 1.
FIG. 1 is a diagram showing a basic circuit configuration of the power conversion device 100 according to the first embodiment. The power conversion device 100 according to the first embodiment includes a main circuit 110 and a controller 8. The main circuit 110 is a power conversion circuit that converts AC power generated by AC voltage output from AC power source 1 into DC power generated by DC voltage and applies it to the load 7. The load 7 is a DC load. A DC load is a load that operates by being supplied with DC power. A load 7 including an inverter that converts DC power into AC power is also included in the DC load referred to here.
　主回路１１０は、限流用のリアクトル２と、サブコンバータ３と、メインコンバータ５と、第１のコンデンサである平滑コンデンサ６とを備える。平滑コンデンサ６は、メインコンバータ５と負荷７との間において、メインコンバータ５及び負荷７のそれぞれに対して互いに並列に接続される。 The main circuit 110 includes a reactor 2 for limiting current, a subconverter 3, a main converter 5, and a smoothing capacitor 6, which is a first capacitor. The smoothing capacitor 6 is connected in parallel to each of the main converter 5 and the load 7 between the main converter 5 and the load 7.
　サブコンバータ３は、スイッチング素子３ａとスイッチング素子３ｂとが直列に接続された第１レグと、スイッチング素子３ｃとスイッチング素子３ｄとが直列に接続された第２レグと、第２のコンデンサである直流コンデンサ４とを有する。第１レグ、第２レグ及び直流コンデンサ４は、互いに並列に接続される。 The subconverter 3 includes a first leg in which the switching element 3a and the switching element 3b are connected in series, a second leg in which the switching element 3c and the switching element 3d are connected in series, and a direct current which is a second capacitor. It has a capacitor 4. The first leg, the second leg and the DC capacitor 4 are connected in parallel with each other.
　直流コンデンサ４及び平滑コンデンサ６の例は、アルミ電解コンデンサ、フィルムコンデンサである。 Examples of the DC capacitor 4 and the smoothing capacitor 6 are an aluminum electrolytic capacitor and a film capacitor.
　メインコンバータ５は、ダイオード５ａとスイッチング素子５ｂとが直列に接続された第３レグと、ダイオード５ｃとスイッチング素子５ｄとが直列に接続された第４レグとを備える。第３レグ及び第４レグ共に、各ダイオードのアノードがスイッチング素子に接続される構成である。第３レグ及び第４レグは、互いに並列に接続される。なお、ダイオード５ａ，５ｃをスイッチング素子に置き替えてもよい。 The main converter 5 includes a third leg in which the diode 5a and the switching element 5b are connected in series, and a fourth leg in which the diode 5c and the switching element 5d are connected in series. Both the third leg and the fourth leg have a configuration in which the anode of each diode is connected to the switching element. The third and fourth legs are connected in parallel with each other. The diodes 5a and 5c may be replaced with switching elements.
　リアクトル２の一端は交流電源１の一方に接続され、リアクトル２の他端は第１レグの中点に接続される。第１レグの中点は、スイッチング素子３ａとスイッチング素子３ｂとの接続点である。他のレグにおいても、スイッチング素子同士の接続点、及びダイオードとスイッチング素子との接続点を「中点」と呼ぶ。 One end of the reactor 2 is connected to one of the AC power supplies 1, and the other end of the reactor 2 is connected to the midpoint of the first leg. The midpoint of the first leg is the connection point between the switching element 3a and the switching element 3b. Also in other legs, the connection point between the switching elements and the connection point between the diode and the switching element are called "midpoints".
　メインコンバータ５において、第３レグの中点は、サブコンバータ３の第２レグの中点に接続され、第４レグの中点は交流電源１の他方に接続される。 In the main converter 5, the midpoint of the third leg is connected to the midpoint of the second leg of the subconverter 3, and the midpoint of the fourth leg is connected to the other of the AC power supply 1.
　スイッチング素子３ａ，３ｂ，３ｃ，３ｄ（以下、適宜「３ａ～３ｄ」と表記）及びスイッチング素子５ｂ，５ｄの一例は、ダイオードが逆並列に接続された図示の金属酸化物半導体電界効果トランジスタ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ：ＭＯＳＦＥＴ）である。逆並列の接続とは、ＭＯＳＦＥＴのドレインとダイオードのカソードとが接続され、ＭＯＳＦＥＴのソースとダイオードのアノードとが接続されることを意味する。なお、ダイオードは、ＭＯＳＦＥＴ自身が内部に有する寄生ダイオードを用いてもよい。寄生ダイオードは、ボディダイオードとも呼ばれる。 An example of the switching elements 3a, 3b, 3c, 3d (hereinafter, appropriately referred to as “3a to 3d”) and the switching elements 5b, 5d is a metal oxide semiconductor field effect transistor (Metal) in which diodes are connected in antiparallel. Oxide Semiconductor (Field Effect Transistor: MOSFET). The anti-parallel connection means that the drain of the MOSFET and the cathode of the diode are connected, and the source of the MOSFET and the anode of the diode are connected. As the diode, a parasitic diode contained in the MOSFET itself may be used. Parasitic diodes are also called body diodes.
　ＭＯＳＦＥＴに代えて、絶縁ゲートバイポーラトランジスタ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ：ＩＧＢＴ）、高電子移動度トランジスタ（Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ：ＨＥＭＴ）を用いてもよい。ＨＥＭＴとしては、カスコード型のＧａＮ（Ｇａｌｌｉｕｍ　Ｎｉｔｒｉｄｅ）－ＨＥＭＴが好適である。 Instead of the MOSFET, an insulated gate bipolar transistor (IGBT) or a high electron mobility transistor (HEMT) may be used. As the HEMT, a cascode type GaN (Gallium Nitride) -HEMT is suitable.
　平滑コンデンサ６は、メインコンバータ５によって変換された直流電圧を平滑して保持する。平滑コンデンサ６に保持される電圧である平滑コンデンサ電圧Ｖｄｃの極性は、矢印で示されている。矢印の先が高電位側であり、逆側が低電位側である。この定義は、サブコンバータ３においても同様である。また、交流電源１においては、矢印の先が高電位であるときを正極性、逆側が高電位であるときを負極性と定義する。 The smoothing capacitor 6 smoothes and holds the DC voltage converted by the main converter 5. The polarity of the smoothing capacitor voltage Vdc, which is the voltage held in the smoothing capacitor 6, is indicated by an arrow. The tip of the arrow is the high potential side, and the opposite side is the low potential side. This definition is the same for the subconverter 3. Further, in the AC power supply 1, the case where the tip of the arrow has a high potential is defined as the positive electrode property, and the case where the opposite side has a high potential is defined as the negative electrode property.
　電力変換装置１００は、更に電圧検出器３０，３１，３３と、電流検出器３２と、を備える。 The power conversion device 100 further includes voltage detectors 30, 31, 33, and a current detector 32.
　電圧検出器３０は、平滑コンデンサ電圧Ｖｄｃを検出する。なお、以下の記載において、平滑コンデンサ電圧を「第１のコンデンサ電圧」と称し、電圧検出器３０を「第１の電圧検出器」と称する場合がある。電圧検出器３０によって検出された平滑コンデンサ電圧Ｖｄｃの検出値は、制御器８に入力される。 The voltage detector 30 detects the smoothing capacitor voltage Vdc. In the following description, the smoothing capacitor voltage may be referred to as "first capacitor voltage", and the voltage detector 30 may be referred to as "first voltage detector". The detected value of the smoothing capacitor voltage Vdc detected by the voltage detector 30 is input to the controller 8.
　電圧検出器３１は、直流コンデンサ４の電圧である直流コンデンサ電圧Ｖｓｕｂを検出する。なお、以下の記載において、直流コンデンサ電圧を「第２のコンデンサ電圧」と称し、電圧検出器３１を「第２の電圧検出器」と称する場合がある。電圧検出器３１によって検出された直流コンデンサ電圧Ｖｓｕｂの検出値は、制御器８に入力される。 The voltage detector 31 detects the DC capacitor voltage Vsub, which is the voltage of the DC capacitor 4. In the following description, the DC capacitor voltage may be referred to as a "second capacitor voltage", and the voltage detector 31 may be referred to as a "second voltage detector". The detected value of the DC capacitor voltage Vsub detected by the voltage detector 31 is input to the controller 8.
　電流検出器３２は、リアクトル２に流れる交流電流ｉａｃを検出する。電流検出器３２によって検出された交流電流ｉａｃの検出値は、制御器８に入力される。 The current detector 32 detects the alternating current iac flowing in the reactor 2. The detected value of the alternating current iac detected by the current detector 32 is input to the controller 8.
　電圧検出器３３は、交流電源１が出力する交流電圧ｖａｃを検出する。なお、電圧検出器３３を「第３の電圧検出器」と称する場合がある。電圧検出器３３によって検出された交流電圧ｖａｃの検出値は、制御器８に入力される。 The voltage detector 33 detects the AC voltage vac output by the AC power supply 1. The voltage detector 33 may be referred to as a "third voltage detector". The detected value of the AC voltage vac detected by the voltage detector 33 is input to the controller 8.
　制御器８は、平滑コンデンサ電圧Ｖｄｃ、直流コンデンサ電圧Ｖｓｕｂ、交流電圧ｖａｃ及び交流電流ｉａｃの各検出値に基づいて、スイッチング素子３ａ～３ｄの導通を制御するためのゲート信号Ｇ３ａ，Ｇ３ｂ，Ｇ３ｃ，Ｇ３ｄ（以下、適宜「Ｇ３ａ～Ｇ３ｄ」と表記）と、スイッチング素子５ｂ，５ｄの導通を制御するためのゲート信号Ｇ５ｂ，Ｇ５ｄを生成する。 The controller 8 has gate signals G3a, G3b, G3c, for controlling conduction of the switching elements 3a to 3d based on the detected values of the smoothing capacitor voltage Vdc, the DC capacitor voltage Vsub, the AC voltage vac, and the AC current iac. G3d (hereinafter, appropriately referred to as “G3a to G3d”) and gate signals G5b and G5d for controlling the conduction of the switching elements 5b and 5d are generated.
　サブコンバータ３及びメインコンバータ５は、それぞれが図示を省略したゲート駆動回路を有する。サブコンバータ３の各ゲート駆動回路は、制御器８から出力されるゲート信号Ｇ３ａ～Ｇ３ｄを用いて駆動パルスを生成し、生成した駆動パルスを対応するスイッチング素子のゲートに印加して当該スイッチング素子を駆動する。メインコンバータ５の各ゲート駆動回路は、制御器８から出力されるゲート信号Ｇ５ｂ，Ｇ５ｄを用いて駆動パルスを生成し、生成した駆動パルスを対応するスイッチング素子のゲートに印加して当該スイッチング素子を駆動する。 Each of the sub-converter 3 and the main converter 5 has a gate drive circuit (not shown). Each gate drive circuit of the subconverter 3 generates a drive pulse using the gate signals G3a to G3d output from the controller 8, and applies the generated drive pulse to the gate of the corresponding switching element to control the switching element. Drive. Each gate drive circuit of the main converter 5 generates a drive pulse using the gate signals G5b and G5d output from the controller 8, and applies the generated drive pulse to the gate of the corresponding switching element to control the switching element. Drive.
　制御器８の内部の構成、及び制御器８の詳細な動作については後述する。 The internal configuration of the controller 8 and the detailed operation of the controller 8 will be described later.
　制御器８において、プロセッサ８ａは、演算装置、マイクロプロセッサ、マイクロコンピュータ、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）、又はＤＳＰ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｌ　Ｐｒｏｃｅｓｓｏｒ）といった演算手段である。 In the controller 8, the processor 8a is an arithmetic unit such as an arithmetic unit, a microprocessor, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor).
　メモリ８ｂは、ＲＡＭ（Ｒａｎｄｏｍ　Ａｃｃｅｓｓ　Ｍｅｍｏｒｙ）、ＲＯＭ（Ｒｅａｄ　Ｏｎｌｙ　Ｍｅｍｏｒｙ）、フラッシュメモリ、ＥＰＲＯＭ（Ｅｒａｓａｂｌｅ　Ｐｒｏｇｒａｍｍａｂｌｅ　ＲＯＭ）、ＥＥＰＲＯＭ（登録商標）（Ｅｌｅｃｔｒｉｃａｌｌｙ　ＥＰＲＯＭ）といった不揮発性又は揮発性の半導体メモリである。 The memory 8b is a non-volatile or volatile semiconductor such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Project ROM), and EEPROM (registered trademark) (Electrically EPROM).
　メモリ８ｂには、後述する制御器８の機能、及び後述する制御器８の機能を実行するプログラムが格納されている。プロセッサ８ａは、図示しないアナログディジタル変換器及びディジタルアナログ変換器を含むインタフェースを介して必要な情報を授受し、メモリ８ｂに格納されたプログラムをプロセッサ８ａが実行することにより、所要の処理を行う。プロセッサ８ａによる演算結果は、メモリ８ｂに記憶することができる。 The memory 8b stores a function of the controller 8 described later and a program for executing the function of the controller 8 described later. The processor 8a exchanges necessary information via an interface including an analog-to-digital converter and a digital-to-digital converter (not shown), and the processor 8a executes a program stored in the memory 8b to perform necessary processing. The calculation result by the processor 8a can be stored in the memory 8b.
　なお、制御器８の機能は、処理回路を用いて実現してもよい。ここで言う処理回路は、単一回路、複合回路、ＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ　Ｓｐｅｃｉｆｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）、ＦＰＧＡ（Ｆｉｅｌｄ－Ｐｒｏｇｒａｍｍａｂｌｅ　Ｇａｔｅ　Ａｒｒａｙ）、又は、これらを組み合わせたものが該当する。なお、処理回路を用いる構成でも、制御器８における一部の処理は、プロセッサ８ａで実施してもよい。 The function of the controller 8 may be realized by using a processing circuit. The processing circuit referred to here corresponds to a single circuit, a composite circuit, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof. Even in a configuration using a processing circuit, some processing in the controller 8 may be performed by the processor 8a.
　上記のように構成された電力変換装置１００は、交流電源１が出力する交流電圧と平滑コンデンサ６に保持される直流電圧である第１のコンデンサ電圧との間で電力変換を行う。この電力変換の機能は、リアクトル２、サブコンバータ３及びメインコンバータ５が担う。また、電力変換装置１００は、直流コンデンサ４に保持される第２のコンデンサ電圧が指令電圧に一致するようにスイッチング素子３ａ～３ｄ，５ｂ，５ｄの導通を制御する。この機能は、制御器８が担う。 The power conversion device 100 configured as described above performs power conversion between the AC voltage output by the AC power supply 1 and the first capacitor voltage which is the DC voltage held in the smoothing capacitor 6. The function of this power conversion is carried out by the reactor 2, the sub-converter 3, and the main converter 5. Further, the power conversion device 100 controls the conduction of the switching elements 3a to 3d, 5b, 5d so that the second capacitor voltage held in the DC capacitor 4 matches the command voltage. The controller 8 is responsible for this function.
　なお、図１では、１つのリアクトル２が交流電源１の一方側に接続される構成を開示しているが、この構成に限定されない。１つのリアクトル２が交流電源１の他方側に接続される構成でもよい。また、分割された２つのリアクトル２が交流電源１の一方側と他方側の双方に接続される構成でもよい。また、分割されたリアクトル２を同一のコアに巻いて、磁気結合した１つのリアクトルとして構成し、交流電源１の一方側又は他方側の何れかに接続してもよい。 Note that FIG. 1 discloses a configuration in which one reactor 2 is connected to one side of the AC power supply 1, but the configuration is not limited to this configuration. One reactor 2 may be connected to the other side of the AC power supply 1. Further, the two divided reactors 2 may be connected to both one side and the other side of the AC power supply 1. Further, the divided reactor 2 may be wound around the same core to form one magnetically coupled reactor, and may be connected to either one side or the other side of the AC power supply 1.
　次に、実施の形態１に係る電力変換装置１００における制御の要点について、図２から図７の図面を参照して説明する。図２は、実施の形態１に係る電力変換装置１００が昇圧動作するときの動作領域の概念の説明に使用する図である。図３は、実施の形態１に係る電力変換装置１００が降圧動作するときの動作領域の概念の説明に使用する図である。図４は、図２及び図３で定義される動作領域と主回路１１０の動作状態との関係を示す図である。図５は、実施の形態１に係る電力変換装置１００が電力変換を行うときの電流経路の例を示す図である。図６は、実施の形態１に係る電力変換装置１００が昇圧動作するときのスイッチングパターンの例を示す図である。図７は、実施の形態１に係る電力変換装置１００が降圧動作するときのスイッチングパターンの例を示す図である。 Next, the main points of control in the power conversion device 100 according to the first embodiment will be described with reference to the drawings of FIGS. 2 to 7. FIG. 2 is a diagram used to explain the concept of an operating region when the power conversion device 100 according to the first embodiment operates for boosting. FIG. 3 is a diagram used to explain the concept of an operating region when the power conversion device 100 according to the first embodiment operates in a step-down operation. FIG. 4 is a diagram showing the relationship between the operating region defined in FIGS. 2 and 3 and the operating state of the main circuit 110. FIG. 5 is a diagram showing an example of a current path when the power conversion device 100 according to the first embodiment performs power conversion. FIG. 6 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the first embodiment operates for boosting. FIG. 7 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the first embodiment operates in a step-down operation.
　図２には、交流電圧ｖａｃの半周期（以下、適宜「交流半周期」と呼ぶ）において、交流電圧ｖａｃの絶対値｜ｖａｃ｜よりも平滑コンデンサ電圧Ｖｄｃが大きい場合の電圧関係が示されている。平滑コンデンサ電圧Ｖｄｃが絶対値｜ｖａｃ｜よりも大きいので、交流電圧ｖａｃを昇圧する必要がある。このため、電力変換装置１００は、昇圧動作となる。以下、電力変換装置１００を昇圧動作させるモードを「昇圧動作モード」と呼ぶ。 FIG. 2 shows the voltage relationship when the smoothing capacitor voltage Vdc is larger than the absolute value | vac | of the AC voltage vac in the half cycle of the AC voltage vac (hereinafter, appropriately referred to as "AC half cycle"). There is. Since the smoothing capacitor voltage Vdc is larger than the absolute value | vac |, it is necessary to boost the AC voltage vac. Therefore, the power conversion device 100 is in a step-up operation. Hereinafter, the mode in which the power conversion device 100 is stepped up is referred to as a “boosting operation mode”.
　また、図３には、交流半周期において、交流電圧ｖａｃの絶対値｜ｖａｃ｜よりも平滑コンデンサ電圧Ｖｄｃが小さい領域を含む場合の電圧関係が示されている。平滑コンデンサ電圧Ｖｄｃが絶対値｜ｖａｃ｜よりも小さいので、交流電圧ｖａｃを降圧する必要がある。このため、電力変換装置１００は、降圧動作となる。以下、電力変換装置１００を降圧動作させるモードを「降圧動作モード」と呼ぶ。 Further, FIG. 3 shows the voltage relationship in the case where the smoothing capacitor voltage Vdc is smaller than the absolute value | vac | of the AC voltage vac in the AC half cycle. Since the smoothing capacitor voltage Vdc is smaller than the absolute value | vac |, it is necessary to step down the AC voltage vac. Therefore, the power conversion device 100 performs a step-down operation. Hereinafter, the mode in which the power conversion device 100 is stepped down is referred to as a "stepping down operation mode".
　図２及び図３において、α１及びα２は、Ｖｓｕｂ＝｜ｖａｃ｜となる位相である。また、β１及びβ２は、Ｖｄｃ＝｜ｖａｃ｜となる位相である。 In FIGS. 2 and 3, α1 and α2 are phases in which Vsub = | vac |. Further, β1 and β2 are phases in which Vdc = | vac |.
　図２および図３において、位相θが、０≦θ＜α１、α２＜θ≦πを満たす動作領域は、｜ｖａｃ｜＜Ｖｓｕｂ＜Ｖｄｃの関係が成り立つ動作領域である。この動作領域を領域１と定義する。 In FIGS. 2 and 3, the operating region in which the phase θ satisfies 0 ≦ θ <α1 and α2 <θ ≦ π is the operating region in which the relationship of | vac | <Vsub <Vdc is established. This operating area is defined as area 1.
　また、図２における、α１≦θ≦α２の領域、及び図３における、α１≦θ＜β１、β２＜θ≦α２を満たす動作領域は、Ｖｓｕｂ≦｜ｖａｃ｜＜Ｖｄｃが成り立つ動作領域である。この動作領域を領域２と定義する。 Further, the region of α1 ≦ θ ≦ α2 in FIG. 2 and the operating region in FIG. 3 that satisfies α1 ≦ θ <β1 and β2 <θ ≦ α2 are operating regions in which Vsub ≦ | vac | <Vdc holds. This operating area is defined as area 2.
　また、図３における、β１≦θ≦β２を満たす動作領域はＶｓｕｂ＜Ｖｄｃ≦｜ｖａｃ｜が成り立つ動作領域である。この動作領域を領域３と定義する。 Further, in FIG. 3, the operating region satisfying β1 ≦ θ ≦ β2 is the operating region where Vsub <Vdc ≦ | vac | holds. This operating area is defined as the area 3.
　図４には、図２及び図３で定義した各動作領域に対応するリアクトル２、直流コンデンサ４の動作状態、及びリアクトル２に印加される電圧であるリアクトル印加電圧の大きさが示されている。 FIG. 4 shows the reactor 2, the operating state of the DC capacitor 4, and the magnitude of the reactor applied voltage, which is the voltage applied to the reactor 2, corresponding to each operating region defined in FIGS. 2 and 3. ..
　リアクトル２の動作状態は、「励磁」及び「リセット」の２つである。「励磁」は、リアクトル２に電磁エネルギーを蓄積させる動作である。「リセット」は、リアクトル２に蓄積された電磁エネルギーを放出させる動作である。 There are two operating states of reactor 2, "excitation" and "reset". "Excitation" is an operation of accumulating electromagnetic energy in the reactor 2. "Reset" is an operation of releasing the electromagnetic energy stored in the reactor 2.
　直流コンデンサ４の動作状態は、「スルー」、「放電」及び「充電」の３つである。「スルー」は、直流コンデンサ４を通らない経路に交流電流ｉａｃを流す動作である。「放電」は、直流コンデンサ４を放電させる動作である。直流コンデンサ４を放電させると、直流コンデンサ４に蓄積された電荷が平滑コンデンサ６に移送される。「充電」は、直流コンデンサ４を充電する動作である。直流コンデンサ４の充電は、交流電源１の電力及びリアクトル２に蓄積された電磁エネルギーを利用して行われる。 There are three operating states of the DC capacitor 4, "through", "discharge", and "charge". “Through” is an operation in which an alternating current iac is passed through a path that does not pass through the direct current capacitor 4. "Discharging" is an operation of discharging the DC capacitor 4. When the DC capacitor 4 is discharged, the electric charge accumulated in the DC capacitor 4 is transferred to the smoothing capacitor 6. "Charging" is an operation of charging the DC capacitor 4. The DC capacitor 4 is charged by using the electric power of the AC power supply 1 and the electromagnetic energy stored in the reactor 2.
　図５には、図４の領域２において、リアクトル印加電圧が「ｖａｃ－Ｖｄｃ＋Ｖｓｕｂ」となるときの電流経路が示されている。図５における矢印は、交流電流ｉａｃが流れる電流経路を示している。図５に示されるように、リアクトル印加電圧が「ｖａｃ－Ｖｄｃ＋Ｖｓｕｂ」となるときは、制御器８によって、スイッチング素子３ｂ，３ｃ，５ｄがオンに制御され、スイッチング素子３ａ，３ｄ，５ｂがオフに制御される。他の動作についても、図５と同様に、交流電流ｉａｃの電流経路を示すことができる。なお、ここでの説明は割愛する。 FIG. 5 shows the current path when the reactor applied voltage becomes “vac-Vdc + Vsub” in the region 2 of FIG. The arrow in FIG. 5 indicates the current path through which the alternating current iac flows. As shown in FIG. 5, when the reactor applied voltage becomes "vac-Vdc + Vsub", the controller 8 controls the switching elements 3b, 3c, 5d to be on and the switching elements 3a, 3d, 5b to be off. Be controlled. For other operations, the current path of the alternating current iac can be shown as in FIG. The explanation here is omitted.
　図６の下段部には、昇圧動作モード時のスイッチングパターンの例が示されている。図７の下段部には、降圧動作モード時のスイッチングパターンの例が示されている。また、図６及び図７の各上段部には、平滑コンデンサ電圧Ｖｄｃ、平滑コンデンサ電圧Ｖｄｃの指令値である平滑コンデンサ電圧指令Ｖｄｃ＊、直流コンデンサ電圧Ｖｓｕｂ、直流コンデンサ電圧Ｖｓｕｂの指令値である直流コンデンサ電圧指令Ｖｓｕｂ＊、交流電圧ｖａｃ及び交流電流ｉａｃの各波形が示されている。 The lower part of FIG. 6 shows an example of a switching pattern in the boost operation mode. An example of the switching pattern in the step-down operation mode is shown in the lower part of FIG. 7. Further, in each upper part of FIGS. 6 and 7, the smoothing capacitor voltage Vdc, the smoothing capacitor voltage command Vdc * which is the command value of the smoothing capacitor voltage Vdc, the DC capacitor voltage Vsub, and the DC which is the command value of the DC capacitor voltage Vsub. The waveforms of the capacitor voltage command Vsub *, the AC voltage vac, and the AC current iac are shown.
　図６において、領域２における区間Ａのスイッチングパターンは、図５の動作となるときのスイッチングパターンである。また、図６の領域１における区間Ｂのスイッチングパターンによって、図４の領域１に示した、直流コンデンサ４が「スルー」で、リアクトル印加電圧が「ｖａｃ」となる動作を実施している。 In FIG. 6, the switching pattern of the section A in the region 2 is the switching pattern at the time of the operation of FIG. Further, according to the switching pattern of the section B in the region 1 of FIG. 6, the operation in which the DC capacitor 4 shown in the region 1 of FIG. 4 is “through” and the reactor applied voltage is “vac” is performed.
　次に、実施の形態１における制御器８の内部の構成について説明する。図８は、実施の形態１における制御器８の内部構成を示すブロック図である。制御器８は、動作領域判定器９と、フィードフォワード（Ｆｅｅｄ　Ｆｏｒｗａｒｄ：ＦＦ）デューティ（Ｄｕｔｙ）（以下「ＦＦ_Ｄｕｔｙ」と表記）演算器１０と、直流コンデンサ電圧制御器１１と、加減算判定器１２と、加算器１２ａ、ゲート信号生成器１３とを備える。 Next, the internal configuration of the controller 8 in the first embodiment will be described. FIG. 8 is a block diagram showing an internal configuration of the controller 8 according to the first embodiment. The controller 8 includes an operating area determination device 9, a feed forward (FF) duty (Duty) (hereinafter referred to as “FF_Duty”) arithmetic unit 10, a DC capacitor voltage controller 11, and an addition / subtraction determination device 12. , The adder 12a, and the gate signal generator 13.
　動作領域判定器９は、交流電圧ｖａｃ、平滑コンデンサ電圧Ｖｄｃ及び直流コンデンサ電圧Ｖｓｕｂの各検出値に基づいて、領域判定信号Ｓｉｇ_ＳＰを生成する。領域判定信号Ｓｉｇ_ＳＰは、判定時における電力変換装置１００の動作状態が図２又は図３のどの領域にあるのかを示す信号である。動作領域判定器９が生成した領域判定信号Ｓｉｇ_ＳＰは、ＦＦ_Ｄｕｔｙ演算器１０と、加減算判定器１２と、ゲート信号生成器１３とに入力される。それぞれの演算器では、動作領域に応じた演算が行われる。 The operating area determination device 9 generates the area determination signal Sig_SP based on the detected values of the AC voltage vac, the smoothing capacitor voltage Vdc, and the DC capacitor voltage Vsub. The area determination signal Sig_SP is a signal indicating in which region of FIG. 2 or FIG. 3 the operating state of the power conversion device 100 at the time of determination is. The area determination signal Sig_SP generated by the operation area determination device 9 is input to the FF_Duty calculator 10, the addition / subtraction determination unit 12, and the gate signal generator 13. In each arithmetic unit, an arithmetic operation is performed according to the operating area.
　ＦＦ_Ｄｕｔｙ演算器１０は、交流電圧ｖａｃの検出値及び領域判定信号Ｓｉｇ_ＳＰに基づいてＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃを演算する。ＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃを演算する際には、図２又は図３に示した各領域において、直流コンデンサ４における充電と放電とが交流半周期ごとに同一回数となるように設定される。例えば、ある交流半周期において、直流コンデンサ４の充電が１回行われれば直流コンデンサ４の放電も１回行われ、直流コンデンサ４の充電が２回行われれば直流コンデンサ４の放電も２回行われる。なお、充電回数及び放電回数の合計値である充放電回数には“０”も含まれる。 The FF_Duty calculator 10 calculates the FF_Duty ratio D_Vdc based on the detected value of the AC voltage vac and the region determination signal Sig_SP. When calculating the FF_Duty ratio D_Vdc, the charging and discharging in the DC capacitor 4 are set to be the same number of times in each AC half cycle in each region shown in FIG. 2 or FIG. For example, in a certain AC half cycle, if the DC capacitor 4 is charged once, the DC capacitor 4 is also discharged once, and if the DC capacitor 4 is charged twice, the DC capacitor 4 is also discharged twice. Will be. In addition, "0" is also included in the charge / discharge count which is the total value of the charge count and the discharge count.
　各動作領域における充電及び放電は、図４を参照して設定される。充放電回数が“０”である場合は、図４における「スルー」が選択される。なお、動作領域ごとに同一回数の「充電」及び「放電」の組が選択されることが好ましいが、これに限定されない。交流半周期の期間内であれば、動作領域を跨って「充電」及び「放電」の組が選択されてもよい。 Charging and discharging in each operating area are set with reference to FIG. When the number of charge / discharge cycles is "0", "through" in FIG. 4 is selected. It is preferable, but not limited to, the set of "charging" and "discharging" of the same number of times is selected for each operating region. As long as it is within the period of the AC half cycle, the set of "charge" and "discharge" may be selected across the operating region.
　また、充放電回数は、直流コンデンサ４の容量、主回路部品の耐圧、及び主回路１１０の力率に基づいて決定することができる。充放電回数が少ない場合、スイッチング損失は低減できるが、制御の応答性が悪化し、力率の低下及び電圧リプル量の増加を招く。このため、電力変換装置１００を安定動作させるためには、コンデンサ容量を大きくする必要がある。一方、充放電回数が多い場合には、コンデンサ容量は小さくて済み、制御の応答性も向上するが、スイッチング損失は増加する。 Further, the number of charge / discharge cycles can be determined based on the capacity of the DC capacitor 4, the withstand voltage of the main circuit component, and the power factor of the main circuit 110. When the number of charge / discharge cycles is small, the switching loss can be reduced, but the responsiveness of the control deteriorates, resulting in a decrease in the power factor and an increase in the amount of voltage ripple. Therefore, in order to operate the power conversion device 100 stably, it is necessary to increase the capacity of the capacitor. On the other hand, when the number of charge / discharge cycles is large, the capacitor capacity can be small and the responsiveness of control is improved, but the switching loss increases.
　図９は、図８に示す直流コンデンサ電圧制御器１１の詳細構成を示すブロック図である。直流コンデンサ電圧制御器１１は、前処理器１１ａと、サンプルホールド器１１ｂとを備える。直流コンデンサ電圧制御器１１は、直流コンデンサ電圧Ｖｓｕｂの検出値に基づいて、直流コンデンサ電圧Ｖｓｕｂが、直流コンデンサ電圧Ｖｓｕｂの指令値である直流コンデンサ電圧指令Ｖｓｕｂ＊に追従するように制御する直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂを生成する。 FIG. 9 is a block diagram showing a detailed configuration of the DC capacitor voltage controller 11 shown in FIG. The DC capacitor voltage controller 11 includes a pretreatment device 11a and a sample hold device 11b. The DC capacitor voltage controller 11 controls the DC capacitor voltage Vsub to follow the DC capacitor voltage command Vsub *, which is a command value of the DC capacitor voltage Vsub, based on the detected value of the DC capacitor voltage Vsub. Generate a command duty ratio D_Vsub.
　前処理器１１ａは、直流コンデンサ電圧指令Ｖｓｕｂ＊と直流コンデンサ電圧Ｖｓｕｂの検出値との偏差を比例（Ｐｒｏｐｏｒｔｉｏｎａｌ）制御し、その制御値を直流コンデンサ電圧指令Ｖｓｕｂ＊で割ることで規格化したデューティ比を演算する。サンプルホールド器１１ｂは、前処理器１１ａの出力をサンプルホールドの周期で値の更新を行い、更新した値を直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂとして加減算判定器１２に出力する。 The preprocessing device 11a proportionally controls the deviation between the DC capacitor voltage command Vsub * and the detected value of the DC capacitor voltage Vsub *, and divides the control value by the DC capacitor voltage command Vsub * to obtain a standardized duty ratio. Is calculated. The sample hold device 11b updates the value of the output of the preprocessing device 11a in the sample hold cycle, and outputs the updated value to the addition / subtraction determination device 12 as the DC capacitor voltage command duty ratio D_Vsub.
　なお、以下の記載において、前述したＦＦ_Ｄｕｔｙ比を「第１のデューティ比」と称し、前述した直流コンデンサ電圧指令デューティ比を「第２のデューティ比」と称する場合がある。 In the following description, the above-mentioned FF_Duty ratio may be referred to as a "first duty ratio", and the above-mentioned DC capacitor voltage command duty ratio may be referred to as a "second duty ratio".
　図１０は、図８に示す加減算判定器１２の動作説明に用いるタイムチャートである。図１１は、図８に示す加減算判定器１２の動作説明に用いるブロック図である。 FIG. 10 is a time chart used for explaining the operation of the addition / subtraction determination device 12 shown in FIG. FIG. 11 is a block diagram used for explaining the operation of the addition / subtraction determination device 12 shown in FIG.
　図１０の波形は、交流電圧ｖａｃの正の半波における領域２の動作の一例である。図１０には、上段側から順に、交流電流ｉａｃの波形と、スイッチング素子３ａ～３ｄ，５ｂ，５ｄのそれぞれを制御するためのゲート信号Ｇ３ａ～Ｇ３ｄ，Ｇ５ｂ，Ｇ５ｄの波形とが示されている。また、図１０の下段部には、直流コンデンサ４の動作状態が示されている。時刻ｔ０～ｔ１，ｔ２～ｔ３では、リアクトル２が励磁され、時刻ｔ１～ｔ２，ｔ３～ｔ４では、リアクトル２の励磁がリセットされる。従って、図１０の例では、励磁及びリセットを１対とする２対のスイッチング制御、即ち、４回のスイッチング制御が行われている。 The waveform in FIG. 10 is an example of the operation of region 2 in the positive half wave of the AC voltage vac. FIG. 10 shows the waveforms of the alternating current iac and the waveforms of the gate signals G3a to G3d, G5b, and G5d for controlling each of the switching elements 3a to 3d, 5b, and 5d in order from the upper stage side. .. Further, the operating state of the DC capacitor 4 is shown in the lower part of FIG. 10. At times t0 to t1 and t2 to t3, the reactor 2 is excited, and at times t1 to t2 and t3 to t4, the excitation of the reactor 2 is reset. Therefore, in the example of FIG. 10, two pairs of switching control with excitation and reset as one pair, that is, four times of switching control are performed.
　加減算判定器１２には、直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂが入力される。加減算判定器１２は、領域判定信号Ｓｉｇ_ＳＰに基づいて、直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂに“１”又は“－１”の値を乗算する。即ち、加減算判定器１２からは、領域判定信号Ｓｉｇ_ＳＰに応じて、符号が反転されない非反転の制御信号“＋Ｄ_Ｖｓｕｂ”、又は符号が反転された制御信号“－Ｄ_Ｖｓｕｂ”が出力される。図１１の上段部には、非反転の制御信号“＋Ｄ_Ｖｓｕｂ”が出力される状況が示されている。図１１の下段部には、反転された制御信号“－Ｄ_Ｖｓｕｂ”が出力される状況が示されている。 The DC capacitor voltage command duty ratio D_Vsub is input to the addition / subtraction determination device 12. The addition / subtraction determination device 12 multiplies the DC capacitor voltage command duty ratio D_Vsub by a value of "1" or "-1" based on the area determination signal Sig_SP. That is, the addition / subtraction determination device 12 outputs a non-inverted control signal “+ D_Vsub” whose sign is not inverted or a control signal “−D_Vsub” whose sign is inverted according to the area determination signal Sig_SP. The upper part of FIG. 11 shows a situation in which a non-inverting control signal “+ D_Vsub” is output. The lower part of FIG. 11 shows a situation in which the inverted control signal “−D_Vsub” is output.
　実施の形態１では、図１０における時刻ｔ１及び時刻ｔ３を変更することで電圧制御を行う。 In the first embodiment, voltage control is performed by changing the time t1 and the time t3 in FIG.
　例えば、外乱により直流コンデンサ電圧Ｖｓｕｂが直流コンデンサ電圧指令Ｖｓｕｂ＊よりも低くなった場合、図１１の上段部に示すように、時刻ｔ１では、加算器１２ａにおいて、ＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃに対して直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂが正で加算される。また、図１１の下段部に示すように、時刻ｔ３では、加算器１２ａにおいて、ＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃに対して直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂが負で加算される。これにより、主回路１１０の動作は、直流コンデンサ４に対する充電量が増加し、放電量が減少する動作となる。 For example, when the DC capacitor voltage Vsub becomes lower than the DC capacitor voltage command Vsub * due to disturbance, as shown in the upper part of FIG. 11, at time t1, the DC capacitor voltage with respect to the FF_Duty ratio D_Vdc in the adder 12a. The command duty ratio D_Vsub is positively added. Further, as shown in the lower part of FIG. 11, at time t3, the DC capacitor voltage command duty ratio D_Vsub is negatively added to the FF_Duty ratio D_Vdc in the adder 12a. As a result, the operation of the main circuit 110 is such that the amount of charge to the DC capacitor 4 increases and the amount of discharge decreases.
　上記とは逆に、直流コンデンサ電圧Ｖｓｕｂが直流コンデンサ電圧指令Ｖｓｕｂ＊よりも高くなった場合、時刻ｔ１では、加算器１２ａにおいて、ＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃに対して直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂが負で加算される。また、時刻ｔ３では、加算器１２ａにおいて、ＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃに対して直流コンデンサ電圧指令デューティ比Ｄ_Ｖｓｕｂが正で加算される。これにより、主回路１１０の動作は、直流コンデンサ４に対する充電量が減少し、放電量が増加する動作となる。 Contrary to the above, when the DC capacitor voltage Vsub becomes higher than the DC capacitor voltage command Vsub *, at time t1, the DC capacitor voltage command duty ratio D_Vsub is negatively added to the FF_Duty ratio D_Vdc in the adder 12a. Will be done. Further, at time t3, the DC capacitor voltage command duty ratio D_Vsub is positively added to the FF_Duty ratio D_Vdc in the adder 12a. As a result, the operation of the main circuit 110 is such that the amount of charge to the DC capacitor 4 decreases and the amount of discharge increases.
　上記の動作により、直流コンデンサ電圧Ｖｓｕｂは、直流コンデンサ電圧指令Ｖｓｕｂ＊通りに制御される。なお、図１０では、交流電圧ｖａｃの正の半波における領域２の動作を説明したが、正の半波における領域１，３、及び負の半波における領域１～３においても、同様の動作で電圧一定制御を行うことができる。 By the above operation, the DC capacitor voltage Vsub is controlled according to the DC capacitor voltage command Vsub *. Although the operation of the region 2 in the positive half wave of the AC voltage vac has been described in FIG. 10, the same operation is performed in the regions 1 and 3 in the positive half wave and the regions 1 to 3 in the negative half wave. It is possible to perform constant voltage control with.
　図８に戻り、ゲート信号生成器１３には、交流電圧ｖａｃと、領域判定信号Ｓｉｇ_ＳＰと、加算器１２ａから出力されるデューティ比総和量Ｄ_ｔｏｔａｌとが入力される。ゲート信号生成器１３は、交流電圧ｖａｃと、領域判定信号Ｓｉｇ_ＳＰと、加算器１２ａから出力されるデューティ比総和量Ｄ_ｔｏｔａｌとに基づいて、ゲート信号Ｇ３ａ～Ｇ３ｄ，Ｇ５ｂ，Ｇ５ｄを生成する。ゲート信号Ｇ３ａ～Ｇ３ｄ，Ｇ５ｂ，Ｇ５ｄは、それぞれスイッチング素子３ａ～３ｄ，５ｂ，５ｄに印加され、スイッチング素子３ａ～３ｄ，５ｂ，５ｄの導通が制御される。 Returning to FIG. 8, the AC voltage vac, the area determination signal Sig_SP, and the total duty ratio D_total output from the adder 12a are input to the gate signal generator 13. The gate signal generator 13 generates gate signals G3a to G3d, G5b, and G5d based on the AC voltage vac, the area determination signal Sig_SP, and the total duty ratio amount D_total output from the adder 12a. The gate signals G3a to G3d, G5b, and G5d are applied to the switching elements 3a to 3d, 5b, and 5d, respectively, and the conduction of the switching elements 3a to 3d, 5b, and 5d is controlled.
　以上の制御により、実施の形態１の電力変換装置１００では、第１のコンデンサ電圧の制御を通じて、負荷７への所要の電力供給が可能となる。また、第１のコンデンサ電圧の制御を行いつつ、第２のコンデンサ電圧を指令値に追従させる電圧一定制御が可能となる。 With the above control, in the power conversion device 100 of the first embodiment, the required power can be supplied to the load 7 through the control of the first capacitor voltage. Further, it is possible to control the voltage constant so that the second capacitor voltage follows the command value while controlling the first capacitor voltage.
　また、実施の形態１において、交流半周期におけるスイッチング回数は、多くても２０回である。即ち、実施の形態１では、主回路１１０のスイッチング素子３ａ～３ｄ，５ｂ，５ｄに対し、交流半周期で十数回以下のスイッチング回数によるスイッチング制御が行われる。 Further, in the first embodiment, the number of switchings in the AC half cycle is at most 20 times. That is, in the first embodiment, switching control is performed for the switching elements 3a to 3d, 5b, and 5d of the main circuit 110 by switching the number of times of switching to a dozen or less times in an AC half cycle.
　交流電圧ｖａｃの周波数を５０Ｈｚとすると、交流半周期は１０［ｍｓ］となる。交流半周期において、２０回のスイッチング制御を周期的に行うとすると、１回のスイッチング制御に要する時間は、０．５［ｍｓ］である。０．５［ｍｓ］を１スイッチング周期とすれば、スイッチング周波数は５［ｋＨｚ］であり、従来に比べて、スイッチング周波数を低減することができる。これにより、スイッチング素子のスイッチング損失及びリアクトルの高周波損失を低減できるので、従来に比べて、電力変換装置を高効率に駆動することができる。 Assuming that the frequency of the AC voltage vac is 50 Hz, the AC half cycle is 10 [ms]. Assuming that the switching control is periodically performed 20 times in the AC half cycle, the time required for one switching control is 0.5 [ms]. If 0.5 [ms] is set as one switching cycle, the switching frequency is 5 [kHz], and the switching frequency can be reduced as compared with the conventional case. As a result, the switching loss of the switching element and the high frequency loss of the reactor can be reduced, so that the power conversion device can be driven with higher efficiency than in the conventional case.
　なお、これまでの説明では、交流半周期において、直流コンデンサ４に対する充放電が少なくとも１回行われることを前提としていたが、これに限定されない。領域１及び領域２のみを用いる昇圧動作の場合、交流半周期における直流コンデンサ４の充放電回数を０回として、平滑コンデンサ電圧Ｖｄｃの制御のみで、主回路１１０を動作させることも可能である。この場合、ＦＦ_Ｄｕｔｙ演算器１０では、図４において、「スルー」の動作のみが選択されて、ＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃが演算される。そして、演算されたＦＦ_Ｄｕｔｙ比Ｄ_Ｖｄｃを用いてゲート信号Ｇ３ａ～Ｇ３ｄ，Ｇ５ｂ，Ｇ５ｄが生成される。この場合、直流コンデンサ電圧Ｖｓｕｂのフィードバック制御が不要となる。このため、事前に動作条件に応じたスイッチング回数、及び導通時間を制御器８のメモリ８ｂに記憶しておき、記憶された情報を読み出して、主回路１１０を動作させてもよい。 In the explanation so far, it has been assumed that the DC capacitor 4 is charged and discharged at least once in the AC half cycle, but the present invention is not limited to this. In the case of the boosting operation using only the region 1 and the region 2, it is possible to operate the main circuit 110 only by controlling the smoothing capacitor voltage Vdc, with the number of charge / discharge of the DC capacitor 4 in the AC half cycle being 0 times. In this case, in the FF_Duty calculator 10, only the “through” operation is selected in FIG. 4, and the FF_Duty ratio D_Vdc is calculated. Then, the gate signals G3a to G3d, G5b, and G5d are generated using the calculated FF_Duty ratio D_Vdc. In this case, feedback control of the DC capacitor voltage Vsub becomes unnecessary. Therefore, the number of switching times and the conduction time according to the operating conditions may be stored in the memory 8b of the controller 8 in advance, and the stored information may be read out to operate the main circuit 110.
　以上説明したように、実施の形態１に係る電力変換装置によれば、制御器は、複数のスイッチング素子を交流電圧の半周期で１回以上、十数回以下（２０回未満）のスイッチング回数でスイッチング制御する。これにより、スイッチング素子のスイッチング損失、及びリアクトルの高周波損失を低減して、電力変換装置を高効率に駆動することができる。また、このスイッチング制御に際し、制御器は、交流電圧の半周期における第２のコンデンサの充電量と放電量とを制御して、第２のコンデンサ電圧を第２のコンデンサ電圧の指令値に一致させる制御を行う。この制御により、スイッチング素子のスイッチング損失及びリアクトルの高周波損失を低減しつつ、主回路動作の力率を高めることができる。これにより、電力変換装置を高効率に駆動することができる。 As described above, according to the power conversion device according to the first embodiment, the controller switches a plurality of switching elements once or more and a dozen times or less (less than 20 times) in a half cycle of the AC voltage. Switching control is performed with. As a result, the switching loss of the switching element and the high frequency loss of the reactor can be reduced, and the power conversion device can be driven with high efficiency. Further, in this switching control, the controller controls the charge amount and the discharge amount of the second capacitor in the half cycle of the AC voltage to match the second capacitor voltage with the command value of the second capacitor voltage. Take control. By this control, the power factor of the main circuit operation can be increased while reducing the switching loss of the switching element and the high frequency loss of the reactor. As a result, the power conversion device can be driven with high efficiency.
　なお、上記の制御において、制御器は、第２のコンデンサを充電する充電時間及び第２のコンデンサを放電させる放電時間を変更しながらスイッチング制御を行うことができる。この制御は、キャリア波を用いずに実施できるので、電力変換装置の高効率駆動を簡易に実施することが可能となる。 In the above control, the controller can perform switching control while changing the charging time for charging the second capacitor and the discharging time for discharging the second capacitor. Since this control can be performed without using carrier waves, it is possible to easily carry out high-efficiency driving of the power conversion device.
　また、上記の制御において、制御器は、交流電圧の半周期内で第２のコンデンサの充電及び放電を各１回以上行い、且つ、充電の回数と放電の回数とが交流電圧の半周期内で等しくなるようにスイッチング制御を行うことが好ましい。これにより、第２のコンデンサ電圧を指令値に追従させる電圧一定制御を確実に実施することができる。 Further, in the above control, the controller charges and discharges the second capacitor once or more within a half cycle of the AC voltage, and the number of times of charging and the number of times of discharging are within the half cycle of the AC voltage. It is preferable to perform switching control so that they are equal to each other. As a result, constant voltage control that causes the second capacitor voltage to follow the command value can be reliably performed.
　また、上記の制御において、第１のコンデンサ電圧を制御するための第１のデューティ比と、第２のコンデンサ電圧を制御するための第２のデューティ比との和であるデューティ比総和量に対し、制御器は、交流電圧の半周期内におけるデューティ比総和量が一定に保たれるように、第２のデューティ比を第１のデューティ比に加減算することが好ましい。これにより、第１のコンデンサ電圧の制御と、第２のコンデンサ電圧を指令値に追従させる電圧一定制御とを両立して実施することができる。 Further, in the above control, with respect to the total duty ratio, which is the sum of the first duty ratio for controlling the first capacitor voltage and the second duty ratio for controlling the second capacitor voltage. The controller preferably adds or subtracts the second duty ratio to the first duty ratio so that the total amount of duty ratios in the half cycle of the AC voltage is kept constant. As a result, it is possible to carry out both the control of the first capacitor voltage and the constant voltage control for making the second capacitor voltage follow the command value.
実施の形態２．
　図１２は、実施の形態２における制御器８Ａの内部構成を示すブロック図である。実施の形態２における制御器８Ａは、図８に示す実施の形態１における制御器８の構成において、ＦＦ_Ｄｕｔｙ演算器１０が高力率制御器１７に置き替えられ、ゲート信号生成器１３がゲート信号生成器１８に置き替えられている。また、キャリア波生成器１６が追加されている。なお、その他の構成については、図８に示す構成と同一又は同等であり、同一又は同等の構成部には、同一の符号を付して、重複する説明は割愛する。また、基本回路構成は、図１と同一又は同等である。 Embodiment 2.
FIG. 12 is a block diagram showing an internal configuration of the controller 8A according to the second embodiment. In the controller 8A according to the second embodiment, in the configuration of the controller 8 according to the first embodiment shown in FIG. 8, the FF_Duty calculator 10 is replaced with the high power factor controller 17, and the gate signal generator 13 is the gate signal. It has been replaced by the generator 18. In addition, a carrier wave generator 16 has been added. The other configurations are the same as or equivalent to the configurations shown in FIG. 8, and the same or equivalent components are designated by the same reference numerals, and duplicate explanations are omitted. The basic circuit configuration is the same as or equivalent to that in FIG.
　図１３は、実施の形態２に係る電力変換装置１００が昇圧動作するときのスイッチングパターンの例を示す図である。また、図１４は、実施の形態２に係る電力変換装置１００が降圧動作するときのスイッチングパターンの例を示す図である。実施の形態１で説明した動作領域の概念は、実施の形態２においても同じである。実施の形態２に係る電力変換装置１００は、動作領域ごとに、キャリア周波数を変更しながら、スイッチング素子３ａ～３ｄ，５ｂ，５ｄに対するスイッチング制御を行う。キャリア周波数が変更されると、スイッチング周波数も変更される。なお、本明細書では、同一のスイッチング周波数が維持される期間を「第１のスイッチング期間」と定義する。 FIG. 13 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the second embodiment operates for boosting. Further, FIG. 14 is a diagram showing an example of a switching pattern when the power conversion device 100 according to the second embodiment operates in a step-down operation. The concept of the operating area described in the first embodiment is the same in the second embodiment. The power conversion device 100 according to the second embodiment performs switching control for the switching elements 3a to 3d, 5b, 5d while changing the carrier frequency for each operating region. When the carrier frequency is changed, so is the switching frequency. In this specification, the period in which the same switching frequency is maintained is defined as the "first switching period".
　図１３及び図１４のスイッチングパターンによれば、各動作領域で、直流コンデンサ４の充電及び放電が１回以上行われるように動作する。なお、前述したように、各動作領域の幅は、平滑コンデンサ電圧Ｖｄｃ及び直流コンデンサ電圧Ｖｓｕｂと、交流電圧ｖａｃとの大小関係で決まるので、各動作領域の幅は変動する。このため、期間の狭い領域では、より高周波数のスイッチング制御による力率制御が行われ、期間の広い領域では、より低周波数のスイッチング制御による力率制御が行われる。一方、前述したように、スイッチング回数は多くても２０回であり、従来の手法に比べて大幅に低減されている。このため、従来よりも、大幅な損失低減が可能となり、電力変換装置を高効率に駆動することができる。 According to the switching patterns of FIGS. 13 and 14, the DC capacitor 4 is operated so as to be charged and discharged once or more in each operating region. As described above, since the width of each operating region is determined by the magnitude relationship between the smoothing capacitor voltage Vdc and the DC capacitor voltage Vsub and the AC voltage vac, the width of each operating region varies. Therefore, in a region with a narrow period, power factor control is performed by switching control at a higher frequency, and in a region with a wide period, power factor control is performed by switching control at a lower frequency. On the other hand, as described above, the number of switching times is at most 20 times, which is significantly reduced as compared with the conventional method. Therefore, it is possible to significantly reduce the loss as compared with the conventional case, and it is possible to drive the power conversion device with high efficiency.
　なお、図１４に示す降圧動作の場合、図１３に示す昇圧動作の場合と比べて動作領域が増える。このため、動作領域ごとのスイッチング回数が同じであれば、交流半周期におけるスイッチング回数は、降圧動作の方が多くなる。また、降圧動作は昇圧動作と異なり、直流コンデンサ４に対する充放電を行いながら動作する必要がある。このため、領域３では、必ず充放電のためのスイッチング制御が行われる。なお、この点は、実施の形態１においても同様である。図４の領域３に示されるように、領域３には「スルー」の動作はなく、放電又は充電の何れかの動作が選択される。 In the case of the step-down operation shown in FIG. 14, the operating area increases as compared with the case of the step-up operation shown in FIG. Therefore, if the number of switchings for each operating region is the same, the number of switchings in the AC half cycle is larger in the step-down operation. Further, the step-down operation is different from the step-up operation, and it is necessary to operate while charging / discharging the DC capacitor 4. Therefore, in the region 3, switching control for charging / discharging is always performed. This point is the same in the first embodiment. As shown in region 3 of FIG. 4, there is no "through" operation in region 3, and either discharge or charge operation is selected.
　図１５は、図１２に示すキャリア波生成器１６の詳細構成を示すブロック図である。キャリア波生成器１６は、スイッチング周波数演算器２０と、周波数変換器２１とを備える。 FIG. 15 is a block diagram showing a detailed configuration of the carrier wave generator 16 shown in FIG. The carrier wave generator 16 includes a switching frequency calculator 20 and a frequency converter 21.
　スイッチング周波数演算器２０は、交流電圧ｖａｃ、直流コンデンサ電圧Ｖｓｕｂ及び平滑コンデンサ電圧Ｖｄｃに基づいて、交流半周期における各動作領域の時間を演算する。また、スイッチング周波数演算器２０は、ユーザが設定した直流コンデンサ４の充放電回数に基づいて、スイッチング周波数の逆数であるスイッチング周期を演算する。 The switching frequency calculator 20 calculates the time of each operating region in the AC half cycle based on the AC voltage vac, the DC capacitor voltage Vsub, and the smoothing capacitor voltage Vdc. Further, the switching frequency calculator 20 calculates a switching cycle which is the reciprocal of the switching frequency based on the number of times of charging / discharging of the DC capacitor 4 set by the user.
　周波数変換器２１は、スイッチング周波数演算器２０が演算したスイッチング周期と、領域判定信号Ｓｉｇ_ＳＰとに基づいて、キャリア波を生成する。なお、キャリア波は、のこぎり波でも、三角波でもよい。 The frequency converter 21 generates a carrier wave based on the switching cycle calculated by the switching frequency calculator 20 and the region determination signal Sig_SP. The carrier wave may be a sawtooth wave or a triangular wave.
　スイッチング周波数演算器２０は、図１５に示すように、第１の時間演算器２０ａと、第２の時間演算器２０ｃと、第３の時間演算器２０ｅと、第４の時間演算器２０ｉと、除算器２０ｂ，２０ｄ，２０ｇ，２０ｊと、加算器２０ｈとを備える。 As shown in FIG. 15, the switching frequency calculator 20 includes a first time calculator 20a, a second time calculator 20c, a third time calculator 20e, a fourth time calculator 20i, and the like. The dividers 20b, 20d, 20g, 20j and the adder 20h are provided.
　第１の時間演算器２０ａは、直流コンデンサ電圧Ｖｓｕｂを交流電圧ｖａｃで除算したものを逆三角関数で時間に変換し、更に角周波数２πｆａｃで除算することで領域１の時間Ｒｔ１を演算する。時間Ｒｔ１は、図２における０からα１までの位相差に相当する時間である。ｆａｃは、交流電圧ｖａｃの周波数である。以下、交流電圧ｖａｃの周波数を「交流電圧周波数」と呼ぶ。スイッチング周波数演算器２０は、時間Ｒｔ１を除算器２０ｂにおいて充放電回数で除算することで領域１のスイッチング周期Ｔｓｗ_１を演算する。 The first time calculator 20a calculates the time Rt1 in the region 1 by dividing the DC capacitor voltage Vsub by the AC voltage vac, converting it into time by an inverse trigonometric function, and further dividing by the angular frequency 2πfac. The time Rt1 is the time corresponding to the phase difference from 0 to α1 in FIG. fac is the frequency of the AC voltage vac. Hereinafter, the frequency of the AC voltage vac is referred to as "AC voltage frequency". The switching frequency calculator 20 calculates the switching cycle Tsw_1 of the region 1 by dividing the time Rt1 by the number of charge / discharge cycles in the divider 20b.
　第２の時間演算器２０ｃは、１の値を交流電圧周波数ｆａｃの２倍値で除算した値から領域１の時間Ｒｔ１の２倍値を減算することで領域２の時間Ｒｔ２ｂを演算する。時間Ｒｔ１の２倍値は、図２における０からα１までの位相差と、α２からπでの位相差とを加算した位相差に相当する時間である。また、１の値を交流電圧周波数ｆａｃの２倍値で除算した値は、図２における０からπまでの位相差に相当する時間である。従って、第２の時間演算器２０ｃの処理により、図２におけるα１からα２までの位相差に相当する、領域２の時間Ｒｔ２ｂが算出される。スイッチング周波数演算器２０は、時間Ｒｔ２ｂを除算器２０ｄにおいて充放電回数で除算することで、昇圧動作モードにおける領域２のスイッチング周期Ｔｓｗ_２ｂを演算する。 The second time calculator 20c calculates the time Rt2b of the region 2 by subtracting the double value of the time Rt1 of the region 1 from the value obtained by dividing the value of 1 by the double value of the AC voltage frequency fac. The double value of the time Rt1 is the time corresponding to the phase difference obtained by adding the phase difference from 0 to α1 in FIG. 2 and the phase difference from α2 to π. Further, the value obtained by dividing the value of 1 by a double value of the AC voltage frequency fac is the time corresponding to the phase difference from 0 to π in FIG. Therefore, by the processing of the second time calculator 20c, the time Rt2b of the region 2 corresponding to the phase difference from α1 to α2 in FIG. 2 is calculated. The switching frequency calculator 20 calculates the switching cycle Tsw_2b of the region 2 in the boost operation mode by dividing the time Rt2b by the number of charges and discharges in the divider 20d.
　降圧動作の場合、領域３までの動作範囲があるため、別の制御ブロックが設けられている。第３の時間演算器２０ｅは、平滑コンデンサ電圧Ｖｄｃを交流電圧ｖａｃで除算したものを逆三角関数で時間に変換し、更に角周波数２πｆａｃで除算し、更に領域１の時間Ｒｔ１を減算することで領域２の時間Ｒｔ２ｓを演算する。角周波数２πｆａｃで除算した値は、図３における０からβ１までの位相差に相当する時間である。このため、角周波数２πｆａｃで除算した値から領域１の時間Ｒｔ１を減算することで領域２の時間Ｒｔ２ｓを演算することができる。スイッチング周波数演算器２０は、時間Ｒｔ２ｓを除算器２０ｇにおいて充放電回数で除算することで、降圧動作モードにおける領域２のスイッチング周期Ｔｓｗ_２ｓを演算する。 In the case of step-down operation, since there is an operating range up to region 3, another control block is provided. The third time calculator 20e divides the smoothing capacitor voltage Vdc by the AC voltage vac, converts it into time by an inverse trigonometric function, further divides it by the angular frequency 2πfac, and further subtracts the time Rt1 in the region 1. The time Rt2s of the region 2 is calculated. The value divided by the angular frequency 2πfac is the time corresponding to the phase difference from 0 to β1 in FIG. Therefore, the time Rt2s of the region 2 can be calculated by subtracting the time Rt1 of the region 1 from the value divided by the angular frequency 2πfac. The switching frequency calculator 20 calculates the switching cycle Tsw_2s of the region 2 in the step-down operation mode by dividing the time Rt2s by the number of charges and discharges in the divider 20g.
　加算器２０ｈは、領域２の時間Ｒｔ２ｓと、領域１の時間Ｒｔ１とを加算することで、図３における０からβ１までの位相差に相当する時間を再度演算している。第４の時間演算器２０ｉは、１の値を交流電圧周波数ｆａｃの２倍値で除算した値から加算器２０ｈの出力の２倍値を減算することで領域３の時間Ｒｔ３を演算する。加算器２０ｈの出力の２倍値は、図３における０からβ１までの位相差と、β２からπでの位相差とを加算した位相差に相当する時間である。また、１の値を交流電圧周波数ｆａｃの２倍値で除算した値は、図３における０からπまでの位相差に相当する時間である。従って、第４の時間演算器２０ｉの処理により、図３におけるβ１からβ２までの位相差に相当する、領域３の時間Ｒｔ３が算出される。スイッチング周波数演算器２０は、時間Ｒｔ３を除算器２０ｊにおいて充放電回数で除算することで、降圧動作モードにおける領域３のスイッチング周期Ｔｓｗ_３を演算する。 The adder 20h recalculates the time corresponding to the phase difference from 0 to β1 in FIG. 3 by adding the time Rt2s in the region 2 and the time Rt1 in the region 1. The fourth time calculator 20i calculates the time Rt3 in the region 3 by subtracting the double value of the output of the adder 20h from the value obtained by dividing the value of 1 by the double value of the AC voltage frequency fac. The double value of the output of the adder 20h is the time corresponding to the phase difference obtained by adding the phase difference from 0 to β1 in FIG. 3 and the phase difference from β2 to π. Further, the value obtained by dividing the value of 1 by a double value of the AC voltage frequency fac is the time corresponding to the phase difference from 0 to π in FIG. Therefore, by the processing of the fourth time calculator 20i, the time Rt3 of the region 3 corresponding to the phase difference from β1 to β2 in FIG. 3 is calculated. The switching frequency calculator 20 calculates the switching cycle Tsw_3 of the region 3 in the step-down operation mode by dividing the time Rt3 by the number of charges and discharges in the divider 20j.
　なお、スイッチング周波数演算器２０は、演算したスイッチング周期Ｔｓｗ_１，Ｔｓｗ_２ｂ，Ｔｓｗ_２ｓ，Ｔｓｗ_３を周波数変換器２１に出力しているが、これに限定されない。スイッチング周期Ｔｓｗ_１，Ｔｓｗ_２ｂ，Ｔｓｗ_２ｓ，Ｔｓｗ_３の逆数を演算し、それぞれの演算値を動作領域に対応するスイッチング周波数として周波数変換器２１に出力してもよい。 The switching frequency calculator 20 outputs the calculated switching cycles Tsw_1, Tsw_2b, Tsw_2s, and Tsw_3 to the frequency converter 21, but is not limited to this. The reciprocals of the switching cycles Tsw_1, Tsw_2b, Tsw_2s, and Tsw_3 may be calculated, and each calculated value may be output to the frequency converter 21 as the switching frequency corresponding to the operating region.
　また、スイッチング周期Ｔｓｗ_１，Ｔｓｗ_２ｂ，Ｔｓｗ_２ｓ，Ｔｓｗ_３をスイッチング周波数の情報とするとき、時間Ｒｔ１，Ｒｔ２ｂ，Ｒｔ２ｓ，Ｒｔ３は、各スイッチング周波数を演算するための基準スイッチング周波数と捉えることができる。このように捉えると、図１５に示すスイッチング周波数演算器２０は、前段部は動作領域に対応した基準スイッチング周波数を演算し、後段部は基準スイッチング周波数と、第２のコンデンサの充放電回数とに基づいてスイッチング周波数を演算するように構成されている。 Further, when the switching cycles Tsw_1, Tsw_2b, Tsw_2s, and Tsw_3 are used as switching frequency information, the times Rt1, Rt2b, Rt2s, and Rt3 can be regarded as reference switching frequencies for calculating each switching frequency. In this way, in the switching frequency calculator 20 shown in FIG. 15, the front stage portion calculates the reference switching frequency corresponding to the operating region, and the rear stage portion determines the reference switching frequency and the number of times of charging / discharging of the second capacitor. It is configured to calculate the switching frequency based on it.
　周波数変換器２１は、スイッチング周波数演算器２０が演算したスイッチング周期Ｔｓｗ_１，Ｔｓｗ_２ｂ，Ｔｓｗ_２ｓ，Ｔｓｗ_３と、領域判定信号Ｓｉｇ_ＳＰとに基づいて、動作領域に対応したキャリア波を生成して、ゲート信号生成器１８に出力する。 The frequency converter 21 generates a carrier wave corresponding to the operating region based on the switching cycles Tsw_1, Tsw_2b, Tsw_2s, Tsw_3 calculated by the switching frequency calculator 20 and the region determination signal Sig_SP, and is a gate signal generator. Output to 18.
　以下、充放電回数について補足する。充放電回数は、交流半周期で１以上となるように０を含めた整数により設定される。充放電回数は、直流コンデンサ４の容量、主回路部品の耐圧、及び主回路１１０の力率に基づいて決定することができる。充放電回数が少ない場合、スイッチング損失は低減できるが、制御の応答性が悪化し、力率の低下及び電圧リプル量の増加を招く。このため、電力変換装置１００を安定動作させるためには、コンデンサ容量を大きくする必要がある。一方、充放電回数が多い場合には、コンデンサ容量は小さくて済み、制御の応答性も向上するが、スイッチング損失は増加する。 Below, we will supplement the number of charges and discharges. The number of charge / discharge cycles is set by an integer including 0 so as to be 1 or more in an AC half cycle. The number of charge / discharge cycles can be determined based on the capacity of the DC capacitor 4, the withstand voltage of the main circuit component, and the power factor of the main circuit 110. When the number of charge / discharge cycles is small, the switching loss can be reduced, but the responsiveness of the control deteriorates, resulting in a decrease in the power factor and an increase in the amount of voltage ripple. Therefore, in order to operate the power conversion device 100 stably, it is necessary to increase the capacity of the capacitor. On the other hand, when the number of charge / discharge cycles is large, the capacitor capacity can be small and the responsiveness of control is improved, but the switching loss increases.
　図１６は、図１２に示す高力率制御器１７の詳細構成を示すブロック図である。高力率制御器１７は、電流指令演算器１７ａと、電流制御器１７ｂと、ＦＦ_Ｄｕｔｙ演算器１７ｃと、加算器１７ｄとを備える。高力率制御器１７は、交流電圧ｖａｃ、平滑コンデンサ電圧Ｖｄｃ及び交流電流ｉａｃの各検出値に基づいて、主回路１１０の力率が１に近づくように制御しながら、平滑コンデンサ電圧Ｖｄｃを指令値に追従するように制御する制御信号Ｄ_ＰＦＣを生成する。 FIG. 16 is a block diagram showing a detailed configuration of the high power factor controller 17 shown in FIG. The high power factor controller 17 includes a current command calculator 17a, a current controller 17b, an FF_Duty calculator 17c, and an adder 17d. The high power factor controller 17 commands the smoothing capacitor voltage Vdc while controlling the power factor of the main circuit 110 to approach 1 based on the detected values of the AC voltage vac, the smoothing capacitor voltage Vdc, and the AC current iac. A control signal D_PFC that controls to follow the value is generated.
　電流指令演算器１７ａは、平滑コンデンサ電圧指令Ｖｄｃ＊と平滑コンデンサ電圧Ｖｄｃの検出値との偏差を比例積分（Ｐｒｏｐｏｒｔｉｏｎａｌ　Ｉｎｔｅｇｒａｌ：ＰＩ）制御することで、電流指令振幅Ｉａｃ＊を演算する。電流指令演算器１７ａは、電流指令振幅Ｉａｃ＊に位相同期ループ（Ｐｈａｓｅ　Ｌｏｃｋｅｄ　Ｌｏｏｐ：ＰＬＬ）制御で生成された交流電圧ｖａｃと同位相の正弦波信号Ｓｉｎ（ωｔ）を乗算して交流電流指令ｉａｃ＊を演算する。なお、平滑コンデンサ電圧Ｖｄｃの電圧制御を行わず、交流電流ｉａｃの高力率制御のみを行う場合には、交流電流指令ｉａｃ＊をユーザが任意に決定、もしくは設定してもよい。 The current command calculator 17a calculates the current command amplitude Iac * by controlling the deviation between the smoothing capacitor voltage command Vdc * and the detected value of the smoothing capacitor voltage Vdc by proportional integral (PI). The current command calculator 17a multiplies the current command amplitude Iac * by the AC voltage vac generated by the phase-locked loop (PLL) control and the sinusoidal signal Sin (ωt) having the same phase, and the AC current command iac. * Is calculated. When the smoothing capacitor voltage Vdc is not controlled and only the high power factor control of the AC current iac is performed, the user may arbitrarily determine or set the AC current command iac *.
　電流制御器１７ｂは、交流電流指令ｉａｃ＊と交流電流ｉａｃとの偏差をＰＩ制御し、その制御値を直流コンデンサ電圧指令Ｖｓｕｂ＊で割ることで規格化した制御デューティ比Ｄ_ＰＦＣ１を演算する。加算器１７ｄは、制御デューティ比Ｄ_ＰＦＣ１と、ＦＦ_Ｄｕｔｙ演算器１７ｃで演算されたＦＦ_Ｄｕｔｙ比Ｄ_ＰＦＣ_ＦＦとを加算し、その加算値を高力率制御用のＦＦ_Ｄｕｔｙ比Ｄ_ＰＦＣとして、図１２の加算器１２ａに出力する。ＦＦ_Ｄｕｔｙ比Ｄ_ＰＦＣ_ＦＦを制御デューティ比Ｄ_ＰＦＣ１に加えることで、高力率制御の応答性を向上させることができる。 The current controller 17b performs PI control of the deviation between the AC current command iac * and the AC current iac, and calculates the standardized control duty ratio D_PFC1 by dividing the control value by the DC capacitor voltage command Vsub *. The adder 17d adds the control duty ratio D_PFC1 and the FF_Duty ratio D_PFC_FF calculated by the FF_Duty calculator 17c, and outputs the added value as the FF_Duty ratio D_PFC for high power rate control to the adder 12a in FIG. do. By adding the FF_Duty ratio D_PFC_FF to the control duty ratio D_PFC1, the responsiveness of the high power factor control can be improved.
　実施の形態２に係る電力変換装置１００では、動作領域に応じて、制御デューティ比Ｄ_ＰＦＣ１を切り替える動作となるため、ＦＦ制御を入れることで、制御の切り替え時における電流変動を抑制することができる。 In the power conversion device 100 according to the second embodiment, the control duty ratio D_PFC1 is switched according to the operating region. Therefore, by inserting the FF control, the current fluctuation at the time of switching the control can be suppressed.
　ＦＦ制御用のＦＦ_Ｄｕｔｙ比Ｄ_ＰＦＣ_ＦＦは、リアクトル２の励磁及びリセットに伴う交流電流ｉａｃの増減量が等しくなるような、理論デューティ比を演算する。理論デューティ比の算出手法については、上記した特許文献１に詳細に記載されているので、当該記載内容を参照されたい。当該記載内容は、本明細書に取り込まれて本明細書の一部を構成する。理論デューティ比の算出手法は、当該公報の記載内容に限定されるものでもなく、理論デューティ比が得られる手法であればどのような手法を用いてもよい。 The FF_Duty ratio D_PFC_FF for FF control calculates the theoretical duty ratio so that the amount of increase / decrease in the AC current iac due to the excitation and reset of the reactor 2 becomes equal. The method for calculating the theoretical duty ratio is described in detail in Patent Document 1 described above, so please refer to the description. The contents of the description are incorporated in the present specification and form a part of the present specification. The method for calculating the theoretical duty ratio is not limited to the contents described in the publication, and any method may be used as long as the theoretical duty ratio can be obtained.
　実施の形態２においても、実施の形態１と同様に、直流コンデンサ４の充電と放電とが、交流半周期において同一回数となるような励磁及びリセットの組が選択される。ＦＦ_Ｄｕｔｙ演算器１７ｃは、選択された励磁及びリセットの組に関する情報に基づいて理論デューティ比を演算する。 Also in the second embodiment, as in the first embodiment, a set of excitation and reset is selected so that the charging and discharging of the DC capacitor 4 have the same number of times in the AC half cycle. The FF_Duty calculator 17c calculates the theoretical duty ratio based on information about the selected excitation and reset pairs.
　図１７は、図１２に示すゲート信号生成器１８の詳細構成を示すブロック図である。ゲート信号生成器１８は、比較部１８ａと、パルス演算器１８ｂとを備える。また、比較部１８ａは、第１比較器１８ａ１と、乗算器１８ａ２と、第２比較器１８ａ３とを備える。 FIG. 17 is a block diagram showing a detailed configuration of the gate signal generator 18 shown in FIG. The gate signal generator 18 includes a comparison unit 18a and a pulse calculator 18b. Further, the comparison unit 18a includes a first comparator 18a1, a multiplier 18a2, and a second comparator 18a3.
　デューティ比総和量Ｄ_ｔｏｔａｌは、乗算器１８ａ２を介して第２比較器１８ａ３の＋端子に入力され、キャリア波は第２比較器１８ａ３の－端子に入力される。第２比較器１８ａ３では、デューティ比総和量Ｄ_ｔｏｔａｌとキャリア波の振幅値とが比較され、デューティ比総和量Ｄ_ｔｏｔａｌがキャリア波の振幅値よりも大きければ、スイッチング素子を導通させるオン信号が生成される。パルス演算器１８ｂは、比較部１８ａから出力されるオン信号及び領域判定信号Ｓｉｇ_ＳＰを用いてゲート信号Ｇ３ａ～Ｇ３ｄ，Ｇ５ｂ，Ｇ５ｄを生成する。ゲート信号Ｇ３ａ～Ｇ３ｄ，Ｇ５ｂ，Ｇ５ｄは、それぞれスイッチング素子３ａ～３ｄ，５ｂ，５ｄに印加され、スイッチング素子３ａ～３ｄ，５ｂ，５ｄの導通が制御される。 The total duty ratio amount D_total is input to the + terminal of the second comparator 18a3 via the multiplier 18a2, and the carrier wave is input to the-terminal of the second comparator 18a3. In the second comparator 18a3, the total duty ratio D_total and the amplitude value of the carrier wave are compared, and if the total duty ratio D_total is larger than the amplitude value of the carrier wave, an on signal for conducting the switching element is generated. .. The pulse calculator 18b generates gate signals G3a to G3d, G5b, and G5d using the on signal output from the comparison unit 18a and the region determination signal Sig_SP. The gate signals G3a to G3d, G5b, and G5d are applied to the switching elements 3a to 3d, 5b, and 5d, respectively, and the conduction of the switching elements 3a to 3d, 5b, and 5d is controlled.
　なお、図１７では、充放電回数が０のときの制御を実現するため、第１比較器１８ａ１と、乗算器１８ａ２とが設けられている。図１７の構成では、充放電回数が０のときに第１比較器１８ａ１の出力は０となり、乗算器１８ａ２の出力も０となるので、第２比較器１８ａ３に入力されるデューティ比総和量Ｄ_ｔｏｔａｌも０となる。なお、図１７の構成は一例であり、これらの構成に限定されない。例えば、デューティ比総和量Ｄ_ｔｏｔａｌがキャリア波の振幅値よりも小さいときにスイッチング素子を導通させるオン信号が生成される構成でもよい。 Note that, in FIG. 17, a first comparator 18a1 and a multiplier 18a2 are provided in order to realize control when the number of charge / discharge cycles is 0. In the configuration of FIG. 17, when the number of charge / discharge cycles is 0, the output of the first comparator 18a1 becomes 0 and the output of the multiplier 18a2 also becomes 0. Therefore, the total duty ratio input to the second comparator 18a3 is D_total. Is also 0. The configuration of FIG. 17 is an example and is not limited to these configurations. For example, an on-signal for conducting the switching element may be generated when the total duty ratio D_total is smaller than the amplitude value of the carrier wave.
　以上の制御により、実施の形態２の電力変換装置１００では、第１のコンデンサ電圧の制御を通じて、負荷７への所要の電力供給が可能となる。また、第１のコンデンサ電圧の制御を行いつつ、第２のコンデンサ電圧を指令値に追従させる電圧一定制御が可能となる。 With the above control, in the power conversion device 100 of the second embodiment, the required power can be supplied to the load 7 through the control of the first capacitor voltage. Further, it is possible to control the voltage constant so that the second capacitor voltage follows the command value while controlling the first capacitor voltage.
　また、実施の形態２においても、交流半周期におけるスイッチング回数は、多くても２０回である。従って、実施の形態２では、主回路１１０のスイッチング素子３ａ～３ｄ，５ｂ，５ｄに対し、交流電圧半周期で十数回以下のスイッチング回数によるスイッチング制御により、第１のコンデンサ電圧の制御と、第２のコンデンサ電圧を指令値に追従させる電圧一定制御とを両立して実施することができる。 Further, also in the second embodiment, the number of switchings in the AC half cycle is at most 20 times. Therefore, in the second embodiment, the first capacitor voltage is controlled by the switching control of the switching elements 3a to 3d, 5b, 5d of the main circuit 110 by the number of switchings of 10 or less times in the AC voltage half cycle. It is possible to carry out both constant voltage control that causes the second capacitor voltage to follow the command value.
　以上説明したように、実施の形態２に係る電力変換装置によれば、制御器は、第１及び第２のコンデンサ電圧の各検出値と、交流電圧の検出値との大小関係に応じて、動作領域を判定し、第１及び第２のコンデンサ電圧の各検出値、並びに交流電圧の検出値に基づいて、動作領域ごとに、スイッチング周波数を変更しながらスイッチング制御を行う。この制御により、スイッチング素子のスイッチング損失及びリアクトルの高周波損失を低減しつつ、主回路動作の力率を高めることができる。これにより、電力変換装置を高効率に駆動することができる。 As described above, according to the power conversion device according to the second embodiment, the controller responds to the magnitude relationship between the detected values of the first and second capacitor voltages and the detected values of the AC voltage. The operating region is determined, and switching control is performed while changing the switching frequency for each operating region based on the detected values of the first and second capacitor voltages and the detected value of the AC voltage. By this control, the power factor of the main circuit operation can be increased while reducing the switching loss of the switching element and the high frequency loss of the reactor. As a result, the power conversion device can be driven with high efficiency.
　なお、上記の制御において、制御器は、同一のスイッチング周波数が維持される期間である第１のスイッチング期間において、第２のコンデンサの充電及び放電を各１回以上行い、且つ、充電の回数と放電の回数とが第１のスイッチング期間内で等しくなるようにスイッチング制御を行うことが好ましい。これにより、第２のコンデンサ電圧を指令値に追従させる電圧一定制御を確実に実施することができる。 In the above control, the controller charges and discharges the second capacitor once or more in the first switching period, which is the period in which the same switching frequency is maintained, and the number of times of charging. It is preferable to perform switching control so that the number of discharges becomes equal within the first switching period. As a result, constant voltage control that causes the second capacitor voltage to follow the command value can be reliably performed.
　また、上記の制御において、第１のコンデンサ電圧を制御するための第１のデューティ比と、第２のコンデンサ電圧を制御するための第２のデューティ比との和であるデューティ比総和量に対し、制御器は、第１のスイッチング期間内におけるデューティ比総和量が一定に保たれるように第２のデューティ比を第１のデューティ比に加減算するようにしてもよい。これにより、第１のコンデンサ電圧の制御と、第２のコンデンサ電圧を指令値に追従させる電圧一定制御とを両立して実施することができる。 Further, in the above control, with respect to the total duty ratio, which is the sum of the first duty ratio for controlling the first capacitor voltage and the second duty ratio for controlling the second capacitor voltage. The controller may add or subtract the second duty ratio to the first duty ratio so that the total amount of duty ratios in the first switching period is kept constant. As a result, it is possible to carry out both the control of the first capacitor voltage and the constant voltage control for making the second capacitor voltage follow the command value.
　また、上記の制御において、制御器は、動作領域ごとに交流電圧と第２のコンデンサ電圧が交差する第１の位相、及び交流電圧と第１のコンデンサ電圧とが交差する第２の位相から基準スイッチング周波数を演算する。制御器は、予め定めた第２のコンデンサの充電回数及び放電回数と、演算で求めた基準スイッチング周波数とに基づいてスイッチング周波数を演算するようにしてもよい。この手法を用いれば、複数の動作領域におけるスイッチング周波数を纏めて演算できるので、動作領域の切り替えに迅速に対応することが可能である。 Further, in the above control, the controller refers from the first phase at which the AC voltage and the second capacitor voltage intersect and the second phase at which the AC voltage and the first capacitor voltage intersect for each operating region. Calculate the switching frequency. The controller may calculate the switching frequency based on the predetermined number of times of charging and discharging of the second capacitor and the reference switching frequency obtained by the calculation. By using this method, the switching frequencies in a plurality of operating regions can be collectively calculated, so that it is possible to quickly respond to the switching of the operating regions.
　また、上記の制御において、制御器は、第１のスイッチング期間内において、第２のコンデンサ電圧を制御するフィードバックデューティ比に、リアクトルの励磁及びリセットに伴う交流電流の増減量が等しくなるような理論デューティ比を加えるようにしてもよい。これにより、動作領域間の切り替えを円滑に行うことができる。 Further, in the above control, the controller has a theory that the amount of increase / decrease in the alternating current due to the excitation and reset of the reactor becomes equal to the feedback duty ratio for controlling the second capacitor voltage within the first switching period. A duty ratio may be added. This makes it possible to smoothly switch between operating areas.
実施の形態３．
　図１８は、実施の形態３に係る電力変換装置１００Ａの基本回路構成を示す図である。実施の形態３における電力変換装置１００Ａは、図１に示す実施の形態１に係る電力変換装置１００の構成において、リアクトル２よりも交流電源１側にダイオードブリッジ２４が設けられている。この構成により、図１８では、主回路１１０のサブコンバータ３に具備されるスイッチング素子３ａ，３ｄが、それぞれダイオード３ａ’，３ｄ’に置き替えられている。また、図１８では、主回路１１０のメインコンバータ５に具備されるスイッチング素子５ｄが、ダイオード５ｄ’に置き替えられている。なお、その他の構成については、図１に示す構成と同一又は同等であり、同一又は同等の構成部には、同一の符号を付して、重複する説明は割愛する。 Embodiment 3.
FIG. 18 is a diagram showing a basic circuit configuration of the power conversion device 100A according to the third embodiment. In the power conversion device 100A according to the third embodiment, the diode bridge 24 is provided on the AC power supply 1 side of the reactor 2 in the configuration of the power conversion device 100 according to the first embodiment shown in FIG. With this configuration, in FIG. 18, the switching elements 3a and 3d provided in the subconverter 3 of the main circuit 110 are replaced with the diodes 3a'and 3d', respectively. Further, in FIG. 18, the switching element 5d provided in the main converter 5 of the main circuit 110 is replaced with the diode 5d'. The other configurations are the same as or equivalent to the configurations shown in FIG. 1, and the same or equivalent components are designated by the same reference numerals, and duplicate explanations are omitted.
　実施の形態３に係る電力変換装置１００Ａの場合、サブコンバータ３には、ダイオードブリッジ２４によって全波整流された電圧波形が印加される。このため、実施の形態３における制御器８の動作は、負の半波の動作がなく、正の半波のみの動作となる。このため、実施の形態１又は実施の形態２における制御器８の機能をそのまま用いることができる。なお、正の半波の動作は、実施の形態１及び実施の形態２と同様であり、ここでの説明は割愛する。 In the case of the power conversion device 100A according to the third embodiment, a voltage waveform rectified by a diode bridge 24 is applied to the subconverter 3. Therefore, the operation of the controller 8 in the third embodiment has no negative half-wave operation and is only a positive half-wave operation. Therefore, the function of the controller 8 in the first embodiment or the second embodiment can be used as it is. The positive half-wave operation is the same as that of the first and second embodiments, and the description thereof is omitted here.
　実施の形態３に係る電力変換装置１００Ａによれば、実施の形態１及び実施の形態２と比べて、スイッチング素子数を減らすことができるので、スイッチング損失の低減が可能となる。また、ダイオードの方がスイッチング素子よりも安価に入手できるため、装置の低コスト化が可能となる。 According to the power conversion device 100A according to the third embodiment, the number of switching elements can be reduced as compared with the first embodiment and the second embodiment, so that the switching loss can be reduced. Further, since the diode can be obtained at a lower cost than the switching element, the cost of the device can be reduced.
　また、実施の形態３に係る電力変換装置１００Ａによれば、制御器８の動作は、正の半波のみの動作となる。このため、実施の形態１及び実施の形態２と比べて、制御器８の機能を簡略化することができる。これにより、装置の低コスト化が可能となる。 Further, according to the power conversion device 100A according to the third embodiment, the operation of the controller 8 is only a positive half wave operation. Therefore, the function of the controller 8 can be simplified as compared with the first embodiment and the second embodiment. This makes it possible to reduce the cost of the device.
実施の形態４．
　実施の形態４では、実施の形態１で説明した電力変換装置１００のモータ駆動装置への適用例について説明する。図１９は、実施の形態４に係るモータ駆動装置１５０の構成例を示す図である。図１９に示す実施の形態４に係るモータ駆動装置１５０では、図１に示す電力変換装置１００の構成に、インバータ７ａ及びモータ７ｂが追加されている。 Embodiment 4.
In the fourth embodiment, an example of application of the power conversion device 100 described in the first embodiment to the motor drive device will be described. FIG. 19 is a diagram showing a configuration example of the motor drive device 150 according to the fourth embodiment. In the motor drive device 150 according to the fourth embodiment shown in FIG. 19, the inverter 7a and the motor 7b are added to the configuration of the power conversion device 100 shown in FIG.
　インバータ７ａの出力側には、モータ７ｂが接続されている。モータ７ｂは、負荷機器の一例である。インバータ７ａは、平滑コンデンサ６に蓄積された直流電力を交流電力に変換し、変換した交流電力をモータ７ｂに供給することでモータ７ｂを駆動する。 A motor 7b is connected to the output side of the inverter 7a. The motor 7b is an example of a load device. The inverter 7a drives the motor 7b by converting the DC power stored in the smoothing capacitor 6 into AC power and supplying the converted AC power to the motor 7b.
　図１９に示すモータ駆動装置１５０は、送風機、圧縮機及び空気調和機といった製品に適用することが可能である。なお、図１９では、実施の形態１に係る電力変換装置１００を適用してモータ駆動装置１５０を構成したが、これに限定されない。実施の形態１に係る電力変換装置１００に代えて、実施の形態２に係る電力変換装置１００、又は実施の形態３に係る電力変換装置１００Ａを用いて構成してもよい。 The motor drive device 150 shown in FIG. 19 can be applied to products such as blowers, compressors and air conditioners. In FIG. 19, the power conversion device 100 according to the first embodiment is applied to configure the motor drive device 150, but the present invention is not limited to this. Instead of the power conversion device 100 according to the first embodiment, the power conversion device 100 according to the second embodiment or the power conversion device 100A according to the third embodiment may be used.
　図２０は、図１９に示すモータ駆動装置１５０を空気調和機に適用した例を示す図である。モータ駆動装置１５０の出力側にはモータ７ｂが接続されており、モータ７ｂは、圧縮要素５０４に連結されている。圧縮機５０５は、モータ７ｂと圧縮要素５０４とを備える。冷凍サイクル部５０６は、四方弁５０６ａ、室内熱交換器５０６ｂ、膨張弁５０６ｃ及び室外熱交換器５０６ｄを含む態様で構成されている。 FIG. 20 is a diagram showing an example in which the motor drive device 150 shown in FIG. 19 is applied to an air conditioner. A motor 7b is connected to the output side of the motor drive device 150, and the motor 7b is connected to the compression element 504. The compressor 505 includes a motor 7b and a compression element 504. The refrigeration cycle unit 506 is configured to include a four-way valve 506a, an indoor heat exchanger 506b, an expansion valve 506c, and an outdoor heat exchanger 506d.
　空気調和機の内部を循環する冷媒の流路は、圧縮要素５０４から、四方弁５０６ａ、室内熱交換器５０６ｂ、膨張弁５０６ｃ、室外熱交換器５０６ｄを経由し、再び四方弁５０６ａを経由して、圧縮要素５０４へ戻る態様で構成されている。モータ駆動装置１５０は、交流電源１より電力の供給を受け、モータ７ｂを回転させる。圧縮要素５０４は、モータ７ｂが回転することによって、冷媒の圧縮動作を実行し、冷媒を冷凍サイクル部５０６の内部で循環させることができる。 The flow path of the refrigerant circulating inside the air conditioner is from the compression element 504 via the four-way valve 506a, the indoor heat exchanger 506b, the expansion valve 506c, the outdoor heat exchanger 506d, and again via the four-way valve 506a. , It is configured to return to the compression element 504. The motor drive device 150 receives electric power from the AC power supply 1 and rotates the motor 7b. The compression element 504 can execute the compression operation of the refrigerant by rotating the motor 7b, and the refrigerant can be circulated inside the refrigeration cycle unit 506.
　実施の形態４に係るモータ駆動装置１５０は、実施の形態１から実施の形態３に係る電力変換装置を備えて構成される。これにより、実施の形態４に係るモータ駆動装置を適用した送風機、圧縮機及び空気調和機といった製品において、実施の形態１から実施の形態３で説明した効果を得ることができる。 The motor drive device 150 according to the fourth embodiment is configured to include the power conversion device according to the first to third embodiments. Thereby, in the products such as the blower, the compressor and the air conditioner to which the motor drive device according to the fourth embodiment is applied, the effects described in the first to third embodiments can be obtained.
　なお、以上の実施の形態に示した構成は、本発明の内容の一例を示すものであり、別の公知の技術と組み合わせることも可能であるし、本発明の要旨を逸脱しない範囲で、構成の一部を省略、変更することも可能である。 The configuration shown in the above embodiments is an example of the content of the present invention, can be combined with another known technique, and is configured without departing from the gist of the present invention. It is also possible to omit or change a part of.
　１　交流電源、２　リアクトル、３　サブコンバータ、３ａ～３ｄ，５ｂ，５ｄ　スイッチング素子、３ａ’，３ｄ’，５ａ，５ｃ，５ｄ’　ダイオード、４　直流コンデンサ、５　メインコンバータ、６　平滑コンデンサ、７　負荷、７ａ　インバータ、７ｂ　モータ、８，８Ａ　制御器、８ａ　プロセッサ、８ｂ　メモリ、９　動作領域判定器、１０，１７ｃ　ＦＦ_Ｄｕｔｙ演算器、１１　直流コンデンサ電圧制御器、１１ａ　前処理器、１１ｂ　サンプルホールド器、１２　加減算判定器、１２ａ，１６ｈ，１７ｄ　加算器、１３，１８　ゲート信号生成器、１６　キャリア波生成器、１７　高力率制御器、１７ａ　電流指令演算器、１７ｂ　電流制御器、１８ａ　比較部、１８ａ１　第１比較器、１８ａ２　乗算器、１８ａ３　第２比較器、１８ｂ　パルス演算器、２０　スイッチング周波数演算器、２０ａ　第１の時間演算器、２０ｂ，２０ｄ，２０ｇ，２０ｊ　除算器、２０ｃ　第２の時間演算器、２０ｅ　第３の時間演算器、２０ｉ　第４の時間演算器、２１　周波数変換器、２４　ダイオードブリッジ、３０，３１，３３　電圧検出器、３２　電流検出器、１００，１００Ａ　電力変換装置、１１０　主回路、１５０　モータ駆動装置、５０４　圧縮要素、５０５　圧縮機、５０６　冷凍サイクル部、５０６ａ　四方弁、５０６ｂ　室内熱交換器、５０６ｃ　膨張弁、５０６ｄ　室外熱交換器。 1 AC power supply, 2 reactor, 3 subconverter, 3a to 3d, 5b, 5d switching element, 3a', 3d', 5a, 5c, 5d' diode, 4 DC capacitor, 5 main converter, 6 smoothing capacitor, 7 load, 7a inverter, 7b motor, 8,8A controller, 8a processor, 8b memory, 9 operating area judge, 10,17c FF_Duty calculator, 11 DC capacitor voltage controller, 11a preprocessing device, 11b sample holder, 12 addition / subtraction Judge, 12a, 16h, 17d adder, 13,18 gate signal generator, 16 carrier wave generator, 17 high voltage controller, 17a current command calculator, 17b current controller, 18a comparison unit, 18a1 first Comparer, 18a2 multiplier, 18a3 second comparer, 18b pulse calculator, 20 switching frequency calculator, 20a first time calculator, 20b, 20d, 20g, 20j divider, 20c second time calculator, 20e 3rd time calculator, 20i 4th time calculator, 21 frequency converter, 24 diode bridge, 30, 31, 33 voltage detector, 32 current detector, 100, 100A power converter, 110 main circuit, 150 motor drive, 504 compression element, 505 compressor, 506 refrigeration cycle section, 506a four-way valve, 506b indoor heat exchanger, 506c expansion valve, 506d outdoor heat exchanger.

Claims (14)

  1. 　少なくとも１つのリアクトルと、複数のスイッチング素子と、第１のコンデンサと、前記リアクトルと前記第１のコンデンサとの間に設けられる第２のコンデンサと、前記スイッチング素子の導通を制御する制御器と、を備え、前記リアクトル、前記スイッチング素子、前記第１のコンデンサ及び前記第２のコンデンサは、交流電源と直流負荷との間に設けられ、
    　前記交流電源の交流電圧と前記第１のコンデンサの電圧である第１のコンデンサ電圧との間で電力変換を行う電力変換装置において、
    　前記制御器は、前記スイッチング素子を前記交流電圧の半周期で１回以上、２０回以下のスイッチング回数でスイッチング制御する
    　電力変換装置。     An at least one reactor, a plurality of switching elements, a first capacitor, a second capacitor provided between the reactor and the first capacitor, and a controller for controlling the conduction of the switching element. The reactor, the switching element, the first capacitor and the second capacitor are provided between an AC power supply and a DC load.
    In a power conversion device that performs power conversion between the AC voltage of the AC power supply and the first capacitor voltage which is the voltage of the first capacitor.
    The controller is a power conversion device that controls switching of the switching element by switching the switching element once or more and 20 times or less in a half cycle of the AC voltage.
  2. 　前記制御器は、前記交流電圧の半周期の期間内で前記第２のコンデンサの充電量と放電量とを制御して、前記第２のコンデンサの電圧である第２のコンデンサ電圧を前記第２のコンデンサ電圧の指令値に一致させる制御を行う
    　請求項１に記載の電力変換装置。     The controller controls the charge amount and the discharge amount of the second capacitor within a half cycle period of the AC voltage, and sets the second capacitor voltage, which is the voltage of the second capacitor, to the second capacitor. The power conversion device according to claim 1, wherein the control is performed so as to match the command value of the capacitor voltage of the above.
  3. 　前記第１のコンデンサ電圧を検出する第１の電圧検出器と、前記第２のコンデンサ電圧を検出する第２の電圧検出器と、前記交流電圧を検出する第３の電圧検出器と、を備え、
    　前記制御器は、前記第１及び第２のコンデンサ電圧の各検出値と、前記交流電圧の検出値との大小関係に応じて、動作領域を判定し、前記第１及び第２のコンデンサ電圧の各検出値、並びに前記交流電圧の検出値に基づいて、前記第２のコンデンサを充電する充電時間及び前記第２のコンデンサを放電させる放電時間を変更しながら前記スイッチング制御を行う
    　請求項２に記載の電力変換装置。     A first voltage detector for detecting the first capacitor voltage, a second voltage detector for detecting the second capacitor voltage, and a third voltage detector for detecting the AC voltage are provided. ,
    The controller determines the operating region according to the magnitude relationship between the detected values of the first and second capacitor voltages and the detected values of the AC voltage, and determines the operating region of the first and second capacitor voltages. The second aspect of claim 2, wherein the switching control is performed while changing the charging time for charging the second capacitor and the discharging time for discharging the second capacitor based on each detected value and the detected value of the AC voltage. Power converter.
  4. 　前記制御器は、前記交流電圧の半周期内で前記第２のコンデンサの充電及び放電を各１回以上行い、且つ、前記充電の回数と前記放電の回数とが前記交流電圧の半周期内で等しくなるように前記スイッチング制御を行う
    　請求項３に記載の電力変換装置。     The controller charges and discharges the second capacitor once or more within a half cycle of the AC voltage, and the number of times of charging and the number of times of discharging are within the half cycle of the AC voltage. The power conversion device according to claim 3, wherein the switching control is performed so as to be equal to each other.
  5. 　前記第１のコンデンサ電圧を制御するための第１のデューティ比と、前記第２のコンデンサ電圧を制御するための第２のデューティ比との和であるデューティ比総和量に対し、
    　前記制御器は、前記交流電圧の半周期内における前記デューティ比総和量が一定に保たれるように、前記第２のデューティ比を前記第１のデューティ比に加減算する
    　請求項２から４の何れか１項に記載の電力変換装置。     With respect to the total duty ratio, which is the sum of the first duty ratio for controlling the first capacitor voltage and the second duty ratio for controlling the second capacitor voltage.
    The controller adds or subtracts the second duty ratio to or subtracts the first duty ratio so that the total amount of the duty ratios in the half cycle of the AC voltage is kept constant. The power conversion device according to item 1.
  6. 　前記第１のコンデンサ電圧を検出する第１の電圧検出器と、前記第２のコンデンサ電圧を検出する第２の電圧検出器と、前記交流電圧を検出する第３の電圧検出器と、を備え、
    　前記制御器は、前記第１及び第２のコンデンサ電圧の各検出値と、前記交流電圧の検出値との大小関係に応じて、動作領域を判定し、前記第１及び第２のコンデンサ電圧の各検出値、並びに前記交流電圧の検出値に基づいて、前記動作領域ごとに、スイッチング周波数を変更しながら前記スイッチング制御を行う
    　請求項２に記載の電力変換装置。     A first voltage detector for detecting the first capacitor voltage, a second voltage detector for detecting the second capacitor voltage, and a third voltage detector for detecting the AC voltage are provided. ,
    The controller determines the operating region according to the magnitude relationship between the detected values of the first and second capacitor voltages and the detected values of the AC voltage, and determines the operating region of the first and second capacitor voltages. The power conversion device according to claim 2, wherein the switching control is performed while changing the switching frequency for each operating region based on each detected value and the detected value of the AC voltage.
  7. 　前記制御器は、同一のスイッチング周波数が維持される期間である第１のスイッチング期間において、前記第２のコンデンサの充電及び放電を各１回以上行い、且つ、前記充電の回数と前記放電の回数とが前記第１のスイッチング期間内で等しくなるように前記スイッチング制御を行う
    　請求項６に記載の電力変換装置。     The controller charges and discharges the second capacitor once or more in each of the first switching period, which is a period in which the same switching frequency is maintained, and the number of times of the charge and the number of times of the discharge. The power conversion device according to claim 6, wherein the switching control is performed so that and the power are equal to each other within the first switching period.
  8. 　前記第１のコンデンサ電圧を制御するための第１のデューティ比と、前記第２のコンデンサ電圧を制御するための第２のデューティ比との和であるデューティ比総和量に対し、
    　前記制御器は、前記第１のスイッチング期間内における前記デューティ比総和量が一定に保たれるように前記第２のデューティ比を前記第１のデューティ比に加減算する
    　請求項７に記載の電力変換装置。     With respect to the total duty ratio, which is the sum of the first duty ratio for controlling the first capacitor voltage and the second duty ratio for controlling the second capacitor voltage.
    The power conversion according to claim 7, wherein the controller adds or subtracts the second duty ratio to the first duty ratio so that the total amount of the duty ratios is kept constant within the first switching period. Device.
  9. 　前記制御器は、前記動作領域ごとに前記交流電圧と前記第２のコンデンサ電圧が交差する第１の位相、及び前記交流電圧と前記第１のコンデンサ電圧とが交差する第２の位相から基準スイッチング周波数を演算し、予め定めた前記第２のコンデンサの充電回数及び放電回数と、前記基準スイッチング周波数とに基づいて前記スイッチング周波数を演算する
    　請求項７又は８に記載の電力変換装置。     The controller performs reference switching from the first phase at which the AC voltage and the second capacitor voltage intersect and the second phase at which the AC voltage and the first capacitor voltage intersect for each operating region. The power conversion device according to claim 7 or 8, wherein the frequency is calculated and the switching frequency is calculated based on the predetermined number of times of charging and discharging of the second capacitor and the reference switching frequency.
  10. 　前記制御器は、前記第１のスイッチング期間内において、前記第２のコンデンサ電圧を制御するフィードバックデューティ比に、前記リアクトルの励磁及びリセットに伴う交流電流の増減量が等しくなるような理論デューティ比を加える
    　請求項７から９の何れか１項に記載の電力変換装置。     The controller has a theoretical duty ratio such that the feedback duty ratio for controlling the second capacitor voltage is equal to the increase / decrease amount of the alternating current due to the excitation and reset of the reactor within the first switching period. The power conversion device according to any one of claims 7 to 9.
  11. 　請求項１から１０の何れか１項に記載の電力変換装置と、
    　前記電力変換装置から出力される直流電力を交流電力に変換するインバータと、を備える
    　モータ駆動装置。     The power conversion device according to any one of claims 1 to 10.
    A motor drive device including an inverter that converts DC power output from the power conversion device into AC power.
  12. 　請求項１１に記載のモータ駆動装置を備える
    　送風機。     A blower comprising the motor driving device according to claim 11.
  13. 　請求項１１に記載のモータ駆動装置を備える
    　圧縮機。     A compressor comprising the motor driving device according to claim 11.
  14. 　請求項１２に記載の送風機及び請求項１３に記載の圧縮機の少なくとも一方を備える
    　空気調和機。     An air conditioner comprising at least one of the blower according to claim 12 and the compressor according to claim 13.
PCT/JP2020/020782 2020-05-26 2020-05-26 Power conversion device, motor drive device, blower, compressor, and air conditioner WO2021240657A1 (en)

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JPH0789742B2 (en) * 1987-02-18 1995-09-27 三菱電機株式会社 Power converter
JPH11164561A (en) * 1997-11-26 1999-06-18 Toshiba Corp Dc power supply equipment and air conditioner
JP2000278955A (en) 1999-01-19 2000-10-06 Matsushita Electric Ind Co Ltd Power unit and air conditioner using the same
JP4337316B2 (en) 2001-09-28 2009-09-30 ダイキン工業株式会社 Power converter
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