WO2021239038A1 - 数据线和充电设备 - Google Patents

数据线和充电设备 Download PDF

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Publication number
WO2021239038A1
WO2021239038A1 PCT/CN2021/096260 CN2021096260W WO2021239038A1 WO 2021239038 A1 WO2021239038 A1 WO 2021239038A1 CN 2021096260 W CN2021096260 W CN 2021096260W WO 2021239038 A1 WO2021239038 A1 WO 2021239038A1
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WO
WIPO (PCT)
Prior art keywords
pin
interface
circuit
terminal
switch
Prior art date
Application number
PCT/CN2021/096260
Other languages
English (en)
French (fr)
Inventor
罗方丁
张涛
Original Assignee
维沃移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 维沃移动通信有限公司 filed Critical 维沃移动通信有限公司
Priority to EP21812216.6A priority Critical patent/EP4160856A4/en
Publication of WO2021239038A1 publication Critical patent/WO2021239038A1/zh
Priority to US18/070,609 priority patent/US20230101861A1/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0042—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by the mechanical construction
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00034—Charger exchanging data with an electronic device, i.e. telephone, whose internal battery is under charge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/70—Structural association with built-in electrical component with built-in switch
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/00032—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by data exchange
    • H02J7/00045—Authentication, i.e. circuits for checking compatibility between one component, e.g. a battery or a battery charger, and another component, e.g. a power source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/70—Structural association with built-in electrical component with built-in switch
    • H01R13/701—Structural association with built-in electrical component with built-in switch the switch being actuated by an accessory, e.g. cover, locking member
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J2207/30—Charge provided using DC bus or data bus of a computer

Definitions

  • This application belongs to the field of communication technology, and specifically relates to a data cable and a charging device.
  • the power delivery (PD) protocol is usually used for fast charging, and the charger that supports PD protocol charging needs to use the configuration channel (Configuration Channel, CC) signal line to communicate, and the charging that supports PD protocol charging
  • the device usually adopts the third standard (Type-C) interface and is matched with a Type-C to Type-C data line.
  • Type-A or Standard-A which communicates through the D+/D- signal line, it cannot support PD protocol charging.
  • the most widely used data line is a data line with a Type-A interface, so that the Type-A interface on a conventional data line does not support PD protocol charging.
  • the purpose of the embodiments of the present application is to provide a data cable and a charging device, which can solve the problem that a data cable with a Type-A interface does not support PD protocol charging.
  • an embodiment of the present application provides a data cable that includes a Type-A interface and a first interface.
  • the Type-A interface and the first interface are connected by a cable.
  • the first interface includes VBUS pin, CC pin, D+ pin, D- pin and GND pin, and the Type-A interface and the VBUS pin, D+ pin, D-pin and GND pin are connected in one-to-one correspondence;
  • the data line is provided with a circuit identification module, the circuit identification module includes a pull-up resistor, a switch circuit, a filter circuit, and a comparator circuit, wherein the first end of the switch circuit is connected to the CC lead of the first interface Pin connection, the second end of the switch circuit is connected to the first end of the pull-up resistor, the third end of the switch circuit is connected to the CC pin of the Type-A interface, and the The second end is connected to the VBUS pin of the first interface, the first end of the filter circuit is connected to the CC pin of the Type-A interface, and the second end of the filter circuit is connected to the comparator circuit. Is connected to the first input terminal of the comparator circuit, the second input terminal of the comparator circuit is connected to the VBUS pin of the first interface, and the output terminal of the comparator circuit is connected to the control terminal of the switch circuit;
  • the first terminal of the switch circuit is in communication with the second terminal or the third terminal of the switch circuit.
  • an embodiment of the present application provides a charging device, including a data line and a charger, the data line is the data line provided in the first aspect, and the charger includes the same type as the type in the data line.
  • a charging device including a data line and a charger, the data line is the data line provided in the first aspect, and the charger includes the same type as the type in the data line.
  • -A interface matching Type-A female socket the Type-A female socket includes: VBUS pin, CC pin, D+ pin, D- pin and GND pin.
  • the CC pin is set in the Type-A interface of the data line, and the CC communication signal transmitted on the CC pin in the Type-A interface is filtered into a stable analog signal through the filter circuit, and used
  • the comparator circuit compares the analog signal to obtain a control signal.
  • the control signal obtained by the comparator circuit is a different control signal, and according to the The control signal controls the switching state of the switch circuit, so that when the first end and the second end of the switch circuit are connected, the CC pin in the Type-A interface is disconnected from the CC pin in the first interface, so that the The data line can only communicate through the D+ pin and D- pin for non-PD protocol communication; when the first end and the third end of the switch circuit are connected, the CC pin in the Type-A interface is connected to the CC pin in the first interface. Pin connection, so that the data line can support non-PD protocol communication through the D+ pin and D- pin at the same time, and support PD protocol communication through the CC pin, so that the data line with Type-A interface can support PD protocol charging .
  • Figure 1 is a structure of a data line provided by an embodiment of the present application.
  • Figure 2 is a structural diagram of an identification module in a data line provided by an embodiment of the present application.
  • FIG. 3 is a circuit diagram of an identification module in a data line provided by an embodiment of the present application.
  • Fig. 4 is a structural diagram of a Type-A interface in a data line provided by an embodiment of the present application.
  • FIG. 1 is a structure of a data line provided by an embodiment of the present application
  • Fig. 2 is a structural diagram of an identification module in a data line provided by an embodiment of the present application.
  • the data line includes: Type-A interface 1 and first interface 2, Type-A interface 1 and first interface 2 are connected by cable 3, Type-A interface 1 and first interface 2 both include VBUS pins, CC pin, D+ pin, D- pin and GND pin, and VBUS pin, D+ pin, D- pin and GND pin in Type-A interface 1 and first interface 2 are connected in one-to-one correspondence ;
  • a circuit identification module 4 is provided in the data line.
  • the circuit identification module 4 includes a pull-up resistor 41, a switch circuit 42, a filter circuit 43, and a comparator circuit 44.
  • the first end of the switch circuit 42 is connected to the first interface 2
  • the CC pin is connected
  • the second end of the switch circuit 42 is connected to the first end of the pull-up resistor 41
  • the third end of the switch circuit 42 is connected to the CC pin of the Type-A interface 1
  • the second end of the pull-up resistor 41 is Connect to the VBUS pin of the first interface 2
  • the first end of the filter circuit 43 is connected to the CC pin of the Type-A interface 1
  • the second end of the filter circuit 43 is connected to the first input end of the comparator circuit 44 for comparison
  • the second input terminal of the comparator circuit 44 is connected to the VBUS pin of the first interface 2, and the output terminal of the comparator circuit 44 is connected to the control terminal of the switch circuit 42;
  • the first terminal of the switch circuit 42 is connected to the second terminal or the third terminal of the switch circuit 42.
  • mobile terminals such as mobile phones often support the rapid charging of DP and DM communication protocols.
  • the data negative signal (DataMinus, DM) charging communication and the data positive signal (Data Positive, DP) charging communication protocol pass through the D+ pin. It transmits communication signals with the D-pin, and electronic devices such as notebooks often support fast charging of the PD communication protocol.
  • the PD communication protocol transmits communication signals through the CC pin.
  • the data lines supporting the PD communication protocol all adopt Type-C to Type-C data lines
  • the data lines supporting the DP/DM communication protocol all adopt Type-A to Type-C data lines. In this way, the data line supporting the PD communication protocol and the data line supporting the DP/DM communication protocol cannot be used in common.
  • the data line in this embodiment is a data line that includes Type-A interface 1, and a CC pin is added to Type-A interface 1, and when the signal of the CC communication protocol is transmitted on the CC pin, the Type -The CC pin in the A interface 1 is connected to the CC pin in the first interface 2, so that the device to be charged can be quickly charged with PD.
  • the first interface 2 in this embodiment may be a Type-C interface, so that the data line can be connected to a device to be charged with a Type-C socket.
  • the first interface 2 may also be an existing interface or other interfaces may appear in the future, which is not specifically limited here.
  • the DP and DM communication channels on the data line are still in a conductive state, which can provide the device to be charged Fast charging with DP and DM protocol.
  • the first end of the switch circuit 42 can be connected to the third end of the switch circuit 42 so that when the data line is inserted into the device to be charged, the PD communication protocol channel is used to communicate with The device to be charged performs CC communication, and can switch the first end of the switch circuit 42 to the switch circuit when the CC communication signal is obtained on the CC pin of the Type-A interface within the CC communication preset time
  • the second end of 42 is connected.
  • the preset time may be 3 seconds, 5 seconds, etc., which is not specifically limited here.
  • connection relationship between the VBUS pin, D+ pin, D- pin, and GND pin in the Type-A interface 1 and the first interface 2 and the wires in the cable 3 are the same as those in the prior art. And the connection relationship of the wires is the same.
  • the first interface 2 is a Type-C interface
  • the pins between the Type-C interface and the Type-A interface 1 and the wires in the cable 3 The connection relationship of is specifically the connection relationship shown in Table 1 below:
  • the CC communication signal when a CC communication signal is received on the CC pin of the Type-A interface 1, the CC communication signal is adjusted to a stable analog signal by the filter circuit 43, and the analog signal is processed by the comparator circuit 44
  • the comparator circuit 44 For comparison, when there is a signal on the CC pin of the Type-A interface 1, the comparator circuit 44 outputs the first control signal, and when there is no signal on the CC pin of the Type-A interface 1, the comparator circuit 44 outputs the second control signal.
  • the control signal makes the output first control signal and the second control signal more accurate, and the switching state of the switch circuit 42 can be controlled more accurately according to the first control signal and the second control signal.
  • the analog signal output by the filter circuit may be a high-level signal.
  • the comparator circuit 44 outputs the first signal in response to the high-level signal.
  • Control signal, and the switch circuit 42 connects its first end and third end in response to the first control signal;
  • the analog signal output by the filter circuit 43 can be It is a low-level signal.
  • the comparator circuit 44 outputs a second control signal in response to the low-level signal, and the switch circuit 42 connects its first terminal and second terminal in response to the second control signal.
  • the filter circuit 43 can also adjust the CC communication signal received on the CC pin of the Type-A interface 1 to other analog signals, and only need to make the signal on the CC pin of the Type-A interface 1.
  • the analog signal can be different, and the analog signal with the difference can be distinguished by the comparator circuit 44, so as to generate a control signal with higher accuracy and more stable.
  • the CC pin is set in the Type-A interface, and the communication signal transmitted on the CC pin in the Type-A interface is adjusted into a control signal through the filter circuit and the comparator circuit to control the CC pin Connect or disconnect with the CC pin in the first interface, so that when there is a signal on the CC pin in the Type-A interface, control the CC pin to connect with the CC pin in the first interface , So that the PD communication channel in the data line is connected to support fast charging of the PD; when there is no signal on the CC pin in the Type-A interface, the CC pin is controlled to be disconnected from the CC pin in the first interface Open the connection, so that the PD communication channel in the data line is disconnected.
  • PD fast charging is not supported.
  • the PD communication channel in the data line can be connected, and the device to be charged can perform PD fast charging; when the device to be charged connected to the data line does not support
  • the PD communication channel in the data line is disconnected, and the DP and DM communication are always connected, so that the device to be charged can be quickly charged using the DP/DM protocol communication.
  • the circuit identification module 4 is provided in the cable 3, and the distance between the circuit identification module 4 and one end of the first interface 2 is smaller than the distance from one end of the Type-A interface 1.
  • the identification module 4 is arranged in the cable 3 to switch the corresponding connection relationship between the CC pin in the Type-A interface 1 and the CC pin in the first interface 2 in the cable 3.
  • the distance between the circuit identification module 4 and one end of the first interface 2 is less than the distance from one end of the Type-A interface 1.
  • the identification module 4 can be arranged close to the first interface 2.
  • the intermediate setting includes the problem of identifying the circuit board structure of the module 4 and affecting the fluency and aesthetics of the cable 3.
  • the distance between the circuit identification module 4 and one end of the first interface 2 is less than the distance from one end of the Type-A interface 1, and the identification module 4 can also be arranged close to the Type-A interface 1, which can also avoid It is a problem that a circuit module with a larger diameter is arranged in the middle of the cable 3, which affects the smoothness and aesthetics of the cable 3.
  • the third end of the switch circuit 42 is connected to the CC wire of the cable 3 connected to the CC pin of the Type-A interface 1.
  • the second end of the pull-up resistor 41 is connected to the VBUS trace in the cable 3
  • the first end of the filter circuit 43 is connected to the CC trace in the cable 3 connected to the CC pin of the Type-A interface 1, filtering
  • the second end of the circuit 43 is connected to the GND trace in the cable 3, and the two ends of the above-mentioned VBUS trace are respectively connected to the VBUS pin of the Type-A interface 1 and the VBUS pin of the first interface 2.
  • the two ends are respectively connected to the GND pin of the Type-A interface 1 and the GND pin of the first interface 2.
  • the switch circuit 42 includes a first switch transistor Q1, a second switch transistor Q2, a third switch transistor Q3, a fourth switch transistor Q4, a first resistor 45, and a second switch transistor Q4.
  • the first pole of the first switching transistor Q1 is the control terminal of the switching circuit 42, the first pole of the first switching transistor Q1 is also connected to the GND pin through the first capacitor 47, and the second pole of the first switching transistor Q1 is connected to the The first pole of the second switching transistor Q2, the first pole of the third switching transistor Q3, and the first pole of the fourth switching transistor Q4 are connected, and the third pole of the first switching transistor Q1 is connected to the GND pin of the first interface 2;
  • the first pole of the second switching transistor Q2 is also connected to the VBUS pin of the first interface 2 through the first resistor 44, the second pole of the second switching transistor Q2 is the second terminal of the switching circuit 42, and the second pole of the second switching transistor Q2 is The first end of the three-pole switch circuit 42;
  • the second terminal of the third switch transistor Q3 is the third terminal of the switch circuit 42, and the third terminal of the third switch transistor Q3 is connected to the second terminal of the first switch transistor Q1 through a second resistor 45;
  • the second pole of the fourth switch transistor Q4 is connected to the third pole of the second switch transistor Q2, and the third pole of the fourth switch transistor Q4 is connected to the third pole of the third switch transistor Q3;
  • the first switching transistor Q1, the third switching transistor Q3, and the fourth switching transistor Q4 are all in the off state, and the second switching transistor Q2 is in the on state.
  • the filter circuit 43 adjusts the signal on the CC pin of the Type-A interface 1 to a high-level signal, and the comparator circuit
  • the first control signal is output according to the high-level signal.
  • the first control signal may be a high-level signal of the first value.
  • the first pole of the first switching transistor Q1 receives the high-level signal of the first value.
  • the first switching transistor Q1 is controlled to be turned on, that is, the second pole and the third pole of the first switching transistor Q1 are connected. At this time, the first pole of the second switching transistor Q2 and the first pole of the third switching transistor Q3 are connected.
  • the electrode and the first electrode of the fourth switching transistor Q4 are connected to the GND pin through the first switching transistor Q1, so that the third switching transistor Q3 and the fourth switching transistor Q4 are turned on, that is, the second electrode of the third switching transistor Q3 and The third pole is connected, the second pole and the third pole of the fourth switch transistor Q4 are connected, and because the first pole of the second switch transistor Q2 is pulled down to connect to the GND pin through the first switch transistor Q1, the second switch The transistor Q2 is turned off, that is, the second pole and the third pole of the second switching transistor Q2 are turned off.
  • the first switch transistor Q1 and the second switch transistor Q2 are N-type transistors, and the third switch transistor Q3 and the fourth switch transistor Q4 are P-type transistors.
  • the first switching transistor Q1 and the second switching transistor Q2 are N-Metal-Oxide Semiconductor (NMOS) tubes, and the third switching transistor Q3 and the fourth switching transistor Q4 are P-type metal oxides.
  • the first electrode of the first switching transistor Q1 can be the gate, the second electrode can be the drain, and the third electrode can be the source; the first electrode of the second switching transistor Q2 can be the gate and the second electrode.
  • the pole can be the drain and the third pole can be the source.
  • the first poles of the third switching transistor Q3 and the fourth switching transistor Q4 are gated, and when the first switching transistor Q1 is turned on, the first poles of the third switching transistor Q3 and the fourth switching transistor Q4 pass through the first pole of the third switching transistor Q3 and the fourth switching transistor Q4.
  • a switching transistor Q1 is pulled down to the GND pin, so that the PMOS transistors Q3 and Q4 are turned on.
  • the first pole of Q2 is also pulled down to the GND pin through the first switching transistor Q1, so that the NMOS transistor Q2 is turned off.
  • the filter circuit 43 when there is no signal on the CC pin of the Type-A interface 1, the filter circuit 43 does not output a level signal, that is, the filter circuit 43 outputs a low-level signal, and the comparator circuit outputs according to the low-level signal
  • the second control signal, the second control signal may be a low-level signal of the second value, and the first pole of the first switching transistor Q1 receives the low-level signal of the second value, so that the first switching transistor Q1 is turned off, the first pole of the second switching transistor Q2 is pulled down to the GND pin through the first switching transistor Q1, so that the NMOS transistor Q2 is turned on, and when the first switching transistor Q1 is turned off, the third switching transistor Q3 and The first pole of the fourth switch transistor Q4 is pulled up to the VBUS pin through the first resistor 45, so that the PMOS transistors Q3 and Q4 are disconnected.
  • the first switch transistor Q1, the second switch transistor Q2, the third switch transistor Q3, and the fourth switch transistor Q4 can also be other types of transistors, and the switches in the switch circuit 42 are changed accordingly.
  • the connection circuit of the transistor connects or disconnects the CC pin of the Type-A interface 1 and the CC pin of the first interface 2 according to the CC signal adjusted by the filter circuit 43, which is not specifically limited here.
  • the second pole of the first switching transistor Q1 is connected to the third pole of the third switching transistor Q3 and the fourth switching transistor Q4 through the second resistor 46.
  • the first pole of the first switching transistor Q1 is also connected to the GND pin through the first capacitor 47, and the control signal output by the comparator circuit 44 can be switched from the first control signal to the second control signal.
  • the first switching transistor Q1 is still turned on during the time when the first capacitor 47 is discharged. In this way, the time delay of the switching circuit 42 can be increased, and the control of the output of the comparator circuit 44 can be avoided. In the process of signal switching, Q1 frequently turns on and off.
  • the switch circuit 42 in this embodiment is an analog signal control circuit. In this way, it is possible to avoid setting a control unit in the identification module 4, and control the switching state of the switch circuit 42 according to the digital control signal sent by the control unit, thereby reducing the switch circuit 42. Production costs.
  • the switch circuit includes a switch 42, the first end of the switch circuit is the stationary end of the switch 42, and the second and third ends of the switch circuit are both switch The moving end of the switch 42.
  • the switch 42 can be switched according to the control signal transmitted by the filter circuit 43.
  • the control signal can be either an analog signal or a digital control signal.
  • the CC pin of the Type-A interface 1 When there is a signal, the comparator circuit 44 sends a first control signal to the switch 42.
  • the switch 42 In response to the first control signal, the switch 42 connects the moving end to the third end, that is, the CC pin of the first interface 2 and The CC pin of the Type-A interface 1 is connected; when there is no signal on the CC pin of the Type-A interface 1, the comparator circuit 44 sends a second control signal to the switch 42 and the switch 42 responds to the second control Signal, connect the moving end to the second end, that is, connect the CC pin of the first interface 2 to the VBUS pin through the pull-up resistor 41.
  • a control unit can also be provided in the switch circuit.
  • the control unit is connected to the comparator circuit 44 and the switch 42 respectively to convert the analog signal output by the comparator circuit 44 into a digital control signal to pass the digital control signal.
  • the control signal controls the switching state of the switch 42.
  • providing the switch 42 in the switch circuit can simplify the structure of the switch circuit.
  • the filter circuit 43 is an RC filter circuit.
  • the signal when there is a signal on the CC pin of Type-A interface 1, the signal can be a fluctuating level signal.
  • the fluctuating level signal can be adjusted to a relatively stable level signal through the RC filter circuit. It is also input to the comparator circuit 44 to promote the comparator circuit 44 to output a more accurate and stable control signal.
  • control signal output by the comparator circuit 44 can be made more stable and reliable.
  • the filter circuit 43 includes a third resistor 431 and a second capacitor 432.
  • the first end of the third resistor 431 is connected to the CC pin of the Type-A interface 1
  • the second end of the third resistor 431 is connected to the first end of the first capacitor 432
  • the second end of the first capacitor 432 is connected to the The GND pin of the first interface 2
  • the first terminal of the first capacitor 432 is also connected to the first input terminal of the comparator circuit 44.
  • the filter circuit 43 when there is no signal on the CC pin of Type-A interface 1, the filter circuit 43 outputs a low-level signal (it can be a level signal with a value of 0); on the CC pin of Type-A interface 1
  • a low-level signal it can be a level signal with a value of 0
  • the first capacitor 432 When there is a fluctuating level signal, when the level signal increases, the first capacitor 432 is charged, and when the level signal decreases, the first capacitor 432 discharges, so that the filter circuit 43 outputs a stable high level Signal (a level signal with a value greater than 0), and the high level signal is input to the comparator circuit 44 for comparison, so that the comparator circuit 44 outputs an accurate control signal to control the switching state of the switch circuit 42.
  • the comparator circuit 44 can be used to compare the level signal output by the filter circuit 43 and output an accurate control signal. Compared with the case where the switching state of the switch circuit 42 is directly controlled according to the level signal output by the filter circuit 43 Since the level signal output by the filter circuit 43 is a solution that fluctuates the level value within the value interval, in this embodiment, the switching state of the switch circuit 42 is controlled according to the control signal output by the comparator circuit 44 with an accurate value. , The control sensitivity of the switch circuit 42 can be improved.
  • the capacitance of the second capacitor 432 is greater than a preset capacitance.
  • the aforementioned preset capacitance value may be determined according to the recognition accuracy of the comparator circuit 44 and the level value and change characteristics of the signal on the CC pin of the Type-A interface 1, which is not specifically limited here.
  • the capacitance value of the second capacitor 432 is greater than the preset capacitance value, so that when the level value of the signal transmitted on the CC pin of the Type-A interface 1 fluctuates, the level of the transmission signal rises.
  • the second capacitor 432 is charged, and when the level of the transmission signal is reduced, the second capacitor 432 is discharged; and when there is no transmission signal on the CC pin of the Type-A interface 1, the second capacitor 432 is exhausted , So there is no output level value.
  • the difference in the control signal output by the switch circuit 44 can improve the control accuracy of the switch circuit 42.
  • the comparator circuit 44 includes: a fourth resistor 441, a fifth resistor 442, a sixth resistor 443, a seventh resistor 444, a comparator 445 and a diode 446.
  • the first end of the fourth resistor 441 is the second input end of the comparator circuit 44, the second end of the fourth resistor 441 is connected to the first end of the fifth resistor 442, and the second end of the fifth resistor 442 is connected to the sixth resistor.
  • the first end of the 443 is connected, and the second end of the sixth resistor 443 is connected to the GND pin;
  • the first terminal of the comparator 445 is the output terminal of the comparator circuit 44
  • the second terminal of the comparator 445 is the first input terminal of the comparator circuit 44
  • the third terminal of the comparator circuit 44 is connected to the fifth resistor 442 and the first input terminal.
  • the fourth terminal of the comparator circuit 44 is connected to the GND pin
  • the fifth terminal of the comparator circuit 44 is connected to the first terminal of the diode 446, the second terminal of the fourth resistor 441 and the fifth resistor 442.
  • the first end is connected, the first end of the comparator circuit 44 is also connected to the GND pin through the seventh resistor 444; the second end of the diode 446 is connected to the GND pin.
  • the comparator 445 when the electrical signal value on the second end of the comparator 445 is greater than the electrical signal value on the third end of the comparator 445, the comparator 445 outputs the first control signal, and the switch circuit 42 responds to the first control signal.
  • the control signal connects the first terminal and the third terminal; when the electrical signal value on the second terminal of the comparator 445 is less than or equal to the electrical signal value on the third terminal of the comparator 445, the comparator 445 outputs the second In response to the control signal, the switch circuit 42 connects its first end and second end in response to the second control signal.
  • the voltage of the comparator 445 is divided by the fifth resistor 442 and the sixth resistor 443, and the current of the comparator 445 is limited by the fourth resistor 441.
  • the diode 446 can reduce the voltage of the fifth terminal of the comparator 445. Keep at a fixed voltage value, for example: 5V (Volt), so that when there is a signal on the CC pin of Type-A interface 1, the high-level signal output by the filter circuit 43 is transmitted to the second end of the comparator 445, so that The level value on the second end of the comparator 445 is greater than the level value of the third end of the comparator 445.
  • 5V Volt
  • the first end of the comparator 445 outputs the first control signal of the first level value
  • the switch circuit 42 responds When the first control signal connects the first terminal and the third terminal; and when there is no signal on the CC pin of the Type-A interface 1, the low-level signal output by the filter circuit 43 is transmitted to the second terminal of the comparator 445 Terminal, make the level value on the second terminal of the comparator 445 less than or equal to the level value of the third terminal of the comparator 445, at this time, the first terminal of the comparator 445 outputs the second control signal of the second level value, The second level value is less than the first level value, and the switch circuit 42 connects its first terminal and second terminal in response to the second control signal.
  • the first terminal of the comparator 445 is connected to the ground terminal through the seventh resistor 444, so that there is a potential difference between the first terminal of the comparator 445 and the ground terminal, so as to avoid the first terminal of the comparator 445. Ground directly.
  • the comparator circuit is formed by the comparator 445, the voltage dividing resistors (442 and 443), the current limiting resistor (441), and the voltage stabilizing device (446) to realize the CC pin of the Type-A interface 1.
  • control signals of different levels are output to the switch circuit 42 so as to control the switching state of the switch circuit 42.
  • the first side of the Type-A interface 1 is provided with a GND pin, a D+ pin, a D- pin, and a VBUS pin.
  • the Type-A interface 1 A CC pin is provided on the second side of the Type-A interface 1, and the first side and the second side of the Type-A interface 1 are opposite sides.
  • each pin in the Type-A interface 1 can also be exchanged or changed, which is not specifically limited here.
  • the structure and working principle of the VBUS pin and the GND pin are the same as those of the VBUS pin in the prior art.
  • the structure and working principle of the pin and the GND pin are the same, and will not be described in detail here.
  • the CC pin is set on the second side of the Type-A interface 1, so that the GND pin, D+ pin, D- pin, and VBUS lead on the first side of the Type-A interface 1
  • the structure and position distribution of the feet are the same as those of the Type-A interface in the prior art, so that the data line provided in this embodiment of the present application is compatible with the conventional Type-A female socket.
  • the charging device only supports the fast charging of the DP/DM communication protocol.
  • An embodiment of the present application also provides a charging device, which includes a charger and the data cable provided in the foregoing embodiment.
  • the charger includes a Type-A female socket that matches the Type-A interface in the data line, and the Type-A female socket includes: VBUS pin, CC pin, D+ pin, D- pin and GND pin.
  • Type-A female socket that matches the Type-A interface of the data line can be understood as: when the Type-A interface of the data line 2 is inserted into the Type-A female socket of the charger 1, Type-A The interface is connected to the same pin in the Type-A female socket.
  • the above-mentioned charger also includes a PD charging module and a D+/D- charging module.
  • the PD charging module is connected to the CC pin to communicate with the device to be charged through the PD protocol through the CC pin, thereby supporting PD fast
  • the D+/D- charging module is connected to the D+ pin and the D- pin to communicate with the device to be charged through the D+ pin and the D- pin to communicate with the DP/DM protocol, thereby supporting DP/DM fast charging.
  • the Type-A female socket that matches the Type-A interface can also be connected to the Type-A interface on the conventional data line.
  • the Type-A female socket of the above charger is connected to the Type-A interface on the conventional data line, only DP/DM protocol charging is supported.
  • the charging device provided in the embodiment of the present application has a Type-A interface, supports PD protocol charging and DP/DM protocol charging, and has the same beneficial effects as the data cable provided in the embodiment of the present application, and will not be repeated here.
  • the method of the above embodiments can be implemented by means of software plus the necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is better. ⁇
  • the technical solution of this application essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes several instructions to make a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of the present application.

Abstract

本申请公开了一种数据线和充电设备，属于通信技术领域。数据线包括Type-A接口、第一接口、线缆和电路识别模块，Type-A接口和第一接口中的VBUS引脚、D+引脚、D-引脚和GND引脚对应连接；电路识别模块包括上拉电阻、开关电路、滤波电路和比较器电路，开关电路的第一端与第一接口的CC引脚连接，第二端通过上拉电阻连接至VBUS引脚，第三端与Type-A接口的CC引脚连接，滤波电路的第一端与Type-A接口的CC引脚连接，第二端与比较器电路的第一输入端连接，比较器电路的第二输入端与第一接口的VBUS引脚连接，且比较器电路的输出端与开关电路的控制端连接；比较器电路控制开关电路的第一端与第二端或第三端连通。

Description

数据线和充电设备
相关申请的交叉引用
本申请主张在2020年5月29日在中国提交的中国专利申请号No.202010479637.9的优先权，其全部内容通过引用包含于此。
技术领域
本申请属于通信技术领域，具体涉及一种数据线和充电设备。
背景技术
随着科技的发展，快速充电的应用越来越广泛。
在相关技术中，通常采用电力输送(Power Delivery，PD)协议进行快速充电，为支持PD协议充电的充电器需要采用配置通道(Configuration Channel，CC)信号线进行通信，该支持PD协议充电的充电器通常采用第三标准(Type-C)接口，并搭配Type-C to Type-C的数据线。对于采用第一标准(Type-A或者Standard-A)接口的数据线，其通过D+/D-信号线进行通信，不能够支持PD协议充电。但是，当前使用最广泛的数据线为具有Type-A接口的数据线，从而使得常规的数据线上的Type-A接口不支持PD协议充电。
发明内容
本申请实施例的目的是提供一种数据线和充电设备，能够解决具有Type–A接口的数据线不支持PD协议充电的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种数据线，包括Type-A接口和第一接口，所述Type-A接口和所述第一接口通过线缆连接，所述Type-A接口和所述第一接口均包括VBUS引脚、CC引脚、D+引脚、D-引脚和GND引脚，且所述Type-A接口和所述第一接口中的VBUS引脚、D+引脚、D-引脚和GND引脚一一对应连接；
所述数据线中设置有电路识别模块，所述电路识别模块包括上拉电阻、开关电路、滤波电路和比较器电路，其中，所述开关电路的第一端与所述第一接口的CC引脚连接，所述开关电路的第二端与所述上拉电阻的第一端连接，所述开关电路的第三端与所述Type-A接口的CC引脚连接，所述上拉电阻的第二端与所述第一接口的VBUS引脚连接，所述滤波电路的第一端与所述Type-A接口的CC引脚连接，所述滤波电路的第二端与所述比较器电路的第一输入端连接，所述比较器电路的第二输入端与所述第一接口的VBUS引脚连接，且所述比较器电路的输出端与所述开关电路的控制端连接；
其中，在所述比较器电路的控制下，所述开关电路的第一端与所述开关电路的第二端或第三端连通。
第二方面，本申请实施例提供了一种充电设备，包括数据线和充电器，所述数据线为第一方面提供的所述数据线，所述充电器包括与所述数据线中的Type-A接口匹配的Type-A母座，所述Type-A母座包括：VBUS引脚、CC引脚、D+引脚、D-引脚和GND引脚。
在本申请实施例中，在数据线的Type-A接口中设置CC引脚，并通过滤波电路将Type-A接口中的CC引脚上传输的CC通信信号滤波成稳定的模拟信号，并利用比较器电路对该模拟信号进行比较以得出控制信号，以在Type-A接口的CC引脚上有信号和无信号时，比较器电路得出的控制信号为不同的控制信号，并根据该控制信号控制开关电路的开关状态，以实现在开关电路的第一端和第二端连通时，Type-A接口中的CC引脚与第一接口中的CC引脚断开连接，从而使得该数据线仅能够通过D+引脚和D-引脚进行非PD协议通信；在开关电路的第一端和第三端连通时，Type-A接口中的CC引脚与第一接口中的CC引脚连通，从而使得该数据线能够同时通过D+引脚和D-引脚支持非PD协议通信，并通过CC引脚支持PD协议通信，从而能够使具有Type–A接口的数据线支持PD协议充电。
附图说明
图1是本申请实施例提供的数据线的结构；
图2是本申请实施例提供的数据线中识别模块的结构图；
图3是本申请实施例提供的数据线中识别模块的电路图；
图4是本申请实施例提供的数据线中Type-A接口的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的数据线和充电设备进行详细地说明。
请同时参阅图1和图2，其中，图1是本申请实施例提供的数据线的结构；
图2是本申请实施例提供的数据线中识别模块的结构图。
其中，数据线，包括：Type-A接口1和第一接口2，Type-A接口1和第一接口2通过线缆3连接，Type-A接口1和第一接口2均包括VBUS引脚、CC引脚、D+引脚、D-引脚和GND引脚，且Type-A接口1和第一接口2中的VBUS引脚、D+引脚、D-引脚和GND引脚一一对应连接；
所述数据线中设置有电路识别模块4，电路识别模块4包括上拉电阻41、开关电路42、滤波电路43和比较器电路44，其中，开关电路42的第一端与第一接口2的CC引脚连接，开关电路42的第二端与上拉电阻41的第一端连接，开关电路42的第三端与Type-A接口1的CC引脚连接，上拉电阻41 的第二端与第一接口2的VBUS引脚连接，滤波电路43的第一端与Type-A接口1的CC引脚连接，滤波电路43的第二端与比较器电路44的第一输入端连接，比较器电路44的第二输入端与第一接口2的VBUS引脚连接，且比较器电路44的输出端与开关电路42的控制端连接；
其中，在比较器电路44的控制下，开关电路42的第一端与开关电路42的第二端或第三端连通。
在现有技术中，手机等移动终端往往支持DP、DM通信协议的快速充电，该数据负信号(DataMinus，DM)充电通信、数据正信号(Data Positive，DP)充电通信通信协议通过D+引脚和D-引脚传输通信信号，而笔记本等电子设备往往支持PD通信协议的快速充电，该PD通信协议通过CC引脚传输通信信号。且现有技术中，支持PD通信协议的数据线均采用Type-C to Type-C形式的数据线，而支持DP/DM通信协议的数据线均采用Type-A to Type-C形式的数据线，这样，使得支持PD通信协议的数据线和支持DP/DM通信协议的数据线不能通用。
而本实施方式中的数据线为包括Type-A接口1的数据线，且在Type-A接口1中增加了CC引脚，并在该CC引脚上传输CC通信协议的信号时，将Type-A接口1中的CC引脚与第一接口2中的CC引脚连通，从而能够对待充电设备进行PD快速充电。另外，本实施方式中的第一接口2可以是Type-C接口，以便于将该数据线与具有Type-C插座的待充电设备连接。
当然，根据科技的发展，第一接口2还可以是现有的或者未来可能出现其他接口，在此并不做具体限定。
另外，在实际应用中，在待充电设备仅支持DP、DM通信协议的非PD快速充电的情况下，该数据线上的DP、DM通信通道仍然处于导通状态，从而能够为待充电设备提供DP、DM协议的快速充电。
需要说明的是，在开关电路42的第一端与开关电路42的第二端连通的情况下，开关电路42的第一端与开关电路42的第三端断开连接；在开关电路42的第一端与开关电路42的第三端连通的情况下，开关电路42的第一端 与开关电路42的第二端断开连接。
另外，在工作中，在数据线未连接电源的情况下，开关电路42的第一端可以与开关电路42的第三端连通，以使数据线插入待充电设备时，利用PD通信协议通道与待充电设备进行CC通信，并可以在该CC通信预设时间内，在Type-A接口的CC引脚上获取到CC通信信号的情况下，将开关电路42的第一端切换至与开关电路42的第二端连通。其中，该预设时间可以是3秒、5秒等，在此不作具体限定。
另外，上述Type-A接口1和第一接口2中的VBUS引脚、D+引脚、D-引脚和GND引脚以及线缆3中各走线的连接关系与现有技术中各引脚以及各走线的连接关系相同，例如：在所述第一接口2为Type-C接口的情况下，Type-C接口与Type-A接口1之间各引脚和线缆3中各走线的连接关系具体为如下表1中所示的连接关系：
表1
Figure PCTCN2021096260-appb-000001
在实施中，在Type-A接口1的CC引脚上接收到CC通信信号的情况下，该CC通信信号通过滤波电路43调整成稳定的模拟信号，并通过比较器电路44对该模拟信号进行比较，以在Type-A接口1的CC引脚上有信号时，比较器电路44输出第一控制信号，在Type-A接口1的CC引脚上无信号时，比较器电路44输出第二控制信号，从而使得输出的第一控制信号和第二控制信号更加精确，能够根据该第一控制信号和第二控制信号更加准确的控制开关 电路42的开关状态。
具体的，在Type-A接口1的CC引脚上有信号的情况下，上述滤波电路输出的模拟信号可以是高电平信号，这样，比较器电路44响应于该高电平信号输出第一控制信号，且开关电路42响应于该第一控制信号连通其第一端和第三端；在Type-A接口1的CC引脚上无信号的情况下，上述滤波电路43输出的模拟信号可以是低电平信号，这样，比较器电路44响应于该低电平信号输出第二控制信号，且开关电路42响应于该第二控制信号连通其第一端和第二端。
当然，在具体实施中，滤波电路43还可以将Type-A接口1的CC引脚上接收到CC通信信号调整成其他模拟信号，仅需使得在Type-A接口1的CC引脚上有信号和无信号时，该模拟信号不同即可，并通过比较器电路44区分该具有差异的模拟信号，从而生成准确率更高，且更加稳定的控制信号。
本实施方式中，在Type-A接口中设置CC引脚，并通过滤波电路和比较器电路将Type-A接口中的CC引脚上传输的通信信号调整成控制信号，以控制该CC引脚与第一接口中的CC引脚连接或者断开连接，从而能够实现在Type-A接口中的CC引脚上有信号的情况下，控制该CC引脚与第一接口中的CC引脚连接，从而使数据线中的PD通信通道连通，以支持PD快速充电；在Type-A接口中的CC引脚上无信号的情况下，控制该CC引脚与第一接口中的CC引脚断开连接，从而使数据线中的PD通信通道断开，此时不支持PD快速充电。这样，能够在与数据线连接的待充电设备支持PD快速充电的情况下，使数据线中的PD通信通道连通，并对待充电设备进行PD快速充电；在与数据线连接的待充电设备不支持PD快速充电的情况下，使数据线中的PD通信通道不连通，而DP、DM通信始终连通，从而对待充电设备进行以DP/DM协议通信的快速充电。
作为一种可选的实施方式，电路识别模块4设置在线缆3中，且电路识别模块4与第一接口2的一端的距离小于与Type-A接口1的一端的距离。
本实施方式中，将识别模块4设置于线缆3中，以在线缆3中切换Type- A接口1中的CC引脚与第一接口2中的CC引脚之间的对应连接关系。
另外，上述电路识别模块4与第一接口2的一端的距离小于与Type-A接口1的一端的距离，可以是将识别模块4靠近第一接口2设置，这样，能够避免在线缆3的中间设置包括识别模块4的电路板结构而影响线缆3的流畅度和美观度的问题。当然，在具体实施中，上述电路识别模块4与第一接口2的一端的距离小于与Type-A接口1的一端的距离，还可以将识别模块4靠近Type-A接口1设置，同样能够避免在线缆3的中间设置直径较大的电路模块而影响线缆3的流畅度和美观度的问题。
另外，在具体实施中，在电路识别模块4设置在线缆3中的情况下，开关电路42的第三端与线缆3中连接至Type-A接口1的CC引脚的CC走线连接，上拉电阻41的第二端与线缆3中的VBUS走线连接，滤波电路43的第一端与线缆3中连接至Type-A接口1的CC引脚的CC走线连接，滤波电路43的第二端与线缆3中的GND走线连接，且上述VBUS走线的两端分别连接Type-A接口1的VBUS引脚和第一接口2的VBUS引脚，GND走线的两端分别连接Type-A接口1的GND引脚和第一接口2的GND引脚。
作为一种可选的实施方式，如图3所示，开关电路42包括第一开关晶体管Q1、第二开关晶体管Q2、第三开关晶体管Q3、第四开关晶体管Q4、第一电阻45、第二电阻46和第一电容47。
其中，第一开关晶体管Q1的第一极为开关电路42的控制端，第一开关晶体管Q1的第一极还通过第一电容47与GND引脚连接，第一开关晶体管Q1的第二极与第二开关晶体管Q2的第一极、第三开关晶体管Q3的第一极和第四开关晶体管Q4的第一极连接，第一开关晶体管Q1的第三极与第一接口2的GND引脚连接；
第二开关晶体管Q2的第一极还通过第一电阻44与第一接口2的VBUS引脚连接，第二开关晶体管Q2的第二极为开关电路42的第二端，第二开关晶体管Q2的第三极为开关电路42的第一端；
第三开关晶体管Q3的第二极为开关电路42的第三端，第三开关晶体管 Q3的第三极通过第二电阻45与第一开关晶体管Q1的第二极连接；
第四开关晶体管Q4的第二极与第二开关晶体管Q2的第三极连接，第四开关晶体管Q4的第三极与第三开关晶体管Q3的第三极连接；
其中，在Type-A接口1的CC引脚上无信号的情况下，第一开关晶体管Q1、第三开关晶体管Q3和第四开关晶体管Q4均处于断开状态，第二开关晶体管Q2处于导通状态；在Type-A接口1的CC引脚上有信号的情况下，第一开关晶体管Q1、第三开关晶体管Q3和第四开关晶体管Q4均处于导通状态，第二开关晶体管Q2处于断开状态。
在具体实施中，在Type-A接口1的CC引脚上有信号传输的情况下，滤波电路43将Type-A接口1的CC引脚上的信号调整为高电平信号，且比较器电路根据该高电平信号输出第一控制信号，该第一控制信号可以是第一取值的高电平信号，这样，第一开关晶体管Q1的第一极接收到该第一取值的高电平信号时，控制第一开关晶体管Q1导通，即第一开关晶体管Q1的第二极和第三极连通，此时，第二开关晶体管Q2的第一极、第三开关晶体管Q3的第一极和第四开关晶体管Q4的第一极通过第一开关晶体管Q1连接至GND引脚，从而使得第三开关晶体管Q3和第四开关晶体管Q4导通，即第三开关晶体管Q3的第二极和第三极连接，第四开关晶体管Q4的第二极和第三极连接，且由于第二开关晶体管Q2的第一极通过第一开关晶体管Q1下拉至与GND引脚连接，从而该第二开关晶体管Q2断开，即第二开关晶体管Q2的第二极和第三极断开。
在一种实施方式中，第一开关晶体管Q1和第二开关晶体管Q2为N型晶体管，第三开关晶体管Q3和第四开关晶体管Q4为P型晶体管。具体的，第一开关晶体管Q1和第二开关晶体管Q2为N型金属氧化物半导体(N-Metal-Oxide Semiconductor，NMOS)管，第三开关晶体管Q3和第四开关晶体管Q4为P型金属氧化物半导体(P-Metal-Oxide Semiconductor，PMOS)管。
在应用中，第一开关晶体管Q1的第一极可以是栅极，第二极可以是漏 极，第三极可以是源极；第二开关晶体管Q2的第一极可以是栅极、第二极可以是漏极、第三极可以是源极，这样，在Type-A接口1的CC引脚上有信号的情况下，第一开关晶体管Q1的第一极接收到高电平信号从而导通第二极和第三极，此时第二开关晶体管Q2的栅极连通至GND引脚，从而使得第二开关晶体管Q2断开。
另外，第三开关晶体管Q3和第四开关晶体管Q4的第一极为栅极，则在第一开关晶体管Q1导通的情况下，第三开关晶体管Q3和第四开关晶体管Q4的第一极通过第一开关晶体管Q1下拉至GND引脚，从而使得PMOS管Q3和Q4导通。此时由于第一开关晶体管Q1导通，使得Q2的第一极也通过第一开关晶体管Q1下拉至GND引脚，从而使得NMOS管Q2断开。
相应的，在Type-A接口1的CC引脚上无信号的情况下，滤波电路43不输出电平信号，即滤波电路43输出低电平信号，且比较器电路根据该低电平信号输出第二控制信号，该第二控制信号可以是第二取值的低电平信号，第一开关晶体管Q1的第一极接收到该第二取值的低电平信号，从而使得第一开关晶体管Q1断开，第二开关晶体管Q2的第一极通过第一开关晶体管Q1下拉至GND引脚，从而使得NMOS管Q2导通，且在第一开关晶体管Q1断开时，第三开关晶体管Q3和第四开关晶体管Q4的第一极通过第一电阻45上拉至VBUS引脚，从而使得PMOS管Q3和Q4断开。
当然，在具体实施中，第一开关晶体管Q1、所述第二开关晶体管Q2、第三开关晶体管Q3和第四开关晶体管Q4还可以是其他类型的晶体管，并相应的改变开关电路42中各个开关晶体管的连接电路，以根据滤波电路43调节后的CC信号，将Type-A接口1的CC引脚与第一接口2的CC引脚连通或者断开连通，在此不做具体限定。
另外，在具体实施中，如图3所示，第一开关晶体管Q1的第二极通过第二电阻46连接至第三开关晶体管Q3和第四开关晶体管Q4的第三极。
这样，可以避免Q1导通时，使Q3和Q4的第一极和第二极短路。
另外，如图3所示，第一开关晶体管Q1的第一极还通过第一电容47连 接至GND引脚，可以在比较器电路44输出的控制信号由第一控制信号切换至第二控制信号时，使该第一电容47放电，从而在该第一电容放电的时间内，使第一开关晶体管Q1仍然导通，这样，可以增加开关电路42的时延，避免比较器电路44输出的控制信号进行切换的过程中，Q1频繁的导通和断开的问题。
本实施方式中的开关电路42为模拟信号控制电路，这样，可以避免在识别模块4中设置控制单元，并根据控制单元发送的数字控制信号控制开关电路42的开关状态，从而能够降低开关电路42的生产成本。
作为一种可选的实施方式，如图2所示，开关电路包括切换开关42，开关电路的第一端为切换开关42的不动端，开关电路的第二端和第三端均为切换开关42的动端。
在具体实施中，切换开关42可以根据滤波电路43传递的控制信号进行切换，该控制信号可以是模拟信号或者数字控制信号中的任一种，具体的，在Type-A接口1的CC引脚上有信号时，比较器电路44向切换开关42发送第一控制信号，将切换开关42响应于该第一控制信号，将动端连接至第三端，即将第一接口2的CC引脚与Type-A接口1的CC引脚连通；在Type-A接口1的CC引脚上无信号时，比较器电路44向切换开关42发送第二控制信号，将切换开关42响应于该第二控制信号，将动端连接至第二端，即将第一接口2的CC引脚通过上拉电阻41连接至VBUS引脚。
在具体实施中，还可以在开关电路中设置控制单元，该控制单元与比较器电路44和切换开关42分别连接，以将比较器电路44输出的模拟信号转换为数字控制信号，以通过该数字控制信号控制切换开关42的开关状态。
本实施方式中，在开关电路中设置切换开关42能够简化开关电路的结构。
作为一种可选的实施方式，滤波电路43为RC滤波电路。
在应用中，在Type-A接口1的CC引脚上有信号时，该信号可以是起伏变化的电平信号，通过RC滤波电路可以起伏变化的电平信号调整为较为平稳的电平信号，并输入至比较器电路44中，促进比较器电路44输出更加准 确和稳定的控制信号。
这样，能够使比较器电路44输出的控制信号更加稳定可靠。
进一步的，如图3所示，滤波电路43包括第三电阻431和第二电容432。
其中，第三电阻431的第一端与Type-A接口1的CC引脚连接，第三电阻431的第二端与第一电容432的第一端连接，第一电容432的第二端与第一接口2的GND引脚连接，第一电容432的第一端还与比较器电路44的第一输入端连接。
在应用中，在Type-A接口1的CC引脚上无信号时，滤波电路43输出低电平信号(可以是取值为0的电平信号)；在Type-A接口1的CC引脚上有起伏变化的电平信号时，在该电平信号升高时，第一电容432充电，在该电平信号降低时，第一电容432放电，从而使得滤波电路43输出平稳的高电平信号(取值大于0的电平信号)，并将该高电平信号输入至比较器电路44中进行比较，以使比较器电路44输出准确的控制信号以控制开关电路42的开关状态。
本实施方式中，可以利用比较器电路44对滤波电路43输出的电平信号进行比较，并输出准确的控制信号，相对于直接根据滤波电路43输出的电平信号控制开关电路42的开关状态时，由于滤波电路43输出的电平信号为一个在取值区间内波动电平值的方案，本实施方式中，根据比较器电路44输出的具有准确取值的控制信号控制开关电路42的开关状态，能够提升开关电路42的控制灵敏度。
可选的，第二电容432的容值大于预设容值。
在具体实施中，上述预设容值可以根据比较器电路44的识别精度以及Type-A接口1的CC引脚上的信号的电平值、变化特性等确定，在此不作具体限定。
本实施方式中，将第二电容432的容值大于预设容值，以在Type-A接口1的CC引脚上传输的信号的电平值具有波动时，在该传输信号的电平升高时，使第二电容432充电，在该传输信号的电平降低时，使第二电容432放 电；而在Type-A接口1的CC引脚上无传输信号时，第二电容432耗尽，从而无输出电平值。从而增加了Type-A接口1的CC引脚上传输低电平信号和Type-A接口1的CC引脚上无传输信号时，滤波电路43输出的模拟信号之间的差异，进而提升了比较器电路44输出的控制信号的差异，能够提升开关电路42的控制准确度。
作为一种可选的实施方式，如图3所示，比较器电路44包括：第四电阻441、第五电阻442、第六电阻443、第七电阻444、比较器445和二极管446。
第四电阻441的第一端为比较器电路44的第二输入端，第四电阻441的第二端与第五电阻442的第一端连接，第五电阻442的第二端与第六电阻443的第一端连接，第六电阻443的第二端与所述GND引脚连接；
比较器445的第一端为比较器电路44的输出端，比较器445的第二端为比较器电路44的第一输入端，比较器电路44的第三端连接于第五电阻442和第六电阻443之间，比较器电路44的第四端与GND引脚连接，比较器电路44的第五端与二极管446的第一端、第四电阻441的第二端和第五电阻442的第一端连接，比较器电路44的第一端还通过第七电阻444与GND引脚连接；二极管446的第二端与GND引脚连接。
其中，在比较器445的第二端上的电信号值大于比较器445的第三端上的电信号值的情况下，比较器445输出第一控制信号，开关电路42响应于所述第一控制信号连通其第一端和第三端；在比较器445的第二端上的电信号值小于或者等于比较器445的第三端上的电信号值的情况下，比较器445输出第二控制信号，开关电路42响应于所述第二控制信号连通其第一端和第二端。
本实施方式中，通过第五电阻442和第六电阻443对比较器445进行分压，且通过第四电阻441对比较器445进行限流，上述二极管446可以将比较器445的第五端的电压保持在固定的电压值，例如：5V(伏特)，以在Type-A接口1的CC引脚上有信号时，滤波电路43输出的高电平信号传输至比较器445的第二端，使比较器445的第二端上的电平值大于比较器445的第三 端的电平值，此时比较器445的第一端输出第一电平值的第一控制信号，且开关电路42响应于该第一控制信号将其第一端和第三端连通；并在Type-A接口1的CC引脚上无信号时，滤波电路43输出的低电平信号传输至比较器445的第二端，使比较器445的第二端上的电平值小于或者等于比较器445的第三端的电平值，此时比较器445的第一端输出第二电平值的第二控制信号，该第二电平值小于第一电平值，且开关电路42响应于该第二控制信号将其第一端和第二端连通。
另外，如图3所示，比较器445的第一端通过第七电阻444连接至接地端，以使比较器445的第一端与接地端之间具有电势差，避免比较器445的第一端直接接地。
本实施方式中，通过比较器445和分压电阻(442和443)、限流电阻(441)以及稳压器件(446)等构成比较器电路，以实现在Type-A接口1的CC引脚上有信号或者无信号的情况下，向开关电路42输出不同电平值的控制信号，从而实现控制开关电路42的开关状态。
作为一种可选的实施方式，如图4所示，该Type-A接口1的第一侧设置有GND引脚、D+引脚、D－引脚以及VBUS引脚，该Type-A接口1的第二侧设置有CC引脚，上述Type-A接口1的第一侧与第二侧为相对的两侧。
当然，上述Type-A接口1中各引脚的分布位置还可以交换或者改变，在此不作具体限定，另外，该VBUS引脚以及GND引脚的结构和工作原理与现有技术中的VBUS引脚以及GND引脚的结构和工作原理相同，在此不再具体阐述。
本实施方式中，将CC引脚设置于Type-A接口1的第二侧，从而可以使Type-A接口1的第一侧上的GND引脚、D+引脚、D－引脚以及VBUS引脚的结构以及位置分布与现有技术中的Type-A接口相同，从而使得该本申请实施例中提供的数据线兼容常规的Type-A母座。
当然，在本申请实施例中提供的数据线与设置有常规Type-A母座的充电器连接的情况下，由于常规的Type-A母座中未设置CC引脚，从而使得Type- A接口1中的CC引脚不能够接收CC信号，此时，该充电设备仅支持DP/DM通信协议的快速充电。
本申请实施例还提供一种充电设备，该充电设备包括充电器和上述实施例提供的数据线。所述充电器包括与所述数据线中的Type-A接口匹配的Type-A母座，所述Type-A母座包括：VBUS引脚、CC引脚、D+引脚、D-引脚和GND引脚。
其中，与所述数据线中的Type-A接口匹配的Type-A母座可以理解为：在数据线2的Type-A接口插入充电器1的Type-A母座的情况下，Type-A接口和Type-A母座中的相同引脚连接。
另外，上述充电器还包括PD充电模块和D+/D-充电模块，具体的，该PD充电模块与CC引脚连接，以通过CC引脚与待充电设备进行PD协议的通信，从而支持PD快速充电，D+/D-充电模块与D+引脚和D-引脚连接，以通过D+引脚和D-引脚与待充电设备进行DP/DM协议的通信，从而支持DP/DM快速充电。
需要说明的是，本实施方式中，上述充电设备的具体工作过程与上述实施例中的数据线2的工作过程对应，在此不再赘述。
另外，在Type-A接口中各引脚呈如图4所示的分布位置的情况下，与Type-A接口匹配的Type-A母座还可以与常规数据线上的Type-A接口连接，且在上述充电器的Type-A母座与常规数据线上的Type-A接口连接的情况下，仅支持DP/DM协议充电。
本申请实施例提供的充电设备具有Type-A接口，且支持PD协议充电和DP/DM协议充电，具有本申请实施例提供的数据线相同的有益效果，在此不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下， 由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和电子设备的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (11)

  1. 一种数据线，包括Type-A接口和第一接口，所述Type-A接口和所述第一接口通过线缆连接，，所述Type-A接口和所述第一接口均包括VBUS引脚、CC引脚、D+引脚、D-引脚和GND引脚，且所述Type-A接口和所述第一接口中的VBUS引脚、D+引脚、D-引脚和GND引脚一一对应连接；
    所述数据线中设置有电路识别模块，所述电路识别模块包括上拉电阻、开关电路、滤波电路和比较器电路，其中，所述开关电路的第一端与所述第一接口的CC引脚连接，所述开关电路的第二端与所述上拉电阻的第一端连接，所述开关电路的第三端与所述Type-A接口的CC引脚连接，所述上拉电阻的第二端与所述第一接口的VBUS引脚连接，所述滤波电路的第一端与所述Type-A接口的CC引脚连接，所述滤波电路的第二端与所述比较器电路的第一输入端连接，所述比较器电路的第二输入端与所述第一接口的VBUS引脚连接，且所述比较器电路的输出端与所述开关电路的控制端连接；
    其中，在所述比较器电路的控制下，所述开关电路的第一端与所述开关电路的第二端或第三端连通。
  2. 根据权利要求1所述的数据线，其中，所述第一接口为Type-C接口。
  3. 根据权利要求1所述的数据线，其中，所述电路识别模块设置在所述线缆中，且所述电路识别模块与所述第一接口的一端的距离小于与所述Type-A接口的一端的距离。
  4. 根据权利要求1所述的数据线，其中，所述开关电路包括第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管、第一电阻、第二电阻和第一电容；
    其中，所述第一开关晶体管的第一极为所述开关电路的控制端，所述第一开关晶体管的第一极还通过所述第一电容与GND引脚连接，所述第一开关晶体管的第二极与所述第二开关晶体管的第一极、所述第三开关晶体管的第一极和所述第四开关晶体管的第一极连接，所述第一开关晶体管的第三极 与所述第一接口的GND引脚连接；
    所述第二开关晶体管的第一极还通过所述第一电阻与所述第一接口的VBUS引脚连接，所述第二开关晶体管的第二极为所述开关电路的第二端，所述第二开关晶体管的第三极为所述开关电路的第一端；
    所述第三开关晶体管的第二极为所述开关电路的第三端，所述第三开关晶体管的第三极通过所述第二电阻与所述第一开关晶体管的第二极连接；
    所述第四开关晶体管的第二极与所述第二开关晶体管的第三极连接，所述第四开关晶体管的第三极与所述第三开关晶体管的第三极连接；
    其中，在所述Type-A接口的CC引脚上无信号的情况下，所述第一开关晶体管、所述第三开关晶体管和所述第四开关晶体管均处于断开状态，所述第二开关晶体管处于导通状态；在所述Type-A接口的CC引脚上有信号的情况下，所述第一开关晶体管、所述第三开关晶体管和所述第四开关晶体管均处于导通状态，所述第二开关晶体管处于断开状态。
  5. 根据权利要求4所述的数据线，其中，所述第一开关晶体管和所述第二开关晶体管为N型晶体管，所述第三开关晶体管和所述第四开关晶体管为P型晶体管。
  6. 根据权利要求5所述的数据线，其中，所述第一开关晶体管和所述第二开关晶体管为NMOS管，所述第三开关晶体管和所述第四开关晶体管为PMOS管。
  7. 根据权利要求1所述的数据线，其中，所述开关电路包括切换开关，所述开关电路的第一端为所述切换开关的不动端，所述开关电路的第二端和第三端均为所述切换开关的动端。
  8. 根据权利要求1至7中任一项所述的数据线，其中，所述滤波电路为RC滤波电路。
  9. 根据权利要求8所述的数据线，其中，所述滤波电路包括第三电阻和第二电容；
    其中，所述第三电阻的第一端与所述Type-A接口的CC引脚连接，所述 第三电阻的第二端与所述第二电容的第一端连接，所述第二电容的第二端与所述第一接口的GND引脚连接，所述第二电容的第一端还与所述比较器电路的第一输入端连接。
  10. 根据权利要求9所述的数据线，其中，所述比较器电路包括：第四电阻、第五电阻、第六电阻、第七电阻、比较器和二极管；
    所述第四电阻的第一端为所述比较器电路的第二输入端，所述第四电阻的第二端与所述第五电阻的第一端连接，所述第五电阻的第二端与所述第六电阻的第一端连接，所述第六电阻的第二端与所述GND引脚连接；
    所述比较器的第一端为所述比较器电路的输出端，所述比较器的第二端为所述比较器电路的第一输入端，所述比较器电路的第三端连接于所述第五电阻和所述第六电阻之间，所述比较器电路的第四端与所述GND引脚连接，所述比较器电路的第五端与所述二极管的第一端、所述第四电阻的第二端和所述第五电阻的第一端连接，所述比较器电路的第一端还通过所述第七电阻与所述GND引脚连接；
    所述二极管的第二端与所述GND引脚连接；
    其中，在所述比较器的第二端上的电信号值大于所述比较器的第三端上的电信号值的情况下，所述比较器输出第一控制信号，所述开关电路响应于所述第一控制信号连通其第一端和第三端；在所述比较器的第二端上的电信号值小于或者等于所述比较器的第三端上的电信号值的情况下，所述比较器输出第二控制信号，所述开关电路响应于所述第二控制信号连通其第一端和第二端。
  11. 一种充电设备，包括数据线和充电器，其中，所述数据线为如权利要求1-10中任一项所述的数据线，所述充电器包括与所述数据线中的Type-A接口匹配的Type-A母座，所述Type-A母座包括：VBUS引脚、CC引脚、D+引脚、D-引脚和GND引脚。
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