WO2021229673A1

WO2021229673A1 - Power semiconductor device

Info

Publication number: WO2021229673A1
Application number: PCT/JP2020/018923
Authority: WO
Inventors: 麻緒澤川; 仁崇宮路; 裕基塩田; 大吉井
Original assignee: 三菱電機株式会社
Priority date: 2020-05-12
Filing date: 2020-05-12
Publication date: 2021-11-18
Also published as: JP7086324B2; JPWO2021229673A1

Abstract

This power semiconductor device is provided with: an insulating substrate (3); a high-voltage electrode (2) on which a semiconductor chip (1) is mounted; a ground electrode (4); a coating layer coating a creepage region extending from an outer-edge portion of a main surface (2fm) of the high-voltage electrode (2) to an end portion of a main surface (3fm) of the insulating substrate (3) via a side portion (2fs); and an encapsulant (7). The coating layer is electrically conductive and is composed of an electrically conductive coating layer (8) and an insulating coating layer (9), the electrically conductive coating layer (8) coating a continuous region on the inside of the creepage region including the outer-edge portion and the insulating substrate (3), the insulating coating layer (9) having a volume resistivity greater than or equal to that of the material of the encapsulant (7) and coating an outer portion of the continuous region of the creepage region and the electrically conductive coating layer (8) continuously. The high-voltage electrode (2) has a conduction maintaining structure formed therein that engages at least a part of the electrically conductive coating layer (8) to maintain conduction with the high-voltage electrode (2).

Description

Power semiconductor devices

This application relates to a semiconductor device for electric power.

Among semiconductor devices, power semiconductor devices, which are called power modules, are composite systems that control power by connecting multiple semiconductor chips according to the application and purpose and storing them in one package (sealed body). It is a semiconductor device. A semiconductor chip for high power control such as an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is mounted, and a large current of 1A to 1000A may flow during driving. Furthermore, in order to withstand long-term use for several years to several decades, it is required to select a material and structural design that does not cause dielectric breakdown even at high voltage while efficiently releasing a large amount of heat generated during driving.

Here, in a power semiconductor device, a boundary surface (hereinafter referred to as a triple junction) in which three materials, a high-voltage electrode, an insulating substrate, and a sealing material, which have a high electric field, are in contact with each other tends to be a discharge starting point. Further, when insulation defects such as peeling between materials, bubbles in the material, and foreign substances are included, the electric field of the insulation defects becomes high, and in particular, when the insulation defects are included in the vicinity of the triple junction, the reliability is significantly lowered. Therefore, there is disclosed a power semiconductor device (power semiconductor device) in which an insulating inorganic glass is applied as a coating material to the end of a high-voltage electrode and a part of an insulating substrate so as to cover the triple junction portion (for example). , Patent Document 1).

Japanese Unexamined Patent Publication No. 2000-340719 (paragraphs 0013 to 0025, FIGS. 3 to 4)

Inorganic glass has high insulating properties, so it can be expected to have an effect of suppressing discharge progress. However, due to the difference in the coefficient of linear expansion from other materials such as electrode materials, peeling is likely to occur due to the thermal stress associated with starting and stopping, the peeled part becomes a high electric field and becomes the discharge starting point, and the long-term insulation reliability deteriorates. was there.

The present application discloses a technique for solving the above-mentioned problems, and aims to obtain a power semiconductor device having high long-term insulation reliability.

The power semiconductor device disclosed in the present application includes an insulating substrate, a high-voltage electrode on which a power semiconductor element is mounted and bonded to one surface of the insulating substrate, and a ground electrode bonded to the other surface of the insulating substrate. At least one of the high-voltage electrode and the ground electrode is set as a plate-shaped coated electrode, and the side portion is formed from the outer edge portion of the main surface located on the opposite side of the joint surface of the coated electrode with the insulating substrate. The coating layer that covers the creeping region up to the end of the surface to which the coated electrode of the insulating substrate is joined, and the side where the coating layer and the high-voltage electrode of the insulating substrate are joined are collectively sealed. The coating layer comprises a sealing body to be stopped, and the coating layer has a conductive coating layer that covers a continuous region including the outer edge portion and the insulating substrate inside the creeping region, and a volume resistance. The ratio is equal to or higher than the material constituting the encapsulant, and the outer portion of the continuous region in the creeping region and the conductive coating layer are continuously coated. A conduction maintenance structure composed of an insulating coating layer, in which the conductive coating layer is locked to the coated electrode to maintain continuity with the coated electrode with respect to a displacement in a direction parallel to the bonding surface. Is formed.

According to the power semiconductor device disclosed in the present application, a continuity maintaining structure is formed so that a portion separated from the electrode by peeling can maintain the same potential as the electrode, so that it is used for power with high long-term insulation reliability. A semiconductor device can be obtained.

1A and 1B are a plan view of the power semiconductor device according to the first embodiment before sealing and a cross-sectional view after sealing, respectively. FIG. 5 is an enlarged partial cross-sectional view of a part of the power semiconductor device according to the first embodiment. 3A to 3D are plan views of high-voltage electrodes having different arrangements of recesses in the power semiconductor device according to the first embodiment. 4A and 4B are a cross-sectional view showing a different configuration on the ground electrode side and a sectional view showing a different configuration of the sealed body in the power semiconductor device according to the first embodiment. FIG. 3 is an enlarged partial cross-sectional view of a part of the power semiconductor device according to the first modification of the first embodiment. 6A to 6D are plan views of high-voltage electrodes having different arrangements of convex portions in the power semiconductor device according to the first modification of the first embodiment. FIG. 3 is an enlarged partial cross-sectional view of a part of a power semiconductor device according to a second modification of the first embodiment. 8A and 8B are a plan view of a high-voltage electrode of the power semiconductor device according to the third modification of the first embodiment and a partial cross-sectional view of a part of the power semiconductor device before encapsulation. .. 9A and 9B are a partial cross-sectional view of the power semiconductor device according to the second embodiment and a partially re-enlarged partial cross-sectional view thereof. 10A and 10B are a partial cross-sectional view of the power semiconductor device according to the third embodiment and a partially re-enlarged partial cross-sectional view thereof. FIG. 3 is an enlarged partial cross-sectional view of a part of a power semiconductor device according to a modification of the third embodiment. It is a partial cross-sectional view of the power semiconductor device which concerns on Embodiment 4. FIG. 13A and 13B are a partial cross-sectional view of the power semiconductor device according to the first modification of the fourth embodiment and a partial cross-sectional view of the power semiconductor device according to the second modification. FIG. 5 is a partial cross-sectional view of the power semiconductor device according to the fifth embodiment.

Embodiment 1.
1 to 4 are for explaining the configuration of the power semiconductor device according to the first embodiment, and FIG. 1 is a plan view (FIG. 1A) showing a state of the power semiconductor device before sealing. It is a cross-sectional view (FIG. 1B) corresponding to the line AA of FIG. 1A showing the state after sealing, and FIG. 2 is an enlarged partial cross-sectional view of the region R1 portion in FIG. 1B. 3A to 3D are plan views of high-voltage electrodes having different arrangements of recesses in the main surface, and FIG. 4 is a cross-sectional view (FIG. 4A) showing a form in which the ground electrode is also used as a heat sink. , FIG. 4B is a cross-sectional view (FIG. 4B) showing a form in which a sealed body is configured without using a case.

5 and 6 are for explaining the configuration of the power semiconductor device according to the first modification, and FIG. 5 is a partial cross-sectional view corresponding to FIG. 2 in which a part of the power semiconductor device is enlarged. 6A to 6D are plan views of high-voltage electrodes having different arrangements of convex portions. Further, FIG. 7 is a partial cross-sectional view corresponding to FIG. 2 in which a part of the power semiconductor device according to the second modification is enlarged, and FIG. 8 is a plan view of a high voltage electrode of the power semiconductor device according to the third modification. FIG. 8A and a partial cross-sectional view (FIG. 8B) of the power semiconductor device before encapsulation corresponding to the line BB of FIG. 8A.

Before explaining the configuration of the power semiconductor device 100 according to each embodiment of the present application, a basic configuration common to a general power semiconductor device will be described. In the basic configuration shown in FIG. 1, the high-voltage electrode 2 on which the semiconductor chip 1 is mounted is bonded to one surface (main surface 3 fm) of the insulating substrate 3, and the solder 5 is bonded to the other surface (back surface 3 fr). The ground electrode 4 to which the heat dissipation base plate 6 is bonded is joined via the ground electrode 4. Then, at least the side of the insulating substrate 3 to which the high voltage electrode 2 is joined is sealed with the sealing body 7.

The semiconductor chip 1 is a semiconductor element used for controlling high power such as an IGBT, MOSFET, and diode. Generally, one semiconductor chip 1 is equipped with one function, but a plurality of functions such as a diode-mounted MOSFET chip may be mounted. The substrate constituting the semiconductor chip 1 is preferably formed of a material called a wide bandgap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), or diamond (C).

If a semiconductor element is formed of a wide bandgap semiconductor material, for example, the power loss is smaller than that of a general silicon element, and the power consumption of the semiconductor element can be reduced. As a result, the thermal design can be increased and the power module can be miniaturized. Further, since silicon carbide and the like have high heat resistance, they can be operated at a higher temperature, but the thermal stress applied to peripheral members tends to be large, and the effect of the conductive maintenance structure described later is enhanced. It is connected to the control element via a bonding wire (aluminum, copper, etc.) or a connecting metal (gold, copper, etc.), but when a plurality of semiconductor chips 1 are mounted, the semiconductor chip is connected via the bonding wire or the connecting metal. It is also possible to connect 1 to each other for use.

The high-pressure electrode 2 is preferably formed of a metal having a high thermal conductivity, for example, copper is preferably used, but the high-pressure electrode 2 may be formed of aluminum or iron in addition to copper, or may be formed of an alloy thereof. You may be. The method of joining the semiconductor chip 1 and the high-voltage electrode 2 may be joined by a silver joining material in addition to the connection by solder (not shown). One or a plurality of high-voltage electrodes 2 are bonded to one insulating substrate 3, and the high-voltage electrodes 2 bonded to one insulating substrate 3 are not limited to the same potential.

Further, in order to mount more semiconductor chips 1, the high-voltage electrode 2 is regarded as a plate, and two surfaces parallel to the surface of the insulating substrate 3 (mainly for joining the bonding surface 2fj with the insulating substrate 3 and the semiconductor chip 1). The surface 2fm) is set to a wider area than the other surfaces (4 sides). This enables a semiconductor device with a smaller volume and a larger current capacity. For example, while the surface parallel to the insulating substrate 3 has a size of several cm × several cm, the length of the side perpendicular to the surface of the insulating substrate 3 (corresponding to the thickness of the plate material) is 0.1 mm to 5 mm or less. Design to be.

The insulating substrate 3 is a plate-shaped member mainly formed of an insulating material. It may be formed of a ceramic material such as alumina, silicon nitride, or aluminum nitride, or may be formed of an organic insulating sheet. The organic insulating sheet refers to a compound structure in which an inorganic filler having high thermal conductivity (alumina, aluminum nitride, boron nitride, etc.) is dispersed and filled in a resin having excellent insulating properties (epoxy resin, etc.). The organic insulating sheet as the insulating substrate 3 preferably has a thickness of 20 μm or more and 500 μm or less.

The ground electrode 4 is also preferably formed of a metal having a high thermal conductivity, and like the high-pressure electrode 2, for example, copper is preferably used, but it may be formed of aluminum or iron in addition to copper. It may be formed of those alloys. In order to prevent the insulating substrate 3 from being damaged by mechanical stress such as vibration and impact, it is preferable that the length of all sides is the same as that of the high voltage electrode 2.

The heat dissipation base plate 6 is preferably formed of a metal having a high thermal conductivity, for example, copper is preferably used, but aluminum or iron may be formed in addition to copper, or an alloy thereof may be used. It may have been done. Further, when connected to a heat radiation fin or the like, which is a well-known component, the power semiconductor device 100 can be dissipated more efficiently.

Of the encapsulants 7, the encapsulant 7s covering the high-voltage electrode 2 has a ^{volume resistivity of 10 10} within the driving temperature range of the power semiconductor device 100 such as _{air, nitrogen gas, SF 6 gas, silicone gel, epoxy resin, and florinate.} It is made of a material having a specific dielectric constant of Ω · cm or more and a relative dielectric constant of 10 or less. ^{The case material 7c is insulated with a volume resistivity of 10 10} Ω · cm or more and a relative permittivity of 10 or less within the driving temperature range of a power semiconductor device 100 such as PPS (Polyphenylene sulfide), LCP (Liquid Crystal Polymer), and epoxy resin. It is made of a sex resin. The surface condition is preferably smoother because dust or sewage in the external environment in which the power semiconductor device 100 is installed may adhere and discharge outside the case material 7c.

On the premise of the above-mentioned basic configuration, in the power semiconductor device 100 disclosed in the present application, the portion that becomes a triple junction via the conductive coating layer 8 is covered with the insulating coating layer 9, and the conductive coating layer 8 and the electrodes are covered. A continuity maintenance structure was formed so that the continuity between the two could be maintained.

Specifically, as shown in FIG. 2, the power semiconductor device 100 according to the first embodiment has a recess 2g in the vicinity of the end (outer edge) of the main surface 2fm on which the semiconductor chip 1 of the high voltage electrode 2 is placed. Is provided. Then, the main surface 2fm of the high-voltage electrode 2 includes the conductive coating layer 8 including the recess 2g portion and covering the region from the side portion 2fs to the main surface 3fm of the insulating substrate 3, and the conductive coating layer 8. An insulating coating layer 9 is provided so as to cover the peripheral portion of the insulating substrate 3 and the main surface 3 fm of the insulating substrate 3.

For the conductive coating layer 8, a material having a ^{volume resistivity of 10-2} Ω · cm or less within the operating temperature range of the power semiconductor device 100 is selected. For example, conductive resins such as polythiophene, polyacetylene, polyaniline, and oligothiophene can be used alone. Further, a compound resin in which carbon (graphene, carbon nanotubes, etc.) is mixed with a conductive resin or an insulating resin (epoxy, silicone, polyimide, etc.) is also possible. Further, a compound resin in which a metal (gold, silver, copper, etc.) filler or metal flakes are mixed with a conductive resin or an insulating resin can be mentioned.

For the insulating coating layer 9, a material having a ^{volume resistivity of 10 12} Ω · cm or more within the operating temperature range of the power semiconductor device 100 is selected. Examples thereof include insulating resins such as epoxy, silicone rubber, polyimide, polyamide and acrylic, and compound resins in which an insulating filler (boron nitride, silica, etc.) is mixed therein. As the insulating coating layer 9, a known coating material for power semiconductor devices can be used, and for example, the inorganic glass described in the background art may be used. Further, it is desirable that the volume resistivity is higher than that of the sealing material 7s, but when the above-mentioned high resistance material is used for the sealing material 7s, the same volume resistivity may be used.

In the recess 2g, in order to maintain the continuity between the conductive coating layer 8 and the high-voltage electrode 2 even when it is repeatedly subjected to thermal stress or the like, the portion that mechanically exerts the anchor effect is the peripheral portion of the main surface 2fm. It is provided continuously or distributed over the entire circumference. For example, it is formed so as to be recessed from the main surface 2 fm by laser, etching, marking or the like. At that time, as shown in FIG. 3A, it may be provided like a continuous groove extending over the entire circumference, or as shown in FIG. 3B, a plurality of recesses 2g may be dispersedly arranged. Furthermore, as a portion where the degree of thermal stress is smaller than that of other portions, the corner portion is preferentially provided as shown in FIG. 3C, or the side intersecting the direction in which the thermal stress is small as shown in FIG. 3D. It may be preferentially provided at the position corresponding to (side portion 2fs).

By providing the recess 2g that functions as a continuity maintenance structure, the conductive coating layer 8 is sandwiched between the inner walls of the recess 2g, and the conductive coating layer 8 sandwiches the side wall and the side portion 2fs on the outer peripheral side of the recess 2g. It is formed. In the power semiconductor device 100, the thermal stress (displacement) in the direction parallel to the main surface 3 fm of the insulating substrate 3 (the xy plane direction) is the main factor of the peeling that becomes the discharge starting point. Therefore, even when peeling occurs between the high-voltage electrode 2 and the conductive coating layer 8 due to thermal stress, at least a part of the conductive coating layer 8 is locked to the portion of the recess 2g of the high-voltage electrode 2 due to contact. Since the continuity is maintained, the potential is the same. As a result, the separated portion between the high-voltage electrode 2 and the conductive coating layer 8 having the same potential does not have a high electric field and does not become a discharge starting point that causes dielectric breakdown.

Of course, if peeling occurs at the interface between the insulating coating layer 9 and the conductive coating layer 8, the potential is different, so that the electric potential is increased. However, the bond between the insulating coating layer 9 and the conductive coating layer 8 is not good. It is stronger than the interface between the high-pressure electrode 2 and the conductive coating layer 8, which is the interface between the metal material and the resin material. Therefore, the first peeling occurs at the interface portion between the high voltage electrode 2 and the conductive coating layer 8, and the stress of the other portion is relaxed. As a result, the peeling is limited to the interface portion between the high-voltage electrode 2 having the same potential and the conductive coating layer 8, and the electric field is not increased, and the generation of the discharge starting point which is the cause of dielectric breakdown can be prevented.

In order to improve heat dissipation, a structure in which the ground electrode 4 and the heat dissipation base plate 6 are integrated is known, and even in the power semiconductor device 100 having the conductive maintenance structure of the present application, as shown in FIG. 4A, grounding is performed. A structure in which the electrode 4 and the heat dissipation base plate 6 are integrated can be applied. Further, a structure in which the sealing material 7s and the case material 7c are integrated is known in order to reduce the size of the device, reduce the cost, and reduce the process. Similarly, in the power semiconductor device 100 of the present application, as shown in FIG. 4B. It is also applicable to a structure using a sealing body 7 in which the sealing material 7s and the case material 7c are integrated.

Next, the process of forming the conductive coating layer 8 and the insulating coating layer 9 in the method for manufacturing the power semiconductor device 100 of the present application will be described. The coating layer such as the conductive coating layer 8 and the insulating coating layer 9 is generally cured after applying an uncured coating material (coating material) to the coated portion. As a method of applying the dressing, there are a dispenser in which the dressing is applied to the portion to be coated with a syringe or a brush, a dipping in which the portion to be coated is immersed in the dressing, and the like. Further, there are methods such as printing a coating material on a portion to be coated with a 3D printer, electrodeposition of adsorbing the coating material by static electricity, and spraying by spraying with gas, which can be appropriately selected.

Depending on the type of covering material, there are some that cure after a while at room temperature, but there are also those that need to be cured by heating, UV irradiation, etc. In addition to the method of applying an uncured covering material, it can be formed by a method of attaching a sheet-shaped covering material to a member and then heating it to bring it into close contact, and it is also possible to coat it by spraying a resin.

Here, suitable conditions for installing the conductive maintenance structure and a modified example in consideration of the conditions will be described. Peeling occurs mainly due to deformation of the members constituting the power semiconductor device 100 due to the thermal cycle during driving, and the stress generated by the difference in the amount of deformation cannot be withstood. Here, in order to mount more semiconductor chips 1 on the high-voltage electrode 2, as described above, the sides (for example, the four sides of the main surface 2fm) in the direction parallel to the main surface 3fm of the insulating substrate 3 (the xy plane direction). ) Is longer than the length of the side in the vertical direction (z direction) (the side in the thickness direction (z direction) of the side portion 4fs). On the other hand, the amount of deformation due to heat ΔX [m] is ^{represented by the product of the coefficient of linear expansion α [K / 10-6} ], the temperature change ΔT [K], and the original size X [m].

Therefore, the deformation amount ΔX is smaller in the direction perpendicular to the main surface 3 fm of the insulating substrate 3 (thickness direction: z direction) and larger in the horizontal direction (direction parallel to the main surface 2 fm: xy plane direction). .. As in the design example described above, when the length of each side of the surface parallel to the main surface 3 fm of the insulating substrate 3 (main surface 2 fm) is several cm and the length of the vertical side is 0.1 mm to 5 mm or less, the parallel side is obtained. Assuming that the amount of deformation in the above direction (xy plane direction) is 1, the vertical direction (z direction) is 1/100 to 1/10. Therefore, as described in FIGS. 3C and 3D, the conductivity maintaining structure needs to be provided at a location where the amount of deformation ΔX due to the thermal cycle is small, or a structure that maintains contacts (maintains continuity) even if deformed. ..

First modification example.
In the first modification, as a conductive maintenance structure, as shown in FIG. 5, in the region covered by the conductive coating layer 8, the height He from the joint surface 2fj is set on the outer edge portion of the main surface 2fm, and the semiconductor chip 1 A convex portion 2p higher than the height Hm of the main region (inner portion) to which is joined is provided.

Also in this case, with respect to the high-voltage electrode 2, the conductive coating layer 8 includes the side portion 2fs from the portion inside the tip surface 2fp of the convex portion 2p of the main surface 2fm to the portion covering the main surface 3fm of the insulating substrate 3. Since it is covered, it has a structure that sandwiches the side wall of the convex portion 2p, and the conductive coating layer 8 is locked against the displacement parallel to the main surface 3fm, so that the contact (conduction) can be maintained.

At that time, as shown in FIG. 6A, it may be provided as a continuous continuous ridge over the entire circumference, or as shown in FIG. 6B, a plurality of convex portions 2p may be dispersedly arranged. Further, as a portion having a small deformation amount ΔX, as shown in FIG. 6C, the corner portion is preferentially provided, and as shown in FIG. 6D, it corresponds to a side (side portion 2fs) intersecting with a direction having a small thermal stress. It may be provided preferentially at the position where it is to be used.

Second modification example.
In the second modification, as a conductive maintenance structure, as shown in FIG. 7, in the region covered by the conductive coating layer 8, the height from the joint surface 2fj is set in the region near the outer edge of the main surface 2fm of the high voltage electrode 2. An inclined portion 2t is provided so that the height becomes higher toward the outside (closer to the outer edge).

Also in this case, the conductive coating layer 8 covers the high-voltage electrode 2 from the portion where the inclined portion 2t of the main surface 2fm is formed to the side portion 2fs and covers the portion covering the main surface 3fm of the insulating substrate 3. .. Therefore, in particular, since the inclined portion 2t portion serves as an anchor and engages the conductive coating layer 8 with respect to the displacement parallel to the main surface 3fm, contact (conduction) can be maintained.

Further, as described in FIG. 6 of the first modification, the inclined portion 2t may be continuously formed over the entire circumference, or may be dispersedly arranged. Further, as a portion having a small deformation amount ΔX, it may be preferentially provided at a corner portion, or may be preferentially provided at a position corresponding to a side (side portion 2fs) intersecting with a direction having a small thermal stress. ..

Third modified example.
In the third modification, as a conductive maintenance structure, as shown in FIGS. 8A and 8B, an indented portion 2b that invades inward from the side portion 2fs of the high voltage electrode 2 is provided. The recessed portion 2b has a portion having a larger cross-sectional area than the portion facing the side portion 2fs (outside), such as a T-shape or a cross shape in a direction parallel to the main surface 2fm (xy-plane direction). It is formed so as to exist inside.

Also in this case, the conductive coating layer 8 including the side portion 2fs from the outer edge portion of the main surface 2fm of the high-voltage electrode 2 and covering up to the portion covering the main surface 3fm of the insulating substrate 3 bites from the side portion 2fs and is on the inner side. A portion having a large cross-sectional area serves as an anchor, and contact (conductivity) can be maintained. At this time, it is desirable to fill the indentation portion 2b with the conductive coating material so that the thickness of the conductive coating layer 8 in the side portion 2fs portion is not thinner than the other portions. The shape of the recessed portion 2b in the direction parallel to the main surface 2fm (the xy plane direction) was stressed in the direction away from the side portion 2fs if it was a hook shape even if the cross-sectional area did not change. In this case as well, the effect of the high-voltage electrode 2 locking the conductive coating layer 8 to maintain continuity can be obtained. Therefore, for example, it may be L-shaped, V-shaped, or divergent.

Further, as shown in FIG. 8B, the insulating coating layer 9 may be formed so as to cover the conductive coating layer 8 in the recessed portion 2b, but the present invention is not limited to this. For example, the conductive coating layer 8 may be filled up to the level of the main surface 2fm of the recessed portion 2b or so as to rise from the main surface 2fm, and the insulating coating layer 9 may be coated from above.

Further, as shown in FIG. 8, the recessed portion 2b increases the effect as a conductive maintenance structure by a synergistic effect with the recess 2g, but the present invention is not limited to this, and has been described in the first modification and the second modification. It may be used in combination with the convex portion 2p and the inclined portion 2t. Furthermore, it is possible to make the recessed portion 2b alone function as a conductive maintenance structure without using it in combination. The place where the entrance of the invagination portion 2b is provided may be distributed over the entire circumference of the side portion 2fs, but may be a part as shown in FIG. It may be preferentially provided at the corresponding position.

Embodiment 2.
In the first embodiment, the interface state between the conductive resin layer and the insulating resin layer is not particularly mentioned. In the second embodiment, a configuration for strengthening the bond at the interface between the conductive resin layer and the insulating resin layer will be described. FIG. 9 is for explaining a certain configuration of the power semiconductor device according to the second embodiment, and FIG. 9A is a partial cross section corresponding to FIG. 2 described in the first embodiment of the power semiconductor device. FIG. 9B is a partial cross-sectional view of the region R2 portion of FIG. 9A re-enlarged.

In the power semiconductor device according to the second embodiment, the same configuration as that of the first embodiment or the modified example can be applied to the configuration excluding the interface portion between the conductive coating layer and the insulating coating layer. The description of the same part will be omitted.

In order for the conductive coating structure to be formed at the same potential portion where the peeling does not become the discharge starting point, it is premised that the peeling does not occur between the conductive coating layer 8 and the insulating coating layer 9. Therefore, in the second embodiment, a configuration or a manufacturing method for strengthening the bond between the conductive coating layer 8 and the insulating coating layer 9 to prevent peeling that can be a discharge starting point will be exemplified.

(1) Use of coupling agents and adhesives.
A conductive coating material is applied to a part of the high-voltage electrode 2 and the insulating substrate 3 and cured, and then a silane coupling material, a triazine thiol compound-containing adhesive or the like is applied, and the insulating coating material is applied and cured. As a result, a chemical bond such as a cross-linking reaction is promoted between the conductive coating layer 8 and the insulating coating layer 9, and the bond at the interface is strengthened. After prebaking the conductive coating layer 8 to make it in a semi-cured state, a coupling material and an adhesive are applied, an insulating coating material is applied, and then the conductive coating layer 8 and the insulating coating layer 9 are cured. Is also good.

(2) Surface activation by plasma irradiation.
A conductive coating material is applied to a part of the high-voltage electrode 2 and the insulating substrate 3 and cured, and then an oxygen plasma or the like is irradiated, and then the insulating coating material is immediately applied and cured. As a result, the surface of the conductive coating layer 8 is activated, the chemical bond with the insulating coating layer 9 is promoted, and the bond at the interface is strengthened. The conductive coating layer 8 may be prebaked to a semi-cured state, and then plasma is irradiated to apply the insulating coating material, and then the conductive coating layer 8 and the insulating coating layer 9 may be cured.

(3) Creation of uneven pattern by etching.
As shown in FIGS. 9A and 9B, a concave-convex pattern is formed on the surface 8f of the conductive coating layer 8 by applying a conductive coating material to the high-voltage electrode 2, curing, and etching, and then the insulating coating. Apply the material and cure. The interface between the conductive coating layer 8 and the insulating coating layer 9 is formed in an uneven shape, the total area is expanded, and the bond becomes stronger.

(4) Creating an uneven pattern using a comb-shaped jig.
A conductive coating material is applied to the high-voltage electrode 2 and prebaked, an uneven pattern as shown in FIG. 9 is created on the surface 8f by a comb-shaped jig, and an insulating coating material is applied and cured from above. In this case, the concave portions and the convex portions are formed in a streak shape, but the interface between the conductive coating layer 8 and the insulating coating layer 9 is formed in a concavo-convex shape, the total area is expanded, and the bond becomes stronger. ..

(5) Roughening by sandblasting.
A conductive coating material is applied to the high-voltage electrode 2 and cured, and then roughened by filing or sandblasting to form an uneven pattern as shown in FIG. 9 on the surface 8f, and then an insulating coating material is applied. By roughening the surface of the conductive coating layer 8, the area of the interface is expanded and the bond becomes stronger.

(6) Layer formation by filler gradient.
The resin used as the base material of the conductive coating layer 8 and the insulating coating layer 9 is unified, a layer structure is formed by a filler gradient, and a coating layer having no layer interface is created by molding. At the time of preparation, the high-voltage electrode 2 is coated with a conductive coating material, prebaked, and an insulating coating material is applied and cured.

(7) Simultaneous curing of the conductive coating layer 8 and the insulating coating layer 9.
Both the coating material forming the conductive coating layer 8 and the coating material forming the insulating coating layer 9 are formed into a film in a prebaked state, and the two layers are overlapped by pressure bonding and then attached to the high-voltage electrode 2 to be cured. At that time, it is preferable to use vacuum pressure bonding or the like so as not to leave defects such as air bubbles between the conductive coating layer 8 and the insulating coating layer 9. Alternatively, the uncured coating material forming the conductive coating layer 8 is applied to the high-voltage electrode 2 and then prebaked, and the uncured insulating coating material is applied thereto and then cured. In either case, it is necessary to select a material that cures at the same temperature as the material that forms the conductive coating layer 8 and the insulating coating layer 9.

(8) Others.
The coating material forming the insulating coating layer 9 is prebaked into a sheet, the coating material forming the conductive coating layer 8 is applied by spraying, and the coated side is attached to the high-voltage electrode 2.

Embodiment 3.
In the above-described first or second embodiment, it is basically assumed that the interface between the conductive coating layer and the high-pressure electrode is more easily peeled off than the interface between the conductive coating layer and the insulating coating layer. It has been described that the first peeling is guided to the interface between the conductive coating layer and the high voltage electrode. In the third embodiment, a configuration in which peeling is preliminarily charged at the interface between the conductive coating layer and the high-voltage electrode will be described. 10A is for explaining the configuration of the power semiconductor device according to the third embodiment, and FIG. 10A is a partial cross-sectional view and a view corresponding to FIG. 2 described in the first embodiment of the power semiconductor device. 10B is a partial cross-sectional view of the region R3 portion of FIG. 10A re-enlarged.

Further, FIG. 11 is a partial cross-sectional view corresponding to FIG. 10B, which is an enlarged part of a power semiconductor device according to a modification for forming a charge peeling. In the power semiconductor device according to the third embodiment, the same configurations as those disclosed in the above-described first and second embodiments can be applied to the configurations other than the charge peeling, and the same portions will be described. Is omitted.

In the power semiconductor device 100 according to the third embodiment, as shown in FIGS. 10A and 10B, a charged peeling Gp is provided between the side portions 2fs of the high voltage electrode 2 and the conductive coating layer 8. I tried to provide it. The target to which the charged peeling Gp is provided is a portion extending from the portion on the insulating substrate 3 side of the side portion 2fs intersecting the main surface 3fm of the insulating substrate 3 to the main surface 3fm of the insulating substrate 3. Then, the area of the region away from the side portion 2fs (proportional to the vertical length Lv) is designed to be wider than the area of the region away from the main surface 3fm of the insulating substrate 3 (proportional to the horizontal length Lh). By this charge peeling Gp, the stress due to the deformation of the high voltage electrode 2 is absorbed, and the stress applied to the interface portion between the conductive coating layer 8 and the insulating coating layer 9 is relaxed. That is, it is possible to prevent the occurrence of peeling at a portion where other peeling is not desired at the expense of the charged peeling Gp.

Also in this case, the electric field of the charged peeling Gp portion is increased by maintaining the continuity between the conductive coating layer 8 and the high voltage electrode 2 in the recess 2g provided as the conductivity maintaining structure on the outer edge of the main surface 2fm of the high voltage electrode 2. This does not mean that the occurrence of the discharge starting point, which is the cause of dielectric breakdown, can be prevented.

The method of forming the charged peeling Gp is illustrated below.
(1) Apply mold release agent.
After applying a mold release agent such as a fluororesin (for example, PTFE, PFE) to the side portion 2fs of the high-voltage electrode 2, a coating material for forming the conductive coating layer 8 and a coating material for forming the insulating coating layer 9 are applied. Apply and cure. Of the side portions 2fs, the portion to which the mold release agent is applied does not adhere to the conductive coating material, so that the charged peeling Gp is formed.

(2) Non-adhesive pasting of sheet material.
A sheet-shaped coating material is used as the coating material for forming the conductive coating layer 8, and the high-voltage electrode 2 is attached to the side portion 2fs of the high-voltage electrode 2 with a gap and cured. Of the side portions 2fs, the portion with a gap does not adhere to the sheet-shaped covering material, so that the charged peeling Gp is formed.

(3) High-voltage electrode shape (modification example).
In the power semiconductor device 100 according to the modified example, as shown in FIG. 11, the side portions 2fs are inclined inward from the main surface 2fm toward the bonding surface 2fj with the insulating substrate 3. As a result, for example, even when the conductive coating layer 8 is formed by using a liquid coating material, the adhesion between the side portion 2fs and the conductive coating layer 8 becomes poor, and the charged peeling Gp is formed at the time of curing or at the initial stage of operation. Can be formed. Of course, when used in combination with the above-mentioned mold release agent and non-adhesive sticking of the sheet material, it is possible to more easily form the charged peeling Gp.

Embodiment 4.
In the above-mentioned first to third embodiments, the configuration in which the conductive maintenance structure and the coating layer are provided for the high-voltage electrode has been described. In the fourth embodiment, a configuration in which a conductive maintenance structure is formed with respect to the ground electrode to provide a coating layer will be described. FIG. 12 is a partial cross-sectional view corresponding to FIG. 2 described in the first embodiment, showing the configuration of the power semiconductor device according to the fourth embodiment.

Further, FIG. 13 is for explaining the configuration of the power semiconductor device according to the modified example, and FIG. 13A is a partial cross-sectional view corresponding to FIG. 12 of the power semiconductor device according to the first modified example, FIG. 13B. Is a partial cross-sectional view corresponding to FIG. 12 of the power semiconductor device according to the second modification. The power semiconductor device according to the fourth embodiment is the same as the configuration disclosed in the first and second embodiments described above, except that the conductive maintenance structure is provided on the ground electrode side, and the same portion is used. Omits the explanation.

In the power semiconductor device 100 according to the fourth embodiment, as shown in FIG. 12, as a conductive maintenance structure, the ground electrode 4 has a conductive maintenance structure in the vicinity of the outer edge portion of the main surface 4fr of the ground electrode 4 corresponding to the main surface 2fm of the high voltage electrode 2. It is provided with a recess of 4 g. Then, as in the basic configuration described in the first embodiment, the high voltage electrode 2 on which the semiconductor chip 1 is mounted is bonded to the main surface 3 fm of the insulating substrate 3, and the ground electrode 4 is bonded to the other surface (back surface 3 fr). The surfaces 4fj are joined. A heat dissipation base plate 6 is bonded to the main surface 4fr of the ground electrode 4 via a solder 5, and the inner surface 6fi side of the heat dissipation base plate 6 including the high voltage electrode 2 portion is a sealing body 7 (only the sealing material 7s is drawn in the figure). ) Is sealed.

That is, the ground electrode 4 includes the conductive coating layer 8 including the recess 4g portion and covering the region from the side portion 4fs to the back surface 3fr of the insulating substrate 3 and the conductive coating layer 8 with respect to the basic configuration. An insulating coating layer 9 is provided to cover the outer edge portion of the main surface 4fr and the back surface 3fr of the insulating substrate 3.

In this way, by providing the recess 4g that functions as a continuity maintenance structure on the ground electrode 4, the structure in which the conductive coating layer 8 is sandwiched between the inner walls of the recess 4g, and the side wall and side portions 4fs on the outer peripheral side of the recess 4g are formed. A structure is formed in which the conductive coating layer 8 is sandwiched. Therefore, even if peeling occurs between the ground electrode 4 and the conductive coating layer 8 due to thermal stress, at least a part of the conductive coating layer 8 is locked to the portion of the recess 4g of the ground electrode 4 and is contacted. Since the continuity is maintained, the potential is the same. Therefore, the separated portion between the ground electrode 4 and the conductive coating layer 8 having the same potential does not have a high electric field and does not serve as a discharge starting point that causes dielectric breakdown.

From the viewpoint of preventing the generation of the discharge starting point, it is considered preferable to provide the insulating coating layer 9 on the high voltage electrode 2 having a high voltage rather than the ground electrode 4 having a ground potential. However, even when the peeling occurs on the side 4fs side of the ground electrode 4, the peeling point has a higher electric field than the surrounding insulation, and the air layer has a lower breaking electric field than the surrounding insulation. Even if the electric field is low, there is a good possibility that it will be the starting point of discharge. Therefore, it is also significant to provide the conductivity maintaining structure on the ground electrode 4 side. When the ground electrode 4 is provided with a coating layer, the heat dissipation base plate 6 is joined by solder 5 after the conductive coating layer 8 and the insulating coating layer 9 are formed. Therefore, the formed coating layer is pressed by the solder 5 and is fixed more firmly than when it is applied to the high-voltage electrode 2, and rather stress is applied, and peeling may easily occur between the coating layer and the ground electrode 4. It is also conceivable that the effect of the conductive maintenance structure will be more exerted.

Suitable conditions for providing the conductive maintenance structure on the ground electrode 4 and a modified example in consideration of the conditions will also be described. The stress applied to the ground electrode 4 by the thermal cycle is ^{expressed by the product of the linear expansion coefficient α [K / 10-6} ], the temperature change ΔT [K], and the original size X [m], as in the high pressure electrode 2. Depends on the amount of deformation ΔX [m]. Therefore, as described with reference to FIG. 3 of the first embodiment, the concave portion 4g is effectively provided in a region where the amount of deformation is relatively small in the outer edge portion of the main surface 4fr of the ground electrode 4, thereby effectively generating a thermal cycle. The contact point between the ground electrode 4 and the conductive coating layer 8 is held so as not to cause total peeling even at the time. Of course, it goes without saying that they may be provided continuously or distributed over the entire circumference.

Further, the conductive maintenance structure is not limited to the concave portion 4g, and the following deformation examples can be applied as in the first modification to the third modification of the first embodiment.

First modification example.
In the first modification, as shown in FIG. 13A, the height He from the joint surface 4fj is the height He from the joint surface 4fj to the outer edge portion of the main surface 4fr of the ground electrode 4, and the main region (inner portion: inner portion:) to which the heat dissipation base plate 6 is soldered. A convex portion 4p higher than the height Hm) is provided. Also in this case, as in the first modification of the first embodiment, the conductive coating layer 8 includes the side portion 4fs from the inner portion of the tip surface 4fp of the convex portion 4p of the heat radiation surface 4fm with respect to the ground electrode 4. , The portion of the insulating substrate 3 covering the back surface 3fr is covered. Therefore, a structure is formed in which the side wall of the convex portion 4p is sandwiched, and the conductive coating layer 8 is locked against a displacement parallel to the back surface 3fr, so that contact (conduction) can be maintained.

Also in this case, as described with FIG. 6A in the first embodiment, the ridges may be provided as a continuous continuous ridge over the entire circumference, and as described with FIG. 6B, a plurality of convex portions 4p may be dispersedly arranged. You may let it. Further, as a portion having a small deformation amount ΔX, as described in FIG. 6C, the corner portion is preferentially provided, or as described in FIG. 6D, a side (side portion 4fs) intersecting with a direction having a small thermal stress. It may be provided preferentially at the position corresponding to.

Second modification example.
In the second modification, as shown in FIG. 13B, in the region covered by the conductive coating layer 8, the height from the joint surface 4fj faces outward toward the region near the outer edge of the main surface 4fr of the ground electrode 4. An inclined portion 4t that becomes higher (closer to the outer edge portion) is provided. Also in this case, as in the second modification of the first embodiment, the conductive coating layer 8 includes the side portion 4fs from the portion where the inclined portion 4t of the main surface 4fr is formed with respect to the ground electrode 4, and the insulating substrate 3 It covers up to the part of the back surface 3fr. Therefore, in particular, since the inclined portion 4t portion serves as an anchor and engages the conductive coating layer 8 with respect to the displacement parallel to the back surface 3fr, contact (conduction) can be maintained.

Further, the inclined portion 4t may be continuously formed over the entire circumference, or may be dispersedly arranged. Further, as a portion having a small deformation amount ΔX, it may be preferentially provided at a corner portion, or may be preferentially provided at a position corresponding to a side (side portion 4 fs) intersecting with a direction having a small thermal stress. ..

Third modified example.
In the third modification, as described with reference to FIG. 8 in the third modification of the first embodiment, as a conductive maintenance structure, an indented portion (invaded portion 2b) that invades inward from the side portion 4fs of the ground electrode 4. Corresponding to). The recessed portion has a portion having a larger cross-sectional area than the portion facing the side portion 4fs (outside), such as a T-shape or a cross shape in a direction parallel to the main surface 4fr (in the xy plane direction). It is formed to exist in.

In addition, also in the present embodiment 4 and each modification, the structure or the manufacturing method shown in any one of (1) to (8) described in the second embodiment is applied, and the conductive coating layer 8 and the insulating property are applied. It is possible to strengthen the bond with the coating layer 9.

Embodiment 5.
In the fifth embodiment, as in the third embodiment with respect to the first and second embodiments, the power semiconductor device described in the fourth embodiment is provided with a charge peeling on the ground electrode side. FIG. 14 is a partial cross-sectional view corresponding to FIG. 12 described in the fourth embodiment, showing the configuration of the power semiconductor device according to the fifth embodiment.

In the power semiconductor device 100 according to the fifth embodiment, as shown in FIG. 14, a charged peeling Gp is provided between the side portion 4fs of the ground electrode 4 and the conductive coating layer 8. The target to be provided with the charged peeling Gp is a portion in contact with the side portion 4fs of the ground electrode 4 intersecting the back surface 3fr of the insulating substrate 3 and a part of the back surface 3fr of the insulating substrate 3. Then, the area of the region away from the side portion 4fs is designed to be wider than the area of the region away from the back surface 3fr of the insulating substrate 3. By this charge peeling Gp, the stress due to the deformation of the ground electrode 4 is absorbed, and the stress applied to the interface portion between the conductive coating layer 8 and the insulating coating layer 9 is relaxed.

Also in this case, the electric field of the charged peeling Gp portion is increased by maintaining the continuity between the conductive coating layer 8 and the ground electrode 4 in the recess 4g provided as the conductivity maintenance structure on the outer edge of the main surface 4fr of the ground electrode 4. In this case, it is possible to prevent the generation of the discharge starting point, which is the cause of dielectric breakdown.

Further, as for the preparation of the charged peeling Gp on the ground electrode 4 side, the preparation methods (1) to (3) exemplified in the third embodiment can be applied.

Further, while various exemplary embodiments and examples are described in the present application, the various features, embodiments, and functions described in one or more embodiments may be specific embodiments. It is not limited to the application exemplified in the embodiment, but can be applied to the embodiment alone or in various combinations. Therefore, innumerable variations not exemplified are envisioned within the scope of the techniques disclosed herein. For example, it includes cases where at least one component is modified, added or omitted, and further, at least one component is extracted and combined with the components disclosed in other embodiments. do.

As described above, according to the power semiconductor device 100 according to each embodiment of the present application, the insulating substrate 3 and the power semiconductor element (semiconductor chip 1) are mounted, and one surface (main surface 3 fm) of the insulating substrate 3 is mounted. ), At least one of the ground electrode 4, the high pressure electrode 2 and the ground electrode 4 bonded to the other surface (back surface 3fr) of the insulating substrate 3 is set as a plate-shaped covering target electrode. , From the outer edge of the main surface 2fm (or main surface 4fr) located on the opposite side of the bonding surface 2fj (or bonding surface 4fj) of the coated electrode to the insulating substrate 3 via the side portion 2fs (or side portion 4fs). , A coating layer (conductive coating layer 8 and insulating coating layer 9) covering the creeping region up to the end of the surface (main surface 3fm or back surface 3fr) to which the electrode to be coated of the insulating substrate 3 is joined, and the coating layer. And a sealant 7 that collectively seals the side to which the high-voltage electrode 2 of the insulating substrate 3 is joined, the coating layer has conductivity, and the outer edge portion and the insulating substrate 3 are formed inside the creepage region. The outer portion of the continuous region in the creeping region where the conductive coating layer 8 covering the continuous region including the conductive coating layer 8 and the volume resistance are equal to or higher than the material constituting the sealing body 7 and are higher than the material constituting the sealing body 7. And the insulating coating layer 9 that continuously covers the conductive coating layer 8, and the coated electrode is displaced in the direction parallel to the bonding surface 2fj (or the bonding surface 4fj) (xy surface direction). On the other hand, a continuity maintenance structure (for example, concave portion 2g, convex portion 2p, inclined portion 2t, recessed portion 2b, concave portion 4g, convex portion 4p, inclined portion) that locks the conductive coating layer 8 to maintain continuity with the object to be coated. Since the portion 4t) is formed so as to be formed, even if peeling occurs, the portion (conductive coating layer 8) separated from the covering target electrode by peeling can maintain the same potential as the covering target electrode, so that the insulation is broken. It does not generate a discharge starting point that causes the above. Therefore, it is possible to obtain a power semiconductor device having high long-term insulation reliability.

As a continuity maintenance structure, a recess 2g (or a recess 4g) recessed from the main surface 2fm (or the main surface 4fr) is provided in a portion of the continuous region near the outer edge of the main surface 2fm (or the main surface 4fr). If the structure is such that the conductive coating layer 8 is sandwiched between the inner walls of the recess 2g or the recess 4g, and the side wall and the side portion 2fs or the side portion 4fs on the outer peripheral side of the recess 2g or the recess 4g are the conductive coating layer. A structure sandwiched by 8 is formed. Therefore, even if the high-voltage electrode 2 or the ground electrode 4 and the conductive coating layer 8 are peeled off due to thermal stress, at least a part of the conductive coating layer 8 is locked at the recess 2g or the recess 4g. , It is possible to easily form a structure having the same potential while maintaining continuity by contact.

As a continuity maintenance structure, the outer edge portion is provided with a convex portion 2p or a convex portion 4p whose height He from the joint surface 2fj (or joint surface 4fj) is higher than that of the inner portion (height Hm). Then, the conductive coating layer 8 has a structure that sandwiches the side wall of the convex portion 2p or the convex portion 4p, and locks the conductive coating layer 8 with respect to a displacement parallel to the main surface 3fm or the back surface 3fr, so that contact (conduction) is achieved. ) Can be maintained.

As a continuity maintenance structure, an inclination in which the height from the joint surface 2fj (or the joint surface 4fj) becomes higher toward the outer edge portion of the continuous region near the outer edge portion of the main surface 2fm (or main surface 4fr). If the portion 2t or the inclined portion 4t is provided, the inclined portion 2t portion or the inclined portion 4t portion serves as an anchor, and the conductive coating layer 8 is locked against a displacement parallel to the main surface 3fm or the back surface 3fr. Therefore, contact (conductivity) can be maintained.

As a continuity maintenance structure, if the recessed portion 2b is provided from the side portion 2fs or the side portion 4fs, and the recessed portion 2b including the hook shape is provided in the cross-sectional shape parallel to the main surface 2fm (or the main surface 4fr). The conductive coating layer 8 that bites into the recessed portion 2b is locked inside the high-voltage electrode 2 or the ground electrode 4, and contact (conduction) can be maintained.

The continuity maintenance structure is selectively formed at a position corresponding to the side portion 2fs or the side portion 4fs that intersects the direction in which the displacement is small in the direction parallel to the joint surface 2fj (or the joint surface 4fj) (xy plane direction). By doing so, it is possible to form a conductive maintenance structure that can be securely locked in a small number of steps.

If peeling (prepared peeling Gp) is formed in advance between the side portion 2fs or the side portion 4fs near the insulating substrate 3 and the conductive coating layer 8, the charged peeling Gp is sacrificed. , It is possible to prevent the occurrence of peeling in the part where other peeling is not desired. Further, due to the above-mentioned continuity maintenance structure, the charged peeling Gp portion does not have a high electric field, and the generation of the discharge starting point, which is the cause of dielectric breakdown, can be more effectively prevented.

If the interface (surface 8f) between the conductive coating layer 8 and the insulating coating layer 9 is formed in an uneven shape, the conductive coating layer 8 and the insulating coating layer 9 are not desired to be peeled off. It is possible to prevent the occurrence of peeling at the interface portion of.

1: Semiconductor chip, 100: Power semiconductor device, 2: High voltage electrode, 2b: Indentation part, 2fj: Joint surface, 2fm: Main surface, 2fp: Tip surface, 2fs: Side part, 2g: Concave part, 2p: Convex part , 2t: Inclined part, 3: Insulated substrate, 3fm: Main surface, 3fr: Back surface, 4: Ground electrode, 4fj: Joint surface, 4fr: Main surface, 4fp: Tip surface, 4fs: Side part, 4g: Recess, 4p : Convex part, 4t: Inclined part, 5: Solder, 6: Heat dissipation base plate, 7: Encapsulant, 7c: Case material, 7s: Encapsulant, 8: Conductive coating layer, 8f: Surface, 9: Insulation Sexual coating layer, Gp: Preparation peeling, He: Height, Hm: Height, Lh: Horizontal length, Lv: Vertical length.

Claims

Insulated board,
A high-voltage electrode on which a power semiconductor element is mounted and bonded to one surface of the insulating substrate,
A ground electrode bonded to the other surface of the insulating substrate,
At least one of the high-voltage electrode and the ground electrode is set as a plate-shaped coated electrode, and the side portion is formed from the outer edge portion of the main surface located on the opposite side of the joint surface of the coated electrode with the insulating substrate. The coating layer that covers the creepage region up to the end of the surface to which the coated electrode of the insulating substrate is joined, and the side where the coating layer and the high voltage electrode of the insulating substrate are joined are collectively sealed. Equipped with a sealing body to stop,
The coating layer has conductivity, and the conductive coating layer that covers a continuous region including the outer edge portion and the insulating substrate inside the creeping region, and the volume resistivity constitute the sealing body. It is equal to or higher than the material constituting the encapsulant, and is composed of an insulating coating layer that continuously covers the outer portion of the continuous region in the creeping region and the conductive coating layer.
The coated electrode is characterized in that a conduction maintaining structure is formed in which the conductive coating layer is locked against a displacement in a direction parallel to the bonding surface to maintain continuity with the coated electrode. Semiconductor device for electric power.
The power supply according to claim 1, wherein the continuity maintaining structure is provided with a recess recessed from the main surface in a portion of the continuous region close to the outer edge portion of the main surface. Semiconductor device.
The power semiconductor device according to claim 1, wherein, as the continuity maintaining structure, a convex portion having a height from the joint surface higher than that of the inner portion is provided on the outer edge portion.
As the continuity maintaining structure, an inclined portion is provided in a portion of the continuous region close to the outer edge portion of the main surface so that the height from the joint surface becomes higher as the height from the joint surface approaches the outer edge portion. The power semiconductor device according to claim 1.
The invention according to any one of claims 1 to 4, wherein the continuity maintaining structure is provided with an recessed portion that is recessed from the side portion and includes a hook shape in a cross-sectional shape parallel to the main surface. The power semiconductor device described.
Any of claims 1 to 5, wherein the continuity maintaining structure is selectively formed at a position corresponding to a side portion where the displacement intersects a small direction in a direction parallel to the joint surface. The power semiconductor device according to item 1.
The power semiconductor device according to any one of claims 1 to 6, wherein a peeling is formed in advance between the side of the side portion close to the insulating substrate and the conductive coating layer. ..
The power semiconductor device according to any one of claims 1 to 7, wherein the interface between the conductive coating layer and the insulating coating layer is formed in an uneven shape.