WO2021227092A1 - 一种多节点主从式网络系统及其中断处理方法 - Google Patents

一种多节点主从式网络系统及其中断处理方法 Download PDF

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WO2021227092A1
WO2021227092A1 PCT/CN2020/090966 CN2020090966W WO2021227092A1 WO 2021227092 A1 WO2021227092 A1 WO 2021227092A1 CN 2020090966 W CN2020090966 W CN 2020090966W WO 2021227092 A1 WO2021227092 A1 WO 2021227092A1
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message
block
hardware
bits
software
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French (fr)
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葛鹏
纪志强
刘晓娟
赵志勇
谢鹏
房亮
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北京国科天迅科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/548—Queue
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt

Definitions

  • This application relates to the field of multi-node communication systems, and in particular to a multi-node master-slave network system and an interrupt processing method thereof.
  • Hardware interrupt is one of the key links in the interaction between software and hardware, and it is also the only way for hardware to initiate interaction actively.
  • Message interrupt is a kind of hardware interrupt, which is used by the hardware to transmit the signal of the completion of the current round of execution and the result of the execution of the message to the software.
  • FC-AE-1553 network is a high-bandwidth, low-latency, high-reliability optical fiber communication bus protocol. Its protocol is formulated by the American National Standards Institute (ANSI) and defines the MIL-STD-1553B protocol to the fiber channel (FC, Fiber Channel) high-level protocol mapping, which provides protocol support for the development of the fiber 1553 bus. Like the traditional MIL-STD-1553B bus, FC-AE-1553 defines a command/response bus standard. At the same time, in order to improve reliability, the transmission channel also uses a dual redundant backup mechanism.
  • FC communication is a high-speed communication
  • the frequency of message interruption is high, and the software must ensure that every interruption must be received and cannot be lost, so as to ensure the reliability of communication.
  • the current message interruption execution process is shown in Figure 2.
  • An interruption only processes one piece of running status information. When the interruption frequency is high, the interruption is likely to be lost or the running status is overwritten.
  • this application proposes a multi-node master-slave network system and an interruption processing method thereof.
  • the first aspect of the embodiments of the present application provides a multi-node master-slave network interrupt processing method.
  • the multi-node master-slave network includes an NC node and a plurality of NT nodes.
  • the method includes: hardware writing running status and counting ; When the count reaches an integer multiple of the response frequency, the hardware reports a message interruption to the software; the hardware writes the running status and writes it into the CQ queue.
  • the CQ block is an independent buffer area in the DDR, and the CQ block is used to store messages The execution result of the software; the software responds to the message interrupt; the software reads the CQ block.
  • the CQ block corresponds to a storage section with a designated start position and end position in the DDR.
  • the hardware maintains a write position. Each time the message is executed, the hardware writes the message completion information to the beginning of the write position.
  • the writing position is shifted backward by one CQ block length; when the writing position coincides with the end position, it means that the CQ section is full, and the hardware resets the writing position to the starting position, starting from the beginning The position continues to be written.
  • the NC-side CQ block includes 4 data words, and the 4 data words are respectively an NC message status word, a message start timestamp, a message end timestamp, and an NT status word.
  • bits 0 to 17 of the NC message status word are message status bits, including various error states and message data buffer status; bits 18 to 21 of the NC message status word are additional flag bits; the NC message The 22nd to 31st bits of the status word are the message index, and the message index is used to obtain the message configuration block corresponding to the CQ block according to the message index.
  • the NT-side CQ block includes 8 data words, and the 8 data words are respectively NT message status word, message start timestamp, message end timestamp, data area pointer, transmitted data length, command word, Sub address and total data length/mode command code.
  • bits 0 to 2 of the NT message status word are error bits; bits 3 to 7 of the NT message status word are additional flag bits; bits 8 to 19 of the NT message status word are message status bits; The 20th to 31st bits of the NT message status word are not used.
  • the NC-side CQ block corresponds to multiple NT-side CQ blocks, and the response frequency of the NC is the same as the response frequency of the NT.
  • the NC activates the message interrupt of the NT through a predefined physical message.
  • the hardware reports a message interrupt request to the software.
  • a second aspect of the embodiments of the present application provides a multi-node master-slave network system.
  • the multi-node master-slave network includes an NC node and a plurality of NT nodes.
  • the network node includes hardware and software, wherein: The hardware is used to: write the running status and count; when the count reaches an integer multiple of the response frequency, report a message interruption to the software; write the running status to the CQ queue.
  • the CQ block is an independent buffer area in the DDR, so The CQ block is used to store the execution result of the message; the software is used to: respond to the message interruption; read the CQ block.
  • the message completion information is stored in a queue (CQ) mode, and a buffer is added between the software and the hardware to solve the problem of the running state being overwritten; in addition, through the CQ block, round counting and response frequency, Control the frequency of hardware reporting interrupts.
  • CQ queue
  • One interrupt software can process multiple message completion messages at one time and read and write multiple pieces of load data at one time, which improves execution efficiency. See the detailed description of the specification for other advantages of this application.
  • Figure 1 is an existing hardware-software interaction process
  • FIG. 1 is an existing message interrupt execution flow
  • Fig. 3 is a schematic diagram of an interrupt processing method of a multi-node master-slave network system according to some embodiments of the present application.
  • Figure 1 is the existing hardware-software interaction process. As shown in Figure 1, the first step, the software initializes the hardware configuration; the second step, the software configures the hardware to work; the third step, the hardware sends an interrupt signal to the software; the fourth step, the software receives the hardware interrupt; the fifth step, the software Read the hardware running status and perform corresponding processing; then the hardware can continue to send interrupt signals to the software.
  • Figure 2 is the current message interrupt execution flow. As shown in Figure 2, the first step is to write the running status of the hardware; the second step is to interrupt the hardware reporting message; the third step is to write the hardware running status to the data block; the fourth step, the software responds to the message interrupt; the fifth step, the software Read the hardware operating status stored in the data block. In the process described in Figure 2, only one piece of running status information is processed at one interruption.
  • the FC-AE-1553 network system is a master-slave network system, which includes a network controller (hereinafter referred to as NC node, Network Controller) and multiple network terminals (hereinafter referred to as NT node, Network Terminal).
  • NC node Network Controller
  • NT node Network Terminal
  • Fig. 3 is a schematic diagram of an interrupt processing method of a multi-node master-slave network system according to some embodiments of the present application.
  • the method includes: hardware writes the running status and counts; when the count reaches an integer multiple of the response frequency, the hardware reports a message interrupt to the software; after the hardware writes the running status, writes it to the CQ queue, the CQ
  • the block is an independent cache area in the DDR.
  • the CQ block is used to store the execution result of the message; the software responds to the message interrupt; and the software reads the CQ block.
  • the message completion information queue is called Completion Queue, abbreviated as CQ, which is used to store the execution results of each round of each message, and the message is stored in an independent buffer.
  • a node in CQ is called a CQ block.
  • CQ corresponds to a storage section specifying the start position (start_pos) and end position (end_pos) in the DDR.
  • the hardware maintains a write position (write_pos).
  • write_pos Each time the message is executed, the hardware writes the message completion information to write_pos In the initial CQ block, writr_pos is shifted backward by one CQ block length (pointing to the next CQ block).
  • write_pos coincides with end_pos, it means that the CQ section is full, and the hardware resets write_pos to start_pos and continues writing from the starting position.
  • the format of the CQ block on the NC side is shown in Table 1. It contains 4 data words, which are NC message status word, message start time stamp, message end time stamp and NT status word (corresponding to the NT status word in the status frame).
  • the 0th to 17th bits of the message status word are the message status bits, including various error status and message data buffer status; the 18th to 21st bits are additional flag bits; the 22nd to 31st bits are the message index, and the CQ can be obtained according to this index
  • the message status bit format on the NC side is shown in Table 2.
  • the format of the NT-side CQ block is shown in Table 3. It contains 8 data words, which are NT message status word, message start timestamp, message end timestamp, data area pointer, transmitted data length, command word, subaddress and total Data length/mode command code.
  • the 0th to 2nd bits of the message status word are error bits
  • the 3rd to 7th bits are additional mark bits
  • the 8th to 19th bits are message status bits
  • the remaining bits are not used.
  • the message configuration block corresponding to the CQ block can be obtained through the sub-address in the CQ block.
  • Table 4 The format of error bits and message status bits on the NT side is shown in Table 4.
  • Response frequency refers to the frequency with which the software responds to the message interruption, that is, the frequency with which the hardware reports the message interruption to the software.
  • the software configures the response frequency value to the hardware, and the hardware counts the message execution rounds. When the count value reaches an integer multiple of the response frequency, the hardware reports a message interruption to the software.
  • the CQ block of the NC corresponds to the CQ block of multiple NTs.
  • the response frequency of the CQ block of the NC can be compared with the CQ block of the NT.
  • Adaptation that is, the hardware response frequency configured by the NC is counted by a single NT. For example, when the message execution round of NT1 is M, the hardware reports a message interrupt request. Correspondingly, the hardware response frequency of the NC configuration is also set to M.
  • the NC can activate the NT message interruption report through a predefined physical message. That is, the NC sends a physical layer message through the fiber channel, and the physical layer message has nothing to do with the upper layer signaling. After the NT receives the message, the hardware reports a message interrupt request to the software. Furthermore, NT can report the amount of buffered data through physical layer signaling, so that NC can locally control all NT's message interrupt reporting behavior, that is, the hardware message interruption of the entire network can be adjusted adaptively, and NC can monitor all NT's cache status to avoid loss or overwriting due to the high frequency of interrupted messages.
  • the CQ block plays a role in establishing an accurate correspondence between message configuration and message completion information
  • One interrupt software can process multiple message completion information at one time and read and write multiple blocks of load data at one time, which improves execution efficiency;
  • the user can obtain the message completion information in real time and monitor the operation process of the message
  • the cyclically used CQ and frequency-controllable interrupt response improve the adaptability of software performance and hardware performance.

Abstract

本申请披露了一种多节点主从式网络系统及其中断处理方法, 所述多节点主从式网络包括NC节点和多个NT节点, 所述方法包括：硬件写运行状态并计数；计数达到响应频度的整数倍时, 硬件向软件上报消息中断；硬件写运行状态后将其写入CQ队列，所述CQ块为DDR中的独立缓存区域, 所述CQ块用于存储消息的执行结果；软件响应消息中断；软件读取CQ块。

Description

一种多节点主从式网络系统及其中断处理方法 技术领域
本申请涉及多节点通信系统领域，具体涉及一种多节点主从式网络系统及其中断处理方法。
背景技术
硬件中断为软件与硬件的交互过程中的关键环节之一，也是硬件主动发起交互的唯一途径。消息中断是硬件中断的一种，用于硬件向软件传递消息本轮次执行完成的信号和执行的结果。
FC-AE-1553网络是一种高带宽、低延迟、高可靠的光纤通信总线协议，其协议由美国国家标准协会(ANSI)制定，并定义了MIL-STD-1553B协议到光纤通道(FC,Fiber Channel)高层协议的映射，它为光纤1553总线的开发提供了协议支撑。与传统MIL-STD-1553B总线一样，FC-AE-1553定义了一个命令/响应式的总线标准，同时为了提高可靠性，传输通道同样采用双冗余备份的机制。
软件与硬件的交互流程如图1所示。其中硬件中断是硬件主动向软件发起交互的唯一途径。
具体到FC通信设备和软件，由于FC通信是高速率通信，消息中断频率高，同时软件必须保证每一次中断都要接收到不能丢失，这样才能保证通信的可靠性。
现状的消息中断执行流程如图2所示，一次中断仅处理一条运行状态信息，当中断频率较高时易发生中断丢失或者运行状态被覆写的情况。
发明内容
针对现有技术中“中断频率较高时易发生中断丢失或者运行状态被覆写”的问题，本申请提出了一种多节点主从式网络系统及其中断处理方法。
本申请实施例的第一方面提供了一种多节点主从式网络中断处理方法，所述多节点主从式网络包括NC节点和多个NT节点，所述 方法包括：硬件写运行状态并计数；计数达到响应频度的整数倍时，硬件向软件上报消息中断；硬件写运行状态后将其写入CQ队列，所述CQ块为DDR中的独立缓存区域，所述CQ块用于存储消息的执行结果；软件响应消息中断；软件读取CQ块。
进一步地，CQ块在DDR中对应一个指定起始位置和结束位置的存储区段，硬件维护一个写入位置，消息每执行一个轮次，硬件将消息完成信息写入以写入位置起始的CQ块中，并将写入位置向后偏移一个CQ块长度；当写入位置与结束位置重合时表示CQ区段已写满，硬件将写入位置重置为起始位置，从起始位置继续写入。
进一步地，所述NC端CQ块包括4个数据字，所述4个数据字分别为NC消息状态字、消息开始时间戳、消息结束时间戳和NT状态字。
进一步地，所述NC消息状态字第0～17位为消息状态位，包含各种错误状态和消息数据缓冲状态；所述NC消息状态字第18～21位为附加标记位；所述NC消息状态字第22～31位为消息索引，消息索引被用于：根据消息索引获取CQ块对应的消息配置块。
进一步地，所述NT端CQ块包括8个数据字，所述8个数据字分别为NT消息状态字、消息开始时间戳、消息结束时间戳、数据区指针、已传输数据长度、命令字、子地址和总数据长度/模式命令代码。
进一步地，所述NT消息状态字第0～2位为错误位；所述NT消息状态字第3～7位为附加标记位；所述NT消息状态字第8～19位为消息状态位；所述NT消息状态字第20～31位未使用。
进一步地，NC端CQ块对应多个NT端CQ块，NC的响应频度与NT的响应频度相同。
进一步地，NC通过预定义的物理消息激活NT的消息中断，NT接收到所述预定义的物理消息后，硬件向软件上报一次消息中断请求。
本申请实施例的第二方面提供了一种多节点主从式网络系统，所述多节点主从式网络包括NC节点和多个NT节点，所述网络节点包括硬件和软件，其中：所述硬件用于：写运行状态并计数；计数达到 响应频度的整数倍时，向软件上报消息中断；写运行状态后将其写入CQ队列，所述CQ块为DDR中的独立缓存区域，所述CQ块用于存储消息的执行结果；所述软件用于：响应消息中断；读取CQ块。
本申请实施例，通过采用队列(CQ)的方式存储消息完成信息，在软件和硬件之间增加了缓冲，解决运行状态被覆写的问题；另外，通过CQ块、轮次计数和响应频度，控制硬件上报中断的频度，一次中断软件可以一次性处理多条消息完成信息和一次性读写多块载荷数据，提升了执行效率。本申请的其他优势见说明书的详细描述。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单的介绍。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图将本申请应用于其它类似情景。除非从语言环境中显而易见或另做说明，图中相同标号代表相同结构和操作。
图1是现有的硬件-软件交互流程；
图2是现有的消息中断执行流程；
图3是根据本申请的一些实施例所示的多节点主从式网络系统的中断处理方法示意图。
具体实施方式
在下面的详细描述中，通过示例阐述了本申请的许多具体细节，以便提供对相关披露的透彻理解。然而，对于本领域的普通技术人员来讲，本申请显而易见的可以在没有这些细节的情况下实施。应当理解的是，本申请中使用“系统”、“装置”、“单元”和/或“模块”术语，是用于区分在顺序排列中不同级别的不同部件、元件、部分或组件的一种方法。然而，如果其他表达式可以实现相同的目的，这些术语可以被其他表达式替换。
应当理解的是，当设备、单元或模块被称为“在……上”、“连接到”或“耦合到”另一设备、单元或模块时，其可以直接在另一设备、 单元或模块上，连接或耦合到或与其他设备、单元或模块通信，或者可以存在中间设备、单元或模块，除非上下文明确提示例外情形。例如，本申请所使用的术语“和/或”包括一个或多个相关所列条目的任何一个和所有组合。
参看下面的说明以及附图，本申请的这些或其他特征和特点、操作方法、结构的相关元素的功能、部分的结合以及制造的经济性可以被更好地理解，其中说明和附图形成了说明书的一部分。然而，可以清楚地理解，附图仅用作说明和描述的目的，并不意在限定本申请的保护范围。可以理解的是，附图并非按比例绘制。
本申请中使用了多种结构图用来说明根据本申请的实施例的各种变形。应当理解的是，前面或下面的结构并不是用来限定本申请。本申请的保护范围以权利要求为准。
图1是现有的硬件-软件交互流程。如图1所示，第一步，软件初始化硬件配置；第二步，软件配置硬件开始工作；第三步，硬件向软件发送中断信号；第四步，软件接收硬件中断；第五步，软件读取硬件运行状态并执行相应处理；随后硬件可继续向软件发送中断信号。
图2是现有的消息中断执行流程。如图2所示，第一步，硬件写运行状态；第二步，硬件上报消息中断；第三步，硬件运行状态写入数据块；第四步，软件响应消息中断；第五步，软件读取存储在数据块中的硬件运行状态。在图2中所述的过程中，一次中断仅处理一条运行状态信息。
FC-AE-1553网络系统为主从式网络系统，系统中包括一个网络控制器(以下简称NC节点，Network Controller)和多个网络终端(以下简称NT节点，Network Terminal)。
图3是根据本申请的一些实施例所示的多节点主从式网络系统的中断处理方法示意图。如图3所示，所述方法包括：硬件写运行状态并计数；计数达到响应频度的整数倍时，硬件向软件上报消息中断；硬件写运行状态后将其写入CQ队列，所述CQ块为DDR中的独立缓存区域，所述CQ块用于存储消息的执行结果；软件响应消息中断；软件读取CQ块。
消息完成信息队列全拼为Completion Queue，缩写为CQ，用于放置每条消息每个轮次的执行结果，该消息存放于一个独立的缓存中。CQ中的一个节点称为一个CQ块。CQ在DDR中对应一个指定起始位置(start_pos)和结束位置(end_pos)的存储区段，硬件维护一个写入位置(write_pos)，消息每执行一个轮次，硬件将消息完成信息写入以write_pos起始的CQ块中，并将writr_pos向后偏移一个CQ块长度(指向下一个CQ块)。当write_pos与end_pos重合时表示CQ区段已写满，硬件将write_pos重置为start_pos，从起始位置继续写入。
NC端CQ块格式如表1所示，包含4个数据字，分别为NC消息状态字、消息开始时间戳、消息结束时间戳和NT状态字(对应状态帧中的NT状态字)。消息状态字第0～17位为消息状态位，包含各种错误状态和消息数据缓冲区状态；第18～21位为附加标记位；第22～31位为消息索引，可根据此索引获取CQ块对应的消息配置块。NC端的消息状态位格式如表2所示。
表1 NC端CQ块格式
Figure PCTCN2020090966-appb-000001
表2 NC消息状态位
Figure PCTCN2020090966-appb-000002
NT端CQ块格式如表3所示，包含8个数据字，分别为NT消息状态字、消息开始时间戳、消息结束时间戳、数据区指针、已传输数据长度、命令字、子地址和总数据长度/模式命令代码。消息状态字第0～2位为错误位，第3～7位为附加标记位，第8～19位为消息状态位，其余位未使用。另外可通过CQ块中的子地址获取CQ块对应的消息配置块。NT端的错误位与消息状态位格式如表4所示。
表3 NT端CQ块格式
Figure PCTCN2020090966-appb-000003
表4 NT错误位和消息状态位
Figure PCTCN2020090966-appb-000004
响应频度即软件响应消息中断的频度，也即硬件向软件上报消息中断的频度。具体是指，软件向硬件配置响应频度数值，硬件对消息执行轮次进行计数，当计数值每达到响应频度的整数倍时，硬件向软件上报一次消息中断。
由于NC负责与多个NT进行通信，因此NC的CQ块对应于多个NT的CQ块，为了减少缓存CQ序列带来的响应延时，可以将NC的CQ块响应频次与NT的CQ块进行适配，也就是NC配置的硬件响应频次按单个NT来计数，例如NT1的消息执行轮次为M时硬件上报一次消息中断请求。而对应的，NC配置的硬件响应频次也设置为M。此时，无论NC的队列中有多少个消息，NC的软件和对应的NT(例如NT1)的软件均在相同的时间获得对应消息的中断消息。这意味着上层应用，例如上层APP侧不会由于缓存不适配而带来额外的时延。这种时延在高可靠通信中仍然可能带来不确定性，尤其是CQ序列的缓存空间较大的时候。
在另外一种实施方式中，NC可以通过预定义的物理消息来激活NT的消息中断上报。也就是，NC通过光纤通道发送一个物理层消息，该物理层消息与上层信令无关，NT收到该消息后，硬件向软件上报一次消息中断请求。进一步，NT可以通过物理层信令上报缓存的数据量，这样NC就可以在本地控制所有NT的消息中断上报行为，也就是整个网络的硬件消息中断均可以自适应的被调整，NC可以监控所有NT的缓存状态，以避免由于中断消息频率过高而导致的丢失或被覆盖。
本申请相比于现有技术，具有如下有益效果：
一、采用队列(CQ)的方式存储消息完成信息，在软件和硬件之间增加了缓冲，解决运行状态被覆写的问题；
二、CQ块起到在消息配置和消息完成信息之间建立准确的对应关系的作用；
三、通过CQ块、轮次计数和响应频度，控制硬件上报中断的频度，一次中断软件可以一次性处理多条消息完成信息和一次性读写多块载荷数据，提升了执行效率；
四、用户可实时获取消息完成信息，对消息的运行过程进行监控；
五、高可靠的中断响应，保证了数据传输的可靠性和顺畅性；
六、循环使用的CQ和频度可控的中断响应，提升了软件性能与硬件性能的适配度。
应当理解的是，本申请的上述具体实施方式仅仅用于示例性说明或解释本申请的原理，而不构成对本申请的限制。因此，在不偏离本申请的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。此外，本申请所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (9)

  1. 一种多节点主从式网络中断处理方法，其特征在于，所述多节点主从式网络包括NC节点和多个NT节点，所述方法包括：
    硬件写运行状态并计数；
    计数达到响应频度的整数倍时，硬件向软件上报消息中断；
    硬件写运行状态后将其写入CQ队列，所述CQ块为DDR中的独立缓存区域，所述CQ块用于存储消息的执行结果；
    软件响应消息中断；
    软件读取CQ块。
  2. 如权利要求1所述的方法，其特征在于，CQ块在DDR中对应一个指定起始位置和结束位置的存储区段，硬件维护一个写入位置，消息每执行一个轮次，硬件将消息完成信息写入以写入位置起始的CQ块中，并将写入位置向后偏移一个CQ块长度；当写入位置与结束位置重合时表示CQ区段已写满，硬件将写入位置重置为起始位置，从起始位置继续写入。
  3. 如权利要求1所述的方法，其特征在于，所述NC端CQ块包括4个数据字，所述4个数据字分别为NC消息状态字、消息开始时间戳、消息结束时间戳和NT状态字。
  4. 如权利要求3所述的方法，其特征在于：
    所述NC消息状态字第0～17位为消息状态位，包含各种错误状态和消息数据缓冲状态；
    所述NC消息状态字第18～21位为附加标记位；
    所述NC消息状态字第22～31位为消息索引，消息索引被用于：根据消息索引获取CQ块对应的消息配置块。
  5. 如权利要求1所述的方法，其特征在于，所述NT端CQ块包括8个数据字，所述8个数据字分别为NT消息状态字、消息开始时 间戳、消息结束时间戳、数据区指针、已传输数据长度、命令字、子地址和总数据长度/模式命令代码。
  6. 如权利要求5所述的方法，其特征在于：
    所述NT消息状态字第0～2位为错误位；
    所述NT消息状态字第3～7位为附加标记位；
    所述NT消息状态字第8～19位为消息状态位；
    所述NT消息状态字第20～31位未使用。
  7. 如权利要求1所述的方法，其特征在于，NC端CQ块对应多个NT端CQ块，NC的响应频度与NT的响应频度相同。
  8. 如权利要求1所述的方法，其特征在于，NC通过预定义的物理消息激活NT的消息中断，NT接收到所述预定义的物理消息后，硬件向软件上报一次消息中断请求。
  9. 一种多节点主从式网络系统，其特征在于，所述多节点主从式网络包括NC节点和多个NT节点，所述网络节点包括硬件和软件，其中：
    所述硬件用于：
    写运行状态并计数；
    计数达到响应频度的整数倍时，向软件上报消息中断；
    写运行状态后将其写入CQ队列，所述CQ块为DDR中的独立缓存区域，所述CQ块用于存储消息的执行结果；
    所述软件用于：
    响应消息中断；
    读取CQ块。
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