WO2021223777A1 - 基于正交频分多址技术的反向散射系统 - Google Patents

基于正交频分多址技术的反向散射系统 Download PDF

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Publication number
WO2021223777A1
WO2021223777A1 PCT/CN2021/101725 CN2021101725W WO2021223777A1 WO 2021223777 A1 WO2021223777 A1 WO 2021223777A1 CN 2021101725 W CN2021101725 W CN 2021101725W WO 2021223777 A1 WO2021223777 A1 WO 2021223777A1
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phase
backscatter
multiple access
division multiple
frequency division
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PCT/CN2021/101725
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English (en)
French (fr)
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朱丰源
冯宇达
李倩茹
田晓华
王新兵
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上海交通大学
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Priority to US17/796,639 priority Critical patent/US11843494B2/en
Publication of WO2021223777A1 publication Critical patent/WO2021223777A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/70—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
    • H04B5/72—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes for local intradevice communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation

Definitions

  • the present invention relates to the field of communication technology, in particular, to a backscatter system based on orthogonal frequency division multiple access technology.
  • a backscatter tag based on IDFT digital frequency synthesis which is suitable for application in OFDMA network.
  • Backscatter communication has attracted widespread attention in the field of Internet of Things in recent years. Its main feature is to use external electromagnetic waves to modulate to realize its own communication. Since there is no need to actively generate electromagnetic waves, even if it is generated for Wi-Fi communication, the power consumption is very low, only tens of microwatts (see the paper by Bryce Kellogg et al. in NSDI in 2016). However, with the expansion of the scale of the Internet of Things, multiple access technologies have gradually changed from time division multiplexing to frequency domain multiplexing. In 2019, Renjie Zhao et al.
  • this patent provides a software-level digital frequency synthesis algorithm to achieve frequency synthesis so that the control of sub-channels and the number of sub-channels can be Modifications at the software level make the practical application of OFDMA backscatter network possible.
  • the purpose of the present invention is to provide a backscatter system based on orthogonal frequency division multiple access technology.
  • a backscatter system based on orthogonal frequency division multiple access technology includes:
  • the analog part includes: an antenna, a radio frequency switch, an envelope detection circuit and a transmission line;
  • the digital logic part includes: a digital frequency synthesis module based on IDFT;
  • the two outputs of the digital logic part control all radio frequency switches, and the envelope detection circuit provides the input of the digital logic part.
  • the antenna absorbs electromagnetic waves in a specific frequency band and provides gain
  • the radio frequency switch switching the impedance state
  • the envelope detection circuit detects/demodulates external signals and obtains energy from them;
  • the transmission line realizes phase shift to further realize IQ modulation
  • the IDFT-based digital frequency synthesis module generates a sub-carrier of a specific frequency and provides a modulation interface.
  • the antenna is connected to an SPDT radio frequency switch, and the SPDT radio frequency switch is respectively connected to the envelope detection circuit and the power splitter.
  • the power splitter is connected to two transmission lines, and each transmission line is connected to a radio frequency switch;
  • Each RF switch is connected to VCC and GND.
  • the transmission line can be replaced by a phase shifter.
  • it also includes a synchronization algorithm for synchronizing with an external excitation signal to avoid inter-symbol crosstalk ISI;
  • the synchronization algorithm is an algorithm in the digital domain and is deployed on a logic unit.
  • the logic unit includes: MCU and FPGA.
  • the synchronization algorithm refers to:
  • IDFT-based low-power digital frequency synthesis algorithm for backscatter communication IDFT-based low-power digital frequency synthesis algorithm for backscatter communication.
  • the synchronization algorithm only calculates the phase change according to the output requirements of the backscatter, and judges that the output is 0/1 according to the phase for controlling the radio frequency switch;
  • the synchronization algorithm can also be applied to the FSK backscatter system or other protocols or applications that involve changes in the backscatter frequency according to different scenarios;
  • the synchronization algorithm corresponds to two specific implementation methods according to different ways of calculating phase changes:
  • Phase calculation based on the multiplier directly use the n obtained by the counter of the sampling clock to multiply to get the current normalized phase, and after the normalized phase is obtained, the phase value is judged to determine the IQ channel output logic value 0/1;
  • Phase calculation based on registers and adders using the characteristic that the sampling clock will increase by 1 every cycle, store the previous accumulated normalized phase in the register, and add the corresponding phase increment for each round to avoid the multiplier Use, after getting the normalized phase, judge the phase value to determine the IQ channel output logic value 0/1.
  • the normalized phase refers to the phase divided by 2 ⁇ .
  • the present invention has the following beneficial effects:
  • the present invention can realize an ultra-large-scale OFDMA backscatter network at low cost. By continuously splitting the spectrum in the digital domain, 1024 sub-carriers can be generated, which is much larger than the existing 48 sub-carriers of OFDMA using analog-digital frequency synthesis system.
  • the tag in the present invention can change the sub-channel and change the symbol rate only through downlink signaling without requiring hardware modification or reconfiguration after power failure. It provides the physical layer foundation for the development of OFDMA backscatter network link layer protocol.
  • Fig. 1 is a working flow chart of OFDMA backscatter tag using digital frequency synthesis in the present invention.
  • Fig. 2 is the phase algorithm (A) in the digital frequency synthesis of the present invention, that is, the algorithm model based on the multiplier.
  • Fig. 3 is the phase algorithm (B) in the digital frequency synthesis of the present invention, that is, the algorithm model based on the register and the adder.
  • Fig. 4 shows the measured data rate of each sub-channel when the tag traverses 1024 sub-channels in the second embodiment.
  • a backscatter system based on orthogonal frequency division multiple access technology includes:
  • the analog part includes: an antenna, a radio frequency switch, an envelope detection circuit and a transmission line;
  • the digital logic part includes: a digital frequency synthesis module based on IDFT;
  • the two outputs of the digital logic part control all radio frequency switches, and the envelope detection circuit provides the input of the digital logic part.
  • the antenna absorbs electromagnetic waves in a specific frequency band and provides gain
  • the radio frequency switch switching the impedance state
  • the envelope detection circuit detects/demodulates external signals and obtains energy from them;
  • the transmission line realizes phase shift to further realize IQ modulation
  • the IDFT-based digital frequency synthesis module generates a sub-carrier of a specific frequency and provides a modulation interface.
  • the antenna is connected to an SPDT radio frequency switch, and the SPDT radio frequency switch is respectively connected to the envelope detection circuit and the power splitter.
  • the power splitter is connected to two transmission lines, and each transmission line is connected to a radio frequency switch;
  • Each RF switch is connected to VCC and GND.
  • the transmission line can be replaced by a phase shifter.
  • a synchronization algorithm which is used to synchronize with an external excitation signal to avoid inter-code crosstalk ISI;
  • the synchronization algorithm is an algorithm in the digital domain and is deployed on a logic unit.
  • the logic unit includes: MCU and FPGA.
  • the synchronization algorithm refers to:
  • IDFT-based low-power digital frequency synthesis algorithm for backscatter communication IDFT-based low-power digital frequency synthesis algorithm for backscatter communication.
  • the synchronization algorithm only calculates the phase change according to the output requirement of backscatter, and judges that the output is 0/1 according to the phase for controlling the radio frequency switch;
  • the synchronization algorithm can also be applied to the FSK backscatter system or other protocols or applications that involve changes in the backscatter frequency according to different scenarios;
  • the synchronization algorithm corresponds to two specific implementation methods according to different ways of calculating phase changes:
  • Phase calculation based on the multiplier directly use the n obtained by the counter of the sampling clock to multiply to get the current normalized phase, and after the normalized phase is obtained, the phase value is judged to determine the IQ channel output logic value 0/1;
  • Phase calculation based on registers and adders using the characteristic that the sampling clock will increase by 1 every cycle, store the previous accumulated normalized phase in the register, and add the corresponding phase increment for each round to avoid the multiplier Use, after getting the normalized phase, judge the phase value to determine the IQ channel output logic value 0/1.
  • the normalized phase refers to the phase divided by 2 ⁇ .
  • the purpose of the present invention is to provide a flexible and practical backscattering system tag design scheme based on digital frequency synthesis.
  • the backscatter system based on orthogonal frequency division multiple access technology includes the following parts:
  • Part 1 Antenna
  • the antenna can match electromagnetic waves in a specific frequency band.
  • the RF switch can select the impedance state of the subsequent circuit.
  • Two transmission lines of different lengths have a difference of 1/8 in electrical length, which enables the tag to perform I/Q modulation.
  • the diode-based envelope detection circuit compares the results of the comparator and the integrator to output a 1-bit sequence.
  • Part 5 Low-power digital frequency synthesis algorithm based on IDFT
  • the digital circuit design for phase calculation includes two design schemes:
  • the algorithm can provide PSK/FSK interface.
  • Part 6 Synchronization algorithm.
  • the synchronous digital circuit receives the 1-bit input of the envelope detector circuit and transfers it into the shift register queue, and then cross-correlates with the preset sequence to obtain a matching trigger signal to enable the digital frequency synthesis algorithm.
  • Antennas are used to absorb electromagnetic waves in a specific frequency band and provide gain.
  • Radio frequency switch used to switch the impedance state.
  • Envelope detection circuit is used to detect/demodulate external signals and obtain energy from them.
  • Transmission line (can be replaced by a phase shifter), used to achieve phase shift to further achieve IQ modulation.
  • the IDFT-based digital frequency synthesis module is used to generate sub-carriers of specific frequencies and provide a modulation interface.
  • Synchronization algorithm used to synchronize with the external excitation signal to avoid inter-symbol interference (ISI).
  • IDFT-based low-power digital frequency synthesis algorithm for backscatter communication.
  • the algorithm is deployed on the MCU/FPGA and can expose interfaces to other chips. Or users can use the algorithm as a sub-module on FPGA/MCU to connect to other modules.
  • the interface includes the K/N and phase interface shown in Figure 2.
  • the interface can be parallel or serial. Its characteristic is that only the phase change is calculated according to the output requirement of the backscatter, and the output is judged to be 0/1 according to the phase, which is used to control the radio frequency switch.
  • the algorithm can also be applied to FSK backscattering systems or other protocols or applications that involve changes in backscattering frequency according to different scenarios. According to the different phase calculation methods, it corresponds to two specific implementation methods:
  • Phase calculation based on multiplier The n obtained by the counter of the sampling clock is directly used for multiplication to obtain the current normalized phase (ie, the phase is divided by 2 ⁇ ). After the normalized phase is obtained, the phase value is judged to determine the IQ channel output logic value 0/1.
  • Phase calculation based on registers and adders. Using the characteristic that the sampling clock will increase by 1 every cycle, the previous accumulated normalized phase (that is, the phase divided by 2 ⁇ ) is stored in the register, and the corresponding phase increment is added every round to avoid the use of multipliers. After the normalized phase is obtained, the phase value is judged to determine the IQ channel output logic value 0/1.
  • the backscatter network composed of backscatter tags provided according to the present invention includes the following parts:
  • Part 1 Have a transmitter that generates a specific excitation signal:
  • the transmitter can perform IQ modulation and send OOK signals, pure carrier and OFDM signals.
  • Part 2 IDFT digital frequency synthesis-based backscatter tags described in the specification of the present invention:
  • the tag can respond to the excitation signal generated by the transmitter and add local data to the phase, and use digital frequency synthesis to generate sub-carriers.
  • the output is converted into I/Q signals through simple logic and output to the RF switch on the I/Q circuit to achieve OFDMA Parallel access.
  • Part 3 Receiver that can receive and demodulate backscattered signals:
  • the receiver can receive IQ data, perform time domain synchronization, frequency domain synchronization, and perform digital signal processing such as FFT.
  • Example 1 Parallel experiment; 100 tags are randomly placed within a 7-meter radius. Both the transmitter and receiver use Mango Communications WARP v3, work in the 2.4GHz frequency band, and are connected to Lenovo ThinkPad P51 laptops via LAN.
  • the transmitter emits the excitation signal, and the synchronization modules of all tags start to perform their respective sub-carrier modulation after synchronizing with the excitation signal.
  • the output after phase modulation is changed into I/Q channel switch control logic signal through logic judgment, and the I channel switch is controlled separately And Q way switch, complete I/Q modulation.
  • their digital frequency synthesis module follows the k parameter and N parameter specified by the transmitter (see part 5 of the manual). Since the sub-channels of all tags do not conflict with each other, their OFDMA signal can be demodulated smoothly by the receiver.

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Abstract

本发明提供了一种基于正交频分多址技术的反向散射系统，包括：模拟部分、数字逻辑部分；所述模拟部分包括：天线、射频开关、包络检波电路和传输线；所述数字逻辑部分包括：基于IDFT的数字频率合成模块；所述数字逻辑部分的两路输出控制所有的射频开关，包络检波电路提供数字逻辑部分的输入。本发明通过这样的设计，OFDMA反向散射标签能够在不重新上电和不修改硬件的情况下，工作在任意给定的子信道上；并能够以指定的符号速率工作。该设计为大批量的OFDMA反向散射标签提供了组网的物理层基础，满足物联网规模日益扩大的容量需求。

Description

基于正交频分多址技术的反向散射系统 技术领域
本发明涉及通信技术领域，具体地，涉及一种基于正交频分多址技术的反向散射系统。尤其地，涉及一种基于IDFT数字频率合成的反向散射标签的设计方法，适合应用于OFDMA网络。
背景技术
反向散射通信近年来在物联网领域引起了广泛的关注。其主要特点是利用外界的电磁波加以调制来实现自身的通信。由于不需要主动生成电磁波，即使生成进行Wi-Fi通信，功耗也非常低，仅几十个微瓦(见2016年Bryce Kellogg等人在NSDI的论文)。然而，随着物联网规模的扩大，多接入技术也逐渐从时分复用变成频域复用。2019年，Renjie Zhao等人在MobiCom上发表了“OFDMA-Enabled Wi-Fi Backscatter”利用802.11g协议中的48个数据子载波分配给48个不同的反向散射标签来实现并行的上行链路，解决了网络的容量问题。然而这48个标签需要用模拟的频率合成器来实现不同的频移，一旦更换子信道，就得改变频移频率，需要重新配置硬件，对网络协议的设计造成了巨大的挑战，并给构建大规模OFDMA网络带来了巨大的工程上的难度。鉴于当前OFDMA反向散射的最大技术难点在于频率合成与硬件之间的耦合关系，本专利提供了一种软件层面的数字频率合成算法来实现频率合成使得子信道的控制、子信道数量都能在软件层面进行改动，使得OFDMA反向散射网络的实际应用成为可能。
发明内容
针对现有技术中的缺陷，本发明的目的是提供一种基于正交频分多址技术的反向散射系统。
根据本发明提供的一种基于正交频分多址技术的反向散射系统，包括：
模拟部分、数字逻辑部分；
所述模拟部分包括：天线、射频开关、包络检波电路和传输线；
所述数字逻辑部分包括：基于IDFT的数字频率合成模块；
所述数字逻辑部分的两路输出控制所有的射频开关，包络检波电路提供数字逻辑部分的输入。
优选地，所述天线：吸收特定频段的电磁波并提供增益；
所述射频开关：切换阻抗状态；
所述包络检波电路：检测/解调外界信号并从中获能；
所述传输线：实现相位移动，以进一步实现IQ调制；
所述基于IDFT的数字频率合成模块：生成特定频率的子载波并提供调制的接口。
优选地，所述天线连接一个SPDT射频开关，SPDT射频开关分别与包络检波电路和功率均分器相连。
优选地，所述
功率均分器连接两路传输线，每一路传输线与射频开关相连；
每个射频开关连接VCC与GND。
优选地，所述传输线可以用移相器代替。
优选地，还包括同步算法，用于与外界的激励信号同步，避免码间串扰ISI；
所述同步算法为数字域的算法，部署在逻辑单元上，逻辑单元包括：MCU、FPGA。
优选地，所述同步算法指：
基于IDFT的应用于反向散射通信的低功耗数字频率合成算法。
优选地，所述同步算法依据反向散射的输出要求仅计算相位变化，并根据相位判断输出为0/1用于控制射频开关；
同步算法也可以根据场景不同运用于FSK的反向散射系统或者其他涉及到反向散射频率变化的协议或应用；
优选地，所述同步算法根据计算相位变化的方式不同，对应两种具体实现方法：
基于乘法器的相位计算：直接利用采样时钟的计数器得到的n做乘法来得到当前归一化相位，得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1；
基于寄存器和加法器的相位计算：利用采样时钟每个周期会加1的特性，将先前的累计的归一化相位，存储在寄存器中，每回合加上对应的相位增量，避免乘法器的使用，得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1。
优选地，所述归一化相位指相位除以2π。
与现有技术相比，本发明具有如下的有益效果：
1、本发明能够低成本地实现超大规模的OFDMA反向散射网络，通过在数字域不断 切分频谱，能产生1024个子载波，远远大于现有的48个子载波的采用模拟数字频率合成的OFDMA系统。
2、实现了OFDMA反向散射的物理层调制与硬件的解耦。相关的物理层参数可以在软件层面控制。而物理层行为的可控直接影响链路层设计和整体网络的功能。
3、本发明中的标签能够在无需修改硬件或掉电重新配置的情况下，仅仅通过下行链路信令进行子信道的变更、符号速率的变化。为OFDMA反向散射网络链路层协议的开发提供了物理层基础。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显：
图1为本发明中采用数字频率合成的OFDMA反向散射标签工作流程图。
图2为本发明中数字频率合成中的相位算法(A)，即基于乘法器的算法模型。
图3为本发明中数字频率合成中的相位算法(B)，即基于寄存器和加法器的算法模型。
图4为实施例二中标签遍历1024个子信道测得的各子信道数据率。
具体实施方式
下面结合具体实施例对本发明进行详细说明。以下实施例将有助于本领域的技术人员进一步理解本发明，但不以任何形式限制本发明。应当指出的是，对本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变化和改进。这些都属于本发明的保护范围。
根据本发明提供的一种基于正交频分多址技术的反向散射系统，包括：
模拟部分、数字逻辑部分；
所述模拟部分包括：天线、射频开关、包络检波电路和传输线；
所述数字逻辑部分包括：基于IDFT的数字频率合成模块；
所述数字逻辑部分的两路输出控制所有的射频开关，包络检波电路提供数字逻辑部分的输入。
具体地，所述天线：吸收特定频段的电磁波并提供增益；
所述射频开关：切换阻抗状态；
所述包络检波电路：检测/解调外界信号并从中获能；
所述传输线：实现相位移动，以进一步实现IQ调制；
所述基于IDFT的数字频率合成模块：生成特定频率的子载波并提供调制的接口。
具体地，所述天线连接一个SPDT射频开关，SPDT射频开关分别与包络检波电路和功率均分器相连。
具体地，所述
功率均分器连接两路传输线，每一路传输线与射频开关相连；
每个射频开关连接VCC与GND。
具体地，所述传输线可以用移相器代替。
具体地，还包括同步算法，用于与外界的激励信号同步，避免码间串扰ISI；
所述同步算法为数字域的算法，部署在逻辑单元上，逻辑单元包括：MCU、FPGA。
具体地，所述同步算法指：
基于IDFT的应用于反向散射通信的低功耗数字频率合成算法。
具体地，所述同步算法依据反向散射的输出要求仅计算相位变化，并根据相位判断输出为0/1用于控制射频开关；
同步算法也可以根据场景不同运用于FSK的反向散射系统或者其他涉及到反向散射频率变化的协议或应用；
具体地，所述同步算法根据计算相位变化的方式不同，对应两种具体实现方法：
基于乘法器的相位计算：直接利用采样时钟的计数器得到的n做乘法来得到当前归一化相位，得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1；
基于寄存器和加法器的相位计算：利用采样时钟每个周期会加1的特性，将先前的累计的归一化相位，存储在寄存器中，每回合加上对应的相位增量，避免乘法器的使用，得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1。
具体地，所述归一化相位指相位除以2π。
下面通过优选例，对本发明进行更为具体地说明。
优选例1：
针对现有OFDMA反向散射系统的缺陷，本发明的目的是提供一种基于数字频率合成的具备灵活性和实用性的反向散射系统标签的设计方案。
根据本发明提供的基于正交频分多址技术的反向散射系统，包括如下部分：
部分1：天线
天线能够匹配特定频段的电磁波。
部分2：射频开关
射频开关能够选择后继电路的阻抗状态。
部分3：传输线
两条不同长度的传输线，电长度相差1/8，使得标签能够进行I/Q调制。
部分4：包络检波电路
基于二极管的包络检波电路，通过比较器与积分器的结果相比较输出1bit的序列。
部分5：基于IDFT的低功耗数字频率合成算法
该算法与普通的IDFT算法相比，仅计算单个子载波的时域信号，即x[n]＝ej 2πkn/N。
由于反向散射的输出为射频开关，只需要1bit的量化结果，因此无需进行三角函数的运算，而只需要计算归一化的相位信息，即
Figure PCTCN2021101725-appb-000001
在得到相位信息后进行简单逻辑判断即可控制开关进行调制。
优选地，相位计算的数字电路设计包括两种设计方案：
基于乘法器的设计。即先计算k与n的乘积并循环右移log(N)位得到p[n]。
基于寄存器和加法器的设计。即将每个时钟周期的计算结果保存在寄存器中，每当n变大1的时候向寄存器中加k循环右移log(N)的结果，即
Figure PCTCN2021101725-appb-000002
该算法可以提供PSK/FSK接口。具体方法为在每个符号开始的时候加载新的k参数和初始化相位参数。即将归一化相位计算写成p[n]＝kn/N+p 0，并提供p 0的赋值接口。
部分6：同步算法。同步数字电路接收包络检波电路的1bit输入，并传入移位寄存器队列中，通过与预设的序列做互相关得到是否匹配的触发信号来使能数字频率合成算法。
优选例2：
一种基于正交频分多址技术的反向散射系统，采用直接数字频率合成的OFDMA反向散射标签。其特征是采用数字算法实现频率合成，用于实现频移和子载波调制；其中：
天线，用于吸收特定频段的电磁波并提供增益。
射频开关，用于切换阻抗状态。
包络检波电路，用于检测/解调外界信号并从中获能。
传输线(可以用移相器代替)，用于实现相位移动，以进一步实现IQ调制。
基于IDFT的数字频率合成模块，用于生成特定频率的子载波并提供调制的接口。
同步算法，用于与外界的激励信号同步，避免码间串扰(ISI)。
即基于IDFT的应用于反向散射通信的低功耗数字频率合成算法。该算法部署在MCU/FPGA上，可以向其他芯片暴露接口。或是用户可以在FPGA/MCU上利用该算法作为子模块，连接其他模块。接口包括图2中所示的K/N和相位接口。接口可以是并行的，亦可以是串行的。其特征是依据反向散射的输出要求仅计算相位变化，并根据相位判断输出为0/1用于控制射频开关。该算法也可以根据场景不同运用于FSK的反向散射系统或者其他涉及到反向散射频率变化的协议或应用。其根据相位计算的方式不同，对应两种具体实现方法：
基于乘法器的相位计算。直接利用采样时钟的计数器得到的n做乘法来得到当前归一化的相位(即相位除以2π)。得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1。
基于寄存器和加法器的相位计算。利用采样时钟每个周期会加1的特性，将先前的累计的归一化相位(即相位除以2π)存储在寄存器中，每回合加上对应的相位增量，避免乘法器的使用。得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1。
优选例3：
根据本发明提供的反向散射标签组成的反向散射网络，包括如下部分：
部分1：具有产生特定激励信号的发射机：
该发射机可以进行IQ调制，发送OOK信号、纯净载波与OFDM信号。
部分2：本发明说明书中描述的基于IDFT数字频率合成的反向散射标签：
该标签可以响应发射机所产生的激励信号并将本地数据加入相位，并利用数字频率合成生成子载波，输出经过简单逻辑变成I/Q信号输出到I/Q路上的射频开关上，实现OFDMA并行接入。
部分3：可以接收并解调反向散射信号的接收机：
该接收机能接收IQ数据，进行时域同步、频域同步并执行FFT等数字信号处理。
具体地，通过实施例来说明本发明中的方法
实施例一：并行实验；半径7米区域内随机放置100个标签，发射机和接收机均采用Mango Communications WARP v3，工作在2.4GHz频段，并与Lenovo ThinkPad P51笔记本电脑通过LAN相连。发射机发射激励信号，所有标签的同步模块与激励信号同步后开始执行各自的子载波调制，将相位调制后的输出通过逻辑判断变成I/Q路的开关控制逻辑信号，分别控制I路开关和Q路开关，完成I/Q调制。在此过程中，他们的数 字频率合成模块遵循发射机指定的k参数和N参数(见说明书部分5)。由于所有的标签的子信道互不冲突，他们的OFDMA信号可以被接收机顺利解调。
实施例二：子载波生成实验。在发射机5米外部署1个标签。通过修改发射机的控制信令，指定该标签的数字频率合成算法在N＝1024的情况下遍历所有的k(k为整数，对应子信道的编号)。在接收机解调以后，得到各个子信道上的物理层数据率。发射机和接收机均采用Mango Communications WARP v3，频段为2.4GHz。结果如图4所示。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
本领域技术人员知道，除了以纯计算机可读程序代码方式实现本发明提供的系统、装置及其各个模块以外，完全可以通过将方法步骤进行逻辑编程来使得本发明提供的系统、装置及其各个模块以逻辑门、开关、专用集成电路、可编程逻辑控制器以及嵌入式微控制器等的形式来实现相同程序。所以，本发明提供的系统、装置及其各个模块可以被认为是一种硬件部件，而对其内包括的用于实现各种程序的模块也可以视为硬件部件内的结构；也可以将用于实现各种功能的模块视为既可以是实现方法的软件程序又可以是硬件部件内的结构。
以上对本发明的具体实施例进行了描述。需要理解的是，本发明并不局限于上述特定实施方式，本领域技术人员可以在权利要求的范围内做出各种变化或修改，这并不影响本发明的实质内容。在不冲突的情况下，本申请的实施例和实施例中的特征可以任意相互组合。

Claims (10)

  1. 一种基于正交频分多址技术的反向散射系统，其特征在于，包括：
    模拟部分、数字逻辑部分；
    所述模拟部分包括：天线、射频开关、包络检波电路和传输线；
    所述数字逻辑部分包括：基于IDFT的数字频率合成模块；
    所述数字逻辑部分的两路输出控制所有的射频开关，包络检波电路提供数字逻辑部分的输入。
  2. 根据权利要求1所述的基于正交频分多址技术的反向散射系统，其特征在于，所述天线：吸收特定频段的电磁波并提供增益；
    所述射频开关：切换阻抗状态；
    所述包络检波电路：检测/解调外界信号并从中获能；
    所述传输线：实现相位移动，以进一步实现IQ调制；
    所述基于IDFT的数字频率合成模块：生成特定频率的子载波并提供调制的接口。
  3. 根据权利要求1所述的基于正交频分多址技术的反向散射系统，其特征在于，所述天线连接一个SPDT射频开关，SPDT射频开关分别与包络检波电路和功率均分器相连。
  4. 根据权利要求3所述的基于正交频分多址技术的反向散射系统，其特征在于，所述功率均分器连接两路传输线，每一路传输线与射频开关相连；
    每个射频开关连接VCC与GND。
  5. 根据权利要求1所述的基于正交频分多址技术的反向散射系统，其特征在于，所述传输线可以用移相器代替。
  6. 根据权利要求1所述的基于正交频分多址技术的反向散射系统，其特征在于，还包括同步算法，用于与外界的激励信号同步，避免码间串扰ISI；
    所述同步算法为数字域的算法，部署在逻辑单元上，逻辑单元包括：MCU、FPGA。
  7. 根据权利要求6所述的基于正交频分多址技术的反向散射系统，其特征在于，所述同步算法指：
    基于IDFT的应用于反向散射通信的低功耗数字频率合成算法。
  8. 根据权利要求7所述的基于正交频分多址技术的反向散射系统，其特征在于，所述同步算法依据反向散射的输出要求仅计算相位变化，并根据相位判断输出为0/1用 于控制射频开关；
    同步算法也可以根据场景不同运用于FSK的反向散射系统或者其他涉及到反向散射频率变化的协议或应用；
  9. 根据权利要求8所述的基于正交频分多址技术的反向散射系统，其特征在于，所述同步算法根据计算相位变化的方式不同，对应两种具体实现方法：
    基于乘法器的相位计算：直接利用采样时钟的计数器得到的n做乘法来得到当前归一化相位，得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1；
    基于寄存器和加法器的相位计算：利用采样时钟每个周期会加1的特性，将先前的累计的归一化相位，存储在寄存器中，每回合加上对应的相位增量，避免乘法器的使用，得到归一化相位后对相位值进行判断决定IQ路输出逻辑值0/1。
  10. 根据权利要求9所述的基于正交频分多址技术的反向散射系统，其特征在于，所述归一化相位指相位除以2π。
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