WO2021212997A1 - 显示面板及其驱动方法、显示装置 - Google Patents
显示面板及其驱动方法、显示装置 Download PDFInfo
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- WO2021212997A1 WO2021212997A1 PCT/CN2021/077575 CN2021077575W WO2021212997A1 WO 2021212997 A1 WO2021212997 A1 WO 2021212997A1 CN 2021077575 W CN2021077575 W CN 2021077575W WO 2021212997 A1 WO2021212997 A1 WO 2021212997A1
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- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Definitions
- the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel, a driving method thereof, and a display device.
- OLED Organic Light Emitting Diode
- OLED can be divided into passive matrix driving organic light-emitting diodes (Passive Matrix Driving OLED, PMOLED) and active matrix driving organic light-emitting diodes (Active Matrix Driving OLED, AMOLED) according to the driving mode.
- Passive Matrix Driving OLED PMOLED
- Active Matrix Driving OLED AMOLED
- LCD liquid crystal displays
- the number of data lines can be reduced and the resolution of the display panel can be improved.
- MUX 1:2 multiplexing
- the sub-pixels are driven row by row according to the turn-on sequence from the first multiplexed signal to the second multiplexed signal for each row.
- This driving method This allows the multiplexed signal to be switched repeatedly by the multiplexer circuit, which increases the power consumption of the device; in another multiplexer circuit, the turn-on sequence of the first multiplexed signal to the second multiplexed signal is performed according to the odd-numbered row, and the second multiplexed signal is the even-numbered row.
- the sub-pixels are driven row by row with the turn-on sequence of the signal to the first multiplexed signal.
- this driving method reduces the power consumption of the device, compared with other rows, the sub-pixels driven by the first multiplexed signal in the first and last rows are The pixel charging time is short, that is, compared with the sub-pixels in other rows, the charging time of some sub-pixels in the first row and the last row is insufficient, and bright lines are easily generated at the positions of the first and last rows.
- An embodiment of the present disclosure provides a display panel, including: a source driving circuit, a multiplexer circuit, and a plurality of sub-pixels arranged in an array.
- the multiplexer circuit is configured to: Under the control of the multiplexed signal, the source driving circuit is controlled to communicate with one or more columns of sub-pixels, and in the j-th frame, the turn-on sequence of the multiplexed signal of the odd-numbered row of sub-pixels is: the J-th multiplexed signal sequence increases to The Nth multiplexed signal and the first multiplexed signal are sequentially increased to the (J-1)th multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is completely opposite to the turn-on sequence of the multiplexed signals of the sub-pixels in the odd-numbered row; j is a natural number greater than or equal to 1, % Is the remainder operator, and N is a natural number greater than 1.
- N 2; the multiplexer circuit is configured to control the source driver circuit and one or more columns of sub-pixels under the control of the first multiplexed signal to the second multiplexed signal.
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, and the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixels is the second multiplexed signal.
- Use signal first multiplexed signal; in the even-numbered frame, the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the second multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels are turned on The sequence is the first multiplexed signal and the second multiplexed signal.
- the plurality of sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels.
- Each sub-pixel includes: a display element and a switching element, and the switching element includes: a first transistor, The control electrode of the transistor is connected to the scan line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the display element.
- the multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing circuit. Use sub-circuits, where:
- the first multiplexing sub-circuit includes 2P second transistors, the control electrode of the second transistor is connected to the first multiplexed signal input terminal, the first electrode of the second transistor is connected to the source drive circuit, and the first electrode of the second transistor is connected to the source drive circuit.
- the two poles are connected to the data line connecting the red sub-pixel or the blue sub-pixel;
- the second multiplexing sub-circuit includes P third transistors, the control electrode of the third transistor is connected to the second multiplexing signal input terminal, the first electrode of the third transistor is connected to the source drive circuit, and the first electrode of the third transistor is connected to the source drive circuit.
- the data line connecting the two poles and the green sub-pixel is connected, and P is a natural number greater than 1.
- the display element is an organic light emitting diode.
- N is 3; the multiplexer circuit is configured to control the source driving circuit and one or more columns of sub-pixels under the control of the first multiplexed signal to the third multiplexed signal.
- the turn-on sequence of the multiplexed signals of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, the third multiplexed signal, and the even-numbered row sub-pixels
- the turn-on sequence of the multiplexed signal is the third multiplexed signal, the second multiplexed signal, and the first multiplexed signal
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: second The multiplexed signal, the third multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels are turned on in the order of the first multiplexed signal, the third multiplexed signal,
- the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixels is the first For the second multiplexed signal, the first multiplexed signal, and the third multiplexed signal, M is a natural number greater than or equal to zero.
- the plurality of sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels.
- Each sub-pixel includes: a display element and a switching element; the switching element includes: a first transistor; The control electrode of the first transistor is connected to the scan line, the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the display element, and the multiplexer circuit includes a first multiplexer The sub-circuit, the second multiplexing sub-circuit and the third multiplexing sub-circuit, where:
- the first multiplexing sub-circuit includes Q second transistors, the control electrode of the second transistor is connected to the first multiplexing signal input terminal, and the first electrode of the second transistor is connected to the source drive circuit, so The second electrode of the second transistor is connected to the data line connected to the red sub-pixel;
- the second multiplexing sub-circuit includes Q third transistors, the control electrode of the third transistor is connected to the second multiplexing signal input terminal, and the first electrode of the third transistor is connected to the source drive circuit, so The second electrode of the third transistor is connected to the data line connected to the blue sub-pixel;
- the third multiplexing sub-circuit includes Q fourth transistors, the control electrode of the fourth transistor is connected to the third multiplexing signal input terminal, the first electrode of the fourth transistor is connected to the source drive circuit, so The second electrode of the fourth transistor is connected to the data line connected to the green sub-pixel, and Q is a natural number greater than 1.
- An embodiment of the present disclosure also provides a display device, including the display panel as described in any of the preceding items.
- the embodiments of the present disclosure also provide a driving method of a display panel, the display panel comprising: a source driving circuit, a multiple selection circuit, a plurality of sub-pixels arranged in an array, and the driving method includes: Under the control of the signal to the N-th multiplexed signal, the source drive circuit is controlled to communicate with one or more columns of sub-pixels, and in the j-th frame, the multiplexed signal of the odd-numbered row of sub-pixels is turned on in the order of: J-th multiplexed
- the signal sequence is increased to the Nth multiplexed signal, the first multiplexed signal is sequentially increased to the (J-1)th multiplexed signal, the multiplexed signal of the sub-pixels in the even row is turned on in sequence and the multiplexed signal of the sub-pixels in the odd row is turned on
- the order is completely opposite; j is a natural number greater than or equal to 1, % Is the remainder operator, and N is a natural number greater
- N is 2
- the driving method includes:
- the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the first multiplexed signal, the second multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the second multiplexed signal and the second multiplexed signal.
- the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the first multiplexed signal and the first multiplexed signal.
- Two-multiplexed signal is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row.
- N is 3, and the driving method includes:
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, the third multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
- the turn-on sequence is the third multiplexed signal, the second multiplexed signal, and the first multiplexed signal
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the second multiplexed signal, the third multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
- the turn-on sequence is the first multiplexed signal, the third multiplexed signal, and the second multiplexed signal;
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the third multiplexed signal, the first multiplexed signal, the second multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
- the turn-on sequence is the second multiplexed signal, the first multiplexed signal, and the third multiplexed signal, and M is a natural number greater than or equal to zero.
- FIG. 1 is one of the structural schematic diagrams of a display panel according to an embodiment of the disclosure
- FIG. 2 is a second structural diagram of a display panel according to an embodiment of the disclosure.
- FIG. 3 is a schematic diagram of the driving timing of the multiplexed signal in the odd-numbered frame of the display panel shown in FIG. 2;
- FIG. 4 is a schematic diagram of the driving timing of the multiplexed signal in the even-numbered frame of the display panel shown in FIG. 2;
- FIG. 5 is a third structural diagram of a display panel according to an embodiment of the disclosure.
- the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
- the thin film transistor used in the embodiments of the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged.
- one of the electrodes is called the first pole, and the other is called the second pole.
- the first pole can be a source or a drain
- the second The electrode can be a drain or a source.
- an embodiment of the present disclosure provides a display panel, including: a source driving circuit 10, a multiple selection circuit 20, and a plurality of sub-pixels 30 arranged in an array.
- the multiple selection circuit 20 is configured to: Under the control of the first multiplexed signal MUX(1) to the N-th multiplexed signal MUXN, the source driving circuit 10 is controlled to communicate with one or more columns of sub-pixels 30, and in the j-th frame, the odd-numbered row of sub-pixels 30
- the multiplexed signal turn-on sequence is: the J-th multiplexed signal MUXJ is sequentially increased to the N-th multiplexed signal MUXN, and the first multiplexed signal MUX(1) is sequentially increased to the (J-1)th multiplexed signal MUX(J-1).
- the turn-on sequence of the multiplexed signal of the sub-pixels 30 in the even-numbered row is completely opposite to the turn-on sequence of the multiplexed signals of the sub-pixels 30 in the odd-numbered row;
- j is a natural number greater than or equal to 1
- % Is the remainder operator is a natural number greater than 1.
- the driving sequence of the multiplexed signal of the odd-numbered row and the even-numbered row is complementary in each frame, and the multiplexed signal of the first row and the last row is made between different frames.
- the driving sequence is complementary, while reducing power consumption, the charging time of each sub-pixel 30 is uniform, the bright lines at the first and last rows are eliminated, and the display effect of the display panel is improved.
- each sub-pixel 30 includes: a switching element 31 and a display element 32.
- the switching element 31 includes: a first transistor M1.
- the control electrode of the first transistor M1 is connected to the scan line.
- the first electrode is connected to the data line, and the second electrode of the first transistor M1 is connected to the display element 32.
- the plurality of sub-pixels 30 may include red sub-pixels, green sub-pixels, and blue sub-pixels. In other embodiments, the plurality of sub-pixels 30 may also include sub-pixels of 4 or any other colors. For example, the plurality of sub-pixels 30 may include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.
- the display element 32 may be an organic light emitting diode or other types of light emitting diodes or the like.
- the structure of the display element 32 can be designed and determined according to the actual application environment, which is not limited here.
- the display panel includes a display area and a non-display area, scan lines, data lines, and sub-pixels are located in the display area, and the multiplexer circuit and source driving circuit are located in the non-display area of the display panel.
- N is 2; the multiplexer circuit 20 is configured to, under the control of the first multiplexed signal MUX(1) to the second multiplexed signal MUX(2), control the source drive
- the circuit 10 is connected to one or more columns of sub-pixels 30, and in the odd-numbered frame, the multiplexed signal of the odd-numbered row of sub-pixels 30 is turned on in the order of: the first multiplexed signal MUX(1), the second multiplexed signal MUX (2)
- the turn-on sequence of the multiplexed signal of the sub-pixel 30 in the even number row is the second multiplexed signal MUX(2) and the first multiplexed signal MUX(1); in the even-numbered frame, the sub-pixel 30 in the odd numbered row
- the turn-on sequence of the multiplexed signal is: the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), and the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixels 30 is
- the multiplexing circuit 20 includes a first multiplexing sub-circuit and a second multiplexing sub-circuit.
- the first multiplexing sub-circuit includes 2P second transistors M2, the control electrode of the second transistor M2 is connected to the first multiplexing signal input terminal MUX1, the first electrode of the second transistor M2 is connected to the source drive circuit 10, and the second transistor M2 is connected to the source drive circuit 10.
- the second electrode of the transistor M2 is connected to the data line connected to the red sub-pixel or the blue sub-pixel.
- the second multiplexing sub-circuit includes P third transistors M3, the control electrode of the third transistor M3 is connected to the second multiplexing signal input terminal MUX2, the first electrode of the third transistor M3 is connected to the source drive circuit 10, and the third transistor M3 is connected to the source drive circuit 10.
- the second electrode of the transistor M3 is connected to the data line connected to the green sub-pixel, and P is a natural number greater than 1.
- the second electrode of the second transistor M2 can also be connected to the data line connected to the red sub-pixel or the green sub-pixel, and the second electrode of the third transistor M3 can also be connected to the data line connected to the blue sub-pixel.
- the second pole of the second transistor M2 can also be connected to the data line connected to the blue sub-pixel or the green sub-pixel, and the second pole of the third transistor M3 can also be connected to the data line connected to the red sub-pixel;
- the structures of the second transistor M2 and the third transistor M3 can be designed and determined according to the actual application environment, and are not limited here.
- the transistors M1 to M3 can all be N-type thin film transistors or P-type thin film transistors, and the transistors M1 to M3 are set to be the same type of thin film transistors, which can unify the process flow, thereby reducing the process process, and helping to improve the product. The yield rate.
- all transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin-film transistors, and thin-film transistors may be thin-film transistors with a bottom-gate structure or a top-gate structure. Thin film transistors, as long as they can achieve switching functions.
- FIG. 3 is a schematic diagram of the multiplexed signal driving timing diagram of the display panel shown in FIG. 2 in the odd-numbered frame
- FIG. 4 is a schematic diagram of the multiplexed signal driving timing diagram of the display panel shown in FIG. 2 in the even-numbered frame.
- the working process of the display panel will be described below in conjunction with the display panel shown in FIG. 2 and the multiplexed signal driving timing diagrams shown in FIGS. 3 and 4.
- transistors M1 to M3 as P-type thin film transistors as an example, when the potential of the gate terminal becomes low, the P-type thin film transistor is turned on, and when the potential of the gate terminal becomes high, the P-type thin film transistor is turned off.
- the working process includes:
- each shift register unit generates a scan signal and outputs it to the scan line; at this time, the odd row
- the turn-on sequence of the multiplexed signal of the sub-pixels 30 is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), that is, the driving sequence of the odd-numbered row sub-pixels 30 is to drive the red sub-pixels and the blue sub-pixels first.
- the turn-on sequence of the multiplexed signals of the even-numbered row sub-pixels 30 is the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), that is, the even-numbered row sub-pixels
- the driving sequence of 30 is to drive the green sub-pixels, then the red sub-pixels and the blue sub-pixels.
- the source drive circuit 10 generates the corresponding data voltage signal, and then the first multiplexed signal MUX(1) and the second multiplexed signal Under the control of the signal MUX(2), the data voltage signal is output to the corresponding sub-pixel 30 through the data line.
- each shift register unit generates a scan signal and outputs it to the scan line; at this time, the odd-numbered row
- the turn-on sequence of the multiplexed signal of the sub-pixel 30 is: the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), that is, the driving sequence of the odd-numbered row sub-pixel 30 is to drive the green sub-pixel first, and then To drive the red sub-pixel and the blue sub-pixel, the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixel 30 is the first multiplexed signal MUX(1) and the second multiplexed signal MUX(2), that is, the even-numbered row sub-pixels
- the driving sequence of 30 is to first drive the red sub-pixel and the blue sub-pixel, and then drive the green sub-pixel.
- the source driving circuit 10 generates the corresponding data voltage signal, and the first multiplexed signal MUX(1) and the second multiplexed signal Under the control of the signal MUX(2), the data voltage signal is output to the corresponding sub-pixel 30 through the data line.
- the multiplexed signal turn-on sequence is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), and the second multiplexed signal MUX(2) , The first multiplexed signal MUX(1), the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1) , Abbreviated as 1221122112211221...; in the even-numbered frame stage, the multiplexed signal turn-on sequence is: the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), the first multiplexed signal MUX(1), The second multiplexed signal MUX(2), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), the first multiplexed signal MUX(1), the second multiplexed signal
- the multiplexed signals are turned on in completely opposite timing between odd and even frames, odd rows and even rows to ensure the same turn-on time between different multiplexed signals, thereby ensuring
- the charging time of each sub-pixel 30 is uniform, the odd-even timing is alternately controlled, and the luminous efficiency of the edge pixels compensate each other, which improves the display effect of the module.
- N is 3.
- the multiplexing circuit 20 is configured to control the communication between the source driving circuit 10 and one or more columns of sub-pixels 30 under the control of the first multiplexed signal MUX(1) to the third multiplexed signal MUX(3), And in the (3M+1)th frame, the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixel 30 is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), and the third multiplexed signal MUX(3), the turn-on sequence of the multiplexed signal of the sub-pixel 30 in the even-numbered row is the third multiplexed signal MUX(3), the second multiplexed signal MUX(2), and the first multiplexed signal MUX(1); (3M+2) frame, the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixel 30 is: the second multiplexed signal MUX(2), the third multiplexed signal MUX(3), the first multiplexed signal MUX
- the multiplexing circuit 20 includes a first multiplexing sub-circuit, a second multiplexing sub-circuit, and a third multiplexing sub-circuit.
- the first multiplexing sub-circuit includes Q second transistors M2, the control electrode of the second transistor M2 is connected to the first multiplexing signal input terminal MUX1, the first electrode of the second transistor M2 is connected to the source drive circuit 10, and the second transistor M2 is connected to the source drive circuit 10.
- the second electrode of the transistor M2 is connected to the data line connected to the red sub-pixel;
- the second multiplexing sub-circuit includes Q third transistors M3, the control electrode of the third transistor M3 is connected to the second multiplexed signal input terminal MUX2, the first electrode of the third transistor M3 is connected to the source drive circuit 10, and the third The second electrode of the transistor M3 is connected to the data line connected to the blue sub-pixel;
- the third multiplexing sub-circuit includes Q fourth transistors M4, the control electrode of the fourth transistor M4 is connected to the third multiplexing signal input terminal MUX3, the first electrode of the fourth transistor M4 is connected to the source drive circuit 10, and the fourth transistor M4 is connected to the source drive circuit 10.
- the second electrode of the transistor M4 is connected to the data line connected to the green sub-pixel, and Q is a natural number greater than 1.
- the transistors M1 to M4 can all be N-type thin film transistors or P-type thin film transistors, and the transistors M1 to M4 are set to be the same type of thin film transistors, which can unify the process flow, thereby reducing the process process, and helping to improve the product.
- the yield rate in some exemplary embodiments, considering the low leakage current of low-temperature polysilicon thin film transistors, all the transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin film transistors, and the thin film transistors may be thin film transistors with bottom gate structure or top The thin film transistor of the gate structure only needs to be able to realize the switching function.
- the multiplexed signal turn-on sequence is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), and the third multiplexed signal MUX( 3), the third multiplexed signal MUX(3), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), the first multiplexed signal MUX(1), the second multiplexed signal MUX( 2), the third multiplexed signal MUX(3), the third multiplexed signal MUX(3), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1)..., abbreviated as 123321123321123321123321...
- the multiplexed signal turn-on sequence is: the second multiplexed signal MUX(2), the third multiplexed signal MUX(3), the first multiplexed signal MUX(1), the first Multiplexed signal MUX(1), third multiplexed signal MUX(3), second multiplexed signal MUX(2), second multiplexed signal MUX(2), third multiplexed signal MUX(3), first The multiplexed signal MUX(1), the first multiplexed signal MUX(1), the third multiplexed signal MUX(3), the second multiplexed signal MUX(2)..., abbreviated as 231132231132231132231132...; in the (3M) +3)
- the multiplexing signal opening sequence is: the third multiplexing signal MUX(3), the first multiplexing signal MUX(1), the second multiplexing signal MUX(2), the second multiplexing signal MUX( 2), the first multiplexed signal
- the multiplexed signal ensures the same turn-on time between different multiplexed signals, thereby ensuring that the charging time of each sub-pixel 30 is uniform, the odd and even timing is alternately controlled, and the luminous efficiency of the edge pixels is compensated for each other, which improves the display effect of the module.
- the embodiments of the present disclosure also provide a driving method of a display panel, the display panel comprising: a source driving circuit, a multiple selection circuit, and a plurality of sub-pixels arranged in an array.
- the driving method includes:
- the source driving circuit Under the control of the first multiplexed signal to the N-th multiplexed signal, the source driving circuit is controlled to communicate with one or more columns of sub-pixels, and in the j-th frame, the multiplexed signal of the odd-numbered row of sub-pixels is turned on in sequence as :
- the J-th multiplexed signal is sequentially incremented to the N-th multiplexed signal
- the first multiplexed signal is sequentially incremented to the (J-1)-th multiplexed signal
- the multiplexed signal turn-on sequence of the even-numbered row sub-pixels is compared with the odd-numbered row sub-pixels
- the turn-on sequence of the multiplexed signal is completely opposite; j is a natural number greater than or equal to 1, % Is the remainder operator, and N is a natural number greater than 1.
- N is 2
- the driving method includes:
- the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the first multiplexed signal, the second multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the second multiplexed signal and the second multiplexed signal.
- the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the first multiplexed signal and the first multiplexed signal.
- Two-multiplexed signal is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row.
- N is 3, and the driving method includes:
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, the third multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
- the turn-on sequence is the third multiplexed signal, the second multiplexed signal, and the first multiplexed signal
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the second multiplexed signal, the third multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
- the turn-on sequence is the first multiplexed signal, the third multiplexed signal, and the second multiplexed signal;
- the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the third multiplexed signal, the first multiplexed signal, the second multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
- the turn-on sequence is the second multiplexed signal, the first multiplexed signal, and the third multiplexed signal, and M is a natural number greater than or equal to zero.
- Some embodiments of the present disclosure also provide a display device, which includes a display panel.
- the display device may be: OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, and any other product or component with display function, which is not limited in the embodiment of the present disclosure. .
- the display panel is the display panel provided in the foregoing embodiment, and its implementation principles and effects are similar, and will not be repeated here.
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Abstract
Description
Claims (10)
- 根据权利要求1所述的显示面板,其中,N为2;所述多路选择电路被配置为,在第一复用信号至第二复用信号的控制下,控制源极驱动电路与一列或多列子像素之间连通,且在第奇数帧时,第奇数行子像素的复用信号开启顺序为:第一复用信号、第二复用信号,第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号;在第偶数帧时,第奇数行子像素的复用信号开启顺序为:第二复用信号、第一复用信号,第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
- 根据权利要求2所述的显示面板,其中,所述多个子像素包括红色子像素、蓝色子像素和绿色子像素,每个子像素包括:显示元件和开关元件,所述开关元件包括:第一晶体管,第一晶体管的控制极与扫描线连接,第一晶体管的第一极与数据线连接,第一晶体管的第二极与显示元件连接,所述多路选择电路包括第一复用子电路和第二复用子电路,其中:所述第一复用子电路包括2P个第二晶体管,第二晶体管的控制极和第一复用信号输入端连接,第二晶体管的第一极和源极驱动电路连接,第二晶体管的第二极和红色子像素或蓝色子像素连接的数据线连接;所述第二复用子电路包括P个第三晶体管,第三晶体管的控制极和第二复用信号输入端连接,第三晶体管的第一极和源极驱动电路连接,第三晶体 管的第二极和绿色子像素连接的数据线连接,P为大于1的自然数。
- 根据权利要求3所述的显示面板,其中,所述显示元件为有机发光二极管。
- 根据权利要求1所述的显示面板,其中,N为3;所述多路选择电路被配置为,在第一复用信号至第三复用信号的控制下,控制源极驱动电路与一列或多列子像素之间连通,且在第(3M+1)帧时,第奇数行子像素的复用信号开启顺序为:第一复用信号、第二复用信号、第三复用信号,第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号;在第(3M+2)帧时,第奇数行子像素的复用信号开启顺序为:第二复用信号、第三复用信号、第一复用信号,第偶数行子像素的复用信号开启顺序为第一复用信号、第三复用信号、第二复用信号;在第(3M+3)帧时,第奇数行子像素的复用信号开启顺序为:第三复用信号、第一复用信号、第二复用信号,第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号,M为大于或等于0的自然数。
- 根据权利要求5所述的显示面板,所述多个子像素包括红色子像素、蓝色子像素和绿色子像素,每个子像素包括:显示元件和开关元件,所述开关元件包括:第一晶体管,所述第一晶体管的控制极与扫描线连接,所述第一晶体管的第一极与数据线连接,所述第一晶体管的第二极与显示元件连接,所述多路选择电路包括第一复用子电路、第二复用子电路和第三复用子电路,其中:所述第一复用子电路包括Q个第二晶体管,所述第二晶体管的控制极和第一复用信号输入端连接,所述第二晶体管的第一极和源极驱动电路连接,所述第二晶体管的第二极和红色子像素连接的数据线连接;所述第二复用子电路包括Q个第三晶体管,所述第三晶体管的控制极和第二复用信号输入端连接,所述第三晶体管的第一极和源极驱动电路连接,所述第三晶体管的第二极和蓝色子像素连接的数据线连接;所述第三复用子电路包括Q个第四晶体管,所述第四晶体管的控制极和 第三复用信号输入端连接,所述第四晶体管的第一极和源极驱动电路连接,所述第四晶体管的第二极和绿色子像素连接的数据线连接,Q为大于1的自然数。
- 一种显示装置,包括如权利要求1至权利要求6任一所述的显示面板。
- 根据权利要求8所述的驱动方法,其中,N为2,所述驱动方法包括:在第奇数帧时,第奇数行子像素的复用信号开启顺序为:第一复用信号、第二复用信号,第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号;在第偶数帧时,第奇数行子像素的复用信号开启顺序为:第二复用信号、第一复用信号,第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
- 根据权利要求8所述的驱动方法,N为3,所述驱动方法包括:在第(3M+1)帧时,第奇数行子像素的复用信号开启顺序为:第一复用信号、第二复用信号、第三复用信号,第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号;在第(3M+2)帧时,第奇数行子像素的复用信号开启顺序为:第二复用信号、第三复用信号、第一复用信号,第偶数行子像素的复用信号开启顺序为第一复用信号、第三复用信号、第二复用信号;在第(3M+3)帧时,第奇数行子像素的复用信号开启顺序为:第三复用信号、第一复用信号、第二复用信号,第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号,M为大于或等于0的自然数。
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