WO2021212997A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

Info

Publication number
WO2021212997A1
WO2021212997A1 PCT/CN2021/077575 CN2021077575W WO2021212997A1 WO 2021212997 A1 WO2021212997 A1 WO 2021212997A1 CN 2021077575 W CN2021077575 W CN 2021077575W WO 2021212997 A1 WO2021212997 A1 WO 2021212997A1
Authority
WO
WIPO (PCT)
Prior art keywords
multiplexed signal
sub
pixels
sequence
transistor
Prior art date
Application number
PCT/CN2021/077575
Other languages
English (en)
French (fr)
Inventor
文慧
龚庆
陆旭
刘照仑
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/435,028 priority Critical patent/US11741905B2/en
Publication of WO2021212997A1 publication Critical patent/WO2021212997A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0232—Special driving of display border areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel, a driving method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • OLED can be divided into passive matrix driving organic light-emitting diodes (Passive Matrix Driving OLED, PMOLED) and active matrix driving organic light-emitting diodes (Active Matrix Driving OLED, AMOLED) according to the driving mode.
  • Passive Matrix Driving OLED PMOLED
  • Active Matrix Driving OLED AMOLED
  • LCD liquid crystal displays
  • the number of data lines can be reduced and the resolution of the display panel can be improved.
  • MUX 1:2 multiplexing
  • the sub-pixels are driven row by row according to the turn-on sequence from the first multiplexed signal to the second multiplexed signal for each row.
  • This driving method This allows the multiplexed signal to be switched repeatedly by the multiplexer circuit, which increases the power consumption of the device; in another multiplexer circuit, the turn-on sequence of the first multiplexed signal to the second multiplexed signal is performed according to the odd-numbered row, and the second multiplexed signal is the even-numbered row.
  • the sub-pixels are driven row by row with the turn-on sequence of the signal to the first multiplexed signal.
  • this driving method reduces the power consumption of the device, compared with other rows, the sub-pixels driven by the first multiplexed signal in the first and last rows are The pixel charging time is short, that is, compared with the sub-pixels in other rows, the charging time of some sub-pixels in the first row and the last row is insufficient, and bright lines are easily generated at the positions of the first and last rows.
  • An embodiment of the present disclosure provides a display panel, including: a source driving circuit, a multiplexer circuit, and a plurality of sub-pixels arranged in an array.
  • the multiplexer circuit is configured to: Under the control of the multiplexed signal, the source driving circuit is controlled to communicate with one or more columns of sub-pixels, and in the j-th frame, the turn-on sequence of the multiplexed signal of the odd-numbered row of sub-pixels is: the J-th multiplexed signal sequence increases to The Nth multiplexed signal and the first multiplexed signal are sequentially increased to the (J-1)th multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is completely opposite to the turn-on sequence of the multiplexed signals of the sub-pixels in the odd-numbered row; j is a natural number greater than or equal to 1, % Is the remainder operator, and N is a natural number greater than 1.
  • N 2; the multiplexer circuit is configured to control the source driver circuit and one or more columns of sub-pixels under the control of the first multiplexed signal to the second multiplexed signal.
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, and the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixels is the second multiplexed signal.
  • Use signal first multiplexed signal; in the even-numbered frame, the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the second multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels are turned on The sequence is the first multiplexed signal and the second multiplexed signal.
  • the plurality of sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels.
  • Each sub-pixel includes: a display element and a switching element, and the switching element includes: a first transistor, The control electrode of the transistor is connected to the scan line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the display element.
  • the multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing circuit. Use sub-circuits, where:
  • the first multiplexing sub-circuit includes 2P second transistors, the control electrode of the second transistor is connected to the first multiplexed signal input terminal, the first electrode of the second transistor is connected to the source drive circuit, and the first electrode of the second transistor is connected to the source drive circuit.
  • the two poles are connected to the data line connecting the red sub-pixel or the blue sub-pixel;
  • the second multiplexing sub-circuit includes P third transistors, the control electrode of the third transistor is connected to the second multiplexing signal input terminal, the first electrode of the third transistor is connected to the source drive circuit, and the first electrode of the third transistor is connected to the source drive circuit.
  • the data line connecting the two poles and the green sub-pixel is connected, and P is a natural number greater than 1.
  • the display element is an organic light emitting diode.
  • N is 3; the multiplexer circuit is configured to control the source driving circuit and one or more columns of sub-pixels under the control of the first multiplexed signal to the third multiplexed signal.
  • the turn-on sequence of the multiplexed signals of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, the third multiplexed signal, and the even-numbered row sub-pixels
  • the turn-on sequence of the multiplexed signal is the third multiplexed signal, the second multiplexed signal, and the first multiplexed signal
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: second The multiplexed signal, the third multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels are turned on in the order of the first multiplexed signal, the third multiplexed signal,
  • the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixels is the first For the second multiplexed signal, the first multiplexed signal, and the third multiplexed signal, M is a natural number greater than or equal to zero.
  • the plurality of sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels.
  • Each sub-pixel includes: a display element and a switching element; the switching element includes: a first transistor; The control electrode of the first transistor is connected to the scan line, the first electrode of the first transistor is connected to the data line, the second electrode of the first transistor is connected to the display element, and the multiplexer circuit includes a first multiplexer The sub-circuit, the second multiplexing sub-circuit and the third multiplexing sub-circuit, where:
  • the first multiplexing sub-circuit includes Q second transistors, the control electrode of the second transistor is connected to the first multiplexing signal input terminal, and the first electrode of the second transistor is connected to the source drive circuit, so The second electrode of the second transistor is connected to the data line connected to the red sub-pixel;
  • the second multiplexing sub-circuit includes Q third transistors, the control electrode of the third transistor is connected to the second multiplexing signal input terminal, and the first electrode of the third transistor is connected to the source drive circuit, so The second electrode of the third transistor is connected to the data line connected to the blue sub-pixel;
  • the third multiplexing sub-circuit includes Q fourth transistors, the control electrode of the fourth transistor is connected to the third multiplexing signal input terminal, the first electrode of the fourth transistor is connected to the source drive circuit, so The second electrode of the fourth transistor is connected to the data line connected to the green sub-pixel, and Q is a natural number greater than 1.
  • An embodiment of the present disclosure also provides a display device, including the display panel as described in any of the preceding items.
  • the embodiments of the present disclosure also provide a driving method of a display panel, the display panel comprising: a source driving circuit, a multiple selection circuit, a plurality of sub-pixels arranged in an array, and the driving method includes: Under the control of the signal to the N-th multiplexed signal, the source drive circuit is controlled to communicate with one or more columns of sub-pixels, and in the j-th frame, the multiplexed signal of the odd-numbered row of sub-pixels is turned on in the order of: J-th multiplexed
  • the signal sequence is increased to the Nth multiplexed signal, the first multiplexed signal is sequentially increased to the (J-1)th multiplexed signal, the multiplexed signal of the sub-pixels in the even row is turned on in sequence and the multiplexed signal of the sub-pixels in the odd row is turned on
  • the order is completely opposite; j is a natural number greater than or equal to 1, % Is the remainder operator, and N is a natural number greater
  • N is 2
  • the driving method includes:
  • the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the first multiplexed signal, the second multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the second multiplexed signal and the second multiplexed signal.
  • the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the first multiplexed signal and the first multiplexed signal.
  • Two-multiplexed signal is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row.
  • N is 3, and the driving method includes:
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, the third multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
  • the turn-on sequence is the third multiplexed signal, the second multiplexed signal, and the first multiplexed signal
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the second multiplexed signal, the third multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
  • the turn-on sequence is the first multiplexed signal, the third multiplexed signal, and the second multiplexed signal;
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the third multiplexed signal, the first multiplexed signal, the second multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
  • the turn-on sequence is the second multiplexed signal, the first multiplexed signal, and the third multiplexed signal, and M is a natural number greater than or equal to zero.
  • FIG. 1 is one of the structural schematic diagrams of a display panel according to an embodiment of the disclosure
  • FIG. 2 is a second structural diagram of a display panel according to an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the driving timing of the multiplexed signal in the odd-numbered frame of the display panel shown in FIG. 2;
  • FIG. 4 is a schematic diagram of the driving timing of the multiplexed signal in the even-numbered frame of the display panel shown in FIG. 2;
  • FIG. 5 is a third structural diagram of a display panel according to an embodiment of the disclosure.
  • the transistors used in all the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • the thin film transistor used in the embodiments of the present disclosure may be an oxide semiconductor transistor. Since the source and drain of the transistor used here are symmetrical, the source and drain can be interchanged.
  • one of the electrodes is called the first pole, and the other is called the second pole.
  • the first pole can be a source or a drain
  • the second The electrode can be a drain or a source.
  • an embodiment of the present disclosure provides a display panel, including: a source driving circuit 10, a multiple selection circuit 20, and a plurality of sub-pixels 30 arranged in an array.
  • the multiple selection circuit 20 is configured to: Under the control of the first multiplexed signal MUX(1) to the N-th multiplexed signal MUXN, the source driving circuit 10 is controlled to communicate with one or more columns of sub-pixels 30, and in the j-th frame, the odd-numbered row of sub-pixels 30
  • the multiplexed signal turn-on sequence is: the J-th multiplexed signal MUXJ is sequentially increased to the N-th multiplexed signal MUXN, and the first multiplexed signal MUX(1) is sequentially increased to the (J-1)th multiplexed signal MUX(J-1).
  • the turn-on sequence of the multiplexed signal of the sub-pixels 30 in the even-numbered row is completely opposite to the turn-on sequence of the multiplexed signals of the sub-pixels 30 in the odd-numbered row;
  • j is a natural number greater than or equal to 1
  • % Is the remainder operator is a natural number greater than 1.
  • the driving sequence of the multiplexed signal of the odd-numbered row and the even-numbered row is complementary in each frame, and the multiplexed signal of the first row and the last row is made between different frames.
  • the driving sequence is complementary, while reducing power consumption, the charging time of each sub-pixel 30 is uniform, the bright lines at the first and last rows are eliminated, and the display effect of the display panel is improved.
  • each sub-pixel 30 includes: a switching element 31 and a display element 32.
  • the switching element 31 includes: a first transistor M1.
  • the control electrode of the first transistor M1 is connected to the scan line.
  • the first electrode is connected to the data line, and the second electrode of the first transistor M1 is connected to the display element 32.
  • the plurality of sub-pixels 30 may include red sub-pixels, green sub-pixels, and blue sub-pixels. In other embodiments, the plurality of sub-pixels 30 may also include sub-pixels of 4 or any other colors. For example, the plurality of sub-pixels 30 may include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.
  • the display element 32 may be an organic light emitting diode or other types of light emitting diodes or the like.
  • the structure of the display element 32 can be designed and determined according to the actual application environment, which is not limited here.
  • the display panel includes a display area and a non-display area, scan lines, data lines, and sub-pixels are located in the display area, and the multiplexer circuit and source driving circuit are located in the non-display area of the display panel.
  • N is 2; the multiplexer circuit 20 is configured to, under the control of the first multiplexed signal MUX(1) to the second multiplexed signal MUX(2), control the source drive
  • the circuit 10 is connected to one or more columns of sub-pixels 30, and in the odd-numbered frame, the multiplexed signal of the odd-numbered row of sub-pixels 30 is turned on in the order of: the first multiplexed signal MUX(1), the second multiplexed signal MUX (2)
  • the turn-on sequence of the multiplexed signal of the sub-pixel 30 in the even number row is the second multiplexed signal MUX(2) and the first multiplexed signal MUX(1); in the even-numbered frame, the sub-pixel 30 in the odd numbered row
  • the turn-on sequence of the multiplexed signal is: the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), and the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixels 30 is
  • the multiplexing circuit 20 includes a first multiplexing sub-circuit and a second multiplexing sub-circuit.
  • the first multiplexing sub-circuit includes 2P second transistors M2, the control electrode of the second transistor M2 is connected to the first multiplexing signal input terminal MUX1, the first electrode of the second transistor M2 is connected to the source drive circuit 10, and the second transistor M2 is connected to the source drive circuit 10.
  • the second electrode of the transistor M2 is connected to the data line connected to the red sub-pixel or the blue sub-pixel.
  • the second multiplexing sub-circuit includes P third transistors M3, the control electrode of the third transistor M3 is connected to the second multiplexing signal input terminal MUX2, the first electrode of the third transistor M3 is connected to the source drive circuit 10, and the third transistor M3 is connected to the source drive circuit 10.
  • the second electrode of the transistor M3 is connected to the data line connected to the green sub-pixel, and P is a natural number greater than 1.
  • the second electrode of the second transistor M2 can also be connected to the data line connected to the red sub-pixel or the green sub-pixel, and the second electrode of the third transistor M3 can also be connected to the data line connected to the blue sub-pixel.
  • the second pole of the second transistor M2 can also be connected to the data line connected to the blue sub-pixel or the green sub-pixel, and the second pole of the third transistor M3 can also be connected to the data line connected to the red sub-pixel;
  • the structures of the second transistor M2 and the third transistor M3 can be designed and determined according to the actual application environment, and are not limited here.
  • the transistors M1 to M3 can all be N-type thin film transistors or P-type thin film transistors, and the transistors M1 to M3 are set to be the same type of thin film transistors, which can unify the process flow, thereby reducing the process process, and helping to improve the product. The yield rate.
  • all transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin-film transistors, and thin-film transistors may be thin-film transistors with a bottom-gate structure or a top-gate structure. Thin film transistors, as long as they can achieve switching functions.
  • FIG. 3 is a schematic diagram of the multiplexed signal driving timing diagram of the display panel shown in FIG. 2 in the odd-numbered frame
  • FIG. 4 is a schematic diagram of the multiplexed signal driving timing diagram of the display panel shown in FIG. 2 in the even-numbered frame.
  • the working process of the display panel will be described below in conjunction with the display panel shown in FIG. 2 and the multiplexed signal driving timing diagrams shown in FIGS. 3 and 4.
  • transistors M1 to M3 as P-type thin film transistors as an example, when the potential of the gate terminal becomes low, the P-type thin film transistor is turned on, and when the potential of the gate terminal becomes high, the P-type thin film transistor is turned off.
  • the working process includes:
  • each shift register unit generates a scan signal and outputs it to the scan line; at this time, the odd row
  • the turn-on sequence of the multiplexed signal of the sub-pixels 30 is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), that is, the driving sequence of the odd-numbered row sub-pixels 30 is to drive the red sub-pixels and the blue sub-pixels first.
  • the turn-on sequence of the multiplexed signals of the even-numbered row sub-pixels 30 is the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), that is, the even-numbered row sub-pixels
  • the driving sequence of 30 is to drive the green sub-pixels, then the red sub-pixels and the blue sub-pixels.
  • the source drive circuit 10 generates the corresponding data voltage signal, and then the first multiplexed signal MUX(1) and the second multiplexed signal Under the control of the signal MUX(2), the data voltage signal is output to the corresponding sub-pixel 30 through the data line.
  • each shift register unit generates a scan signal and outputs it to the scan line; at this time, the odd-numbered row
  • the turn-on sequence of the multiplexed signal of the sub-pixel 30 is: the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), that is, the driving sequence of the odd-numbered row sub-pixel 30 is to drive the green sub-pixel first, and then To drive the red sub-pixel and the blue sub-pixel, the turn-on sequence of the multiplexed signal of the even-numbered row sub-pixel 30 is the first multiplexed signal MUX(1) and the second multiplexed signal MUX(2), that is, the even-numbered row sub-pixels
  • the driving sequence of 30 is to first drive the red sub-pixel and the blue sub-pixel, and then drive the green sub-pixel.
  • the source driving circuit 10 generates the corresponding data voltage signal, and the first multiplexed signal MUX(1) and the second multiplexed signal Under the control of the signal MUX(2), the data voltage signal is output to the corresponding sub-pixel 30 through the data line.
  • the multiplexed signal turn-on sequence is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), and the second multiplexed signal MUX(2) , The first multiplexed signal MUX(1), the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1) , Abbreviated as 1221122112211221...; in the even-numbered frame stage, the multiplexed signal turn-on sequence is: the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), the first multiplexed signal MUX(1), The second multiplexed signal MUX(2), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), the first multiplexed signal MUX(1), the second multiplexed signal
  • the multiplexed signals are turned on in completely opposite timing between odd and even frames, odd rows and even rows to ensure the same turn-on time between different multiplexed signals, thereby ensuring
  • the charging time of each sub-pixel 30 is uniform, the odd-even timing is alternately controlled, and the luminous efficiency of the edge pixels compensate each other, which improves the display effect of the module.
  • N is 3.
  • the multiplexing circuit 20 is configured to control the communication between the source driving circuit 10 and one or more columns of sub-pixels 30 under the control of the first multiplexed signal MUX(1) to the third multiplexed signal MUX(3), And in the (3M+1)th frame, the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixel 30 is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), and the third multiplexed signal MUX(3), the turn-on sequence of the multiplexed signal of the sub-pixel 30 in the even-numbered row is the third multiplexed signal MUX(3), the second multiplexed signal MUX(2), and the first multiplexed signal MUX(1); (3M+2) frame, the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixel 30 is: the second multiplexed signal MUX(2), the third multiplexed signal MUX(3), the first multiplexed signal MUX
  • the multiplexing circuit 20 includes a first multiplexing sub-circuit, a second multiplexing sub-circuit, and a third multiplexing sub-circuit.
  • the first multiplexing sub-circuit includes Q second transistors M2, the control electrode of the second transistor M2 is connected to the first multiplexing signal input terminal MUX1, the first electrode of the second transistor M2 is connected to the source drive circuit 10, and the second transistor M2 is connected to the source drive circuit 10.
  • the second electrode of the transistor M2 is connected to the data line connected to the red sub-pixel;
  • the second multiplexing sub-circuit includes Q third transistors M3, the control electrode of the third transistor M3 is connected to the second multiplexed signal input terminal MUX2, the first electrode of the third transistor M3 is connected to the source drive circuit 10, and the third The second electrode of the transistor M3 is connected to the data line connected to the blue sub-pixel;
  • the third multiplexing sub-circuit includes Q fourth transistors M4, the control electrode of the fourth transistor M4 is connected to the third multiplexing signal input terminal MUX3, the first electrode of the fourth transistor M4 is connected to the source drive circuit 10, and the fourth transistor M4 is connected to the source drive circuit 10.
  • the second electrode of the transistor M4 is connected to the data line connected to the green sub-pixel, and Q is a natural number greater than 1.
  • the transistors M1 to M4 can all be N-type thin film transistors or P-type thin film transistors, and the transistors M1 to M4 are set to be the same type of thin film transistors, which can unify the process flow, thereby reducing the process process, and helping to improve the product.
  • the yield rate in some exemplary embodiments, considering the low leakage current of low-temperature polysilicon thin film transistors, all the transistors in the embodiments of the present disclosure may be low-temperature polysilicon thin film transistors, and the thin film transistors may be thin film transistors with bottom gate structure or top The thin film transistor of the gate structure only needs to be able to realize the switching function.
  • the multiplexed signal turn-on sequence is: the first multiplexed signal MUX(1), the second multiplexed signal MUX(2), and the third multiplexed signal MUX( 3), the third multiplexed signal MUX(3), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1), the first multiplexed signal MUX(1), the second multiplexed signal MUX( 2), the third multiplexed signal MUX(3), the third multiplexed signal MUX(3), the second multiplexed signal MUX(2), the first multiplexed signal MUX(1)..., abbreviated as 123321123321123321123321...
  • the multiplexed signal turn-on sequence is: the second multiplexed signal MUX(2), the third multiplexed signal MUX(3), the first multiplexed signal MUX(1), the first Multiplexed signal MUX(1), third multiplexed signal MUX(3), second multiplexed signal MUX(2), second multiplexed signal MUX(2), third multiplexed signal MUX(3), first The multiplexed signal MUX(1), the first multiplexed signal MUX(1), the third multiplexed signal MUX(3), the second multiplexed signal MUX(2)..., abbreviated as 231132231132231132231132...; in the (3M) +3)
  • the multiplexing signal opening sequence is: the third multiplexing signal MUX(3), the first multiplexing signal MUX(1), the second multiplexing signal MUX(2), the second multiplexing signal MUX( 2), the first multiplexed signal
  • the multiplexed signal ensures the same turn-on time between different multiplexed signals, thereby ensuring that the charging time of each sub-pixel 30 is uniform, the odd and even timing is alternately controlled, and the luminous efficiency of the edge pixels is compensated for each other, which improves the display effect of the module.
  • the embodiments of the present disclosure also provide a driving method of a display panel, the display panel comprising: a source driving circuit, a multiple selection circuit, and a plurality of sub-pixels arranged in an array.
  • the driving method includes:
  • the source driving circuit Under the control of the first multiplexed signal to the N-th multiplexed signal, the source driving circuit is controlled to communicate with one or more columns of sub-pixels, and in the j-th frame, the multiplexed signal of the odd-numbered row of sub-pixels is turned on in sequence as :
  • the J-th multiplexed signal is sequentially incremented to the N-th multiplexed signal
  • the first multiplexed signal is sequentially incremented to the (J-1)-th multiplexed signal
  • the multiplexed signal turn-on sequence of the even-numbered row sub-pixels is compared with the odd-numbered row sub-pixels
  • the turn-on sequence of the multiplexed signal is completely opposite; j is a natural number greater than or equal to 1, % Is the remainder operator, and N is a natural number greater than 1.
  • N is 2
  • the driving method includes:
  • the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the first multiplexed signal, the second multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the second multiplexed signal and the second multiplexed signal.
  • the turn-on sequence of the multiplexed signal of the sub-pixels in the odd-numbered row is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row is the first multiplexed signal and the first multiplexed signal.
  • Two-multiplexed signal is: the second multiplexed signal, the first multiplexed signal, and the turn-on sequence of the multiplexed signal of the sub-pixels in the even-numbered row.
  • N is 3, and the driving method includes:
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the first multiplexed signal, the second multiplexed signal, the third multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
  • the turn-on sequence is the third multiplexed signal, the second multiplexed signal, and the first multiplexed signal
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the second multiplexed signal, the third multiplexed signal, the first multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
  • the turn-on sequence is the first multiplexed signal, the third multiplexed signal, and the second multiplexed signal;
  • the turn-on sequence of the multiplexed signal of the odd-numbered row sub-pixels is: the third multiplexed signal, the first multiplexed signal, the second multiplexed signal, and the multiplexed signal of the even-numbered row sub-pixels
  • the turn-on sequence is the second multiplexed signal, the first multiplexed signal, and the third multiplexed signal, and M is a natural number greater than or equal to zero.
  • Some embodiments of the present disclosure also provide a display device, which includes a display panel.
  • the display device may be: OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, and any other product or component with display function, which is not limited in the embodiment of the present disclosure. .
  • the display panel is the display panel provided in the foregoing embodiment, and its implementation principles and effects are similar, and will not be repeated here.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示面板及其驱动方法、显示装置，显示面板包括：源极驱动电路、多路选择电路、阵列排布的多个子像素，多路选择电路被配置为：在第一复用信号至第N复用信号的控制下，控制源极驱动电路与一或多列子像素连通，且在第j帧时，第奇数行子像素的复用信号开启顺序为：第J复用信号顺序递增至第N复用信号、第一复用信号顺序递增至第(J-1)复用信号，第偶数行子像素的复用信号开启顺序与第奇数行子像素的复用信号开启顺序完全相反；j为大于或等于1的自然数，（I），％为取余运算符，N为大于1的自然数。本公开通过使不同帧间和不同行间的复用信号开启顺序相互互补，在降低功耗的同时，使得每子像素充电均匀，提高了显示面板的显示效果。

Description

显示面板及其驱动方法、显示装置
本申请要求于2020年4月21日提交中国专利局、申请号为2020103180726、发明名称为“一种显示面板及其驱动方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域，尤其涉及一种显示面板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)为主动发光显示器件，具有自发光、广视角、高对比度、较低耗电、极高反应速度等优点。随着显示技术的不断发展，OLED技术越来越多的应用于柔性显示装置中。
OLED按驱动方式可分为无源矩阵驱动有机发光二极管(Passive Matrix Driving OLED，PMOLED)和有源矩阵驱动有机发光二极管(Active Matrix Driving OLED，AMOLED)两种，由于AMOLED显示装置具有低制造成本、高应答速度、省电、可用于便携式设备的直流驱动、工作温度范围大等等优点，而有望成为取代液晶显示器(Liquid Crystal Display，LCD)的下一代新型平面显示器。
通过在源极驱动电路和数据线之间设置多路选择电路，可以减少数据线的数量，提高显示面板的分辨率。以1:2复用(MUX)为例，在一种多路选择电路中，按照每一行均为第一复用信号到第二复用信号的开启顺序逐行驱动子像素，这种驱动方式使得多路选择电路反复切换复用信号，增加了设备功耗；在另一种多路选择电路中，按照奇数行为第一复用信号到第二复用信号的开启顺序，偶数行为第二复用信号到第一复用信号的开启顺序逐行驱动子像素，这种驱动方式虽然减少了设备功耗，但是与其他行相比，第一行和最后一行的第一复用信号驱动的子像素充电时间较短，即第一行和最后一行 的部分子像素与其他行的子像素相比，充电时间不足，容易在第一行和最后一行的位置产生亮线。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示面板，包括：源极驱动电路、多路选择电路、阵列排布的多个子像素，所述多路选择电路被配置为：在第一复用信号至第N复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第j帧时，第奇数行子像素的复用信号开启顺序为：第J复用信号顺序递增至第N复用信号、第一复用信号顺序递增至第(J-1)复用信号，第偶数行子像素的复用信号开启顺序与第奇数行子像素的复用信号开启顺序完全相反；j为大于或等于1的自然数，
Figure PCTCN2021077575-appb-000001
％为取余运算符，N为大于1的自然数。
在一些可能的实现方式中，N为2；所述多路选择电路被配置为，在第一复用信号至第二复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第奇数帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号；在第偶数帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
在一些可能的实现方式中，所述多个子像素包括红色子像素、蓝色子像素和绿色子像素，每个子像素包括：显示元件和开关元件，所述开关元件包括：第一晶体管，第一晶体管的控制极与扫描线连接，第一晶体管的第一极与数据线连接，第一晶体管的第二极与显示元件连接，所述多路选择电路包括第一复用子电路和第二复用子电路，其中：
所述第一复用子电路包括2P个第二晶体管，第二晶体管的控制极和第一复用信号输入端连接，第二晶体管的第一极和源极驱动电路连接，第二晶 体管的第二极和红色子像素或蓝色子像素连接的数据线连接；
所述第二复用子电路包括P个第三晶体管，第三晶体管的控制极和第二复用信号输入端连接，第三晶体管的第一极和源极驱动电路连接，第三晶体管的第二极和绿色子像素连接的数据线连接，P为大于1的自然数。
在一些可能的实现方式中，所述显示元件为有机发光二极管。
在一些可能的实现方式中，N为3；所述多路选择电路被配置为，在第一复用信号至第三复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第(3M+1)帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号、第三复用信号，第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号；在第(3M+2)帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第三复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第三复用信号、第二复用信号；在第(3M+3)帧时，第奇数行子像素的复用信号开启顺序为：第三复用信号、第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号，M为大于或等于0的自然数。
在一些可能的实现方式中，所述多个子像素包括红色子像素、蓝色子像素和绿色子像素，每个子像素包括：显示元件和开关元件，所述开关元件包括：第一晶体管，所述第一晶体管的控制极与扫描线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与显示元件连接，所述多路选择电路包括第一复用子电路、第二复用子电路和第三复用子电路，其中：
所述第一复用子电路包括Q个第二晶体管，所述第二晶体管的控制极和第一复用信号输入端连接，所述第二晶体管的第一极和源极驱动电路连接，所述第二晶体管的第二极和红色子像素连接的数据线连接；
所述第二复用子电路包括Q个第三晶体管，所述第三晶体管的控制极和第二复用信号输入端连接，所述第三晶体管的第一极和源极驱动电路连接，所述第三晶体管的第二极和蓝色子像素连接的数据线连接；
所述第三复用子电路包括Q个第四晶体管，所述第四晶体管的控制极和 第三复用信号输入端连接，所述第四晶体管的第一极和源极驱动电路连接，所述第四晶体管的第二极和绿色子像素连接的数据线连接，Q为大于1的自然数。
本公开实施例还提供了一种显示装置，包括如前任一项所述的显示面板。
本公开实施例还提供了一种显示面板的驱动方法，所述显示面板包括：源极驱动电路、多路选择电路、阵列排布的多个子像素，所述驱动方法包括：在第一复用信号至第N复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第j帧时，第奇数行子像素的复用信号开启顺序为：第J复用信号顺序递增至第N复用信号、第一复用信号顺序递增至第(J-1)复用信号，第偶数行子像素的复用信号开启顺序与第奇数行子像素的复用信号开启顺序完全相反；j为大于或等于1的自然数，
Figure PCTCN2021077575-appb-000002
％为取余运算符，N为大于1的自然数。
在一些可能的实现方式中，N为2，所述驱动方法包括：
在第奇数帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号；
在第偶数帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
在一些可能的实现方式中，N为3，所述驱动方法包括：
在第(3M+1)帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号、第三复用信号，第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号；
在第(3M+2)帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第三复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第三复用信号、第二复用信号；
在第(3M+3)帧时，第奇数行子像素的复用信号开启顺序为：第三复用信 号、第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号，M为大于或等于0的自然数。
在阅读并理解了附图概述和本公开实施例的实施方式后，可以明白其他方面。
附图说明
附图用来提供对本公开实施例技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例的一种显示面板的结构示意图之一；
图2为本公开实施例的一种显示面板的结构示意图之二；
图3为图2所示显示面板在第奇数帧时的复用信号驱动时序示意图；
图4为图2所示显示面板在第偶数帧时的复用信号驱动时序示意图；
图5为本公开实施例的一种显示面板的结构示意图之三。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本领域技术人员可以理解，本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在一些示例性实施例中，本 公开实施例中使用的薄膜晶体管可以是氧化物半导体晶体管。由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为漏极或源极。
如图1所示，本公开实施例提供了一种显示面板，包括：源极驱动电路10、多路选择电路20、阵列排布的多个子像素30，多路选择电路20被配置为：在第一复用信号MUX(1)至第N复用信号MUXN的控制下，控制源极驱动电路10与一列或多列子像素30之间连通，且在第j帧时，第奇数行子像素30的复用信号开启顺序为：第J复用信号MUXJ顺序递增至第N复用信号MUXN、第一复用信号MUX(1)顺序递增至第(J-1)复用信号MUX(J-1)，第偶数行子像素30的复用信号开启顺序与第奇数行子像素30的复用信号开启顺序完全相反；j为大于或等于1的自然数，
Figure PCTCN2021077575-appb-000003
％为取余运算符，N为大于1的自然数。
本公开实施例提供的显示面板，通过在每一帧时，使第奇数行和第偶数行的复用信号的驱动顺序互补，并在不同帧间，使第一行和最后一行的复用信号的驱动顺序互补，在降低功耗的同时，使得每个子像素30充电时间均匀，消除了第一行和最后一行位置处的亮线，提高了显示面板的显示效果。
在一种示例性实施例中，每个子像素30包括：开关元件31和显示元件32，开关元件31包括：第一晶体管M1，第一晶体管M1的控制极与扫描线连接，第一晶体管M1的第一极与数据线连接，第一晶体管M1的第二极与显示元件32连接。
在一种实施例中，多个子像素30可以包括红色子像素、绿色子像素和蓝色子像素。在其他实施例中，多个子像素30也可以包括4种或其他任意多种颜色的子像素。例如，多个子像素30可以包括红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一种示例性实施例中，显示元件32可以为有机发光二极管或其他类型的发光二极管等。在实际应用中，显示元件32的结构可以根据实际应用环境来设计确定，在此不作限定。
本公开实施例中，显示面板包括：显示区域和非显示区域，扫描线、数据线和子像素位于显示区域，多路选择电路和源极驱动电路位于显示面板的非显示区域。
在一种示例性实施例中，N为2；多路选择电路20被配置为，在第一复用信号MUX(1)至第二复用信号MUX(2)的控制下，控制源极驱动电路10与一列或多列子像素30之间连通，且在第奇数帧时，第奇数行子像素30的复用信号开启顺序为：第一复用信号MUX(1)、第二复用信号MUX(2)，第偶数行子像素30的复用信号开启顺序为第二复用信号MUX(2)、第一复用信号MUX(1)；在第偶数帧时，第奇数行子像素30的复用信号开启顺序为：第二复用信号MUX(2)、第一复用信号MUX(1)，第偶数行子像素30的复用信号开启顺序为第一复用信号MUX(1)、第二复用信号MUX(2)。
在一种示例性实施例中，如图2所示，多路选择电路20包括第一复用子电路和第二复用子电路。
第一复用子电路包括2P个第二晶体管M2，第二晶体管M2的控制极和第一复用信号输入端MUX1连接，第二晶体管M2的第一极和源极驱动电路10连接，第二晶体管M2的第二极和红色子像素或蓝色子像素连接的数据线连接。
第二复用子电路包括P个第三晶体管M3，第三晶体管M3的控制极和第二复用信号输入端MUX2连接，第三晶体管M3的第一极和源极驱动电路10连接，第三晶体管M3的第二极和绿色子像素连接的数据线连接，P为大于1的自然数。
在另一些实施例中，第二晶体管M2的第二极也可以和红色子像素或绿色子像素连接的数据线连接，第三晶体管M3的第二极也可以和蓝色子像素连接的数据线连接；或者，第二晶体管M2的第二极也可以和蓝色子像素或绿色子像素连接的数据线连接，第三晶体管M3的第二极也可以和红色子像素连接的数据线连接；在实际应用中，第二晶体管M2和第三晶体管M3的结构可以根据实际应用环境来设计确定，在此不作限定。
在本实施例中，晶体管M1至M3均可以为N型薄膜晶体管或P型薄膜晶体管，晶体管M1至M3设置为相同类型的薄膜晶体管，可以统一工艺流 程，进而减少工艺制程，有助于提高产品的良率。此外，在一些实施例中，考虑到低温多晶硅薄膜晶体管的漏电流较小，因此，本公开实施例所有晶体管可以为低温多晶硅薄膜晶体管，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。
图3为图2所示显示面板在第奇数帧时的复用信号驱动时序示意图，图4为图2所示显示面板在第偶数帧时的复用信号驱动时序示意图。下面结合图2所示的显示面板和图3、图4所示的复用信号驱动时序图，对该显示面板的工作过程进行描述。以晶体管M1至M3均为P型薄膜晶体管为例，当栅极端的电位变低时，P型薄膜晶体管导通，当栅极端的电位变高时，P型薄膜晶体管截止，其工作过程包括：
第奇数帧阶段，即第一帧、第三帧、第五帧……阶段，如图3所示，每个移位寄存器单元产生一个扫描信号，并输出至扫描线；此时，第奇数行子像素30的复用信号开启顺序为：第一复用信号MUX(1)、第二复用信号MUX(2)，即，第奇数行子像素30的驱动顺序为先驱动红色子像素和蓝色子像素、再驱动绿色子像素，第偶数行子像素30的复用信号开启顺序为第二复用信号MUX(2)、第一复用信号MUX(1)，即，第偶数行子像素30的驱动顺序为先驱动绿色子像素、再驱动红色子像素和蓝色子像素，源极驱动电路10产生对应的数据电压信号，并在第一复用信号MUX(1)和第二复用信号MUX(2)的控制下，通过数据线将数据电压信号输出至对应的子像素30。
第偶数帧阶段，即第二帧、第四帧、第六帧……阶段，如图4所示，每个移位寄存器单元产生一个扫描信号，并输出至扫描线；此时，第奇数行子像素30的复用信号开启顺序为：第二复用信号MUX(2)、第一复用信号MUX(1)，即，第奇数行子像素30的驱动顺序为先驱动绿色子像素、再驱动红色子像素和蓝色子像素，第偶数行子像素30的复用信号开启顺序为第一复用信号MUX(1)、第二复用信号MUX(2)，即，第偶数行子像素30的驱动顺序为先驱动红色子像素和蓝色子像素、再驱动绿色子像素，源极驱动电路10产生对应的数据电压信号，并在第一复用信号MUX(1)和第二复用信号MUX(2)的控制下，通过数据线将数据电压信号输出至对应的子像素30。
从上述工作过程可以看出，在第奇数帧阶段，复用信号开启顺序为：第 一复用信号MUX(1)、第二复用信号MUX(2)、第二复用信号MUX(2)、第一复用信号MUX(1)、第一复用信号MUX(1)、第二复用信号MUX(2)、第二复用信号MUX(2)、第一复用信号MUX(1)，简写为1221122112211221……；在第偶数帧阶段，复用信号开启顺序为：第二复用信号MUX(2)、第一复用信号MUX(1)、第一复用信号MUX(1)、第二复用信号MUX(2)、第二复用信号MUX(2)、第一复用信号MUX(1)、第一复用信号MUX(1)、第二复用信号MUX(2)，简写为2112211221122112……。由此可以看出，本实施例通过在奇数帧和偶数帧、奇数行和偶数行间采用完全相反的时序开启复用信号，保证了不同的复用信号之间相同的开启时间，从而保证了每个子像素30充电时间均匀，奇偶时序交替控制，边缘像素发光效率相互补偿，改善了模组的显示效果。
在另一种示例性实施例中，N为3。
多路选择电路20被配置为，在第一复用信号MUX(1)至第三复用信号MUX(3)的控制下，控制源极驱动电路10与一列或多列子像素30之间连通，且在第(3M+1)帧时，第奇数行子像素30的复用信号开启顺序为：第一复用信号MUX(1)、第二复用信号MUX(2)、第三复用信号MUX(3)，第偶数行子像素30的复用信号开启顺序为第三复用信号MUX(3)、第二复用信号MUX(2)、第一复用信号MUX(1)；在第(3M+2)帧时，第奇数行子像素30的复用信号开启顺序为：第二复用信号MUX(2)、第三复用信号MUX(3)、第一复用信号MUX(1)，第偶数行子像素30的复用信号开启顺序为第一复用信号MUX(1)、第三复用信号MUX(3)、第二复用信号MUX(2)；在第(3M+3)帧时，第奇数行子像素30的复用信号开启顺序为：第三复用信号MUX(3)、第一复用信号MUX(1)、第二复用信号MUX(2)，第偶数行子像素30的复用信号开启顺序为第二复用信号MUX(2)、第一复用信号MUX(1)、第三复用信号MUX(3)，M为大于或等于0的自然数。
在一种示例性实施例中，如图5所示，多路选择电路20包括第一复用子电路、第二复用子电路和第三复用子电路。
第一复用子电路包括Q个第二晶体管M2，第二晶体管M2的控制极和第一复用信号输入端MUX1连接，第二晶体管M2的第一极和源极驱动电路 10连接，第二晶体管M2的第二极和红色子像素连接的数据线连接；
第二复用子电路包括Q个第三晶体管M3，第三晶体管M3的控制极和第二复用信号输入端MUX2连接，第三晶体管M3的第一极和源极驱动电路10连接，第三晶体管M3的第二极和蓝色子像素连接的数据线连接；
第三复用子电路包括Q个第四晶体管M4，第四晶体管M4的控制极和第三复用信号输入端MUX3连接，第四晶体管M4的第一极和源极驱动电路10连接，第四晶体管M4的第二极和绿色子像素连接的数据线连接，Q为大于1的自然数。
在本实施例中，晶体管M1至M4均可以为N型薄膜晶体管或P型薄膜晶体管，晶体管M1至M4设置为相同类型的薄膜晶体管，可以统一工艺流程，进而减少工艺制程，有助于提高产品的良率。此外，在一些示例性实施例中，考虑到低温多晶硅薄膜晶体管的漏电流较小，因此，本公开实施例的所有晶体管可以为低温多晶硅薄膜晶体管，薄膜晶体管可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。
N为3时显示面板的工作过程可以按照前述N＝2时的工作过程类推，此处不再赘述。在N＝3时，在第(3M+1)帧阶段，复用信号开启顺序为：第一复用信号MUX(1)、第二复用信号MUX(2)、第三复用信号MUX(3)、第三复用信号MUX(3)、第二复用信号MUX(2)、第一复用信号MUX(1)、第一复用信号MUX(1)、第二复用信号MUX(2)、第三复用信号MUX(3)、第三复用信号MUX(3)、第二复用信号MUX(2)、第一复用信号MUX(1)……，简写为123321123321123321123321……；在第(3M+2)帧阶段，复用信号开启顺序为：第二复用信号MUX(2)、第三复用信号MUX(3)、第一复用信号MUX(1)、第一复用信号MUX(1)、第三复用信号MUX(3)、第二复用信号MUX(2)、第二复用信号MUX(2)、第三复用信号MUX(3)、第一复用信号MUX(1)、第一复用信号MUX(1)、第三复用信号MUX(3)、第二复用信号MUX(2)……，简写为231132231132231132231132……；在第(3M+3)帧阶段，复用信号开启顺序为：第三复用信号MUX(3)、第一复用信号MUX(1)、第二复用信号MUX(2)、第二复用信号MUX(2)、第一复用信号MUX(1)、第三复用信号MUX(3)、第三复用信号MUX(3)、第一复用信号MUX(1)、第二复用信号MUX(2)、第二 复用信号MUX(2)、第一复用信号MUX(1)、第三复用信号MUX(3)……，简写为312213312213312213312213……。由此可以看出，本实施例通过在第(3M+1)帧、第(3M+2)帧、第(3M+3)帧之间、奇数行和偶数行之间采用完全相反的时序开启复用信号，保证了不同的复用信号之间相同的开启时间，从而保证了每个子像素30充电时间均匀，奇偶时序交替控制，边缘像素发光效率相互补偿，改善了模组的显示效果。
本公开实施例还提供了一种显示面板的驱动方法，该显示面板包括：源极驱动电路、多路选择电路、阵列排布的多个子像素，该驱动方法包括：
在第一复用信号至第N复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第j帧时，第奇数行子像素的复用信号开启顺序为：第J复用信号顺序递增至第N复用信号、第一复用信号顺序递增至第(J-1)复用信号，第偶数行子像素的复用信号开启顺序与第奇数行子像素的复用信号开启顺序完全相反；j为大于或等于1的自然数，
Figure PCTCN2021077575-appb-000004
％为取余运算符，N为大于1的自然数。
在一种示例性实施例中，N为2，该驱动方法包括：
在第奇数帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号；
在第偶数帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
在一种示例性实施例中，N为3，该驱动方法包括：
在第(3M+1)帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号、第三复用信号，第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号；
在第(3M+2)帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第三复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为 第一复用信号、第三复用信号、第二复用信号；
在第(3M+3)帧时，第奇数行子像素的复用信号开启顺序为：第三复用信号、第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号，M为大于或等于0的自然数。
本公开一些实施例还提供了一种显示装置，该显示装置包括：显示面板。
可选地，该显示装置可以为：OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例对此不作任何限定。
其中，显示面板为前述实施例提供的显示面板，其实现原理和实现效果类似，在此不再赘述。
有以下几点需要说明：
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种显示面板，包括：源极驱动电路、多路选择电路、阵列排布的多个子像素，其中：
    所述多路选择电路被配置为：在第一复用信号至第N复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第j帧时，第奇数行子像素的复用信号开启顺序为：第J复用信号顺序递增至第N复用信号、第一复用信号顺序递增至第(J-1)复用信号，第偶数行子像素的复用信号开启顺序与第奇数行子像素的复用信号开启顺序完全相反；j为大于或等于1的自然数，
    Figure PCTCN2021077575-appb-100001
    ％为取余运算符，N为大于1的自然数。
  2. 根据权利要求1所述的显示面板，其中，N为2；
    所述多路选择电路被配置为，在第一复用信号至第二复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第奇数帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号；在第偶数帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
  3. 根据权利要求2所述的显示面板，其中，所述多个子像素包括红色子像素、蓝色子像素和绿色子像素，每个子像素包括：显示元件和开关元件，所述开关元件包括：第一晶体管，第一晶体管的控制极与扫描线连接，第一晶体管的第一极与数据线连接，第一晶体管的第二极与显示元件连接，所述多路选择电路包括第一复用子电路和第二复用子电路，其中：
    所述第一复用子电路包括2P个第二晶体管，第二晶体管的控制极和第一复用信号输入端连接，第二晶体管的第一极和源极驱动电路连接，第二晶体管的第二极和红色子像素或蓝色子像素连接的数据线连接；
    所述第二复用子电路包括P个第三晶体管，第三晶体管的控制极和第二复用信号输入端连接，第三晶体管的第一极和源极驱动电路连接，第三晶体 管的第二极和绿色子像素连接的数据线连接，P为大于1的自然数。
  4. 根据权利要求3所述的显示面板，其中，所述显示元件为有机发光二极管。
  5. 根据权利要求1所述的显示面板，其中，N为3；
    所述多路选择电路被配置为，在第一复用信号至第三复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第(3M+1)帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号、第三复用信号，第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号；在第(3M+2)帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第三复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第三复用信号、第二复用信号；在第(3M+3)帧时，第奇数行子像素的复用信号开启顺序为：第三复用信号、第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号，M为大于或等于0的自然数。
  6. 根据权利要求5所述的显示面板，所述多个子像素包括红色子像素、蓝色子像素和绿色子像素，每个子像素包括：显示元件和开关元件，所述开关元件包括：第一晶体管，所述第一晶体管的控制极与扫描线连接，所述第一晶体管的第一极与数据线连接，所述第一晶体管的第二极与显示元件连接，所述多路选择电路包括第一复用子电路、第二复用子电路和第三复用子电路，其中：
    所述第一复用子电路包括Q个第二晶体管，所述第二晶体管的控制极和第一复用信号输入端连接，所述第二晶体管的第一极和源极驱动电路连接，所述第二晶体管的第二极和红色子像素连接的数据线连接；
    所述第二复用子电路包括Q个第三晶体管，所述第三晶体管的控制极和第二复用信号输入端连接，所述第三晶体管的第一极和源极驱动电路连接，所述第三晶体管的第二极和蓝色子像素连接的数据线连接；
    所述第三复用子电路包括Q个第四晶体管，所述第四晶体管的控制极和 第三复用信号输入端连接，所述第四晶体管的第一极和源极驱动电路连接，所述第四晶体管的第二极和绿色子像素连接的数据线连接，Q为大于1的自然数。
  7. 一种显示装置，包括如权利要求1至权利要求6任一所述的显示面板。
  8. 一种显示面板的驱动方法，所述显示面板包括：源极驱动电路、多路选择电路、阵列排布的多个子像素，所述驱动方法包括：
    在第一复用信号至第N复用信号的控制下，控制源极驱动电路与一列或多列子像素之间连通，且在第j帧时，第奇数行子像素的复用信号开启顺序为：第J复用信号顺序递增至第N复用信号、第一复用信号顺序递增至第(J-1)复用信号，第偶数行子像素的复用信号开启顺序与第奇数行子像素的复用信号开启顺序完全相反；j为大于或等于1的自然数，
    Figure PCTCN2021077575-appb-100002
    ％为取余运算符，N为大于1的自然数。
  9. 根据权利要求8所述的驱动方法，其中，N为2，所述驱动方法包括：
    在第奇数帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号；
    在第偶数帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第二复用信号。
  10. 根据权利要求8所述的驱动方法，N为3，所述驱动方法包括：
    在第(3M+1)帧时，第奇数行子像素的复用信号开启顺序为：第一复用信号、第二复用信号、第三复用信号，第偶数行子像素的复用信号开启顺序为第三复用信号、第二复用信号、第一复用信号；
    在第(3M+2)帧时，第奇数行子像素的复用信号开启顺序为：第二复用信号、第三复用信号、第一复用信号，第偶数行子像素的复用信号开启顺序为第一复用信号、第三复用信号、第二复用信号；
    在第(3M+3)帧时，第奇数行子像素的复用信号开启顺序为：第三复用信号、第一复用信号、第二复用信号，第偶数行子像素的复用信号开启顺序为第二复用信号、第一复用信号、第三复用信号，M为大于或等于0的自然数。
PCT/CN2021/077575 2020-04-21 2021-02-24 显示面板及其驱动方法、显示装置 WO2021212997A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/435,028 US11741905B2 (en) 2020-04-21 2021-02-24 Display panel, driving method for same, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010318072.6 2020-04-21
CN202010318072.6A CN111477180B (zh) 2020-04-21 2020-04-21 一种显示面板及其驱动方法、显示装置

Publications (1)

Publication Number Publication Date
WO2021212997A1 true WO2021212997A1 (zh) 2021-10-28

Family

ID=71756092

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/077575 WO2021212997A1 (zh) 2020-04-21 2021-02-24 显示面板及其驱动方法、显示装置

Country Status (3)

Country Link
US (1) US11741905B2 (zh)
CN (1) CN111477180B (zh)
WO (1) WO2021212997A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111477180B (zh) * 2020-04-21 2024-04-12 京东方科技集团股份有限公司 一种显示面板及其驱动方法、显示装置
CN114664224A (zh) * 2022-03-31 2022-06-24 合肥京东方光电科技有限公司 一种显示面板及显示设备

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101739935A (zh) * 2008-11-25 2010-06-16 精工爱普生株式会社 电光装置的驱动装置和方法、电光装置及电子设备
CN106383624A (zh) * 2016-10-26 2017-02-08 厦门天马微电子有限公司 一种阵列基板、显示面板及其驱动方法和显示装置
CN106842657A (zh) * 2017-03-27 2017-06-13 武汉华星光电技术有限公司 一种液晶面板驱动电路及液晶显示装置
CN108335663A (zh) * 2018-05-14 2018-07-27 京东方科技集团股份有限公司 显示面板的驱动方法及显示面板、显示装置
CN109346021A (zh) * 2018-11-28 2019-02-15 武汉华星光电技术有限公司 显示面板的驱动方法
US20190147798A1 (en) * 2017-11-14 2019-05-16 Samsung Display Co., Ltd. Display device
CN109884833A (zh) * 2019-05-09 2019-06-14 南京中电熊猫平板显示科技有限公司 一种多路分用电路、液晶显示装置以及像素补偿方法
US20190251908A1 (en) * 2018-02-12 2019-08-15 Samsung Display Co., Ltd. Display device
CN111477180A (zh) * 2020-04-21 2020-07-31 京东方科技集团股份有限公司 一种显示面板及其驱动方法、显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100367010B1 (ko) * 2000-06-08 2003-01-09 엘지.필립스 엘시디 주식회사 액정표시장치 및 그 구동방법
JP2006030529A (ja) * 2004-07-15 2006-02-02 Seiko Epson Corp 電気光学装置用駆動回路及び電気光学装置用駆動方法、並びに電気光学装置及び電子機器
JP5754182B2 (ja) * 2011-03-10 2015-07-29 セイコーエプソン株式会社 駆動用集積回路および電子機器
KR102071566B1 (ko) * 2013-02-27 2020-03-03 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 구동 방법
KR102063130B1 (ko) * 2013-04-16 2020-01-08 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102118096B1 (ko) * 2013-12-09 2020-06-02 엘지디스플레이 주식회사 액정표시장치
KR102275693B1 (ko) * 2014-12-22 2021-07-09 엘지디스플레이 주식회사 선택회로 및 이를 구비한 표시장치
KR102509164B1 (ko) * 2016-09-29 2023-03-13 엘지디스플레이 주식회사 표시장치 및 그를 이용한 서브픽셀 트랜지션 방법
US10360869B2 (en) 2017-03-27 2019-07-23 Wuhan China Star Optoelectronics Technology Co., Ltd. Liquid crystal panel driving circuit and liquid crystal display device
CN107993629B (zh) * 2018-01-31 2020-05-29 武汉华星光电技术有限公司 液晶显示装置的驱动方法
US10748495B2 (en) * 2018-04-12 2020-08-18 Wuhan China Star Optoelectronics Technology Co., Ltd. Pixel driving circuit and liquid crystal display circuit with the same
CN108648680A (zh) * 2018-06-25 2018-10-12 厦门天马微电子有限公司 一种显示面板、其驱动方法、驱动装置及显示装置
US10789894B2 (en) 2018-11-28 2020-09-29 Wuhan China Star Optoelectronics Technology Co., Ltd. Drive method for display panel

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101739935A (zh) * 2008-11-25 2010-06-16 精工爱普生株式会社 电光装置的驱动装置和方法、电光装置及电子设备
CN106383624A (zh) * 2016-10-26 2017-02-08 厦门天马微电子有限公司 一种阵列基板、显示面板及其驱动方法和显示装置
CN106842657A (zh) * 2017-03-27 2017-06-13 武汉华星光电技术有限公司 一种液晶面板驱动电路及液晶显示装置
US20190147798A1 (en) * 2017-11-14 2019-05-16 Samsung Display Co., Ltd. Display device
US20190251908A1 (en) * 2018-02-12 2019-08-15 Samsung Display Co., Ltd. Display device
CN108335663A (zh) * 2018-05-14 2018-07-27 京东方科技集团股份有限公司 显示面板的驱动方法及显示面板、显示装置
CN109346021A (zh) * 2018-11-28 2019-02-15 武汉华星光电技术有限公司 显示面板的驱动方法
CN109884833A (zh) * 2019-05-09 2019-06-14 南京中电熊猫平板显示科技有限公司 一种多路分用电路、液晶显示装置以及像素补偿方法
CN111477180A (zh) * 2020-04-21 2020-07-31 京东方科技集团股份有限公司 一种显示面板及其驱动方法、显示装置

Also Published As

Publication number Publication date
US20220328009A1 (en) 2022-10-13
CN111477180B (zh) 2024-04-12
US11741905B2 (en) 2023-08-29
CN111477180A (zh) 2020-07-31

Similar Documents

Publication Publication Date Title
CN110178174B (zh) 一种栅极驱动电路及其控制方法、移动终端
CN108399895B (zh) 显示面板及其驱动方法、显示装置
CN107154239B (zh) 一种像素电路、驱动方法、有机发光显示面板及显示装置
EP3869491A1 (en) Array substrate, driving method, organic light emitting display panel and display device
CN110136630B (zh) 一种显示面板及其驱动方法、显示装置
WO2016050015A1 (zh) 有机电致发光显示器件、其驱动方法及显示装置
WO2017053477A1 (en) Hybrid micro-driver architectures having time multiplexing for driving displays
EP3783592A1 (en) Display panel and driving method therefor, and display device
CN110955091B (zh) 一种显示面板及其驱动方法、显示装置
US20140035965A1 (en) Display panel, display apparatus, and electronic system
US11450270B2 (en) Pixel circuit and method of driving the same, display device
US9286833B2 (en) Buffer circuit, scanning circuit, display device, and electronic equipment
CN113192551B (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
US9035936B2 (en) Level shifter circuit, scanning circuit, display device and electronic equipment
US20120139965A1 (en) Organic light emitting diode display and method for driving display panel thereof
WO2020238490A1 (zh) 像素电路、显示基板、显示装置及驱动方法
WO2021212997A1 (zh) 显示面板及其驱动方法、显示装置
WO2021023201A1 (zh) 像素阵列、阵列基板及显示装置
CN114758624A (zh) 像素电路及其驱动方法、阵列基板、显示面板和显示装置
CN113178221A (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2024088027A1 (zh) 显示基板及其驱动方法、显示装置
US20180330685A1 (en) Shift register and driving method therefor, gate driving circuit and display apparatus
US20240005872A1 (en) Pixel array and display panel
KR102554380B1 (ko) 전계발광표시장치
CN110136672B (zh) 一种显示面板、其驱动方法及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21793200

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21793200

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 15.05.2023)

122 Ep: pct application non-entry in european phase

Ref document number: 21793200

Country of ref document: EP

Kind code of ref document: A1