WO2021212770A1 - Fpga-based mac address management apparatus and method for ethernet switch - Google Patents

Abstract

Disclosed is an FPGA-based MAC address management method for an Ethernet switch. The method comprises the following steps: S01, a receiving module receiving an Ethernet data packet and transmitting same to a MAC extraction module; S02, the MAC extraction module extracting a MAC address from the Ethernet data packet and transmitting same to a MAC address translation module; S03, the MAC address translation module translating the MAC address into a read address of a RAM module and transmitting the read address to the RAM module; S04, the RAM module determining, according to the read address of the RAM module, a network port to be transmitted and transmitting same to a sending module; and S05, the sending module sending the Ethernet data packet to the corresponding network port. By means of the FPGA-based MAC address management apparatus and method for an Ethernet switch provided in the present invention, the forwarding efficiency of Ethernet data is improved, and the present invention has the advantages of a fast response and a high processing speed.

Description

FPGA-based MAC address management device and method of Ethernet switch

cross reference

This application claims the priority of the Chinese patent application with the application number CN202010321634.2 filed on April 22, 2020. The content of the above application is included here by reference.

Technical field

The present invention relates to the field of communication technology, in particular to an FPGA-based MAC address management device and method of an Ethernet switch.

technical background

In a computer network, the data link layer completes the node-to-node communication, and the Layer 2 Ethernet switch is a data link layer device. The MAC (Media Access Control) address is an identifier used to identify the host in network communications. There is a MAC address table in the cache of the switch. When data needs to be forwarded, the switch will inquire whether there is an entry corresponding to the destination MAC address in the address table. If there is, the switch will immediately send the data packet to the forwarding port of the entry ; If not, the switch will broadcast the data message to all ports except the receiving port, and try its best to ensure that the destination host receives the data message. Therefore, the construction and maintenance of the switch address table determines the direction and efficiency of data forwarding.

In the prior art, MAC layer address table storage and lookup are mostly based on hash tables. Hashing is a technology used to insert, delete, and search in the average time of Changshu. The hash table accesses records by mapping the key code value to a position in the table. This mapping function is called the hashing function, and the array that stores the records is called the hash table. The switch address table stores a subset of all MAC addresses, so address conflicts will inevitably occur.

The capacity of the MAC address table is limited, so the switch uses an aging mechanism to maintain the MAC address table to ensure maximum utilization of address table entry resources. When the switch constructs an entry, it will start the aging timer of the entry accordingly. If the switch never receives the MAC address of the entry within the aging time, the switch will use the entry If deleted, invalid entries will not continue to occupy MAC address table resources. In this way, even if the equipment in the network is replaced or removed, the MAC address table of the switch can always keep the latest topology record in the network. A proper aging time can improve the utilization of MAC address table entry resources, but too long or too short aging time will affect the performance of the switch. If the aging time is too long, too many MAC address entries saved in the switch will consume the address table resources, and topology changes in the network cannot be updated in time; if the aging time is too short, valid MAC address entries will be It is deleted prematurely by the switch, thereby reducing the forwarding efficiency of the switch.

The traditional MAC address table processing mechanism is mainly implemented in software. As the speed of the Ethernet link interface develops from 1Gb/s to 10Gb/s, software-based algorithms are restricted in speed by serial computer systems.

After the emergence of a new generation of field programmable gate array (FPGA), the algorithm was described by a hard circuit. All the delays only come from the gate circuit, and the delay of the general gate circuit is in the ns level. The number of clock cycles required for system operation is reduced, and a truly high rate is achieved.

It can be seen that how to quickly find the MAC address, improve the forwarding efficiency, and filter unnecessary Ethernet packets to maintain the reliability of network communication are technical problems existing in the current prior art.

Summary of the invention

The purpose of the present invention is to provide an FPGA-based MAC address management device and method for an Ethernet switch, which improves the forwarding efficiency of Ethernet data, and has the advantages of fast response and high processing speed.

In order to achieve the above objective, the present invention adopts the following technical solution: a method for managing MAC addresses of an FPGA-based Ethernet switch, including the following steps:

S01: The receiving module receives the Ethernet data packet and transmits it to the MAC extraction module;

S02: The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module;

S03: The MAC address conversion module converts the MAC address to the RAM module read address and transmits it to the RAM module;

S04: The RAM module determines the network port to be transmitted according to the read address of the RAM module, and transmits it to the sending module;

S05: The sending module sends the Ethernet data packet to the corresponding network port.

Further, the receiving module, the MAC extraction module, the MAC address conversion module, the RAM module and the sending module are all located in the FPGA chip.

Further, the MAC address is composed of M bytes of data, and M is an integer greater than zero.

Further, in the step S03, the MAC address conversion module converts the M-byte MAC address into an N-bit RAM module read address, and N is an integer greater than zero.

Further, the storage depth of the RAM module is 2 ^N.

Further, in the step S04, the RAM module outputs an X-bit port data according to the RAM module read address, each bit in the port data represents a corresponding network port to be transmitted, and there is only one X-bit port data in the X-bit port data. The bit data is high level, and the remaining X-1 bit port data is low level.

Further, the MAC address is composed of 6 bytes of data, the read address of the RAM module is 11 bits, the storage depth of the RAM module is 2048, and the port data is 32 bits.

Further, in the step S03, the MAC address conversion module extracts 11 bits from the last 3 bytes of the MAC address as the RAM module read address, and the first 3 bytes of the MAC address are fixed bytes.

An FPGA-based MAC address management device for an Ethernet switch includes an FPGA chip. The FPGA chip includes a receiving module, a MAC extracting module, a MAC address conversion module, a RAM module, and a sending module. The receiving module is used to receive Ethernet Network data packet, the output terminal of the receiving module is connected to the input terminal of the MAC extraction module and the input terminal of the sending module at the same time, the output terminal of the MAC extraction module is connected to the input terminal of the MAC address conversion module, and the address The output terminal of the conversion module is connected to the input terminal of the RAM module, the output terminal of the RAM module is connected to the input terminal of the sending module, and the sending module determines the sending port and sends the Ethernet data packet;

The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module to convert it to the RAM module read address. The RAM module determines the network port to be transmitted according to the RAM module read address and transmits it to the sending module , The sending module sends the Ethernet data packet to the corresponding network port.

The present invention has the following beneficial effects: the present invention does not need to perform aging and other processing on the MAC address table like a switch, so a certain forwarding efficiency can be improved; the present invention uses FPGA to process data and has the advantages of fast response and high speed.

Description of the drawings

Figure 1 is a schematic diagram of the structure of the MAC address management device of the present invention.

Summary of the invention

The content of the present invention will be further described in detail below in conjunction with the accompanying drawings of the specification. It should be understood that the present invention can have various changes in different examples, which do not depart from the scope of the present invention, and the descriptions and diagrams therein are essentially for illustrative purposes, rather than limiting the present invention. It should be noted that the drawings all adopt a very simplified form and all use imprecise ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

As shown in Figure 1, the invention provides an FPGA-based MAC address management device for an Ethernet switch, including an FPGA chip. The FPGA chip includes a receiving module, a MAC extraction module, a MAC address conversion module, a RAM module, and a sending module. , The receiving module is connected to computer equipment for receiving Ethernet data packets. The output of the receiving module is connected to the input of the MAC extraction module and the input of the sending module at the same time. The output of the MAC extraction module is connected to the input of the MAC address conversion module. The output terminal of the address conversion module is connected to the input terminal of the RAM module, and the output terminal of the RAM module is connected to the input terminal of the sending module. The sending module determines the sending port and sends the Ethernet data packet to the computer device. The FPGA chip in the present invention is used to realize the function of MAC address management in the switch. The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module to convert it into a RAM module read address. The RAM module is based on the RAM module The read address determines the network port to be transmitted, and transmits it to the sending module, and the sending module sends the Ethernet data packet to the corresponding network port.

In the present invention, random access memory (RAM) is used in the RAM module, which is an internal memory that directly exchanges data with the CPU. It can be read and written at any time and has a very fast speed. It is usually used as an operating system or other operating systems. Temporary data storage medium for the program.

The invention provides an FPGA-based MAC address management method for an Ethernet switch, which includes the following steps:

S01: The receiving module receives the Ethernet data packet, buffers the Ethernet data packet, and transmits it to the MAC extraction module;

S02: The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module; the MAC address is composed of M bytes of data, and M is an integer greater than 0, for example, it can be 6 bytes of data The first three bytes of data data0, data1, and data2 are fixed to a fixed value (configurable by software), and the last three bytes of data are used to indicate the network port corresponding to the MAC address.

S03: The MAC address conversion module converts the MAC address to the RAM module read address and transmits it to the RAM module; the MAC address conversion module converts the M-byte MAC address to the N-bit RAM module read address, where N is an integer greater than 0, The storage depth of the RAM module is 2 ^N. For example, when the MAC address is 6-character data, some information in the last three characters of the MAC address can be extracted and converted into an 11-bit RAM module read address.

S04: The RAM module determines the network port to be transmitted according to the read address of the RAM module, and transmits it to the sending module; the RAM module outputs an X-bit port data according to the read address of the RAM module, and each bit in the port data represents the corresponding to be transmitted For network ports, only one bit of X-bit port data is high, and the remaining X-1 bit port data is low.

In the present invention, a random access memory (RAM) is used in the RAM module, which is an internal memory that directly exchanges data with the CPU. It can read and write at any time and is fast. It is usually used as an operating system or other operating systems. Temporary data storage medium of the program. When the RAM module read address is N-bit data, set the RAM module to a storage depth of 2 ^N (that is, the depth that can be addressed by the N-bit RAM module read address), and the data width is X bits After receiving the N-bit RAM module read address converted by the MAC address conversion module, it will output an X-bit port data. Each bit in the port data represents the corresponding network port to be transmitted. Only the X-bit port data One bit of data is high level, and the remaining X-1 bit port data is low level. The network port corresponding to the bit of high level is the network port specified in the MAC address.

S05: The sending module sends the Ethernet data packet to the corresponding network port. Note: The Ethernet data packet is directly transmitted from the receiving module to the sending module. The sending module uses the extracted network port information as arbitration judgment information to arbitrate which network port the currently received Ethernet packet should be forwarded to.

Example 1

The invention provides an FPGA-based MAC address management method for an Ethernet switch, which includes the following steps:

S01: The receiving module receives the Ethernet data packet, buffers the Ethernet data packet, and transmits it to the MAC extraction module;

S02: The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module; as shown in Table 1, the MAC address is composed of 6 bytes of data, and the first 3 bytes are fixed to a fixed value. Data0 is fixed to 0x00, data1 is fixed to 0x0f, data2 is fixed to 0xe2, and the last three bytes are used to indicate the network port corresponding to the MAC address.

Table 1: Schematic table of MAC address conversion module conversion

Data field	Date0	Date1	Date2	Date3	Date4	Date5
Value	0x00	0x0f	0xe2	xx	xx	xx
illustrate	Fixed value	Fixed value	Fixed value	Bit0～1	Bit0～6	Bit0～1

S03: The MAC address conversion module converts the MAC address to the RAM module read address and transmits it to the RAM module; as shown in Table 1, the MAC address conversion module converts the 6-byte MAC address into an 11-bit RAM module read address, and converts it The rule is shown in Figure 3. The 11-bit RAM module read address is composed of the lower two bits of data3 plus the lower 7 bits of data4 plus the lower 2 bits of data5.

S04: The RAM module determines the network port to be transmitted according to the read address of the RAM module, and transmits it to the sending module; the RAM module contains RAM, and its storage depth is 2048 (that is, the depth that can be addressed by the 11-bit RAM module read address), The data width is 32 bits. After receiving the 11-bit RAM module read address converted by the MAC address conversion module, a 32-bit port data will be output. Each bit of this value represents the network port that needs to be forwarded.

In the present invention, random access memory (RAM) is used in the RAM module, which is an internal memory that directly exchanges data with the CPU. It can be read and written at any time and has a very fast speed. It is usually used as an operating system or other operating systems. The temporary data storage medium of the program, as shown in Table 2, when the RAM module reads the 11-bit data, set the RAM module to the storage depth of 2048 (that is, the depth that the 11-bit address can address, Addr0-Addr2047 ), the data width is 32 bits, after receiving the 11-bit RAM module read address converted by the MAC address conversion module, a 32-bit port data Port0-Port31 will be output, each bit in the port data represents the corresponding to be transmitted For the network port, only one bit of the 32-bit port data is high level, and the remaining 31-bit port data is low level. The network port corresponding to the bit where the high level is located is the network port specified in the MAC address. Each bit in the port data represents the corresponding network port to be transmitted. Only one bit of the 32-bit port data is high level, the remaining 31-bit port data is low level, and the bit where the high level is located corresponds to the network port It is the network port specified in the MAC address.

Table 2: Schematic diagram of the address space of the RAM module

S05: The sending module sends the Ethernet data packet to the corresponding network port.

The invention does not need to perform aging and other processing on the MAC address table like a switch, so a certain forwarding efficiency can be improved; the invention uses FPGA to process data and has the advantages of fast response and high speed.

The above are only the preferred embodiments of the present invention, and the described embodiments are not used to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made using the contents of the description and drawings of the present invention should be included in the same reasoning. Within the protection scope of the appended claims of the present invention.

Claims (9)

1. An FPGA-based MAC address management method for an Ethernet switch is characterized in that it includes the following steps:

   S01: The receiving module receives the Ethernet data packet and transmits it to the MAC extraction module;

   S02: The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module;

   S03: The MAC address conversion module converts the MAC address to the RAM module read address and transmits it to the RAM module;

   S04: The RAM module determines the network port to be transmitted according to the read address of the RAM module, and transmits it to the sending module;

   S05: The sending module sends the Ethernet data packet to the corresponding network port.
2. The method for managing the MAC address of an FPGA-based Ethernet switch according to claim 1, wherein the receiving module, the MAC extraction module, the MAC address conversion module, the RAM module, and the sending module are all located in the FPGA chip.
3. The method for managing a MAC address of an FPGA-based Ethernet switch according to claim 1, wherein the MAC address is composed of M bytes of data, and M is an integer greater than zero.
4. The MAC address management method of an FPGA-based Ethernet switch according to claim 3, wherein the MAC address conversion module in step S03 converts the M-byte MAC address into an N-bit RAM module read address , N is an integer greater than 0.
5. The method for managing the MAC address of an FPGA-based Ethernet switch according to claim 4, wherein the storage depth of the RAM module is ^2N .
6. The method for managing the MAC address of an FPGA-based Ethernet switch according to claim 4, wherein in step S04, the RAM module outputs an X-bit port data according to the RAM module read address, and the port data is Each bit represents a corresponding network port to be transmitted, and only one bit of the X-bit port data is high level, and the remaining X-1 bit port data is low level.
7. The MAC address management method of an FPGA-based Ethernet switch according to claim 4, wherein the MAC address is composed of 6 bytes of data, the read address of the RAM module is 11 bits, and the RAM The memory depth of the module is 2048, and the port data is 32 bits.
8. The MAC address management method of an FPGA-based Ethernet switch according to claim 7, wherein the MAC address conversion module in step S03 extracts 11 bits from the last 3 bytes of the MAC address as RAM Module read address, the first 3 bytes of the MAC address are fixed bytes.
9. An FPGA-based MAC address management device for an Ethernet switch, which is characterized in that it includes an FPGA chip. The FPGA chip includes a receiving module, a MAC extracting module, a MAC address conversion module, a RAM module, and a sending module. The receiving module For receiving Ethernet data packets, the output end of the receiving module is connected to the input end of the MAC extraction module and the input end of the sending module at the same time, and the output end of the MAC extraction module is connected to the input end of the MAC address conversion module , The output terminal of the address conversion module is connected to the input terminal of the RAM module, the output terminal of the RAM module is connected to the input terminal of the sending module, and the sending module determines the sending port and sends the Ethernet data packet;

   The MAC extraction module extracts the MAC address from the Ethernet data packet and transmits it to the MAC address conversion module to convert it to the RAM module read address. The RAM module determines the network port to be transmitted according to the RAM module read address and transmits it to the sending module , The sending module sends the Ethernet data packet to the corresponding network port.

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