CN114567614B - Method and device for realizing ARP protocol processing based on FPGA - Google Patents
Method and device for realizing ARP protocol processing based on FPGA Download PDFInfo
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- CN114567614B CN114567614B CN202210224897.0A CN202210224897A CN114567614B CN 114567614 B CN114567614 B CN 114567614B CN 202210224897 A CN202210224897 A CN 202210224897A CN 114567614 B CN114567614 B CN 114567614B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/10—Mapping addresses of different types
- H04L61/103—Mapping addresses of different types across network layers, e.g. resolution of network layer into physical layer addresses or address resolution protocol [ARP]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Abstract
The invention discloses a method and a device for realizing ARP protocol processing based on FPGA. The invention adopts FPGA hardware to bear ARP protocol processing process, reduces the occupation of CPU time in ARP protocol processing process, and can also prevent the impact of ARP flooding attack on CPU; the ARP protocol is processed in an FPGA hardware mode, so that the ARP analysis response speed can be improved, and the IP data transmission delay can be reduced; on one hand, the whole ARP protocol processing flow is solidified and cannot be modified by the FPGA; on the other hand, the MAC address mapping table is realized in the FPGA and cannot be tampered by software without being in a system memory, so that the security of the network system is improved.
Description
Technical Field
The invention relates to a method and a device for realizing ARP protocol processing based on FPGA, belonging to the technical field of computer network communication.
Background
FPGA (Field Programmable Gate Array) Field Programmable Gate Array (FPGA) is a product developed further on the basis of programmable devices such as PAL (programmable array logic) and GAL (general array logic), and is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate numbers of the original programmable devices.
The ARP (Address Resolution Protocol) protocol is a basic network protocol, the operation of which is generally transparent to the application program or system, is usually implemented in the network protocol stack of the operating system, the CPU executes a specific software module to implement ARP protocol processing, and the parsing result is put into the device memory for caching.
At present, when processing ARP messages, network devices need to occupy system resources including CPU time and memory space, and meanwhile, because of requirements of system memory access and MAC table lookup efficiency, security and lookup efficiency of buffering MAC address tables in a memory are very critical in an operation process of a network system, and conventional network devices and hosts all adopt software to implement ARP processing procedures, which has certain defects in both security and lookup efficiency.
Disclosure of Invention
Therefore, the invention provides a method and a device for realizing ARP protocol processing based on FPGA, which realize ARP protocol processing in a manner of FPGA hardware and solve the problems of safety and efficiency of ARP processing in a traditional pure software manner.
In order to achieve the above object, the present invention provides the following technical solutions: in a first aspect, a method for implementing ARP processing based on FPGA is provided, including the following steps:
s001: resetting and initializing operation parameters of an FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
s002: receiving a network data packet through the initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing;
s101: analyzing the network data packet as a normal data communication IP packet, and turning to S102;
s102: the address retrieval unit searches the destination MAC address entry of the network data packet in the MAC address mapping table, and goes to S103;
s103: judging the search result of S102: if the destination MAC address entry exists, the process goes to S104; otherwise go to S105;
s104: delivering the destination MAC address entry and the network data packet to subsequent processing logic;
s105: triggering a request sending unit to generate a corresponding ARP request packet, carrying out a request process of a destination MAC address, and turning to S106;
s106: an ARP request packet is broadcast through a communication interface, and an ARP request is sent to a target device.
As a preferred method for implementing ARP processing based on FPGA, in S002, if the network packet is an ARP reply packet, the process goes to S201:
s201: receiving an ARP response packet of the target device, and turning to S202;
s202: the response processing unit analyzes the ARP response packet data, extracts address information and goes to S203;
s203: refreshing the MAC address mapping table and writing the newly added entry into the table entry.
As a preferred method for implementing ARP processing based on FPGA, in S002, if the network data packet is an ARP request packet, the process goes to S301:
s301: receiving an ARP request packet of the target device, and turning to S302;
s302: judging whether the request is a request for resolving the local IP address: if the IP is the local IP, the process goes to S304; otherwise go to S303;
s303: directly ending the treatment;
s304: triggering the response processing unit to generate a corresponding ARP response packet, filling the MAC address of the host into the ARP response packet, and turning to S305 next;
s305: and sending the ARP response packet to the target device through the network communication port which receives the ARP request packet.
As a preferred scheme of the method for implementing ARP processing based on FPGA, in S001, according to a set aging policy, unused MAC address entries in a preset time are deleted at regular time.
In a second aspect, there is provided an apparatus for implementing ARP protocol processing based on FPGA, and a method for implementing ARP protocol processing based on FPGA according to the first aspect or any possible implementation manner thereof, including:
the parameter configuration unit is used for resetting and initializing the running parameters of the FPGA module, wherein the running parameters comprise a network interface, a local address, the number of cache entries, ageing time and whether a high-speed expansion interface is started or not;
the data identification unit is used for receiving the network data packet through the initialized MAC interface and carrying out type identification on the network data packet;
the address retrieval unit is used for searching a destination MAC address entry of the network data packet in the MAC address mapping table if the network data packet is a normal data communication IP packet;
the searching and judging unit is used for judging the searching result and judging whether the MAC address mapping table has a destination MAC address item or not;
the first sending unit is used for giving the destination MAC address item and the network data packet to the subsequent processing logic when the destination MAC address item exists in the MAC address mapping table;
the second sending unit is used for generating a corresponding ARP request packet when the destination MAC address item does not exist in the MAC address mapping table, carrying out the request process of the destination MAC address, broadcasting the ARP request packet through the communication interface and sending the ARP request to the target equipment.
As a preferred scheme of the device for realizing ARP protocol processing based on the FPGA, the device further comprises a response processing unit, if the network data packet is an ARP response packet, the ARP response packet data is analyzed through the response processing unit, address information is extracted, an MAC address mapping table is refreshed, and the newly added item is written into the table item.
The device for realizing ARP protocol processing based on the FPGA further comprises an analysis judging unit for judging whether the network data packet is a request for analyzing the local IP address if the network data packet is an ARP request packet.
As a preferred scheme of the device for realizing ARP protocol processing based on the FPGA, the device further comprises an ending processing unit which is used for directly ending the processing when judging that the request is not a request for analyzing the local IP address.
The device for realizing ARP protocol processing based on the FPGA further comprises a response processing unit, wherein the response processing unit is used for generating a corresponding ARP response packet when judging that the request of analyzing the local IP address is received, filling the MAC address of the local into the ARP response packet, and sending the ARP response packet to the target device through a network communication port receiving the ARP request packet.
As a preferred scheme of the device for realizing ARP protocol processing based on the FPGA, the device further comprises an aging control unit, which is used for deleting unused MAC address entries in preset time at regular time according to a set aging strategy.
The invention has the following advantages: the FPGA hardware is used for bearing the ARP protocol processing process, so that the occupation of the ARP protocol processing process to CPU time is reduced, and the impact of ARP flooding attack to the CPU can be prevented; the ARP protocol is processed in an FPGA hardware mode, so that the ARP analysis response speed can be improved, and the IP data transmission delay can be reduced; on one hand, the whole ARP protocol processing flow is solidified and cannot be modified by the FPGA; on the other hand, the MAC address mapping table is realized in the FPGA and cannot be tampered by software without being in a system memory, so that the security of the network system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those of ordinary skill in the art that the drawings in the following description are exemplary only and that other implementations can be obtained from the extensions of the drawings provided without inventive effort.
The structures, proportions, sizes, etc. shown in the present specification are shown only for the purposes of illustration and description, and are not intended to limit the scope of the invention, which is defined by the claims, so that any structural modifications, changes in proportions, or adjustments of sizes, which do not affect the efficacy or the achievement of the present invention, should fall within the scope of the invention.
Fig. 1 is a flow chart of a method for implementing ARP processing based on FPGA in embodiment 1 of the present invention;
fig. 2 is a schematic diagram of an apparatus for implementing ARP protocol processing based on FPGA in embodiment 2 of the present invention.
Detailed Description
Other advantages and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, by way of illustration, is to be read in connection with certain specific embodiments, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1, embodiment 1 of the present invention provides a method for implementing ARP protocol processing based on FPGA, including the following steps:
s001: resetting and initializing operation parameters of an FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
s002: receiving a network data packet through the initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing;
s101: analyzing the network data packet as a normal data communication IP packet, and turning to S102;
s102: the address retrieval unit searches the destination MAC address entry of the network data packet in the MAC address mapping table, and goes to S103;
s103: judging the search result of S102: if the destination MAC address entry exists, the process goes to S104; otherwise go to S105;
s104: delivering the destination MAC address entry and the network data packet to subsequent processing logic;
s105: triggering a request sending unit to generate a corresponding ARP request packet, carrying out a request process of a destination MAC address, and turning to S106;
s106: an ARP request packet is broadcast through a communication interface, and an ARP request is sent to a target device.
Specifically, after the FPGA module is powered on, resetting is completed, a configuration management instruction is received, operating parameters such as a network interface, a local address, the number of cache entries, aging time, whether a high-speed expansion interface is started or not and the like of the FPGA are initialized, a network data packet is received through an initialized MAC interface, the type of the network data packet is identified, if the network data packet is a normal data communication IP packet, an address retrieval unit searches a destination MAC address entry of the network data packet in an MAC address mapping table, and a search result is judged: if the destination MAC address entry exists, the destination MAC address entry and the network data packet are handed to subsequent processing logic; if the destination MAC address item does not exist, triggering the request sending unit to generate a corresponding ARP request packet, carrying out the request process of the destination MAC address, broadcasting the ARP request packet through a communication interface, and sending an ARP request to the target equipment.
In this embodiment, in S002, if the network packet is an ARP reply packet, the process goes to S201:
s201: receiving an ARP response packet of the target device, and turning to S202;
s202: the response processing unit analyzes the ARP response packet data, extracts address information and goes to S203;
s203: refreshing the MAC address mapping table and writing the newly added entry into the table entry.
Specifically, if the network data packet is an ARP reply packet, the reply processing unit parses the ARP reply packet data, extracts address information, refreshes the MAC address mapping table, and writes the newly added entry into the table entry.
In this embodiment, in S002, if the network packet is an ARP request packet, the process goes to S301:
s301: receiving an ARP request packet of the target device, and turning to S302;
s302: judging whether the request is a request for resolving the local IP address: if the IP is the local IP, the process goes to S304; otherwise go to S303;
s303: directly ending the treatment;
s304: triggering the response processing unit to generate a corresponding ARP response packet, filling the MAC address of the host into the ARP response packet, and turning to S305 next;
s305: and sending the ARP response packet to the target device through the network communication port which receives the ARP request packet.
Specifically, if the network data packet is an ARP request packet, determining whether the network data packet is a request for resolving a local IP address: if the IP is the local IP, triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local IP into the ARP response packet, and sending the ARP response packet to the target equipment through a network communication port which receives the ARP request packet; if the IP is not the local IP, the processing is directly ended
In this embodiment, in S001, according to the set aging policy, the unused MAC address entries in the preset time are deleted at regular time. According to the set aging strategy, address entries which are not used in the MAC address mapping table for a period of time are deleted at regular time, so that new address entries can be stored, and effective utilization of RAM space is realized.
In summary, after the FPGA module of the present invention is powered on, reset is completed, a configuration management instruction is received, a network interface, a local address, the number of cache entries, an aging time, whether to enable a high-speed expansion interface, etc. of the FPGA are initialized, a network data packet is received through the initialized MAC interface, a type identification is performed on the network data packet, if the network data packet is a normal data communication IP packet, an address retrieval unit searches a destination MAC address entry of the network data packet in a MAC address mapping table, and a search result is determined: if the destination MAC address entry exists, the destination MAC address entry and the network data packet are handed to subsequent processing logic; if the destination MAC address item does not exist, triggering the request sending unit to generate a corresponding ARP request packet, carrying out the request process of the destination MAC address, broadcasting the ARP request packet through a communication interface, and sending an ARP request to the target equipment. If the network data packet is an ARP response packet, the response processing unit analyzes the ARP response packet data, extracts address information, refreshes the MAC address mapping table, and writes the newly added entry into the table entry. If the network data packet is an ARP request packet, judging whether the network data packet is a request for analyzing the local IP address or not: if the IP is the local IP, triggering a response processing unit to generate a corresponding ARP response packet, filling the MAC address of the local IP into the ARP response packet, and sending the ARP response packet to the target equipment through a network communication port which receives the ARP request packet; if the IP is not the local IP, the processing is directly ended. In addition, according to the set aging strategy, address entries which are not used in the MAC address mapping table for a period of time are deleted at regular time, so that new address entries can be ensured to be stored, and effective utilization of RAM space is realized. The invention adopts FPGA hardware to bear ARP protocol processing process, reduces the occupation of CPU time in ARP protocol processing process, and can also prevent the impact of ARP flooding attack on CPU; the ARP protocol is processed in an FPGA hardware mode, so that the ARP analysis response speed can be improved, and the IP data transmission delay can be reduced; on one hand, the whole ARP protocol processing flow is solidified and cannot be modified by the FPGA; on the other hand, the MAC address mapping table is realized in the FPGA and cannot be tampered by software without being in a system memory, so that the security of the network system is improved.
Example 2
Referring to fig. 2, embodiment 2 of the present invention further provides an apparatus for implementing ARP protocol processing based on FPGA, and a method for implementing ARP protocol processing based on FPGA in embodiment 1 or any possible implementation manner thereof includes:
the parameter configuration unit 1 is used for resetting and initializing operation parameters of the FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
a data identification unit 2, configured to receive a network data packet through an initialized MAC interface, and perform type identification on the network data packet;
an address retrieval unit 3, configured to, if the network data packet is a normal data communication IP packet, find a destination MAC address entry of the network data packet in a MAC address mapping table;
the search judging unit 4 is used for judging the search result and judging whether the destination MAC address entry exists in the MAC address mapping table;
a first sending unit 5, configured to send the destination MAC address entry and the network packet to subsequent processing logic when the destination MAC address entry exists in the MAC address mapping table;
the second sending unit 6 is configured to generate a corresponding ARP request packet when the destination MAC address entry does not exist in the MAC address mapping table, perform a request procedure of the destination MAC address, broadcast the ARP request packet through the communication interface, and send an ARP request to the target device.
In this embodiment, the method further includes a response processing unit 7, if the network data packet is an ARP response packet, the response processing unit analyzes the ARP response packet data, extracts address information, refreshes the MAC address mapping table, and writes the newly added entry into the table entry.
In this embodiment, the device further includes an analysis and determination unit 8, configured to determine whether the network packet is an ARP request packet, and determine whether the network packet is a request for analyzing a local IP address.
In this embodiment, the method further includes an end processing unit 9 for directly ending the processing when it is determined that the request for resolving the local IP address is not received.
In this embodiment, the device further includes a response processing unit 10, configured to generate a corresponding ARP reply packet when determining that the request for resolving the IP address of the device is a request, fill the MAC address of the device into the ARP reply packet, and send the ARP reply packet to the target device through the network communication port that receives the ARP request packet.
In this embodiment, the device further includes an aging control unit 11, configured to delete the unused MAC address entries in the preset time at regular intervals according to the set aging policy.
In this embodiment, the MAC address mapping table is implemented by a RAM, and is used for storing MAC address mapping entries.
In this embodiment, a CPU interface unit 12 is further configured to implement communication with a CPU, receive configuration of parameters of the CPU, and perform read-write operations, and access registers and storage spaces of each unit module inside.
In this embodiment, a high-speed communication interface unit 13 is further configured, and is configured to perform cascade communication between multiple FPGAs, and convert the interconnection bus into high-speed SerDes communication, so as to implement processing capacity and function expansion.
In this embodiment, interconnection of each functional module inside is realized through an interconnection bus; caching of network data packets is performed by the storage unit 14; and the network data packet is transmitted and received through the connection of the MAC interface and the network PHY.
The invention can be widely applied to various network communication devices or computer hosts. In an IP network data processing equipment system for realizing an ARP protocol processing device based on an FPGA, the system consists of an FPGA SoC chip, a DDR4 memory, a network PHY chip, FLASH storage, a power supply, a clock, a plurality of network interface connectors and the like.
FPGA SoC chip: 1 fusion SoC chip XCZU7EV of Xilinx company is selected for implementation, and FPGA and ARM processor cores are integrated inside. The FPGA realizes the transceiving and processing of network data, and also realizes the ARP protocol processing function here; the ARM processor realizes the configuration and management of the FPGA part through an internal AXI bus.
DDR4 memory: 4 MTMT40A256M16 chips are selected as DDR4, and are used as memory parts for running ARM processors of FPGA SoC chips and used as memories for running system software and application programs.
Network PHY chip: and a plurality of RTL8211 gigabit realization network PHY circuits are selected for physical link layer network communication, and are connected with the FPGA SoC chip through RGMII protocol to receive and transmit network data.
FLASH storage: 1 MT25QU256ABA chip and FLASH memory are selected as persistent storage parts for the ARM processor of the FPGA SoC chip to operate, and the persistent storage parts are used for system software, file systems and application programs to permanently hold, and data are guided and read from the persistent storage parts after the system is powered on.
It should be noted that, because the content of information interaction and execution process between the modules/units of the above-mentioned apparatus is based on the same concept as the method embodiment in embodiment 1 of the present application, the technical effects brought by the content are the same as the method embodiment of the present application, and the specific content can be referred to the description in the foregoing illustrated method embodiment of the present application, which is not repeated herein.
Example 3
Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk, SSD), etc.
Example 4
the processor and the memory complete communication with each other through a bus; the memory stores program instructions executable by the processor, which invokes the program instructions to perform the method of embodiment 1 or any possible implementation thereof for implementing ARP protocol processing based on FPGA.
Specifically, the processor may be implemented by hardware or software, and when implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like; when implemented in software, the processor may be a general-purpose processor, implemented by reading software code stored in a memory, which may be integrated in the processor, or may reside outside the processor, and which may reside separately.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.).
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may alternatively be implemented in program code executable by computing devices, so that they may be stored in a memory device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.
While the invention has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.
Claims (4)
1. The method for realizing ARP protocol processing based on the FPGA is characterized by comprising the following steps:
s001: resetting and initializing operation parameters of an FPGA module, wherein the operation parameters comprise a network interface, a local address, the number of cache entries, aging time and whether a high-speed expansion interface is started or not of the FPGA;
s002: receiving a network data packet through the initialized MAC interface, performing type identification on the network data packet, and if the network data packet is a normal data communication IP packet, turning to S101 for processing;
s101: analyzing the network data packet as a normal data communication IP packet, and turning to S102;
s102: the address retrieval unit searches the destination MAC address entry of the network data packet in the MAC address mapping table, and goes to S103;
s103: judging the search result of S102: if the destination MAC address entry exists, the process goes to S104; otherwise go to S105;
s104: delivering the destination MAC address entry and the network data packet to subsequent processing logic;
s105: triggering a request sending unit to generate a corresponding ARP request packet, carrying out a request process of a destination MAC address, and turning to S106;
s106: broadcasting an ARP request packet through a communication interface, and sending an ARP request to target equipment;
in S002, if the network packet is an ARP reply packet, the process proceeds to S201:
s201: receiving an ARP response packet of the target device, and turning to S202;
s202: the response processing unit analyzes the ARP response packet data, extracts address information and goes to S203;
s203: refreshing the MAC address mapping table, and writing the newly added entry into the table entry;
in S002, if the network packet is an ARP request packet, the process proceeds to S301:
s301: receiving an ARP request packet of the target device, and turning to S302;
s302: judging whether the request is a request for resolving the local IP address: if the IP is the local IP, the process goes to S304; otherwise go to S303;
s303: directly ending the treatment;
s304: triggering the response processing unit to generate a corresponding ARP response packet, filling the MAC address of the host into the ARP response packet, and turning to S305 next;
s305: and sending the ARP response packet to the target device through the network communication port which receives the ARP request packet.
2. The method for implementing ARP processing according to claim 1, wherein in S001, according to a set aging policy, unused MAC address entries in a preset time are deleted at regular time.
3. An apparatus for implementing ARP protocol processing based on FPGA, and a method for implementing ARP protocol processing based on FPGA according to any one of claims 1 to 2, comprising:
the parameter configuration unit is used for resetting and initializing the running parameters of the FPGA module, wherein the running parameters comprise a network interface, a local address, the number of cache entries, ageing time and whether a high-speed expansion interface is started or not;
the data identification unit is used for receiving the network data packet through the initialized MAC interface and carrying out type identification on the network data packet;
the address retrieval unit is used for searching a destination MAC address entry of the network data packet in the MAC address mapping table if the network data packet is a normal data communication IP packet;
the searching and judging unit is used for judging the searching result and judging whether the MAC address mapping table has a destination MAC address item or not;
the first sending unit is used for giving the destination MAC address item and the network data packet to the subsequent processing logic when the destination MAC address item exists in the MAC address mapping table;
the second sending unit is used for generating a corresponding ARP request packet when the destination MAC address item does not exist in the MAC address mapping table, carrying out a request process of the destination MAC address, broadcasting the ARP request packet through a communication interface and sending an ARP request to the target equipment;
the response processing unit is used for analyzing the ARP response packet data, extracting address information, refreshing the MAC address mapping table and writing the newly added entry into the table entry if the network data packet is the ARP response packet;
the analysis judging unit is used for judging whether the network data packet is a request for analyzing the local IP address or not if the network data packet is an ARP request packet;
the system also comprises an ending processing unit, a processing unit and a processing unit, wherein the ending processing unit is used for directly ending processing when judging that the request is not a request for resolving the local IP address;
and the response processing unit is used for generating a corresponding ARP response packet when judging that the request for analyzing the local IP address is received, filling the MAC address of the local into the ARP response packet, and sending the ARP response packet to the target equipment through the network communication port which receives the ARP request packet.
4. The device for implementing ARP processing according to claim 3, further comprising an aging control unit configured to delete unused MAC address entries in a preset time at regular intervals according to a set aging policy.
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| CN105530330A (en) * | 2015-12-07 | 2016-04-27 | 中国电子科技集团公司第十研究所 | Method for improving operation efficiency of ARP protocol in space information network |
| CN108243262A (en) * | 2016-12-26 | 2018-07-03 | 大唐移动通信设备有限公司 | Learning method, device and the network three-layer equipment of ARP table |
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| CN113872949B (en) * | 2021-09-18 | 2023-08-22 | 山东云海国创云计算装备产业创新中心有限公司 | Address resolution protocol response method and related device |
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| CN105530330A (en) * | 2015-12-07 | 2016-04-27 | 中国电子科技集团公司第十研究所 | Method for improving operation efficiency of ARP protocol in space information network |
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