WO2021208734A1 - 一种串行总线的数据传输方法及通信装置 - Google Patents
一种串行总线的数据传输方法及通信装置 Download PDFInfo
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- H—ELECTRICITY
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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Definitions
- the present invention relates to the field of communication technology, in particular to a serial bus data transmission method and communication device.
- a communication device that can implement multiple applications, it usually has at least two integrated circuit chips, one of which is a modem (modem), which is used to implement cellular communication functions, and can be understood as a communication system; the other chip is application processing Application Processor (AP for short) is used to implement functions such as shooting, display, 2D/3D engine, etc., and can be understood as an application processing system.
- modem modem
- AP application processing Application Processor
- a system needs to be equipped with an independent off-chip memory.
- a modem and an application processor are usually paired with an off-chip memory. This causes the communication device to have multiple off-chip memories at the same time, leading to an increase in overall cost.
- too much off-chip memory will also increase the area of a printed circuit board (PCB) that integrates various systems, which is not conducive to the miniaturization of communication devices.
- PCB printed circuit board
- the technical problem solved by the present invention is how to better realize data transmission with low time delay and high reliability.
- an embodiment of the present invention provides a serial bus data transmission method, including: acquiring data to be transmitted, and packaging the data into at least one data packet, the data packet being a long packet or a short packet. Packet, the long packet and the short packet have different data lengths; the at least one data packet is transmitted using the serial bus.
- the data length of the payload in the short packet is determined according to the width of a single data transmitted by the serial bus.
- the data length of the payload in the long packet is N times the data length of the payload in the short packet, and N is a positive integer greater than or equal to 2.
- the data packet includes: a header, which is used to carry transmission information of the data packet; The width of a single data is determined.
- the data packet further includes an ECC error correction code.
- the payload of the long packet includes multiple intervals, and each interval has a corresponding ECC error correction code.
- the packet header includes: a channel identification field, which is used to indicate a channel for transmitting the data packet; and a CC indication field, which is used to support flow control.
- the data to be transmitted comes from multiple data sources
- the packaging the data into at least one data packet includes: separately packaging data from different data sources to obtain the at least one data packet;
- Using the serial bus to transmit the at least one data packet includes: using the same physical path of the serial bus to transmit the at least one data packet, wherein the data packets of different data sources are distinguished based on different channel identification fields.
- the packet header further includes: a data line width indication field, which is used to indicate the width of the data line used by the data source of this transmission; a data position indication field, which is used to indicate that the data packet transmitted this time is in the data The position in the line.
- an embodiment of the present invention also provides a serial bus data transmission method, including: using the serial bus to receive at least one data packet, the data packet is a long packet or a short packet, and the long packet The packet and the short packet have different data lengths; the at least one received data packet is unpacked to obtain the transmitted data.
- the data packet includes an ECC error correction code
- the data transmission method further includes: for each received data packet, verifying the data packet based on the ECC error correction code; The result is that a one-bit error occurs, then the error is corrected; if the check result is that an error greater than one bit occurs, then it is reported to the upper layer.
- an embodiment of the present invention also provides a communication device, including: an application processor; a modem; a shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage Module, the modem and the application processor are coupled through a serial bus and indirectly access the shared memory through the application processor; wherein the modem and the application processor use the above-mentioned data transmission method for data transmission .
- the embodiment of the present invention provides a data transmission method of a serial bus, including: obtaining data to be transmitted, and packing the data into at least one data packet, the data packet being a long packet or a short packet, and the long packet And short packets have different data lengths; the serial bus is used to transmit the at least one data packet.
- the solution of this embodiment adopts a simple packaging method to minimize additional expenditure. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, the solution of this embodiment uses two data packets of different lengths to transmit data of different lengths.
- the data sending end can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted, making it possible to balance efficiency and implementation.
- an embodiment of the present invention also provides a communication device, including: an application processor; a modem; a shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage module, the The modem and the application processor are coupled through a serial bus and indirectly access the shared memory through the application processor; wherein, the modem and the application processor use the above-mentioned data transmission method for data transmission.
- the solution of this embodiment provides an improved communication device, which enables multiple systems with large-capacity, high-bandwidth, and low-latency memory access requirements to share the same physical memory, which helps reduce overall costs and improve system competitiveness.
- the shared storage module is hung under the application processor, the application processor can directly access the shared storage module, and the modem indirectly accesses the shared storage module through the application processor.
- multiple large-capacity, high-bandwidth, low-latency systems can share an off-chip physical memory.
- the delay of data transmission is reduced to a range acceptable to the modem, which makes it possible to improve data transmission efficiency and bandwidth, which is beneficial to better reduce delay.
- FIG. 1 is a schematic diagram of the principle of a communication device according to an embodiment of the present invention.
- FIG. 2 is a flowchart of a first serial bus data transmission method according to an embodiment of the present invention
- Figure 3 is a schematic diagram of the structure of the short packet in Figure 2;
- Figure 4 is a schematic diagram of the structure of the long bag in Figure 2;
- FIG. 5 is a flowchart of a second serial bus data transmission method according to an embodiment of the present invention.
- Fig. 6 is a flowchart of a third serial bus data transmission method according to an embodiment of the present invention.
- FIG. 7 is a schematic diagram of the structure of the data packet in FIG. 6;
- FIG. 8 is a flowchart of a fourth serial bus data transmission method according to an embodiment of the present invention.
- Fig. 9 is a schematic diagram of the principle of a modem according to an embodiment of the present invention.
- each system of the existing communication device is independently configured with off-chip physical memory, the overall cost is high, and the PCB area is large, which is not conducive to miniaturization.
- the prior art also has a solution based on dual-port memory (memory) to realize shared memory.
- dual-port memory memory
- the interface of dual-port memory is mainly parallel, and the speed is usually not high.
- the maximum bandwidth that the existing dual-port memory can provide is about 6.4Gbps, which is far lower than the requirements of systems that require large-capacity, high-bandwidth, and low-latency memory access.
- high bandwidth means that the bandwidth requirement of the system to access the off-chip physical memory is above 16Gbps; low latency means that the system access to the off-chip physical memory requires a delay of less than 1000ns.
- the inventor of the present application found through analysis that the existing high-speed transmission technology generally uses 128 bits as a basic physical (PHY) transmission unit. However, in practical applications, the length of 128 bits is not necessarily the most effective. On the other hand, in order to adapt to complex application scenarios, existing high-speed transmission technologies such as high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI Express, also known as PCIE) and USB packaging are more complicated.
- PCI Express Peripheral Component Interconnect Express
- PCIE Peripheral Component Interconnect Express
- an embodiment of the present invention provides a serial bus data transmission method, including: acquiring data to be transmitted, and packaging the data into at least one data packet, the data packet being a long packet or a short packet. Packet, the long packet and the short packet have different data lengths; the at least one data packet is transmitted using the serial bus.
- the solution of this embodiment adopts a simple packaging method to minimize additional expenditure. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, the solution of this embodiment uses two data packets of different lengths to transmit data of different lengths.
- the data sending end can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted, making it possible to balance efficiency and implementation.
- Fig. 1 is a schematic diagram of the principle of a communication device according to an embodiment of the present invention.
- the communication device may be a user equipment such as a mobile phone.
- the communication device 1 described in this embodiment may include: an application processor 11; a modem 12; and a shared storage module 13.
- the application processor 11 is coupled to the shared storage module 13 and can directly To access the shared memory module 13
- the modem 12 is coupled to the application processor 11 and indirectly accesses the shared memory 13 through the application processor 11.
- directness can be relative to indirectness, that is, the data access of the application processor 11 to the shared memory module 13 does not need to be transferred through other systems, while the data access of the modem 12 to the shared memory module 13 needs to pass through other systems. (Such as application processor 11) transit.
- the direct access described in this embodiment does not mean that the application processor 11 and the shared storage module 13 are directly connected by a data line.
- the application processor 11 and the shared storage module 13 may be connected through an interface or the like. At this time, it can also be considered that the application processor 11 directly accesses the shared storage module 13.
- the application processor 11 may include: a storage control unit 111, the storage control unit 111 communicates with the shared storage module 13, and the storage control unit 111 may be configured to receive the modem 12 And access the shared storage module 13 according to the access request.
- the storage control unit 111 may also be used to feed back the access result of the shared storage module 13 to the modem 12.
- the data transmission in the application processor 11 is performed based on the first bus (bus) 112, and the data transmission in the modem 12 is performed based on the second bus 121.
- the standard data format used for data transmission on the first bus 112 and the standard data format used for data transmission on the second bus 121 may be the same or different.
- the application processor 11 and the modem 12 can each use a data transmission protocol specified by an existing protocol for data transmission.
- the first bus 112 can be understood as a common channel in the application processor 11.
- the second bus 121 can be understood as a common channel in the modem 12.
- data transmission between the storage control unit 111 and the shared storage module 13 can also be based on a bus, and the standard data format used for data transmission is the same as the standard data format used for data transmission on the first bus 112.
- the standard data format used for data transmission on the second bus 121 may be the same or different.
- the application processor 11 may include a first processing module (Processor) 113, and the first processing module 113 may access the shared storage module 13 through the first bus 112 and the storage control unit 111 according to system operation requirements.
- processor a first processing module
- the first processing module 113 may access the shared storage module 13 through the first bus 112 and the storage control unit 111 according to system operation requirements.
- the modem 12 may include a second processing module 122, and the second processing module 122 may send an access request through the second bus 121 to request access to the shared storage module 13 according to the needs of system operation.
- the access request is transmitted to the first bus 112 through the coupling relationship between the modem 12 and the application processor 11, and then sent to the shared storage module 13 through the storage control unit 111.
- the application processor 11 and the modem 12 can communicate with each other through a serial bus 14.
- the serial bus 14 adopts a private data format when transmitting data, and the private data format is different from the aforementioned first bus 112, second bus 121, storage control unit 111, and shared storage module 13.
- the said standard data format is different from the aforementioned first bus 112, second bus 121, storage control unit 111, and shared storage module 13.
- the delay of data transmission is reduced to the acceptable range of the modem 12, which makes it possible to improve the data transmission efficiency and bandwidth, which is beneficial to better reduce the delay.
- the application processor 11 and the modem 12 respectively include an interface unit (link).
- the interface unit of the application processor 11 is marked as the first interface unit 114
- the interface unit of the modem 12 is marked as As the second interface unit 123.
- the first interface unit 114 and the second interface unit 123 are used to connect to the serial bus 14 and convert the data format of the data between the private data format and the respective standard data format of the application processor 11 and the modem 12.
- the second processing module 122 initiates a read command, and the read command is sequentially transmitted to the storage control unit through the second bus 121, the serial bus 14, the first interface unit 114, and the first bus 112. 111. Then, it is transmitted to the shared storage module 13 through the storage control unit 111.
- the shared storage module 13 feeds back the data pointed to by the read command, the data is gradually transferred to the second processing module 122 via the reverse path of the aforementioned path.
- the first interface unit 114 may change the data format of each data packet in the data from the data format adopted by the application processor 11
- the standard data format is converted to the private data format adopted by the serial bus 14. Then it is transmitted to the second interface unit 123 via the serial bus 14.
- the second interface unit 123 may convert the data format of each data packet in the data from the private data format to the standard data format adopted by the modem 12. Then, it is transmitted to the second processing module 122 through the second bus 121.
- the second processing module 122 initiates a write command, and the write command and the data to be written into the shared memory module 13 sequentially pass through the second bus 121, the serial bus 14, the first interface unit 114, The first bus 112 is transmitted to the storage control unit 111. Then, it is transmitted to the shared storage module 13 through the storage control unit 111.
- the second interface unit 123 can convert the data format of each data packet in the data from the standard data format adopted by the modem 12 To the private data format used by the serial bus 14. Then, it is transmitted to the first interface unit 114 via the serial bus 14.
- the first interface unit 114 may convert the data format of each data packet in the data from the private data format to the standard data format adopted by the application processor 11. Then, it is transferred to the storage control unit 111 through the first bus 112 for data writing.
- the shared memory module 13 may be a double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM for short, or DDR for short).
- DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
- the data transmitted by the serial bus 14 can be packaged into at least one data packet. Next, several different data transmission processes of the serial bus 14 will be described in detail.
- the first data transmission method of the serial bus 14 in the embodiment of the present invention may include the following steps:
- Step S101 Obtain data to be transmitted, and pack the data into at least one data packet, the data packet being a long packet or a short packet, and the long packet and the short packet have different data lengths;
- Step S102 Use the serial bus to transmit the at least one data packet.
- the steps S101 and S102 may be executed by the first interface unit 114.
- the steps S101 and S102 may be executed by the second interface unit 123.
- the at least one data packet may be all long packets, or all short packets, or a combination of long packets and short packets.
- long packets and/or short packets can be flexibly selected according to the size of the data to be transmitted to obtain the at least one data packet.
- the data length of the payload in the short packet may be determined according to the width of a single data transmitted by the serial bus 14.
- the width of the single data may be the width of most single data transmitted on the serial bus 14.
- the inventor of the present application found through analysis that the existing high-speed transmission technology generally uses 128 bits as a basic physical (PHY) transmission unit. However, in practical applications, the length of 128 bits is not necessarily the most effective. On the other hand, in order to adapt to complex application scenarios, existing high-speed transmission technologies such as high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI Express, also known as PCIE) and USB packaging are more complicated.
- PCI Express Peripheral Component Interconnect Express
- PCIE Peripheral Component Interconnect Express
- this implementation minimizes additional expenditures by designing a simple packaging method. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, this implementation defines two data packets of different lengths for transmitting data of different lengths.
- the data sending end (such as the first interface unit 114 or the second interface unit 123) can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted.
- the width of a single data is usually 73 bits when transmitting data based on AXI. Then, if data transmission is performed according to the existing 128 bits as the basic unit, a lot of bits will obviously be wasted.
- the data length of the payload of the short packet is determined to be 77 bits. Further, the overall data length of the short packet may be 112 bits. On the basis of ensuring that sufficient transmission information and a 77-bit payload are effectively accommodated, and is an entire packet, the overall data length of the data packet is reduced as much as possible. Among them, the whole packet means that the data length of the data packet is an integral multiple of 16, and 16 is defined by the physical layer.
- the short packet 3 may include: a header 31, used to carry the transmission information of the data packet; and a packet body 32, used to carry at least a part of the data.
- the packet body 32 may include a payload 321, and the length of the packet body 32 may be determined according to the width of a single data transmitted by the serial bus 14. For example, the data length of the payload 321 is 77 bits.
- the packet header 31 may include a channel identification field (Channel Identification, ChID for short) 311, which is used to indicate a channel for transmitting the data packet (short packet 3 in this embodiment).
- ChID Channel Identification
- the packet header 31 may also include a credit counter (Credit Counter, CC for short) indication field 312, which is used to support flow control.
- the CC indication field 312 may include a CC identification (CCID) and a credit value (Credit). Wherein, the CC identifier is used to indicate the channel to which the short packet 3 belongs, and the credit value is used to indicate the credit value of the channel.
- the packet header 31 may include multiple sets of CC indication fields 312.
- FIG. 3 shows three sets of CC indication fields 312, which are respectively denoted as CCID0 and Credit0 groups, CCID1 and Credit1 groups, and CCID2 and Credit2 groups.
- the CC indicator fields 312 of different groups correspond to different channels.
- the short packet 3 may also include an ECC error correction code 33.
- the receiving end of the data packet checks the short packet 3 based on the ECC error correction code 33, if the check result is that a one-bit error occurs, the error is corrected If the check result is an error greater than one bit, it is reported to the upper layer.
- the upper layer may be the application layer of the communication device 1.
- the data length of the ECC error correction code 33 may be 9 bits, and the data length of the packet header 31 may be 26 bits.
- the packet body 32 collectively constitutes a short packet 3 with a total length of 112 bits.
- the data length of the payload 321 of the packet body 32 can be adjusted according to the width of the single data to be transmitted.
- the data length of the corresponding short packet 3 can also be adjusted appropriately.
- the data length of the payload in the long packet may be N times the data length of the payload in the short packet, and N is a positive integer greater than or equal to 2.
- the data length of the payload 421 in the long packet 4 may be three times the data length of the payload 321 in the short packet 3 shown in FIG. In this way, 4 groups of 73-bit data can be packed in the long packet 4.
- the long packet 4 may also include a packet header 41, a packet body 42, and an ECC check code 43.
- the packet header 41 may be used to carry the transmission information of the long packet 4.
- the header 41 may include a channel identification field (ChID) and a CC indication field.
- the packet header 41 may also include a data line width indication field (Data Width, DW for short), which is used to indicate the width of the data line used by the data source for this transmission.
- Data Width Data Width, DW for short
- the packet header 41 may also include a data position indication field (Position, Pos for short), which is used to indicate the position of the data packet (long packet 4 in this embodiment) transmitted this time in the data line.
- a data position indication field Position, Pos for short
- the payload 421 of the long packet 4 may include multiple intervals, and each interval has a corresponding ECC error correction code 43.
- the payload 421 may include 3 intervals, and the data length of each interval is 86 bits, 103 bits, and 103 bits, respectively. Each interval is followed by an ECC error correction code 43 corresponding to the interval.
- the data to be transmitted may come from multiple data sources, and the step S101 may include the step of separately packaging data from different data sources to obtain the at least one data packet.
- the step S102 may include the step of using the same physical path of the serial bus 14 to transmit the at least one data packet, wherein the data packets of different data sources are distinguished based on different channel identification fields (ChID).
- ChID channel identification fields
- ChID channel identification field
- Fig. 5 is a flowchart of a second serial bus data transmission method according to an embodiment of the present invention.
- the second interface unit 123 as the data receiving end can execute this implementation Example solution to receive the short packet 3 and/or the long packet 4.
- the first interface unit 114 as the data receiving end can execute the solution of this embodiment to receive the short message. Pack 3 and/or Long Pack 4.
- the data transmission method may include the following steps:
- Step S201 Use the serial bus to receive at least one data packet, where the data packet is a long packet or a short packet, and the long packet and the short packet have different data lengths;
- Step S202 Unpack the at least one received data packet to obtain transmitted data.
- steps S201 to S202 can be regarded as execution steps corresponding to the steps S101 to S102 in the embodiment shown in FIG. 2 to FIG. They are complementary. Therefore, for the explanation of the terms involved in this embodiment, reference may be made to the related descriptions of the embodiments shown in FIG. 2 to FIG. 4, which will not be repeated here.
- the standard data format used for data transmission in the transfer demodulator 12 is to perform unpacking processing on the at least one received data packet. And convert the received data format of the at least one data packet into a corresponding standard data format.
- the data transmission method of this embodiment may further include the step of: for each received data packet, the data packet is adjusted based on the ECC error correction code. Perform verification; if the verification result is that a one-bit error occurs, then the error is corrected; if the verification result is that an error greater than one bit occurs, then it is reported to the upper layer.
- CRC Cyclic Redundancy Check
- the short packet 3 and the long packet 4 are transmitted in a one-bit error correction and two-bit error detection (SEC-DED ECC) mode.
- SEC-DED ECC one-bit error correction and two-bit error detection
- the ECC error correction code can be replaced with another type of error correction code for verification by the data receiving end.
- Fig. 6 is a flowchart of a third serial bus data transmission method according to an embodiment of the present invention.
- the data transmission method of the serial bus 14 in this embodiment may include the following steps:
- Step S301 Obtain the data to be transmitted, and pack the data into at least one data packet, the data length of the data packet is configurable, and the data packet includes a length indication field (Length) and at least one data packet Unit, the length indication field is used to indicate the number of data packet units;
- Step S302 Use the serial bus to transmit the at least one data packet.
- the steps S301 and S302 may be executed by the first interface unit 114. Conversely, when the data to be transmitted is transmitted by the second interface unit 123 to the first interface unit 114, the steps S301 and S302 may be executed by the second interface unit 123.
- the data packet 5 with variable data length described in this embodiment may include a packet header 51 and a packet body 52.
- the packet header 51 may be used to carry the transmission information of the data packet 5.
- the packet header 51 may include a channel identification field (ChID) and a CC indicator field.
- the packet body 52 may be used to carry at least one data packet unit 521.
- Data0, Data1,..., Datan are taken as examples for exemplary display.
- the data length of different data packet units 521 may be the same or different.
- the data length of each data packet unit 521 in the data packet 5 may be determined by a configuration register.
- the data to be transmitted can come from multiple data sources. Among them, at least one data packet unit 521 in the same data packet 5 can come from the same data source, and the data packet unit 521 in different data packets 5 can come from different data sources. . That is, data from different data sources are packed into different data packages 5.
- a transmission block 53 can be obtained by packing per unit data length.
- the data packet 5 may include multiple transmission blocks 53, and the data length of each transmission block 53 is fixed. Since the data length of the data packet 5 is configurable, the number of transmission blocks 53 included in different data packets 5 may be different.
- the unit data length may be 119 bits. That is, starting from the header 51 of the data packet 5, there is a packet for every 119 bits. These 119 bits may not have the header 51, and a certain data packet unit 521 may even be interrupted.
- the last few or part of the last data packet unit 521 of the previous data packet 5 may be packed with the header 51 and/or at least a part of the data packet unit 521 of the next data packet 5 Into a transmission block 53.
- the transmission block 53 may include a payload 531 and an error correction code 532.
- the data length of the payload 531 is 119 bits.
- the payload 531 of the transmission block 53 is obtained by packing every 119 bits from the header 51 of the data packet 5, and then the corresponding error correction code 532 is added to form the transmission block 53.
- the error correction code 532 may be an ECC error correction code.
- the length of the physical layer transmission block used is 128 bits. That is, the data length of the transmission block 53 adopts 128 bits common to the existing transmission protocol, wherein the data length of the payload 531 is 119 bits for transmitting data, and the ECC error correction code 532 is 9 bits.
- the at least one data packet 5 may be packaged end to end as a whole.
- Fig. 8 is a flowchart of a fourth serial bus data transmission method according to an embodiment of the present invention.
- the second interface unit 123 as the data receiving end can execute this implementation Example scheme to receive the at least one data packet 5.
- the first interface unit 114 as the data receiving end can execute the solution of this embodiment to receive the at least One data packet 5.
- the data transmission method may include the following steps:
- Step S401 Use the serial bus to receive at least one data packet, the data length of the data packet is configurable, the data packet includes a length indication field and at least one data packet unit, and the length indication field is used for Indicating the number of data packet units;
- Step S402 unpacks the received at least one data packet to obtain the transmitted data.
- steps S401 to S402 can be regarded as the execution steps corresponding to the steps S301 to S302 in the embodiment shown in FIG. 6 to FIG. They are complementary. Therefore, for the explanation of the terms involved in this embodiment, reference may be made to the related description of the embodiment shown in FIG. 6 and FIG. 7, which will not be repeated here.
- step S402 it can be used as the standard data format for data transmission in the application processor 11 to which the first interface unit 114 belongs to the data receiving end, or the second interface unit 123 as the data receiving end belongs to
- the received at least one data packet 5 is unpacked.
- the received data format of the at least one data packet 5 is converted into a corresponding standard data format.
- the data transmission method of this embodiment may further include the step: for each transmission block 53 in each data packet 5, based on the transmission block 53
- the ECC error correction code 532 in the transmission block 53 checks the data contained in the transmission block 53 (carried in the payload 531); if the check result is one bit error, then the error is corrected; if the check result is more than one bit The error will be reported to the upper level.
- CRC Cyclic Redundancy Check
- the transmitted data packet 5 uses a one-bit error correction and two-bit error detection (SEC-DED ECC) mode.
- SEC-DED ECC single-bit error correction and two-bit error detection
- the ECC error correction code can be replaced with another type of error correction code for verification by the data receiving end.
- the communication device 1 may further include: an additional sharing module (not shown), the additional sharing module may be coupled to the application processor 11 and indirectly accessed through the application processor 11 Mentioned shared storage module 13.
- the additional sharing module may be an off-chip accelerator.
- the additional shared module may also be an embedded neural network processor (Neural-network Processing Unit, NPU for short).
- NPU Neuro-network Processing Unit
- the shared memory solution in this embodiment is not only applicable to the scenario where the application processor 11 and the modem 12 share the shared memory module 13, but also applicable to the scenario where more systems share the shared memory module 13 .
- the access delay performance is improved.
- the access to the shared storage module 13 related to cache misses is improved, and the access to the shared storage module 13 that is not cached is improved.
- the modem 6 may include: a buffer module 62 for buffering data accessed by the modem 6.
- the modem 6 may further include a function module 61, and the buffer module 62 buffers the data accessed by the function module 61.
- the modem 6 may be coupled to an external processing device (not shown in FIG. 9), the function module 61 indirectly accesses the shared storage module 13 through the external processing device to obtain data, and the external processing device is connected to the shared storage module 13
- the storage module 13 is coupled to and can directly access the shared storage module 13.
- the data accessed by each functional module 61 is buffered, so as to reduce the frequency of the modem 6 accessing the shared memory module 13.
- a better balance can be achieved between the high latency of the external memory and the real-time requirements of the modem.
- the modem 6 described in this embodiment may be applied to the shared memory scenario shown in FIG. 1, and the modem 12 shown in FIG. 1 may adopt the specific structure of the modem 6 described in this embodiment.
- the external processing device is the application processor 11 shown in FIG. 1.
- the functional module 61 may include a Microcontroller Unit (Microcontroller Unit, MCU for short). Further, the MCU may include multiple sub-units, as shown in processor cluster #1 to processor cluster #N in the figure, and N is greater than or equal to 1.
- MCU Microcontroller Unit
- the functional module 61 may include a hardware accelerator. Similar to the MCU, the hardware accelerator may also include multiple subunits, as shown in hardware accelerator #1 to hardware accelerator #M in the figure, and M is greater than or equal to 1.
- any functional module 61 in the modem 6 when reading data, when any functional module 61 in the modem 6 reads data, it can read the cache module 62 first, if it hits, return the reading result, if it misses, continue to pass The application processor 11 accesses the shared storage module 13.
- the data buffered by the buffer module 62 may be data accessed by the functional module 61 of the modem 6 with high frequency in history.
- the historical access results of the functional module 61 in the shared storage module 13 are statistically analyzed by means of simulation or experiment, and the historical high-frequency access data of the functional module 61 is comprehensively analyzed according to the frequency and the amount of data accessed.
- the data is cached in the cache module 62 in advance for the function module 61 to access.
- the data cached in the cache module 62 may be data that has been accessed by the functional module 61 of the modem 6 with high frequency in history and has a small amount of data.
- the cache module 62 may include a plurality of first cache sub-modules 621, and different first cache sub-modules 621 may correspond to different functional modules 61.
- each processor cluster may be configured with a corresponding first cache sub-module 621.
- each hardware accelerator may also be configured with a corresponding first cache submodule 621.
- the functional module 61 For each of the functional modules 61, when the functional module 61 reads data, it first reads the corresponding first cache sub-module 621, if it is hit, it returns the reading result, if it is not hit, it continues to pass the The application processor 11 accesses the shared storage module 13.
- processor cluster #1 Take processor cluster #1 as an example. When the processor cluster #1 reads data, it first reads the first cache submodule 621 corresponding to it. The application processor 11 accesses the shared storage module 13.
- the data can be cached in the first cache submodule 621 corresponding to the processor cluster #1 to For later use.
- the cache module 62 may further include a second cache sub-module 622, and the second cache sub-module 622 may correspond to multiple functional modules 61.
- the second buffer sub-module 622 may be coupled to the bus 63 in the modem 6 to buffer data transmitted on the bus 63.
- the bus 63 may be the second bus 121 in FIG. 1.
- the functional module 61 when the functional module 61 reads data, it first reads the corresponding first cache sub-module 621, if it hits, it returns the reading result, and if it misses, it reads the corresponding first cache sub-module 621.
- the second cache sub-module 622 continues to access the shared storage module 13 through the application processor 11 if it is still missed.
- hardware accelerator #1 when the hardware accelerator #1 reads data, it first reads the first cache submodule 621 corresponding to it.
- the second cache sub-module 622 continues to access the shared storage module 13 through the application processor 11 if it still misses.
- the data may be preferentially cached to the first cache submodule 621 corresponding to the hardware accelerator #1 for preparation Use later.
- the first cache submodule 621 corresponding to the hardware accelerator #1 is full at this time, the data may be cached in the second cache submodule 622.
- the second buffer submodule 622 may be directly coupled to an interface unit for connecting the serial bus between the modem 6 and the external processing device.
- the second buffer sub-module 622 may be coupled to the second interface unit 123 in FIG. 1 to buffer the data received by the second interface unit 123.
- the processor cluster may include a coherency interface for implementing memory coherency management among the first cache sub-module 621, the second cache sub-module 622, and the shared storage module 13.
- the first cache sub-module 621 may preferentially cache the data accessed by the corresponding functional module 61. Further, if the first cache sub-module 621 is full, the data accessed by the functional module 61 corresponding to the first cache sub-module 621 is cached to the second cache sub-module 622.
- the second buffer sub-module 622 may preferentially buffer the data that has been accessed by the functional module 61 of the modem 6 with high frequency in history. For example, for pre-cached data, it can be preferentially placed in the public cache space (i.e., the second cache submodule 622) for later use.
- the number and size of each of the first cache sub-module 621 and the second cache sub-module 622 may be divided and determined according to the statistical results of the corresponding functional module 61 and the modem 6's overall access to the shared storage module 13. of. That is, the size of each of the first cache sub-module 621 and the second cache sub-module 622 can be flexibly adjusted (Size Tuning).
- a larger first cache submodule 621 may be allocated in a targeted manner.
- a plurality of first buffer sub-modules 621 are temporarily allocated to the functional module 61 to make full use of the buffer space of the modem 6.
- the capacity of the second cache sub-module 622 may be greater than the capacity of the first cache sub-module 621. Further, the delay performance requirement of the second cache sub-module 622 may be slightly lower than the delay performance requirement of the first cache sub-module 621.
- the first cache sub-module 621 may be an L1-level random access memory (Random Access Memory, RAM for short).
- the second cache sub-module 622 may be a relatively low-level but large-capacity RAM.
- the first cache sub-module 621 may also be an L2 level RAM.
- the modem 6 itself may be configured with a traditional cache (Cache) 64.
- the solution of this embodiment is provided with an additional amount of cache module 62 (such as RAM) in the modem 6 to reduce access to data with a small amount of data but with a higher frequency. External access requirements.
- a part of the first cache sub-module 621 is additionally configured in the MCU.
- a part of the first cache sub-module 621 can also be configured according to requirements.
- bus 63 can also be externally provided with part of the second cache sub-module 622 (RAM and Cache).
- the solution of this embodiment can be widely applied to various types of external memories to improve the access delay performance.
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Abstract
Description
Claims (12)
- 一种串行总线的数据传输方法,其特征在于,包括:获取待传输的数据,并将所述数据打包为至少一个数据包,所述数据包为长包或短包,所述长包和短包具有不同的数据长度;使用所述串行总线传输所述至少一个数据包。
- 根据权利要求1所述的数据传输方法,其特征在于,所述短包中的有效载荷的数据长度根据所述串行总线传输的单个数据的宽度确定。
- 根据权利要求1或2所述的数据传输方法,其特征在于,所述长包中的有效载荷的数据长度是所述短包中的有效载荷的数据长度的N倍,N为大于等于2的正整数。
- 根据权利要求1所述的数据传输方法,其特征在于,所述数据包包括:包头,用于承载所述数据包的传输信息;包体,用于承载所述数据的至少一部分,所述包体的长度根据所述串行总线传输的单个数据的宽度确定。
- 根据权利要求4所述的数据传输方法,其特征在于,所述数据包还包括ECC纠错码。
- 根据权利要求5所述的数据传输方法,其特征在于,所述长包的有效载荷包括多个区间,其中每一区间具有相对应的ECC纠错码。
- 根据权利要求4所述的数据传输方法,其特征在于,所述包头包括:信道标识字段,用于指示传输所述数据包的信道;CC指示字段,用于支持流控。
- 根据权利要求7所述的数据传输方法,其特征在于,所述待传输的数据来自多个数据源,所述将所述数据打包为至少一个数据包包括:将不同数据源的数据分别打包,以得到所述至少一个数据包;所述使用所述串行总线传输所述至少一个数据包包括:使用所述串行总线的同一物理通路传输所述至少一个数据包,其中,不同数据源的数据包基于不同的信道标识字段相区分。
- 根据权利要求7所述的数据传输方法,其特征在于,所述包头还包括:数据线宽度指示字段,用于指示本次传输数据源所采用的数据线的宽度;数据位置指示字段,用于指示本次传输的数据包在所述数据线中的位置。
- 一种串行总线的数据传输方法,其特征在于,包括:使用所述串行总线接收至少一个数据包,所述数据包为长包或短包,所述长包和短包具有不同的数据长度;解包接收到的所述至少一个数据包,以获取传输的数据。
- 根据权利要求10所述的数据传输方法,其特征在于,所述数据包包括ECC纠错码,所述数据传输方法还包括:对于接收到的每一数据包,基于所述ECC纠错码对所述数据包进行校验;若校验结果为出现一比特错误,则纠错;若校验结果为出现大于一比特的错误,则上报上层。
- 一种通信装置,其特征在于,包括:应用处理器;调制解调器;共享存储模块,所述应用处理器与所述共享处理模块耦接并可直接访问所述共享存储模块,所述调制解调器与所述应用处理器通过串行总线耦接并通过所述应用处理器间接访问所述共享存储器;其中,所述调制解调器与所述应用处理器采用上述权利要求1至11中任一项所述方法进行数据传输。
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CN114124594A (zh) * | 2020-08-28 | 2022-03-01 | 深圳市中兴微电子技术有限公司 | 数据传输方法和系统、芯片 |
CN113971151B (zh) * | 2021-10-28 | 2024-07-26 | 上海兆芯集成电路股份有限公司 | 串行传输控制器及其数据传输方法 |
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