WO2021208734A1 - 一种串行总线的数据传输方法及通信装置 - Google Patents

一种串行总线的数据传输方法及通信装置 Download PDF

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Publication number
WO2021208734A1
WO2021208734A1 PCT/CN2021/084221 CN2021084221W WO2021208734A1 WO 2021208734 A1 WO2021208734 A1 WO 2021208734A1 CN 2021084221 W CN2021084221 W CN 2021084221W WO 2021208734 A1 WO2021208734 A1 WO 2021208734A1
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Prior art keywords
data
packet
serial bus
transmission method
data transmission
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PCT/CN2021/084221
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English (en)
French (fr)
Inventor
冀晋
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展讯通信（上海）有限公司
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Publication of WO2021208734A1 publication Critical patent/WO2021208734A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H04L1/0043—Realisations of complexity reduction techniques, e.g. use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/009—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location arrangements specific to transmitters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0091—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location arrangements specific to receivers, e.g. format detection

Definitions

  • the present invention relates to the field of communication technology, in particular to a serial bus data transmission method and communication device.
  • a communication device that can implement multiple applications, it usually has at least two integrated circuit chips, one of which is a modem (modem), which is used to implement cellular communication functions, and can be understood as a communication system; the other chip is application processing Application Processor (AP for short) is used to implement functions such as shooting, display, 2D/3D engine, etc., and can be understood as an application processing system.
  • modem modem
  • AP application processing Application Processor
  • a system needs to be equipped with an independent off-chip memory.
  • a modem and an application processor are usually paired with an off-chip memory. This causes the communication device to have multiple off-chip memories at the same time, leading to an increase in overall cost.
  • too much off-chip memory will also increase the area of a printed circuit board (PCB) that integrates various systems, which is not conducive to the miniaturization of communication devices.
  • PCB printed circuit board
  • the technical problem solved by the present invention is how to better realize data transmission with low time delay and high reliability.
  • an embodiment of the present invention provides a serial bus data transmission method, including: acquiring data to be transmitted, and packaging the data into at least one data packet, the data packet being a long packet or a short packet. Packet, the long packet and the short packet have different data lengths; the at least one data packet is transmitted using the serial bus.
  • the data length of the payload in the short packet is determined according to the width of a single data transmitted by the serial bus.
  • the data length of the payload in the long packet is N times the data length of the payload in the short packet, and N is a positive integer greater than or equal to 2.
  • the data packet includes: a header, which is used to carry transmission information of the data packet; The width of a single data is determined.
  • the data packet further includes an ECC error correction code.
  • the payload of the long packet includes multiple intervals, and each interval has a corresponding ECC error correction code.
  • the packet header includes: a channel identification field, which is used to indicate a channel for transmitting the data packet; and a CC indication field, which is used to support flow control.
  • the data to be transmitted comes from multiple data sources
  • the packaging the data into at least one data packet includes: separately packaging data from different data sources to obtain the at least one data packet;
  • Using the serial bus to transmit the at least one data packet includes: using the same physical path of the serial bus to transmit the at least one data packet, wherein the data packets of different data sources are distinguished based on different channel identification fields.
  • the packet header further includes: a data line width indication field, which is used to indicate the width of the data line used by the data source of this transmission; a data position indication field, which is used to indicate that the data packet transmitted this time is in the data The position in the line.
  • an embodiment of the present invention also provides a serial bus data transmission method, including: using the serial bus to receive at least one data packet, the data packet is a long packet or a short packet, and the long packet The packet and the short packet have different data lengths; the at least one received data packet is unpacked to obtain the transmitted data.
  • the data packet includes an ECC error correction code
  • the data transmission method further includes: for each received data packet, verifying the data packet based on the ECC error correction code; The result is that a one-bit error occurs, then the error is corrected; if the check result is that an error greater than one bit occurs, then it is reported to the upper layer.
  • an embodiment of the present invention also provides a communication device, including: an application processor; a modem; a shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage Module, the modem and the application processor are coupled through a serial bus and indirectly access the shared memory through the application processor; wherein the modem and the application processor use the above-mentioned data transmission method for data transmission .
  • the embodiment of the present invention provides a data transmission method of a serial bus, including: obtaining data to be transmitted, and packing the data into at least one data packet, the data packet being a long packet or a short packet, and the long packet And short packets have different data lengths; the serial bus is used to transmit the at least one data packet.
  • the solution of this embodiment adopts a simple packaging method to minimize additional expenditure. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, the solution of this embodiment uses two data packets of different lengths to transmit data of different lengths.
  • the data sending end can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted, making it possible to balance efficiency and implementation.
  • an embodiment of the present invention also provides a communication device, including: an application processor; a modem; a shared storage module, the application processor is coupled to the shared processing module and can directly access the shared storage module, the The modem and the application processor are coupled through a serial bus and indirectly access the shared memory through the application processor; wherein, the modem and the application processor use the above-mentioned data transmission method for data transmission.
  • the solution of this embodiment provides an improved communication device, which enables multiple systems with large-capacity, high-bandwidth, and low-latency memory access requirements to share the same physical memory, which helps reduce overall costs and improve system competitiveness.
  • the shared storage module is hung under the application processor, the application processor can directly access the shared storage module, and the modem indirectly accesses the shared storage module through the application processor.
  • multiple large-capacity, high-bandwidth, low-latency systems can share an off-chip physical memory.
  • the delay of data transmission is reduced to a range acceptable to the modem, which makes it possible to improve data transmission efficiency and bandwidth, which is beneficial to better reduce delay.
  • FIG. 1 is a schematic diagram of the principle of a communication device according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a first serial bus data transmission method according to an embodiment of the present invention
  • Figure 3 is a schematic diagram of the structure of the short packet in Figure 2;
  • Figure 4 is a schematic diagram of the structure of the long bag in Figure 2;
  • FIG. 5 is a flowchart of a second serial bus data transmission method according to an embodiment of the present invention.
  • Fig. 6 is a flowchart of a third serial bus data transmission method according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the structure of the data packet in FIG. 6;
  • FIG. 8 is a flowchart of a fourth serial bus data transmission method according to an embodiment of the present invention.
  • Fig. 9 is a schematic diagram of the principle of a modem according to an embodiment of the present invention.
  • each system of the existing communication device is independently configured with off-chip physical memory, the overall cost is high, and the PCB area is large, which is not conducive to miniaturization.
  • the prior art also has a solution based on dual-port memory (memory) to realize shared memory.
  • dual-port memory memory
  • the interface of dual-port memory is mainly parallel, and the speed is usually not high.
  • the maximum bandwidth that the existing dual-port memory can provide is about 6.4Gbps, which is far lower than the requirements of systems that require large-capacity, high-bandwidth, and low-latency memory access.
  • high bandwidth means that the bandwidth requirement of the system to access the off-chip physical memory is above 16Gbps; low latency means that the system access to the off-chip physical memory requires a delay of less than 1000ns.
  • the inventor of the present application found through analysis that the existing high-speed transmission technology generally uses 128 bits as a basic physical (PHY) transmission unit. However, in practical applications, the length of 128 bits is not necessarily the most effective. On the other hand, in order to adapt to complex application scenarios, existing high-speed transmission technologies such as high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI Express, also known as PCIE) and USB packaging are more complicated.
  • PCI Express Peripheral Component Interconnect Express
  • PCIE Peripheral Component Interconnect Express
  • an embodiment of the present invention provides a serial bus data transmission method, including: acquiring data to be transmitted, and packaging the data into at least one data packet, the data packet being a long packet or a short packet. Packet, the long packet and the short packet have different data lengths; the at least one data packet is transmitted using the serial bus.
  • the solution of this embodiment adopts a simple packaging method to minimize additional expenditure. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, the solution of this embodiment uses two data packets of different lengths to transmit data of different lengths.
  • the data sending end can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted, making it possible to balance efficiency and implementation.
  • Fig. 1 is a schematic diagram of the principle of a communication device according to an embodiment of the present invention.
  • the communication device may be a user equipment such as a mobile phone.
  • the communication device 1 described in this embodiment may include: an application processor 11; a modem 12; and a shared storage module 13.
  • the application processor 11 is coupled to the shared storage module 13 and can directly To access the shared memory module 13
  • the modem 12 is coupled to the application processor 11 and indirectly accesses the shared memory 13 through the application processor 11.
  • directness can be relative to indirectness, that is, the data access of the application processor 11 to the shared memory module 13 does not need to be transferred through other systems, while the data access of the modem 12 to the shared memory module 13 needs to pass through other systems. (Such as application processor 11) transit.
  • the direct access described in this embodiment does not mean that the application processor 11 and the shared storage module 13 are directly connected by a data line.
  • the application processor 11 and the shared storage module 13 may be connected through an interface or the like. At this time, it can also be considered that the application processor 11 directly accesses the shared storage module 13.
  • the application processor 11 may include: a storage control unit 111, the storage control unit 111 communicates with the shared storage module 13, and the storage control unit 111 may be configured to receive the modem 12 And access the shared storage module 13 according to the access request.
  • the storage control unit 111 may also be used to feed back the access result of the shared storage module 13 to the modem 12.
  • the data transmission in the application processor 11 is performed based on the first bus (bus) 112, and the data transmission in the modem 12 is performed based on the second bus 121.
  • the standard data format used for data transmission on the first bus 112 and the standard data format used for data transmission on the second bus 121 may be the same or different.
  • the application processor 11 and the modem 12 can each use a data transmission protocol specified by an existing protocol for data transmission.
  • the first bus 112 can be understood as a common channel in the application processor 11.
  • the second bus 121 can be understood as a common channel in the modem 12.
  • data transmission between the storage control unit 111 and the shared storage module 13 can also be based on a bus, and the standard data format used for data transmission is the same as the standard data format used for data transmission on the first bus 112.
  • the standard data format used for data transmission on the second bus 121 may be the same or different.
  • the application processor 11 may include a first processing module (Processor) 113, and the first processing module 113 may access the shared storage module 13 through the first bus 112 and the storage control unit 111 according to system operation requirements.
  • processor a first processing module
  • the first processing module 113 may access the shared storage module 13 through the first bus 112 and the storage control unit 111 according to system operation requirements.
  • the modem 12 may include a second processing module 122, and the second processing module 122 may send an access request through the second bus 121 to request access to the shared storage module 13 according to the needs of system operation.
  • the access request is transmitted to the first bus 112 through the coupling relationship between the modem 12 and the application processor 11, and then sent to the shared storage module 13 through the storage control unit 111.
  • the application processor 11 and the modem 12 can communicate with each other through a serial bus 14.
  • the serial bus 14 adopts a private data format when transmitting data, and the private data format is different from the aforementioned first bus 112, second bus 121, storage control unit 111, and shared storage module 13.
  • the said standard data format is different from the aforementioned first bus 112, second bus 121, storage control unit 111, and shared storage module 13.
  • the delay of data transmission is reduced to the acceptable range of the modem 12, which makes it possible to improve the data transmission efficiency and bandwidth, which is beneficial to better reduce the delay.
  • the application processor 11 and the modem 12 respectively include an interface unit (link).
  • the interface unit of the application processor 11 is marked as the first interface unit 114
  • the interface unit of the modem 12 is marked as As the second interface unit 123.
  • the first interface unit 114 and the second interface unit 123 are used to connect to the serial bus 14 and convert the data format of the data between the private data format and the respective standard data format of the application processor 11 and the modem 12.
  • the second processing module 122 initiates a read command, and the read command is sequentially transmitted to the storage control unit through the second bus 121, the serial bus 14, the first interface unit 114, and the first bus 112. 111. Then, it is transmitted to the shared storage module 13 through the storage control unit 111.
  • the shared storage module 13 feeds back the data pointed to by the read command, the data is gradually transferred to the second processing module 122 via the reverse path of the aforementioned path.
  • the first interface unit 114 may change the data format of each data packet in the data from the data format adopted by the application processor 11
  • the standard data format is converted to the private data format adopted by the serial bus 14. Then it is transmitted to the second interface unit 123 via the serial bus 14.
  • the second interface unit 123 may convert the data format of each data packet in the data from the private data format to the standard data format adopted by the modem 12. Then, it is transmitted to the second processing module 122 through the second bus 121.
  • the second processing module 122 initiates a write command, and the write command and the data to be written into the shared memory module 13 sequentially pass through the second bus 121, the serial bus 14, the first interface unit 114, The first bus 112 is transmitted to the storage control unit 111. Then, it is transmitted to the shared storage module 13 through the storage control unit 111.
  • the second interface unit 123 can convert the data format of each data packet in the data from the standard data format adopted by the modem 12 To the private data format used by the serial bus 14. Then, it is transmitted to the first interface unit 114 via the serial bus 14.
  • the first interface unit 114 may convert the data format of each data packet in the data from the private data format to the standard data format adopted by the application processor 11. Then, it is transferred to the storage control unit 111 through the first bus 112 for data writing.
  • the shared memory module 13 may be a double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM for short, or DDR for short).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • the data transmitted by the serial bus 14 can be packaged into at least one data packet. Next, several different data transmission processes of the serial bus 14 will be described in detail.
  • the first data transmission method of the serial bus 14 in the embodiment of the present invention may include the following steps:
  • Step S101 Obtain data to be transmitted, and pack the data into at least one data packet, the data packet being a long packet or a short packet, and the long packet and the short packet have different data lengths;
  • Step S102 Use the serial bus to transmit the at least one data packet.
  • the steps S101 and S102 may be executed by the first interface unit 114.
  • the steps S101 and S102 may be executed by the second interface unit 123.
  • the at least one data packet may be all long packets, or all short packets, or a combination of long packets and short packets.
  • long packets and/or short packets can be flexibly selected according to the size of the data to be transmitted to obtain the at least one data packet.
  • the data length of the payload in the short packet may be determined according to the width of a single data transmitted by the serial bus 14.
  • the width of the single data may be the width of most single data transmitted on the serial bus 14.
  • the inventor of the present application found through analysis that the existing high-speed transmission technology generally uses 128 bits as a basic physical (PHY) transmission unit. However, in practical applications, the length of 128 bits is not necessarily the most effective. On the other hand, in order to adapt to complex application scenarios, existing high-speed transmission technologies such as high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCI Express, also known as PCIE) and USB packaging are more complicated.
  • PCI Express Peripheral Component Interconnect Express
  • PCIE Peripheral Component Interconnect Express
  • this implementation minimizes additional expenditures by designing a simple packaging method. Furthermore, by optimizing the length of the data packet, both efficiency and realization are taken into consideration. Specifically, this implementation defines two data packets of different lengths for transmitting data of different lengths.
  • the data sending end (such as the first interface unit 114 or the second interface unit 123) can flexibly select short packets and/or long packets to pack according to the size of the data to be transmitted.
  • the width of a single data is usually 73 bits when transmitting data based on AXI. Then, if data transmission is performed according to the existing 128 bits as the basic unit, a lot of bits will obviously be wasted.
  • the data length of the payload of the short packet is determined to be 77 bits. Further, the overall data length of the short packet may be 112 bits. On the basis of ensuring that sufficient transmission information and a 77-bit payload are effectively accommodated, and is an entire packet, the overall data length of the data packet is reduced as much as possible. Among them, the whole packet means that the data length of the data packet is an integral multiple of 16, and 16 is defined by the physical layer.
  • the short packet 3 may include: a header 31, used to carry the transmission information of the data packet; and a packet body 32, used to carry at least a part of the data.
  • the packet body 32 may include a payload 321, and the length of the packet body 32 may be determined according to the width of a single data transmitted by the serial bus 14. For example, the data length of the payload 321 is 77 bits.
  • the packet header 31 may include a channel identification field (Channel Identification, ChID for short) 311, which is used to indicate a channel for transmitting the data packet (short packet 3 in this embodiment).
  • ChID Channel Identification
  • the packet header 31 may also include a credit counter (Credit Counter, CC for short) indication field 312, which is used to support flow control.
  • the CC indication field 312 may include a CC identification (CCID) and a credit value (Credit). Wherein, the CC identifier is used to indicate the channel to which the short packet 3 belongs, and the credit value is used to indicate the credit value of the channel.
  • the packet header 31 may include multiple sets of CC indication fields 312.
  • FIG. 3 shows three sets of CC indication fields 312, which are respectively denoted as CCID0 and Credit0 groups, CCID1 and Credit1 groups, and CCID2 and Credit2 groups.
  • the CC indicator fields 312 of different groups correspond to different channels.
  • the short packet 3 may also include an ECC error correction code 33.
  • the receiving end of the data packet checks the short packet 3 based on the ECC error correction code 33, if the check result is that a one-bit error occurs, the error is corrected If the check result is an error greater than one bit, it is reported to the upper layer.
  • the upper layer may be the application layer of the communication device 1.
  • the data length of the ECC error correction code 33 may be 9 bits, and the data length of the packet header 31 may be 26 bits.
  • the packet body 32 collectively constitutes a short packet 3 with a total length of 112 bits.
  • the data length of the payload 321 of the packet body 32 can be adjusted according to the width of the single data to be transmitted.
  • the data length of the corresponding short packet 3 can also be adjusted appropriately.
  • the data length of the payload in the long packet may be N times the data length of the payload in the short packet, and N is a positive integer greater than or equal to 2.
  • the data length of the payload 421 in the long packet 4 may be three times the data length of the payload 321 in the short packet 3 shown in FIG. In this way, 4 groups of 73-bit data can be packed in the long packet 4.
  • the long packet 4 may also include a packet header 41, a packet body 42, and an ECC check code 43.
  • the packet header 41 may be used to carry the transmission information of the long packet 4.
  • the header 41 may include a channel identification field (ChID) and a CC indication field.
  • the packet header 41 may also include a data line width indication field (Data Width, DW for short), which is used to indicate the width of the data line used by the data source for this transmission.
  • Data Width Data Width, DW for short
  • the packet header 41 may also include a data position indication field (Position, Pos for short), which is used to indicate the position of the data packet (long packet 4 in this embodiment) transmitted this time in the data line.
  • a data position indication field Position, Pos for short
  • the payload 421 of the long packet 4 may include multiple intervals, and each interval has a corresponding ECC error correction code 43.
  • the payload 421 may include 3 intervals, and the data length of each interval is 86 bits, 103 bits, and 103 bits, respectively. Each interval is followed by an ECC error correction code 43 corresponding to the interval.
  • the data to be transmitted may come from multiple data sources, and the step S101 may include the step of separately packaging data from different data sources to obtain the at least one data packet.
  • the step S102 may include the step of using the same physical path of the serial bus 14 to transmit the at least one data packet, wherein the data packets of different data sources are distinguished based on different channel identification fields (ChID).
  • ChID channel identification fields
  • ChID channel identification field
  • Fig. 5 is a flowchart of a second serial bus data transmission method according to an embodiment of the present invention.
  • the second interface unit 123 as the data receiving end can execute this implementation Example solution to receive the short packet 3 and/or the long packet 4.
  • the first interface unit 114 as the data receiving end can execute the solution of this embodiment to receive the short message. Pack 3 and/or Long Pack 4.
  • the data transmission method may include the following steps:
  • Step S201 Use the serial bus to receive at least one data packet, where the data packet is a long packet or a short packet, and the long packet and the short packet have different data lengths;
  • Step S202 Unpack the at least one received data packet to obtain transmitted data.
  • steps S201 to S202 can be regarded as execution steps corresponding to the steps S101 to S102 in the embodiment shown in FIG. 2 to FIG. They are complementary. Therefore, for the explanation of the terms involved in this embodiment, reference may be made to the related descriptions of the embodiments shown in FIG. 2 to FIG. 4, which will not be repeated here.
  • the standard data format used for data transmission in the transfer demodulator 12 is to perform unpacking processing on the at least one received data packet. And convert the received data format of the at least one data packet into a corresponding standard data format.
  • the data transmission method of this embodiment may further include the step of: for each received data packet, the data packet is adjusted based on the ECC error correction code. Perform verification; if the verification result is that a one-bit error occurs, then the error is corrected; if the verification result is that an error greater than one bit occurs, then it is reported to the upper layer.
  • CRC Cyclic Redundancy Check
  • the short packet 3 and the long packet 4 are transmitted in a one-bit error correction and two-bit error detection (SEC-DED ECC) mode.
  • SEC-DED ECC one-bit error correction and two-bit error detection
  • the ECC error correction code can be replaced with another type of error correction code for verification by the data receiving end.
  • Fig. 6 is a flowchart of a third serial bus data transmission method according to an embodiment of the present invention.
  • the data transmission method of the serial bus 14 in this embodiment may include the following steps:
  • Step S301 Obtain the data to be transmitted, and pack the data into at least one data packet, the data length of the data packet is configurable, and the data packet includes a length indication field (Length) and at least one data packet Unit, the length indication field is used to indicate the number of data packet units;
  • Step S302 Use the serial bus to transmit the at least one data packet.
  • the steps S301 and S302 may be executed by the first interface unit 114. Conversely, when the data to be transmitted is transmitted by the second interface unit 123 to the first interface unit 114, the steps S301 and S302 may be executed by the second interface unit 123.
  • the data packet 5 with variable data length described in this embodiment may include a packet header 51 and a packet body 52.
  • the packet header 51 may be used to carry the transmission information of the data packet 5.
  • the packet header 51 may include a channel identification field (ChID) and a CC indicator field.
  • the packet body 52 may be used to carry at least one data packet unit 521.
  • Data0, Data1,..., Datan are taken as examples for exemplary display.
  • the data length of different data packet units 521 may be the same or different.
  • the data length of each data packet unit 521 in the data packet 5 may be determined by a configuration register.
  • the data to be transmitted can come from multiple data sources. Among them, at least one data packet unit 521 in the same data packet 5 can come from the same data source, and the data packet unit 521 in different data packets 5 can come from different data sources. . That is, data from different data sources are packed into different data packages 5.
  • a transmission block 53 can be obtained by packing per unit data length.
  • the data packet 5 may include multiple transmission blocks 53, and the data length of each transmission block 53 is fixed. Since the data length of the data packet 5 is configurable, the number of transmission blocks 53 included in different data packets 5 may be different.
  • the unit data length may be 119 bits. That is, starting from the header 51 of the data packet 5, there is a packet for every 119 bits. These 119 bits may not have the header 51, and a certain data packet unit 521 may even be interrupted.
  • the last few or part of the last data packet unit 521 of the previous data packet 5 may be packed with the header 51 and/or at least a part of the data packet unit 521 of the next data packet 5 Into a transmission block 53.
  • the transmission block 53 may include a payload 531 and an error correction code 532.
  • the data length of the payload 531 is 119 bits.
  • the payload 531 of the transmission block 53 is obtained by packing every 119 bits from the header 51 of the data packet 5, and then the corresponding error correction code 532 is added to form the transmission block 53.
  • the error correction code 532 may be an ECC error correction code.
  • the length of the physical layer transmission block used is 128 bits. That is, the data length of the transmission block 53 adopts 128 bits common to the existing transmission protocol, wherein the data length of the payload 531 is 119 bits for transmitting data, and the ECC error correction code 532 is 9 bits.
  • the at least one data packet 5 may be packaged end to end as a whole.
  • Fig. 8 is a flowchart of a fourth serial bus data transmission method according to an embodiment of the present invention.
  • the second interface unit 123 as the data receiving end can execute this implementation Example scheme to receive the at least one data packet 5.
  • the first interface unit 114 as the data receiving end can execute the solution of this embodiment to receive the at least One data packet 5.
  • the data transmission method may include the following steps:
  • Step S401 Use the serial bus to receive at least one data packet, the data length of the data packet is configurable, the data packet includes a length indication field and at least one data packet unit, and the length indication field is used for Indicating the number of data packet units;
  • Step S402 unpacks the received at least one data packet to obtain the transmitted data.
  • steps S401 to S402 can be regarded as the execution steps corresponding to the steps S301 to S302 in the embodiment shown in FIG. 6 to FIG. They are complementary. Therefore, for the explanation of the terms involved in this embodiment, reference may be made to the related description of the embodiment shown in FIG. 6 and FIG. 7, which will not be repeated here.
  • step S402 it can be used as the standard data format for data transmission in the application processor 11 to which the first interface unit 114 belongs to the data receiving end, or the second interface unit 123 as the data receiving end belongs to
  • the received at least one data packet 5 is unpacked.
  • the received data format of the at least one data packet 5 is converted into a corresponding standard data format.
  • the data transmission method of this embodiment may further include the step: for each transmission block 53 in each data packet 5, based on the transmission block 53
  • the ECC error correction code 532 in the transmission block 53 checks the data contained in the transmission block 53 (carried in the payload 531); if the check result is one bit error, then the error is corrected; if the check result is more than one bit The error will be reported to the upper level.
  • CRC Cyclic Redundancy Check
  • the transmitted data packet 5 uses a one-bit error correction and two-bit error detection (SEC-DED ECC) mode.
  • SEC-DED ECC single-bit error correction and two-bit error detection
  • the ECC error correction code can be replaced with another type of error correction code for verification by the data receiving end.
  • the communication device 1 may further include: an additional sharing module (not shown), the additional sharing module may be coupled to the application processor 11 and indirectly accessed through the application processor 11 Mentioned shared storage module 13.
  • the additional sharing module may be an off-chip accelerator.
  • the additional shared module may also be an embedded neural network processor (Neural-network Processing Unit, NPU for short).
  • NPU Neuro-network Processing Unit
  • the shared memory solution in this embodiment is not only applicable to the scenario where the application processor 11 and the modem 12 share the shared memory module 13, but also applicable to the scenario where more systems share the shared memory module 13 .
  • the access delay performance is improved.
  • the access to the shared storage module 13 related to cache misses is improved, and the access to the shared storage module 13 that is not cached is improved.
  • the modem 6 may include: a buffer module 62 for buffering data accessed by the modem 6.
  • the modem 6 may further include a function module 61, and the buffer module 62 buffers the data accessed by the function module 61.
  • the modem 6 may be coupled to an external processing device (not shown in FIG. 9), the function module 61 indirectly accesses the shared storage module 13 through the external processing device to obtain data, and the external processing device is connected to the shared storage module 13
  • the storage module 13 is coupled to and can directly access the shared storage module 13.
  • the data accessed by each functional module 61 is buffered, so as to reduce the frequency of the modem 6 accessing the shared memory module 13.
  • a better balance can be achieved between the high latency of the external memory and the real-time requirements of the modem.
  • the modem 6 described in this embodiment may be applied to the shared memory scenario shown in FIG. 1, and the modem 12 shown in FIG. 1 may adopt the specific structure of the modem 6 described in this embodiment.
  • the external processing device is the application processor 11 shown in FIG. 1.
  • the functional module 61 may include a Microcontroller Unit (Microcontroller Unit, MCU for short). Further, the MCU may include multiple sub-units, as shown in processor cluster #1 to processor cluster #N in the figure, and N is greater than or equal to 1.
  • MCU Microcontroller Unit
  • the functional module 61 may include a hardware accelerator. Similar to the MCU, the hardware accelerator may also include multiple subunits, as shown in hardware accelerator #1 to hardware accelerator #M in the figure, and M is greater than or equal to 1.
  • any functional module 61 in the modem 6 when reading data, when any functional module 61 in the modem 6 reads data, it can read the cache module 62 first, if it hits, return the reading result, if it misses, continue to pass The application processor 11 accesses the shared storage module 13.
  • the data buffered by the buffer module 62 may be data accessed by the functional module 61 of the modem 6 with high frequency in history.
  • the historical access results of the functional module 61 in the shared storage module 13 are statistically analyzed by means of simulation or experiment, and the historical high-frequency access data of the functional module 61 is comprehensively analyzed according to the frequency and the amount of data accessed.
  • the data is cached in the cache module 62 in advance for the function module 61 to access.
  • the data cached in the cache module 62 may be data that has been accessed by the functional module 61 of the modem 6 with high frequency in history and has a small amount of data.
  • the cache module 62 may include a plurality of first cache sub-modules 621, and different first cache sub-modules 621 may correspond to different functional modules 61.
  • each processor cluster may be configured with a corresponding first cache sub-module 621.
  • each hardware accelerator may also be configured with a corresponding first cache submodule 621.
  • the functional module 61 For each of the functional modules 61, when the functional module 61 reads data, it first reads the corresponding first cache sub-module 621, if it is hit, it returns the reading result, if it is not hit, it continues to pass the The application processor 11 accesses the shared storage module 13.
  • processor cluster #1 Take processor cluster #1 as an example. When the processor cluster #1 reads data, it first reads the first cache submodule 621 corresponding to it. The application processor 11 accesses the shared storage module 13.
  • the data can be cached in the first cache submodule 621 corresponding to the processor cluster #1 to For later use.
  • the cache module 62 may further include a second cache sub-module 622, and the second cache sub-module 622 may correspond to multiple functional modules 61.
  • the second buffer sub-module 622 may be coupled to the bus 63 in the modem 6 to buffer data transmitted on the bus 63.
  • the bus 63 may be the second bus 121 in FIG. 1.
  • the functional module 61 when the functional module 61 reads data, it first reads the corresponding first cache sub-module 621, if it hits, it returns the reading result, and if it misses, it reads the corresponding first cache sub-module 621.
  • the second cache sub-module 622 continues to access the shared storage module 13 through the application processor 11 if it is still missed.
  • hardware accelerator #1 when the hardware accelerator #1 reads data, it first reads the first cache submodule 621 corresponding to it.
  • the second cache sub-module 622 continues to access the shared storage module 13 through the application processor 11 if it still misses.
  • the data may be preferentially cached to the first cache submodule 621 corresponding to the hardware accelerator #1 for preparation Use later.
  • the first cache submodule 621 corresponding to the hardware accelerator #1 is full at this time, the data may be cached in the second cache submodule 622.
  • the second buffer submodule 622 may be directly coupled to an interface unit for connecting the serial bus between the modem 6 and the external processing device.
  • the second buffer sub-module 622 may be coupled to the second interface unit 123 in FIG. 1 to buffer the data received by the second interface unit 123.
  • the processor cluster may include a coherency interface for implementing memory coherency management among the first cache sub-module 621, the second cache sub-module 622, and the shared storage module 13.
  • the first cache sub-module 621 may preferentially cache the data accessed by the corresponding functional module 61. Further, if the first cache sub-module 621 is full, the data accessed by the functional module 61 corresponding to the first cache sub-module 621 is cached to the second cache sub-module 622.
  • the second buffer sub-module 622 may preferentially buffer the data that has been accessed by the functional module 61 of the modem 6 with high frequency in history. For example, for pre-cached data, it can be preferentially placed in the public cache space (i.e., the second cache submodule 622) for later use.
  • the number and size of each of the first cache sub-module 621 and the second cache sub-module 622 may be divided and determined according to the statistical results of the corresponding functional module 61 and the modem 6's overall access to the shared storage module 13. of. That is, the size of each of the first cache sub-module 621 and the second cache sub-module 622 can be flexibly adjusted (Size Tuning).
  • a larger first cache submodule 621 may be allocated in a targeted manner.
  • a plurality of first buffer sub-modules 621 are temporarily allocated to the functional module 61 to make full use of the buffer space of the modem 6.
  • the capacity of the second cache sub-module 622 may be greater than the capacity of the first cache sub-module 621. Further, the delay performance requirement of the second cache sub-module 622 may be slightly lower than the delay performance requirement of the first cache sub-module 621.
  • the first cache sub-module 621 may be an L1-level random access memory (Random Access Memory, RAM for short).
  • the second cache sub-module 622 may be a relatively low-level but large-capacity RAM.
  • the first cache sub-module 621 may also be an L2 level RAM.
  • the modem 6 itself may be configured with a traditional cache (Cache) 64.
  • the solution of this embodiment is provided with an additional amount of cache module 62 (such as RAM) in the modem 6 to reduce access to data with a small amount of data but with a higher frequency. External access requirements.
  • a part of the first cache sub-module 621 is additionally configured in the MCU.
  • a part of the first cache sub-module 621 can also be configured according to requirements.
  • bus 63 can also be externally provided with part of the second cache sub-module 622 (RAM and Cache).
  • the solution of this embodiment can be widely applied to various types of external memories to improve the access delay performance.

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Abstract

一种串行总线的数据传输方法及通信装置，所述方法包括：获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；使用所述串行总线传输所述至少一个数据包。通过本发明提供方案能够更好的实现低时延、高可靠性的数据传输，且数据传输效率更高，额外支出少。

Description

一种串行总线的数据传输方法及通信装置
本申请要求2020年4月17日提交中国专利局、申请号为2020103071856、发明名称为“一种串行总线的数据传输方法及通信装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，具体地涉及一种串行总线的数据传输方法及通信装置。
背景技术
现有高速传输技术一般都使用128比特作为一个基本的物理(PHY)传输单元。但在实际应用中，128比特的长度并不一定是最有效的。此外，为适应复杂的应用场景，现有高速传输技术如高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，简称PCI Express，亦即PCIE)和USB打包都比较复杂。
上述两个问题导致现有数据传输模式无法满足通信装置对低延迟、高可靠的要求。
另一方面，为满足用户的多样化需求，手机等通信装置除了实现通话功能外，还逐渐扩展出摄像、游戏等多样化功能。这些应用可以是基于独立的系统来控制和实现的。
因此，对于能够实现多种应用的通信装置，通常至少具有两个集成电路芯片，其中一个芯片为调制解调器(modem)，用于实现蜂窝通信功能，可以理解为通信系统；其中另一个芯片为应用处理器(Application Processor，简称AP)，用于实现诸如拍摄、显示、2D/3D引擎等功能，可以理解为应用处理系统。
通常而言，如果一个系统要求大容量、高带宽、低延迟的内存访问，则系统需要搭配一个独立的片外存储器。以通信装置为例，调制解调器和应用处理器通常会各自搭配一个片外存储器。这就导致通信装置同时拥有多个片外存储器，导致整体成本上升。并且，过多的片外存储器还会导致集成各系统的印刷电路板(Printed Circuit Board，简称PCB)的面积增加，不利于通信装置的小型化设计。
如果要使多个系统共享片外存储器，则对数据传输的低延迟、高可靠性、高带宽的要求更为严苛，现有的数据传输模式显然无法满足。
发明内容
本发明解决的技术问题是如何更好的实现低时延、高可靠性的数据传输。
为解决上述技术问题，本发明实施例提供一种串行总线的数据传输方法，包括：获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；使用所述串行总线传输所述至少一个数据包。
可选的，所述短包中的有效载荷的数据长度根据所述串行总线传输的单个数据的宽度确定。
可选的，所述长包中的有效载荷的数据长度是所述短包中的有效载荷的数据长度的N倍，N为大于等于2的正整数。
可选的，所述数据包包括：包头，用于承载所述数据包的传输信息；包体，用于承载所述数据的至少一部分，所述包体的长度根据所述串行总线传输的单个数据的宽度确定。
可选的，所述数据包还包括ECC纠错码。
可选的，所述长包的有效载荷包括多个区间，其中每一区间具有相对应的ECC纠错码。
可选的，所述包头包括：信道标识字段，用于指示传输所述数据 包的信道；CC指示字段，用于支持流控。
可选的，所述待传输的数据来自多个数据源，所述将所述数据打包为至少一个数据包包括：将不同数据源的数据分别打包，以得到所述至少一个数据包；所述使用所述串行总线传输所述至少一个数据包包括：使用所述串行总线的同一物理通路传输所述至少一个数据包，其中，不同数据源的数据包基于不同的信道标识字段相区分。
可选的，所述包头还包括：数据线宽度指示字段，用于指示本次传输数据源所采用的数据线的宽度；数据位置指示字段，用于指示本次传输的数据包在所述数据线中的位置。
为解决上述技术问题，本发明实施例还提供一种串行总线的数据传输方法，包括：使用所述串行总线接收至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；解包接收到的所述至少一个数据包，以获取传输的数据。
可选的，所述数据包包括ECC纠错码，所述数据传输方法还包括：对于接收到的每一数据包，基于所述ECC纠错码对所述数据包进行校验；若校验结果为出现一比特错误，则纠错；若校验结果为出现大于一比特的错误，则上报上层。
为解决上述技术问题，本发明实施例还提供一种通信装置，包括：应用处理器；调制解调器；共享存储模块，所述应用处理器与所述共享处理模块耦接并可直接访问所述共享存储模块，所述调制解调器与所述应用处理器通过串行总线耦接并通过所述应用处理器间接访问所述共享存储器；其中，所述调制解调器与所述应用处理器采用上述数据传输方法进行数据传输。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
本发明实施例提供一种串行总线的数据传输方法，包括：获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；使用所述串行总线 传输所述至少一个数据包。
本实施例方案采用一种简单的打包方式来尽量减少额外支出。进一步，通过优化数据包长度来兼顾效率和实现。具体而言，本实施例方案采用两种不同长度的数据包，用来传输不同长度的数据。数据发送端可以根据待传输的数据的大小灵活选择短包和/或长包来打包，使得兼顾效率和实现成为可能。
进一步，本发明实施例还提供一种通信装置，包括：应用处理器；调制解调器；共享存储模块，所述应用处理器与所述共享处理模块耦接并可直接访问所述共享存储模块，所述调制解调器与所述应用处理器通过串行总线耦接并通过所述应用处理器间接访问所述共享存储器；其中，所述调制解调器与所述应用处理器采用上述数据传输方法进行数据传输。
本实施例方案提供一种改进的通信装置，能够使多个有大容量、高带宽、低延迟内存访问需求的系统共享同一物理存储器，利于降低整体成本，提高系统竞争力。具体而言，共享存储模块挂在应用处理器下，应用处理器能够直接访问共享存储模块，而调制解调器则通过应用处理器间接地访问共享存储模块。由此，可以使得多个大容量、高带宽、低延迟系统共享一个片外物理内存。进一步，通过特别设计的数据包格式和相应的打包/解包方式，将数据传输的延迟降低到调制解调器能够接受的范围，使得提高数据传输效率和带宽成为可能，利于更好的降低延迟。
附图说明
图1是本发明实施例一种通信装置的原理示意图；
图2是本发明实施例第一种串行总线的数据传输方法的流程图；
图3是图2中短包的结构示意图；
图4是图2中长包的结构示意图；
图5是本发明实施例第二种串行总线的数据传输方法的流程图；
图6是本发明实施例第三种串行总线的数据传输方法的流程图；
图7是图6中数据包的结构示意图；
图8是本发明实施例第四种串行总线的数据传输方法的流程图；
图9是本发明实施例一种调制解调器的原理示意图。
具体实施方式
如背景技术所言，现有通信装置的各个系统分别独立配置片外物理内存，整体成本高，且PCB面积大，不利于小型化设计。
虽然现有技术也有基于双口存储器(memory)实现共享存储器的方案。但是，双口存储器的接口主要是并口，且速率通常不高。现有双口存储器能够提供的带宽最大约为6.4Gbps，远低于有大容量、高带宽、低延迟内存访问需求的系统的要求。一般而言，高带宽是指系统访问片外物理内存带宽要求在16Gbps以上；低延迟是指系统访问片外物理内存延迟要求低于1000ns。
如果要使多个系统共享片外存储器，则对数据传输的低延迟、高可靠性、高带宽的要求更为严苛，现有的数据传输模式显然无法满足。
本申请发明人经过分析发现，现有高速传输技术一般都使用128比特作为一个基本的物理(PHY)传输单元。但在实际应用中，128比特的长度并不一定是最有效的。另一方面，为适应复杂的应用场景，现有高速传输技术如高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，简称PCI Express，亦即PCIE)和USB打包都比较复杂。
为解决上述技术问题，本发明实施例提供一种串行总线的数据传输方法，包括：获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；使用所述串行总线传输所述至少一个数据包。
本实施例方案采用一种简单的打包方式来尽量减少额外支出。进一步，通过优化数据包长度来兼顾效率和实现。具体而言，本实施例方案采用两种不同长度的数据包，用来传输不同长度的数据。数据发送端可以根据待传输的数据的大小灵活选择短包和/或长包来打包，使得兼顾效率和实现成为可能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明实施例一种通信装置的原理示意图。
所述通信装置可以为手机等用户设备。
具体地，参考图1，本实施例所述的通信装置1可以包括：应用处理器11；调制解调器12；共享存储模块13，所述应用处理器11与所述共享存储模块13耦接并可直接访问所述共享存储模块13，所述调制解调器12与所述应用处理器11耦接并通过所述应用处理器11间接访问所述共享存储器13。
其中，直接可以是相对于间接而言的，也即，应用处理器11对共享存储模块13的数据存取无需经过其他系统中转，而调制解调器12对共享存储模块13的数据存取需要经过其他系统(如应用处理器11)中转。
需要指出的是，本实施例所述直接访问并不意味着应用处理器11与共享存储模块13是采用数据线直接连接的。在实际应用中，应用处理器11与共享存储模块13之间可以通过接口等连接，此时同样可以认为应用处理器11是直接访问共享存储模块13的。
在一个具体实施中，所述应用处理器11可以包括：存储控制单元111，所述存储控制单元111与所述共享存储模块13相通信，所述存储控制单元111可以用于接收所述调制解调器12的访问请求，并根据所述访问请求访问所述共享存储模块13。
进一步地，所述存储控制单元111还可以用于向所述调制解调器 12反馈对所述共享存储模块13的访问结果。
例如，应用处理器11内的数据传输基于第一总线(bus)112进行，调制解调器12内的数据传输基于第二总线121进行。所述第一总线112上进行数据传输时采用的标准数据格式与所述第二总线121上进行数据传输时采用的标准数据格式可以相同，也可以不同。应用处理器11和调制解调器12内部可以各自采用现有协议规定的数据传输协议进行数据传输。
所述第一总线112可以理解为应用处理器11内的公共通道。类似的，所述第二总线121可以理解为调制解调器12内的公共通道。
进一步，存储控制单元111与共享存储模块13之间也可以基于总线进行数据传输，且数据传输时采用的标准数据格式与所述第一总线112上进行数据传输时采用的标准数据格式与所述第二总线121上进行数据传输时采用的标准数据格式可以相同，也可以不同。
进一步，应用处理器11可以包括第一处理模块(Processor)113，所述第一处理模块113可以根据系统运行需要通过第一总线112和存储控制单元111访问所述共享存储模块13。
进一步，调制解调器12可以包括第二处理模块122，所述第二处理模块122可以根据系统运行需要通过第二总线121发送访问请求，以请求访问共享存储模块13。所述访问请求通过调制解调器12和应用处理器11之间的耦接关系传递至第一总线112，进而通过存储控制单元111发送至共享存储模块13。
接下来对调制解调器12和应用处理器11之间的耦接关系以及相应的数据传输方式进行具体阐述。
在一个具体实施中，所述应用处理器11和调制解调器12之间可以通过串行总线14相通信。具体地，所述串行总线14传输数据时采用私有数据格式，并且，所述私有数据格式不同于前述第一总线112、第二总线121以及存储控制单元111和共享存储模块13之间所采用 的所述标准数据格式。
由此，通过特别设计的数据包格式和相应的打包/解包方式，将数据传输的延迟降低到调制解调器12能够接受的范围，使得提高数据传输效率和带宽成为可能，利于更好的降低延迟。
例如，参考图1，所述应用处理器11和调制解调器12分别包括接口单元(link)，为便于区分，将应用处理器11的接口单元记作第一接口单元114，将调制解调器12的接口单元记作第二接口单元123。
所述第一接口单元114和第二接口单元123用于连接所述串行总线14，并将数据的数据格式在私有数据格式与应用处理器11和调制解调器12各自的标准数据格式之间转换。
在一个典型的应用场景中，第二处理模块122发起读取命令，所述读取命令依次通过第二总线121、串行总线14、第一接口单元114、第一总线112传输至存储控制单元111。进而通过存储控制单元111传输至共享存储模块13。
所述共享存储模块13反馈所述读取命令指向的数据时，所述数据经由前述路径的反向路径逐步传送至所述第二处理模块122。
在传送过程中，当所述数据传送至所述第一接口单元114时，所述第一接口单元114可以将所述数据中的每一数据包的数据格式从所述应用处理器11采用的标准数据格式转换至所述串行总线14所采用的私有数据格式。然后再通过串行总线14传送至第二接口单元123。
响应于接收到基于私有数据格式的数据，所述第二接口单元123可以将所述数据中每一数据包的数据格式从私有数据格式转换为调制解调器12所采用的标准数据格式。然后再通过第二总线121传送至第二处理模块122。
在另一个典型的应用场景中，第二处理模块122发起写命令，所述写命令以及需要写入共享存储模块13的数据依次通过第二总线 121、串行总线14、第一接口单元114、第一总线112传输至存储控制单元111。进而通过存储控制单元111传输至共享存储模块13。
在传送过程中，当所述数据传送至所述第二接口单元123时，所述第二接口单元123可以将所述数据中每一数据包的数据格式从调制解调器12所采用的标准数据格式转换至所述串行总线14所采用的私有数据格式。然后再通过串行总线14传送至所述第一接口单元114。
响应于接收到基于私有数据格式的数据，所述第一接口单元114可以将所述数据中每一数据包的数据格式从私有数据格式转换为所述应用处理器11采用的标准数据格式。然后再通过第一总线112传送至存储控制单元111进行数据写入。
在一个具体实施中，所述共享存储模块13可以是双倍速率同步动态随机存储器(Double Data Rate Synchronous Dynamic Random Access Memory，简称DDR SDRAM，可简称DDR)。
所述串行总线14传输的数据可以打包为至少一个数据包，接下来对所述串行总线14的几种不同的数据传输过程进行具体阐述。
在一个具体实施中，参考图2，本发明实施例第一种串行总线14的数据传输方法可以包括如下步骤：
步骤S101，获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；
步骤S102，使用所述串行总线传输所述至少一个数据包。
具体地，结合图1，当所述待传输的数据是由第一接口单元114传送至第二接口单元123时，所述步骤S101和步骤S102可以是由第一接口单元114执行的。反之，当所述待传输的数据是由第二接口单元123传送至第一接口单元114时，所述步骤S101和步骤S102可以是由第二接口单元123执行的。
进一步地，所述至少一个数据包可以都是长包，或者都是短包，或者是长包和短包的组合。在实际应用中，可以根据待传输的数据的大小灵活选择长包和/或短包以打包得到所述至少一个数据包。
在一个具体实施中，所述短包中的有效载荷(payload)的数据长度可以根据所述串行总线14传输的单个数据的宽度确定。
具体地，所述单个数据的宽度可以是以串行总线14上传输的大多数单个数据的宽度为准。
本申请发明人经过分析发现，现有高速传输技术一般都使用128比特作为一个基本的物理(PHY)传输单元。但在实际应用中，128比特的长度并不一定是最有效的。另一方面，为适应复杂的应用场景，现有高速传输技术如高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，简称PCI Express，亦即PCIE)和USB打包都比较复杂。
针对前述两个问题，本实施通过设计一种简单的打包方式来尽量减少额外支出。进一步，通过优化数据包长度来兼顾效率和实现。具体而言，本实施定义两种不同长度的数据包，用来传输不同长度的数据。数据发送端(如第一接口单元114或第二接口单元123)可以根据待传输的数据的大小灵活选择短包和/或长包来打包。
以演进的可扩展界面(Advanced eXtensible Interface，简称AXI)总线协议为例，基于AXI传输数据时单个数据的宽度通常为73比特。则如果按照现有128比特为基本单位进行数据传输，显然会浪费很多比特。
基于此，本实施中，将所述短包的有效载荷的数据长度确定为77比特。进一步，所述短包整体的数据长度可以为112比特。以在确保有效容纳足够的传输信息以及77比特的有效载荷的，且为整包的基础上，将所述数据包的整体数据长度尽可能的缩小。其中，整包是指数据包的数据长度为16的整倍数，16由物理层定义。
在一个具体实施中，参考图3，短包3可以包括：包头31，用于承载所述数据包的传输信息；包体32，用于承载所述数据的至少一部分。
具体地，包体32可以包括有效载荷321，所述包体32的长度可以根据所述串行总线14传输的单个数据的宽度确定。例如，所述有效载荷321的数据长度为77比特。
进一步地，包头31可以包括信道标识字段(Channel Identification，简称ChID)311，用于指示传输所述数据包(本实施例为短包3)的信道。
进一步，所述包头31还可以包括信用计数器(Credit Counter，简称CC)指示字段312，用于支持流控。例如，CC指示字段312可以包括CC标识(CCID)和信用值(Credit)。其中，CC标识用于指示所述短包3所属信道，信用值用于指示所述信道的信用值。
进一步，所述包头31可以包括多组CC指示字段312，例如，图3示出了3组CC指示字段312，分别记作CCID0和Credit0组、CCID1和Credit1组以及CCID2和Credit2组。其中，不同组的CC指示字段312对应于不同的信道。
进一步，所述短包3还可以包括ECC纠错码33。相应的，所述数据包(本实施例为短包3)的接收端基于所述ECC纠错码33对所述短包3进行校验时，若校验结果为出现一比特错误时纠错，若校验结果为出现大于一比特的错误时上报上层。例如，所述上层可以为通信装置1的应用层。
在图3所示短包3中，ECC纠错码33的数据长度可以为9比特，包头31的数据长度可以为26比特。由此，包体32共同组成总长112比特的短包3。
在一个变化例中，对于采用如PCIE协议标准传输的数据，可以根据传输的单个数据的宽度调整所述包体32的有效载荷321的数据 长度。相应的所述短包3的数据长度也可以适当调整。
在一个具体实施中，长包中的有效载荷的数据长度可以是所述短包中的有效载荷的数据长度的N倍，N为大于等于2的正整数。
例如，参考图4，长包4中有效载荷421的数据长度可以是图3所示短包3中有效载荷321的数据长度的3倍。由此，可以在长包4中打包入4组均为73比特的数据。
具体地，与短包3的结构相类似，所述长包4也可以包括包头41、包体42和ECC校验码43。
其中，包头41可以用于承载长包4的传输信息。例如，包头41可以包括信道标识字段(ChID)和CC指示字段。
进一步，包头41还可以包括数据线宽度指示字段(Data Width，简称DW)，用于指示本次传输数据源所采用的数据线的宽度。
进一步，包头41还可以包括数据位置指示字段(Position，简称Pos)，用于指示本次传输的数据包(本实施例为长包4)在所述数据线中的位置。
进一步，所述长包4的有效载荷421可以包括多个区间，其中每一区间具有相对应的ECC纠错码43。
例如，参考图4，所述有效载荷421可以包括3个区间，各区间的数据长度分别为86比特、103比特和103比特。每一区间后面配置有对应于该区间的ECC纠错码43。
所述ECC纠错码43的数据长度为9比特，所述包头41的数据长度为17比特。由此，长包4的长度为112×3＝336比特。
在一个具体实施中，所述待传输的数据可以来自多个数据源，所述步骤S101可以包括步骤：将不同数据源的数据分别打包，以得到所述至少一个数据包。
相应的，所述步骤S102可以包括步骤：使用所述串行总线14的同一物理通路传输所述至少一个数据包，其中，不同数据源的数据包基于不同的信道标识字段(ChID)相区分。
也即，不同数据源的数据不会打包到一个数据包，但在通过串行总线14传输时，可以基于信道标识字段(ChID)支持将多路数据打包后用一套物理通路传输。
图5是本发明实施例第二种串行总线的数据传输方法的流程图。
具体地，结合图1和图2，当第一接口单元114采用图2所示实施例所述方案打包数据并通过串行总线14传输时，作为数据接收端的第二接口单元123可以执行本实施例方案，以接收所述短包3和/或长包4。反之，当第二接口单元123采用图2所示实施例所述方案打包数据并通过串行总线14传输时，作为数据接收端的第一接口单元114可以执行本实施例方案，以接收所述短包3和/或长包4。
具体地，参考图5，所述数据传输方法可以包括如下步骤：
步骤S201，使用所述串行总线接收至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；
步骤S202，解包接收到的所述至少一个数据包，以获取传输的数据。
本领域技术人员理解，所述步骤S201至步骤S202可以视为与上述图2至图4所示实施例所述步骤S101至步骤S102相呼应的执行步骤，两者在具体的实现原理和逻辑上是相辅相成的。因而，本实施例中涉及名词的解释可以参考图2至图4所示实施例的相关描述，这里不再赘述。
进一步地，在所述步骤S202中，可以作为数据接收端的所述第一接口单元114所属应用处理器11内进行数据传输时的标准数据格式，或者作为数据接收端的所述第二接口单元123所属所述调职解调器12内进行数据传输时的标准数据格式，对接收到的所述至少一个 数据包进行解包处理。并将接收到的所述至少一个数据包的数据格式转换为对应的标准数据格式。
在一个具体实施中，在执行所述步骤S202时或之后，本实施例所述数据传输方法还可以包括步骤：对于接收到的每一数据包，基于所述ECC纠错码对所述数据包进行校验；若校验结果为出现一比特错误，则纠错；若校验结果为出现大于一比特的错误，则上报上层。
本申请发明人经过分析发现，现有的数据传输方案普遍采用循环冗余校验(Cyclic Redundancy Check，简称CRC)检错。虽然CRC可以很好地检查数据传输后有没有出错，但是CRC不能纠正数据错误。一旦发现数据出错后，现有技术方案普遍采用数据重传来补救。而重传不仅造成了很大的数据延时，而且实现也很复杂。
而在本实施例所述共享存储器场景中，传输的短包3和长包4选用了一比特纠错、两比特检错(SEC-DED ECC)模式。这样对于出现的一比特错误，数据接收端可以马上纠正，而不必重传。进一步，由于出现两比特或更多比特出错的概率已经很低，所以可以由上层处理。由此，使得通过串行总线14传输数据的低时延效果更为显著。
在一个变化例中，所述ECC纠错码可以替换为其他类型的纠错码，以供数据接收端校验。
图6是本发明实施例第三种串行总线的数据传输方法的流程图。
具体地，参考图6，本实施例所述串行总线14的数据传输方法可以包括如下步骤：
步骤S301，获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包的数据长度是可配置的，所述数据包中包含长度指示字段(Length)和至少一个数据包单元，所述长度指示字段用于指示所述数据包单元的数量；
步骤S302，使用所述串行总线传输所述至少一个数据包。
结合图1，当所述待传输的数据是由第一接口单元114传送至第二接口单元123时，所述步骤S301和步骤S302可以是由第一接口单元114执行的。反之，当所述待传输的数据是由第二接口单元123传送至第一接口单元114时，所述步骤S301和步骤S302可以是由第二接口单元123执行的。
由此，能够最大限度地提高传输效率。
具体而言，参考图7，本实施例所述数据长度可变的数据包5可以包括包头51和包体52。
所述包头51可以用于承载所述数据包5的传输信息。例如，与上述图2至图4所示实施例中的短包3和长包4相类似，所述包头51可以包括信道标识字段(ChID)以及CC指示字段。
所述包体52可以用于承载至少一个数据包单元521，图7中以Data0,Data1,…,Datan为例进行示例性展示。所述包头51还可以包括所述长度指示字段(Length)，Length＝n表示所述包体52承载的数据包单元521的数量为n个。
不同数据包单元521的数据长度可以是相同的，也可以是不相同的。例如，所述数据包5中每一数据包单元521的数据长度可以由配置(configuration)寄存器确定。
所述待传输的数据可以来自多个数据源，其中，同一数据包5内的至少一个数据包单元521可以来自相同的数据源，不同数据包5内的数据包单元521可以来自不同的数据源。也即，不同数据源的数据打包到不同的数据包5。
进一步地，传输所述数据包5时，在物理层，可以自所述数据包5的包头51开始，每单位数据长度打包得到一个传输块(block)53。换言之，在物理层的层面上，所述数据包5可以包括多个传输块53，每一传输块53的数据长度是固定的。而由于数据包5的数据长度是可配置的，因而不同数据包5包括的传输块53的数量可以是不相同 的。
例如，所述单位数据长度可以为119比特。也即，自所述数据包5的包头51开始每119比特打一个包，这119比特可能没有包头51，甚至也可能打断某个数据包单元521。
进一步而言，还可能存在这样的情形，即前一数据包5的最后几个或最后一个数据包单元521的一部分可能与后一数据包5的包头51和/或至少一部分数据包单元521打包成一个传输块53。
在一个具体实施中，所述传输块53可以包括有效载荷531和纠错码532。其中，所述有效载荷531的数据长度为119比特。
在物理层，自所述数据包5的包头51开始每119比特打包得到所述传输块53的有效载荷531，然后再加上对应的纠错码532，从而形成所述传输块53。
例如，所述纠错码532可以为ECC纠错码。
在本实施例中，所采用的物理层传输块(block)长度为128比特。也即，所述传输块53的数据长度采用现有传输协议通用的128比特，其中有效载荷531的数据长度为119比特，用于传输数据，ECC纠错码532为9比特。
进一步地，所述至少一个数据包5可以是首尾相接地打包为一体。
图8是本发明实施例第四种串行总线的数据传输方法的流程图。
具体地，结合图1和图6，当第一接口单元114采用图6所示实施例所述方案打包数据并通过串行总线14传输时，作为数据接收端的第二接口单元123可以执行本实施例方案，以接收所述至少一个数据包5。反之，当第二接口单元123采用图2所示实施例所述方案打包数据并通过串行总线14传输时，作为数据接收端的第一接口单元114可以执行本实施例方案，以接收所述至少一个数据包5。
具体地，参考图8，所述数据传输方法可以包括如下步骤：
步骤S401，使用所述串行总线接收至少一个数据包，所述数据包的数据长度是可配置的，所述数据包中包含长度指示字段和至少一个数据包单元，所述长度指示字段用于指示所述数据包单元的数量；
步骤S402解包接收到的所述至少一个数据包，以获取传输的数据。
本领域技术人员理解，所述步骤S401至步骤S402可以视为与上述图6至图4所示实施例所述步骤S301至步骤S302相呼应的执行步骤，两者在具体的实现原理和逻辑上是相辅相成的。因而，本实施例中涉及名词的解释可以参考图6和图7所示实施例的相关描述，这里不再赘述。
进一步地，在所述步骤S402中，可以作为数据接收端的所述第一接口单元114所属应用处理器11内进行数据传输时的标准数据格式，或者作为数据接收端的所述第二接口单元123所属所述调职解调器12内进行数据传输时的标准数据格式，对接收到的所述至少一个数据包5进行解包处理。并将接收到的所述至少一个数据包5的数据格式转换为对应的标准数据格式。
在一个具体实施中，在执行所述步骤S402时或之后，本实施例所述数据传输方法还可以包括步骤：对于每一数据包5中的每一传输块53，基于所述传输块53中的ECC纠错码532对所述传输块53中包含的数据(承载于有效载荷531)进行校验；若校验结果为出现一比特错误，则纠错；若校验结果为出现大于一比特的错误，则上报上层。
本申请发明人经过分析发现，现有的数据传输方案普遍采用循环冗余校验(Cyclic Redundancy Check，简称CRC)检错。虽然CRC可以很好地检查数据传输后有没有出错，但是CRC不能纠正数据错误。一旦发现数据出错后，现有技术方案普遍采用数据重传来补救。 而重传不仅造成了很大的数据延时，而且实现也很复杂。
而在本实施例所述共享存储器场景中，传输的数据包5选用了一比特纠错、两比特检错(SEC-DED ECC)模式。这样对于出现的一比特错误，数据接收端可以马上纠正，而不必重传。进一步，由于出现两比特或更多比特出错的概率已经很低，所以可以由上层处理。由此，使得通过串行总线14传输数据的低时延效果更为显著。
在一个变化例中，所述ECC纠错码可以替换为其他类型的纠错码，以供数据接收端校验。
在一个具体实施中，所述通信装置1还可以包括：附加共享模块(图未示)，所述附加共享模块可以与所述应用处理器11耦接并通过所述应用处理器11间接访问所述共享存储模块13。
例如，所述附加共享模块可以为片外加速器。
又例如，所述附加共享模块还可以为嵌入式神经网络处理器(Neural-network Processing Unit，简称NPU)。
也即，本实施例所述共享存储器的方案，不仅适用于应用处理器11与调制解调器12共享所述共享存储模块13的场景，还可以适用于更多个系统共享所述共享存储模块13的场景。
进一步，在基于上述图1至图8所示多个芯片(如应用处理器11和调制解调器12)共享外部存储器(如所述共享存储模块13)方案的基础上，为解决外部存储器的高延迟与调制解调器12的实时性需求之间的冲突，本实施例方案还提供一种改进的调制解调器，旨在解决外部存储器的访问延迟过大，严重约束系统实时性能需求的问题。
具体而言，通过分析外部存储器(如所述共享存储模块13)的访问模式及调制解调器12的功能模块(如MCU和硬件加速器)的访问特点，提升访问延迟性能。进而改善与缓存未命中相关的共享存储模块13访问，改善未缓存的共享存储模块13访问。
在一个具体实施中，参考图9，调制解调器6可以包括：缓存模块62，用于缓存所述调制解调器6访问过的数据。
进一步，所述调制解调器6还可以包括功能模块61，所述缓存模块62缓存的是所述功能模块61访问过的数据。
进一步，所述调制解调器6可以与外部处理器件(图9未示)耦接，所述功能模块61通过所述外部处理器件间接访问共享存储模块13以获取数据，所述外部处理器件与所述共享存储模块13耦接并可直接访问所述共享存储模块13。
由此，通过在调制解调器6内部增设缓存模块62的方式，缓存各功能模块61访问过的数据，以降低调制解调器6访问共享存储模块13的频率。由此，能够在外部存储器的高延迟与调制解调器的实时性需求之间更好的取得平衡。
进一步，本实施例所述调制解调器6可以应用于图1所示共享存储器场景，如图1示出的调制解调器12可以采用本实施例所述调制解调器6的具体结构。相应的，所述外部处理器件即为图1示出的应用处理器11。
在一个具体实施中，所述功能模块61可以包括微控制单元(Microcontroller Unit，简称MCU)。进一步，所述MCU可以包括多个子单元，如图中处理器集群#1至处理器集群#N所示，N大于等于1。
在一个具体实施中，所述功能模块61可以包括硬件加速器。与MCU相类似，所述硬件加速器也可以包括多个子单元，如图中硬件加速器#1至硬件加速器#M所示，M大于等于1。
在一个具体实施中，读数据时，所述调制解调器6中的任一功能模块61读取数据时，可以先读取所述缓存模块62，如果命中就返回读取结果，如果未命中就继续通过所述应用处理器11访问所述共享存储模块13。
进一步地，所述缓存模块62缓存的可以是所述调制解调器6的功能模块61历史上高频访问的数据。
例如，通过仿真或实验等方式统计分析功能模块61历史上在共享存储模块13的访问结果，根据频度和访问的数据量大小等综合分析所述功能模块61历史上高频访问的数据。并将这些数据预先缓存至所述缓存模块62供功能模块61访问。
为进一步优化数据传输效率，缓存到缓存模块62的可以是所述调制解调器6的功能模块61历史上高频访问且数据量较小的数据。
在一个具体实施中，所述缓存模块62可以包括多个第一缓存子模块621，不同的第一缓存子模块621可以对应不同的功能模块61。
例如，每一处理器集群可以各自配置对应的第一缓存子模块621。
又例如，每一硬件加速器也可以各自配置对应的第一缓存子模块621。
对于每一所述功能模块61，所述功能模块61读取数据时，先读取相对应的所述第一缓存子模块621，如果命中就返回读取结果，如果未命中就继续通过所述应用处理器11访问所述共享存储模块13。
以处理器集群#1为例，所述处理器集群#1读取数据时，先读取与其相对应的第一缓存子模块621，如果命中就返回读取结果，如果未命中就继续通过所述应用处理器11访问所述共享存储模块13。
相应的，对于处理器集群#1通过所述应用处理器11访问所述共享存储模块13获取的数据，可以将该数据缓存到所述处理器集群#1对应的第一缓存子模块621，以备后用。
在一个具体实施中，所述缓存模块62还可以包括第二缓存子模块622，所述第二缓存子模块622可以对应多个功能模块61。
例如，所述第二缓存子模块622可以与所述调制解调器6内的总线63耦接，以缓存总线63上传输的数据。其中，所述总线63可以 是图1中的第二总线121。
相应的，对于每一所述功能模块61，所述功能模块61读取数据时，先读取相对应的第一缓存子模块621，如果命中就返回读取结果，如果未命中就读取所述第二缓存子模块622，如果仍未命中就继续通过所述应用处理器11访问所述共享存储模块13。
以硬件加速器#1为例，所述硬件加速器#1读取数据时，先读取与其相对应的第一缓存子模块621，如果命中就返回读取结果，如果未命中就读取所述第二缓存子模块622，如果仍未命中就继续通过所述应用处理器11访问所述共享存储模块13。
相应的，对于硬件加速器#1通过所述应用处理器11访问所述共享存储模块13获取的数据，可以将该数据优先缓存到所述硬件加速器#1对应的第一缓存子模块621，以备后用。但是，如果此时所述硬件加速器#1对应的第一缓存子模块621已满，则可以将所述数据缓存到所述第二缓存子模块622。
在一个具体实施中，所述第二缓存子模块622可以与用于连接调制解调器6与外部处理器件之间的串行总线的接口单元直接耦接。例如，第二缓存子模块622可以与图1中的第二接口单元123耦接，以缓存第二接口单元123接收到的数据。
在一个具体实施中，处理器集群可以包括一致性接口，用于实现第一缓存子模块621、第二缓存子模块622与共享存储模块13之间的内存一致性管理。
在一个具体实施中，所述第一缓存子模块621可以优先缓存相对应的功能模块61访问过的数据。进一步，若第一缓存子模块621已满，再将第一缓存子模块621对应的功能模块61访问过的数据缓存到第二缓存子模块622。
在一个具体实施中，所述第二缓存子模块622可以优先缓存所述调制解调器6的功能模块61历史上高频访问的数据。例如，对于预 缓存的数据，可以优先放到公共缓存空间(即第二缓存子模块622)，以备后用。
在一个具体实施中，各第一缓存子模块621和第二缓存子模块622的数量以及大小，可以是根据对相对应的功能模块61以及调制解调器6整体访问共享存储模块13的统计结果来划分确定的。也即，各第一缓存子模块621和第二缓存子模块622的大小是可以灵活调整(Size Tuning)的。
进一步，针对访问需求较高的功能模块61，可以针对性的分配较大的第一缓存子模块621。或者，针对该功能模块61临时分配多个第一缓存子模块621，以充分利用调制解调器6的缓存空间。
在一个具体实施中，所述第二缓存子模块622的容量可以大于所述第一缓存子模块621的容量。进一步，所述第二缓存子模块622对延迟性能要求可以略低于所述第一缓存子模块621对延迟性能的要求。
在一个具体实施中，所述第一缓存子模块621可以是L1级随机存取存储器(Random Access Memory，简称RAM)。所述第二缓存子模块622可以是比较低级但容量大的RAM。
或者，所述第一缓存子模块621也可以是L2级RAM。
在一个具体实施中，所述调制解调器6本身可以配置传统的缓存(Cache)64。本实施例方案为改善外部存储器(如共享存储模块13)的访问延迟性能，在调制解调器6中额外配置适量的缓存模块62(如RAM)来降低访问数据量较少但频度较高的数据的外部访问需求。
具体而言，MCU里除配置传统的缓存(Cache)之外，额外配置一部分第一缓存子模块621。
类似的，硬件加速器里，也可以根据需求配置一部分第一缓存子模块621。
类似的，总线63也可以外置部分第二缓存子模块622(RAM和Cache)。
本实施例方案可以广泛适用于各类外部存储器，用于改善访问延迟性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (12)

  1. 一种串行总线的数据传输方法，其特征在于，包括：
    获取待传输的数据，并将所述数据打包为至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；
    使用所述串行总线传输所述至少一个数据包。
  2. 根据权利要求1所述的数据传输方法，其特征在于，所述短包中的有效载荷的数据长度根据所述串行总线传输的单个数据的宽度确定。
  3. 根据权利要求1或2所述的数据传输方法，其特征在于，所述长包中的有效载荷的数据长度是所述短包中的有效载荷的数据长度的N倍，N为大于等于2的正整数。
  4. 根据权利要求1所述的数据传输方法，其特征在于，所述数据包包括：
    包头，用于承载所述数据包的传输信息；
    包体，用于承载所述数据的至少一部分，所述包体的长度根据所述串行总线传输的单个数据的宽度确定。
  5. 根据权利要求4所述的数据传输方法，其特征在于，所述数据包还包括ECC纠错码。
  6. 根据权利要求5所述的数据传输方法，其特征在于，所述长包的有效载荷包括多个区间，其中每一区间具有相对应的ECC纠错码。
  7. 根据权利要求4所述的数据传输方法，其特征在于，所述包头包括：
    信道标识字段，用于指示传输所述数据包的信道；
    CC指示字段，用于支持流控。
  8. 根据权利要求7所述的数据传输方法，其特征在于，所述待传输的数据来自多个数据源，所述将所述数据打包为至少一个数据包包括：将不同数据源的数据分别打包，以得到所述至少一个数据包；所述使用所述串行总线传输所述至少一个数据包包括：使用所述串行总线的同一物理通路传输所述至少一个数据包，其中，不同数据源的数据包基于不同的信道标识字段相区分。
  9. 根据权利要求7所述的数据传输方法，其特征在于，所述包头还包括：
    数据线宽度指示字段，用于指示本次传输数据源所采用的数据线的宽度；
    数据位置指示字段，用于指示本次传输的数据包在所述数据线中的位置。
  10. 一种串行总线的数据传输方法，其特征在于，包括：
    使用所述串行总线接收至少一个数据包，所述数据包为长包或短包，所述长包和短包具有不同的数据长度；
    解包接收到的所述至少一个数据包，以获取传输的数据。
  11. 根据权利要求10所述的数据传输方法，其特征在于，所述数据包包括ECC纠错码，所述数据传输方法还包括：
    对于接收到的每一数据包，基于所述ECC纠错码对所述数据包进行校验；
    若校验结果为出现一比特错误，则纠错；
    若校验结果为出现大于一比特的错误，则上报上层。
  12. 一种通信装置，其特征在于，包括：
    应用处理器；
    调制解调器；
    共享存储模块，所述应用处理器与所述共享处理模块耦接并可直接访问所述共享存储模块，所述调制解调器与所述应用处理器通过串行总线耦接并通过所述应用处理器间接访问所述共享存储器；
    其中，所述调制解调器与所述应用处理器采用上述权利要求1至11中任一项所述方法进行数据传输。
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