WO2021208647A1 - 数据传输装置及方法 - Google Patents

数据传输装置及方法 Download PDF

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Publication number
WO2021208647A1
WO2021208647A1 PCT/CN2021/080229 CN2021080229W WO2021208647A1 WO 2021208647 A1 WO2021208647 A1 WO 2021208647A1 CN 2021080229 W CN2021080229 W CN 2021080229W WO 2021208647 A1 WO2021208647 A1 WO 2021208647A1
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Prior art keywords
data
data transmission
transmission device
signal
clock
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PCT/CN2021/080229
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English (en)
French (fr)
Inventor
杨国华
许迪
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苏州库瀚信息科技有限公司
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Priority to US17/996,171 priority Critical patent/US11822503B2/en
Publication of WO2021208647A1 publication Critical patent/WO2021208647A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/3625—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a time dependent access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention generally relates to the field of data transmission technology, and particularly relates to a data transmission device and method, a data transmission system, and a two-way data transmission system.
  • Another type of bus interface design uses a lower frequency clock to reduce power consumption, but at the cost of a complex clock and data recovery scheme on the receiver side.
  • the purpose of the present invention is to provide a data transmission device and method, which can increase the data transmission rate and reduce the power consumption.
  • the present application discloses a data transmission device, which includes a transmitter and a receiver connected by N data lines, where N is an integer greater than 1, wherein the transmitter includes:
  • N first transmitting units respectively output transmission signals to the N data lines
  • the encoder is configured to control the output level of one and only one first transmitting unit on each transmission signal to be inverted according to the currently sent data unit, so that there is one and only one data line in the N data lines The level in is inverted;
  • the receiver includes:
  • N receiving units respectively receive transmission signals from the N data lines
  • the decoder is connected to the N receiving units and configured to decode the data unit corresponding to the data line according to the level-inverted data line among the N data lines.
  • the encoder is further configured to encode data to avoid sending more than two identical data units consecutively, so that the same one of the N data lines is inverted more than two consecutive times.
  • the decoder further decodes the data encoded by the encoder.
  • the encoder includes a state machine
  • the decoder includes a state machine
  • the data transmission device further includes a clock generator for generating a clock signal, and the clock signal samples a data unit sent by the encoder to generate the transmission signal;
  • the receiver also includes clock recovery logic, which is connected to the N receiving units and used to perform clock recovery operations on the transmission signals output by the N receiving units and output a recovered clock signal.
  • the recovered clock signal pairs
  • the decoded data unit is sampled and output.
  • the clock signal is a non-differential clock signal.
  • the receiving unit includes an edge detection module and an edge feedback module
  • the edge detection module is used to detect the level inversion of the N data lines
  • the edge feedback module obtains the edge detection module output And output to the edge detection module for the next detection.
  • the encoder outputs multiple M-bit data units one by one, where M is an integer greater than one.
  • the application also discloses a data transmission system, which includes a plurality of data transmission devices as described above, and further includes:
  • the asynchronous clock recovery logic performs asynchronous logic operations on the clock signals output by the receivers of the multiple data transmission devices, and outputs the recovered clock signals.
  • the multiple data transmission devices share the same clock generator.
  • the multiple data transmission devices are respectively used to transmit data of different sizes.
  • the application also discloses a data transmission method for transmitting data between a transmitter and a receiver connected by N data lines, where N is an integer greater than 1, and the method includes:
  • the data unit is sampled and then output.
  • the decoded data unit is sampled and output by the recovered clock signal.
  • the method further includes: encoding data to avoid sending more than two identical data units consecutively, so that the same one of the N data lines undergoes level inversion more than two consecutive times.
  • the application also discloses a two-way data transmission system, including a master data transmission device and a slave data transmission device connected by N data lines, where N is an integer greater than 1; wherein, the master data transmission device includes the aforementioned A transmitter and a receiver.
  • the slave data transmission device includes the transmitter and the receiver as described above.
  • the two-way data transmission system further includes: a clock generator connected to the transmitter of the master data transmission device; and a clock recovery/generator connected to the transmitter of the slave data transmission device.
  • the two-way data transmission system further includes a transmission controller for controlling the transmission process between the master data transmission device and the slave data transmission device to avoid transmission conflicts.
  • the feature A+B+C is disclosed, and in another example, the feature A+B+D+E is disclosed, and the features C and D are equivalent technical means that play the same role.
  • Feature E can technically be combined with feature C.
  • the A+B+C+D solution should not be regarded as recorded because it is technically infeasible, and A+B+ The C+E plan should be deemed to have been documented.
  • Figure 1 shows a schematic diagram of a data transmission device in the prior art.
  • Fig. 2 shows a schematic diagram of a data transmission device in an embodiment of the present application.
  • Fig. 3 shows a schematic diagram of a data transmission device in another embodiment of the present application.
  • Fig. 4 shows a schematic diagram of a receiving unit in an embodiment of the present application.
  • Fig. 5 shows a schematic diagram of a data transmission system in an embodiment of the present application.
  • Fig. 6 shows a schematic diagram of a two-way data transmission system in an embodiment of the present application.
  • Fig. 7 shows a flowchart of a data transmission method in an embodiment of the present application.
  • FIG. 2 shows a schematic diagram of the data transmission device 1000.
  • the device 1000 includes a transmitter 100, a channel 200, and a receiver 300.
  • the transmitter 100 and the receiver 300 The N data lines 201.1,..., 201.N in the channel 200 are connected, where N is an integer greater than one. For example, N is 4, 5, 8, etc.
  • the transmitter 100 includes:
  • the N first transmitting units 102 respectively output transmission signals to the N data lines 201;
  • the encoder 101 is configured to control the output level of one and only one first transmitting unit 102 corresponding to the data unit to be inverted on each transmission signal according to the data unit currently to be sent, so that on each transmission signal There are and only one of the N data lines 201 has the level inverted.
  • the encoder outputs multiple M-bit data units one by one, where M is an integer greater than one.
  • the input of the encoder is multiple M-bit data units, and the multiple M-bit data units are output to 2 M data lines or more than 2 M data lines.
  • the input of the encoder 101 is multiple 2 bits, and the encoder 101 outputs the multiple input 2 bits one by one, and outputs to 4 or more than 4 (for example, 5) data lines.
  • the input of the encoder 101 is multiple With 3 bits, the encoder outputs 8 or more (for example, 9, 10) data lines.
  • the transmitter 100 further includes N double-edge flip-flops 103, and each double-edge flip-flop 103 is respectively connected to a transmitting unit 102, and the dual-edge flip-flop 103 is activated on the rising edge and the falling edge of data at the same time. Sampling along the edge can increase the data transmission speed.
  • the data transmission device 1000 further includes a clock generator 104 for generating the clock signal.
  • the clock generator 104 is connected to each dual-edge flip-flop 103 and provides the clock signal to the dual-edge flip-flop 103.
  • the clock generator 104 is directly connected to each transmitting unit 102.
  • the clock signal samples the data unit sent by the encoder 101 to generate the transmission signal.
  • the transmission signal is sent by the transmitting unit 102 to the data line for transmission.
  • the clock signal is a non-differential clock signal, that is, the clock signal is a single ended signal.
  • the receiver 300 includes:
  • N receiving units 301 respectively receive the transmission signal from the N data lines 201;
  • the decoder 302 is connected to the N receiving units 301 and configured to decode the data unit corresponding to the data line according to the level-inverted data line of the N data lines 201.
  • the receiver 300 further includes a double-edge flip-flop 304.
  • the double-edge flip-flop 304 performs sampling on the rising edge and the falling edge of the data at the same time, which can increase the data transmission speed.
  • the data transmission state further includes a clock recovery logic 303, which is connected to the N receiving units 301 and used to perform clock recovery operations on the transmission signals output by the N receiving units 301, and output the recovered Clock signal, the recovered clock signal samples the decoded data unit and then outputs it.
  • a clock recovery logic 303 which is connected to the N receiving units 301 and used to perform clock recovery operations on the transmission signals output by the N receiving units 301, and output the recovered Clock signal, the recovered clock signal samples the decoded data unit and then outputs it.
  • the encoder 101 on the first clock signal, sends a data unit A, for example, "00", after the clock signal is sampled to generate an output signal and then transmitted via the data line, the data line 201.1 corresponding to the data unit A The level in the data C is reversed from 0 to 1.
  • the encoder 101 On the second clock signal, the encoder 101 sends a data unit C, such as "01”, and the level in the data line 201.N corresponding to the data C is reversed from 0 to 1.
  • the encoder 101 On the third clock signal, sends a data unit C, such as "01”, and the level of the data line 201.N corresponding to the data unit C is flipped from 1 to 0.
  • Encoder 101 sends data unit B, for example, "10" and the level of data line 201.2 corresponding to data unit B is inverted from 0 to 1.
  • encoder 101 sends data unit A, for example, The level of "00" in the data line 201.1 corresponding to the data unit A is flipped from 1 to 0, and so on. Therefore, on each transmission signal, there is one and only one data line corresponding to the currently sent data unit whose level is inverted.
  • the encoder 101 is further configured to encode data to avoid the same one of the N data lines on two or more consecutive clock signals. A level flip occurs.
  • the decoder 302 also decodes the data encoded by the encoder 101. As shown in FIG. 3, the encoder 101 causes the data B to be sent on the third clock signal, avoiding the continuous transmission of the data C, thereby avoiding the back-to-back phenomenon.
  • the encoder outputs multiple M-bit data units, it outputs to 2 M data lines.
  • it needs to output to more than 2 M data lines. For example, in the embodiment of FIG. 2, 4 data lines are required, while in the embodiment of FIG. 3, 5 data lines are required.
  • the encoder 101 encodes data in many ways.
  • the encoder 101 and the decoder 302 include a state machine (not shown in the figure), and the state machine stores the data unit transmitted on the previous clock signal.
  • the input to the encoder 101 is 2-bit data, and the data has four valid data: 00, 01, 10, 11.
  • the encoder 302 state machine has 6 states: Z, A, B, C, D, E. Among them, the state Z is the initial state of the encoder 101.
  • the other 5 states are: State A represents the last data line 201.1 inversion, State B represents the last data line 201.2 inversion, State C represents the last data line 201.3 inversion, State D represents the last data line 201.4 inversion, and State E represents The data line 201.5 was flipped last time.
  • the decoder 302 uses a state machine to store the result of the last decoding, and as long as the data line 201.5 is turned over, the data transmitted at this time can be regarded as consistent with the state machine.
  • the architecture in Figure 3 can achieve higher power efficiency by transmitting the same data. This is because in the traditional architecture shown in Figure 1, there are four data lines and one clock line in the five signal buses, of which four data lines need to be flipped on average on each clock, and the clock line must be inverted. Inversion, so 3 signal lines need to be inverted for every 4 bits transmitted, that is, 3/4 signal conversions are required for every bit transmitted. In the architecture shown in Figure 3, only one signal line needs to be inverted for every two bits transmitted, that is, 1/2 signal conversion is required for each bit transmitted. Compared with 3/4 of the traditional architecture, the conversion rate of this application is Low directly brings power consumption benefits. In fact, the traditional architecture requires the clock signal to be a differential signal during high-speed transmission, that is, the traditional architecture requires 6 signal lines and requires more inversions. Compared with this solution, the power consumption efficiency of this application is more obvious.
  • the receiving unit 301 includes an edge detection module 3011 and an edge feedback module 3012.
  • the edge detection module 3011 is used to detect the level inversion of the N data lines 201, so The edge feedback module 3012 obtains the signal output by the edge detection module 3011 and outputs it to the edge detection module 3011 for the next detection.
  • the state of the corresponding data line can be predicted For example, when the state of the data line is 1, the next data unit that transmits the same data, the state of the data line should be 0, when the state of the data line is 0, the next transmission of the same data On the unit, the state of the data line should be 1, that is to say, the change of the data line is determined, and the edge feedback module can increase the speed of data detection, thereby increasing the data transmission speed.
  • a data transmission system which includes a plurality of data transmission devices as described above, and also includes: asynchronous clock recovery logic for performing clock signals output by the receivers of the multiple data transmission devices Asynchronous logic operation, and output the recovered clock signal.
  • Fig. 5 shows a schematic diagram of a data transmission system 2000, which includes two data transmission devices 1000, 1000' described in the first embodiment. The system shown in FIG. 5 only uses two data transmission devices as an example for description, and those skilled in the art should understand that this application is not limited thereto.
  • the clock recovery logic 303 of the first data transmission device 1000 and the second data transmission device 1000' are respectively connected to the asynchronous clock recovery logic 400, and the asynchronous clock recovery logic 400 combines and outputs the clock signal extracted by the clock recovery logic 303.
  • the decoders 302 of the first data transmission device 1000 and the second data transmission device 1000' are respectively connected to a third double-edge flip-flop 500, and the third double-edge flip-flop 500 outputs the clock of 400 according to the asynchronous clock recovery logic
  • the signal samples and outputs the signals output by the decoder 302 of the first data transmission device 1000 and the second data transmission device 1000'.
  • the encoders 101 of the first data transmission device 1000 and the second data transmission device 1000' are further configured to encode data to avoid the occurrence of data in the N data lines on more than two consecutive clock signals. The level of the same line is reversed twice in a row.
  • the decoders of the first data transmission device 1000 and the second data transmission device 1000' also decode the data encoded by the encoder 101.
  • first data transmission device 1000 and the second data transmission device 1000' share the same clock generator 600. In other embodiments, the first data transmission device 1000 and the second data transmission device 1000' may also use respective clock generators.
  • the first data transmission device 1000 and the second data transmission device 1000' are respectively used to transmit data of different sizes.
  • the first data transmission device 1000 can transmit S bits of data
  • the second data transmission device 1000' can transmit L bits of data.
  • the data of the same size is transmitted, and the data transmission of the data transmission system takes less time than two transmissions using only one data transmission device.
  • the operating speed of the high-speed signal bus interface depends on the matching of the delays between all bus signals, so the high-speed bus design imposes restrictions on how many parallel signals can be applied to the bus.
  • narrow buses can be combined to form a wide bus, and the receiver clock of the narrow bus can be "ANDed" together.
  • Muller C-components are used to generate the final receiver clock of the broadband bus. Extend the bus width while the bus is running,
  • FIG. 6 shows a schematic diagram of a two-way data transmission system 3000.
  • the system 3000 includes a master data transmission device 700 and a slave data transmission device 800 connected by N data lines. , Where N is an integer greater than 1.
  • the master data transmission device 700 includes the transmitter 100 and the receiver 300 described in the first embodiment
  • the slave data transmission device 800 includes the transmitter 100 and the receiver 300 described in the first embodiment. It can be understood that the master data transmission device 700 and the slave data transmission device 800 may share the same channel, that is, the same N data lines.
  • the two-way data transmission system 3000 further includes: a clock generator 910 connected to the transmitter of the master data transmission device and a clock recovery/generator 920 connected to the transmitter of the slave data transmission device 800 .
  • the two-way data transmission system 3000 further includes a transmission controller (not shown in the figure) for controlling the transmission process between the master data transmission device 700 and the slave data transmission device 800, Avoid transmission conflicts.
  • the transmission controller may be a command/address controller.
  • the transmission controller includes a command/address generator and a command/address receiver connected by a command/address bus, and the command/address receiver is connected with the clock recovery/generator.
  • the fourth embodiment of the present application discloses a data transmission method for transmitting data between a transmitter and a receiver connected by N data lines, where N is an integer greater than 1, and the method can pass the aforementioned
  • the data transmission device 1000, the data transmission system 2000 or the two-way data transmission system 3000 are realized.
  • FIG. 7 shows a flowchart of a data transmission method in an embodiment of the present application, and the method includes:
  • Step S101 sending multiple data units one by one
  • Step S102 in each transmission signal, there is one and only one data line corresponding to the data unit currently sent, and the level of the data line is reversed;
  • Step S103 extract the transmission signal, and decode the data unit corresponding to the data line according to the level-inverted data line among the N data lines;
  • step S104 the data unit is sampled and then output.
  • the method further includes: encoding data to avoid sending more than two identical data units consecutively, so that the same one of the N data lines is inverted more than two consecutive times.
  • the method further includes:
  • the decoded data unit is sampled by the recovered clock signal and then output
  • an act is performed based on a certain element, it means that the act is performed at least based on that element, which includes two situations: performing the act only based on the element, and performing the act based on the element and Other elements perform the behavior.
  • Multiple, multiple, multiple, etc. expressions include two, two, two, and two or more, two or more, and two or more expressions.

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Abstract

本申请公开了一种数据传输装置及方法，用于在以N条数据线连接的发射机和接收机之间传输数据，N为大于1的整数，所述方法包括：逐个发送多个数据单元；在每个传输信号上有且仅有一条与当前发送的数据单元对应的数据线中的电平发生翻转；提取出所述传输信号，根据所述N条数据线中电平翻转的数据线解码出该数据线对应的数据单元；对所述数据单元进行采样后输出。

Description

数据传输装置及方法 技术领域
本发明一般涉及数据传输技术领域，特别涉及一种数据传输装置及方法、数据传输系统、双向数据传输系统。
背景技术
传统的高速并行总线接口依赖于数据和时钟/选通脉冲上的差分(differential)信号，例如，高速DDR4 DRAM接口。最近提出了具有单端时钟转发的数据单端(single ended)信号，如图1所示，以实现低功耗下的高速操作。
另一类总线接口设计采用了一个较低频率的时钟以降低功耗，但以接收机侧的复杂时钟和数据恢复方案为代价。
发明内容
本发明的目的在于提供一种数据传输装置及方法，提高数据传输速率，降低功耗。
本申请公开了一种数据传输装置，包括以N条数据线连接的发射机和接收机，N为大于1的整数；其中，所述发射机包括：
N个第一发射单元，分别输出传输信号到所述N条数据线；
编码器，被配置为根据当前发送的数据单元控制在每个传输信号上有且仅有一个第一发射单元输出的电平发生翻转，使得所述N条数据线中有且仅有一条数据线中的电平发生翻转；
所述接收机包括：
N个接收单元，分别从所述N条数据线接收传输信号；
解码器，连接所述N个接收单元并配置为根据所述N条数据线中电平翻转的数据线解码出该数据线对应的数据单元。
在一个优选例中，所述编码器还被配置为编码数据以避免连续发送两个以上相同的数据单元，使得所述N条数据线中的同一条连续两次以上发生电平的翻转。
在一个优选例中，所述解码器还对所述编码器编码的数据进行解码。
在一个优选例中，所述编码器包括状态机，所述解码器包括状态机。
在一个优选例中，所述数据传输装置还包括时钟生成器，用于生成时钟信号，所述时钟信号采样所述编码器发送的数据单元生成所述传输信号；
所述接收机还包括时钟恢复逻辑，其连接所述N个接收单元并用于将所述N个接收单元输出的传输信号进行时钟恢复运算，并输出恢复的时钟信号，所述恢复的时钟信号对解码的数据单元进行采样后输出。
在一个优选例中，所述时钟信号为非差分时钟信号。
在一个优选例中，所述接收单元包括边沿检测模块和边沿反馈模块，所述边沿检测模块用于检测所述N条数据线的电平翻转，所述边沿反馈模块获取所述边沿检测模块输出的信号，并输出到所述边沿检测模块以用于下一次的检测。
在一个优选例中，所述编码器将多个M比特的数据单元逐个输出，其中，M为大于1的整数。
本申请还公开了一种数据传输系统，该系统包括多个如前文描述的数据传输装置，还包括：
异步时钟恢复逻辑，将所述多个数据传输装置的接收机输出的时钟信号进行异步逻辑运算，并输出恢复的时钟信号。
在一个优选例中，所述多个数据传输装置共用同一个时钟生成器。
在一个优选例中，所述多个据传输装置分别用于传输不同大小的数据。
本申请还公开了一种数据传输方法，用于在以N条数据线连接的发射机和接收机之间传输数据，N为大于1的整数，所述方法包括：
逐个发送多个数据单元；
在每个传输信号上有且仅有一条与当前发送的数据单元对应的数据线中的电平发生翻转；
提取出所述传输信号，根据所述N条数据线中电平翻转的数据线解码出该数据线对应的数据单元；
对所述数据单元进行采样后输出。
在一个优选例中，还包括：
通过时钟信号采样当前发送的数据单元生成所述传输信号；
将所述传输信号进行时钟恢复运算，并输出恢复的时钟信号；
通过所述恢复的时钟信号对解码的数据单元进行采样后输出。
在一个优选例中，还包括：编码数据以避免连续发送两个以上相同的数据单元，使得所述N条数据线中的同一条连续两次以上发生电平的翻转。
本申请还公开了一种双向数据传输系统，包括以N条数据线连接的主数据传输装置和从数据传输装置，N为大于1的整数；其中，所述主数据传输装置包括如前文描述的发射机和接收机，所述从数据传输装置包括如前文描述的发射机和接收机。
在一个优选例中，所述双向数据传输系统还包括：连接所述主数据传输装置的发射机的时钟生成器；连接所述从数据传输装置的发射机的时钟恢复/生成器。
在一个优选例中，所述双向数据传输系统还包括传输控制器，用于控制所述主数据传输装置和所述从数据传输装置之间的传输过程，避免发生传输冲突。
相对于现有技术，本申请至少具有以下有益效果：
本申请中，在每个传输信号上，所述N条数据线中有且仅有一条与当前 发送的数据单元对应的数据线中的电平发生翻转，可以降低功耗，提高数据传输速度。
本申请的说明书中记载了大量的技术特征，分布在各个技术方案中，如果要罗列出本申请所有可能的技术特征的组合(即技术方案)的话，会使得说明书过于冗长。为了避免这个问题，本申请上述发明内容中公开的各个技术特征、在下文各个实施方式和例子中公开的各技术特征、以及附图中公开的各个技术特征，都可以自由地互相组合，从而构成各种新的技术方案(这些技术方案均因视为在本说明书中已经记载)，除非这种技术特征的组合在技术上是不可行的。例如，在一个例子中公开了特征A+B+C，在另一个例子中公开了特征A+B+D+E，而特征C和D是起到相同作用的等同技术手段，技术上只要择一个使用即可，不可能同时采用，特征E技术上可以与特征C相组合，则，A+B+C+D的方案因技术不可行而应当不被视为已经记载，而A+B+C+E的方案应当视为已经被记载。
附图说明
参考以下附图描述本申请的非限制性和非穷举性实施例，其中除非另有说明，否则相同的附图标记在各个附图中指代相同的部分。
图1示出了现有技术中数据传输装置的示意图。
图2示出了本申请一实施例中数据传输装置的示意图。
图3示出了本申请另一实施例中数据传输装置的示意图。
图4示出了本申请一实施例中接收单元的示意图。
图5示出了本申请一实施例中数据传输系统的示意图。
图6示出了本申请一实施例中双向数据传输系统的示意图。
图7示出了本申请一实施例中数据传输方法的流程图。
具体实施方式
现在将描述本申请的各个方面和示例。以下描述提供了用于彻底理解和实现这些示例的描述的具体细节。然而，本领域技术人员将理解，可以在没有许多这些细节的情况下实践本申请。
另外，可能未详细示出或描述一些众所周知的结构或功能，以便简明扼要并避免不必要地模糊相关描述。
在下面给出的描述中使用的术语旨在以其最广泛的合理方式解释，即使它与本申请的某些特定示例的详细描述一起使用。以下甚至可以强调某些术语，然而，任何旨在以任何受限制的方式解释的术语将在本详细描述部分中明确且具体地定义。
实施例一
本申请的实施例一中公开了一种数据传输装置1000，图2示出了数据传输装置1000的示意图，该装置1000包括发射机100、通道200和接收机300，发射机100和接收机300以通道200中的N条数据线201.1，……，201.N连接，其中，N为大于1的整数。例如，N为4、5、8等。
其中，所述发射机100包括：
N个第一发射单元102，分别输出传输信号到所述N条数据线201；
编码器101，被配置根据当前要发送的数据单元控制在每个传输信号上有且仅有一个与该数据单元对应的第一发射单元102输出的电平发生翻转，使得在每个传输信号上所述N条数据线201有且仅有一条数据线中的电平发生翻转。
在一实施例中，所述编码器将多个M比特的数据单元逐个输出，其中，M为大于1的整数。编码器的输入是多个M比特的数据单元，将该多个M比特的数据单元，并输出到2 M条数据线或大于2 M条的数据线。例如，编码器101的输入是多个2比特，编码器101将输入的多个2比特逐个输出，并且输出到4或大于4(例如，5)条数据线，编码器101的输入是多个3比特， 编码器输出到8或大于8(例如，9，10)条数据线。
在一实施例中，所述发射机100还包括N个双沿触发器103，每一个双沿触发器103分别连接一个发射单元102，所述双沿触发器103同时在数据的上升沿和下降沿进行采样，可以提高数据传输速度。
在一实施例中，所述数据传输装置1000还包括时钟生成器104，用于生成所述时钟信号。所述时钟生成器104连接每一个双沿触发器103，并将所述时钟信号提供给双沿触发器103。在不包括双沿触发器103的实施例中，所述时钟生成器104直接连接每一个发射单元102。其中，所述时钟信号采样所述编码器101发送的数据单元生成所述传输信号。所述传输信号由所述发射单元102发送到数据线进行传输。
在一实施例中，所述时钟信号为非差分时钟信号，即，所述时钟信号为单端(single ended)信号。
其中，所述接收机300包括：
N个接收单元301，分别从所述N条数据线201接收所述传输信号；
解码器302，连接所述N个接收单元301并配置为根据所述N条数据线201中电平翻转的数据线解码出该数据线对应的数据单元。
在一实施例中，所述接收机300还包括双沿触发器304，双沿触发器304同时在数据的上升沿和下降沿进行采样，可以提高数据传输速度。
在一实施例中，所述数据传输状态还包括时钟恢复逻辑303，其连接所述N个接收单元301并用于将所述N个接收单元301输出的传输信号进行时钟恢复运算，并输出恢复的时钟信号，所述恢复的时钟信号对解码的数据单元进行采样后输出。
在一实施例中，第一个时钟信号上，编码器101发送数据单元A，例如，“00”，经时钟信号采样生成输出信号后经数据线传输，与该数据单元A对应的数据线201.1中的电平由0翻转为1，第二个时钟信号上，编码器101发送数据单元C，例如“01”，与该数据C对应的数据线201.N中的电平由0翻 转为1，第三个时钟信号上，编码器101发送数据单元C，例如“01”，与该数据单元C对应的数据线201.N中的电平由1翻转为0，第四个时钟信号上，编码器101发送数据单元B，例如，“10”与该数据单元B对应的数据线201.2中的电平由0翻转为1，第五个时钟信号上，编码器101发送数据单元A，例如，“00”与该数据单元A对应的数据线201.1中的电平由1翻转为0，依次类推。因此，在每个传输信号上有且仅有一条与当前发送的数据单元对应的数据线中的电平发生翻转。
从图2中可以看出，当连续发送两个数据单元C时，数据线201.N连续发生两次翻转，形成背靠背(back-to-back)现象。在另一实施例中，为了避免传输过程中产生背靠背现象，所述编码器101还被配置为编码数据以避免连续两个以上的时钟信号上所述N条数据线中的同一条连续两次发生电平的翻转。在该实施例中，所述解码器302还对所述编码器101编码的数据进行解码。参考图3所示，所述编码器101使得在第三个时钟信号发送数据B，避免连续传输数据C，从而避免背靠背现象。需要说明的是，编码器将多个M比特的数据单元输出时，输出到2 M条数据线，然而为了避免背靠背现象，需要输出到大于2 M条的数据线。例如，图2的实施例中，需要4条数据线，而图3的实施例中，需要5条数据线。
所述编码器101对数据的编码方式很多。在一实施例中，所述编码器101和解码器302中包括状态机(图中未示出)，所述状态机存储上一个时钟信号上传输的数据单元。例如，编码器101中输入为2比特数据，该数据有四个有效数据：00，01，10，11。编码器302状态机有6个状态：Z,A,B,C,D,E。其中，状态Z为编码器101起始状态。其他5个状态分别为：状态A代表上次数据线201.1翻转，状态B代表上次数据线201.2翻转，状态C代表上次数据线201.3翻转，状态D代表上次数据线201.4翻转，状态E代表上次数据线201.5翻转。如果编码器101的输入是00，而状态机的状态不是A，那么翻转数据线201.1，新状态为A。如果编码器101的输入是00，而状态机 的状态是A，那么翻转数据线201.5，新状态为E。编码器101的输入是01,10,11，状态B,C,D时，采用类似方法翻转数据线。因此，如果编码器输入为连续同一个数据单元，例如01，01，01，则数据线201.2，201.5，201.2依次翻转，从而避免每一条数据线上的背靠背翻转。在该实施例中，解码器302利用状态机存储上次解码结果，只要看到数据线201.5翻转就可将此时传输的数据认定为和状态机一致。
与图1中的传统架构相比，图3中的架构中传输相同数据可以实现更高的功率效率。这是因为在图1所示的传统架构里，5条信号总线中有4条数据线和一条时钟线，其中4条数据线在每个时钟上平均2条线需要翻转，并且时钟线一定会翻转，所以每传输4个比特需要3条信号线发生翻转，也就是每传输一个比特需要3/4个信号转换。而图3所示的架构里，每传输两个比特只需一条信号线发生翻转，也就是每传输一个比特需要1/2个信号转换，相比传统架构的3/4，本申请的转换率低直接带来功耗效益。实际上传统架构在高速传输时要求时钟信号为差分信号，也就是传统架构需要6条信号线，需要的翻转更多，相对于该方案本申请的功耗效率更明显。
在一实施例中，参考图4所示，所述接收单元301包括边沿检测模块3011和边沿反馈模块3012，所述边沿检测模块3011用于检测所述N条数据线201的电平翻转，所述边沿反馈模块3012获取所述边沿检测模块3011输出的信号，并输出到所述边沿检测模块3011以用于下一次的检测。本实施例中，在每个时钟信号上有且仅有一条与当前发送的数据单元对应的数据线中的电平发生翻转，因此当传输相同的数据单元时，对应的数据线的状态可以预测，例如，当该数据线上的状态为1时，下一个传输相同的数据单元上，该条数据线的状态应当是0，当该数据线上的状态为0时，下一个传输相同的数据单元上，该条数据线的状态应当是1，也就是说，数据线的变化是确定的，采用边沿反馈模块可以提高数据检测的速度，从而提高数据传输速度。
实施例二
本申请的实施例二中公开了一种数据传输系统，包括多个前文所述的数据传输装置，还包括：异步时钟恢复逻辑，将所述多个数据传输装置的接收机输出的时钟信号进行异步逻辑运算，并输出恢复的时钟信号。图5示出了数据传输系统2000的示意图，该系统2000包括两个实施例一中描述的数据传输装置1000、1000’。图5中所示的系统仅以2个数据传输装置为例进行说明，本领域技术人员应当理解，本申请并不以此为限。
第一数据传输装置1000和第二数据传输装置1000’的时钟恢复逻辑303分别连接异步时钟恢复逻辑400，所述异步时钟恢复逻辑400将所述时钟恢复逻辑303提取的时钟信号合并输出。
所述第一数据传输装置1000和第二数据传输装置1000’的解码器302分别连接第三双沿触发器500，所述第三双沿触发器500根据所述异步时钟恢复逻辑输出400的时钟信号对所述第一数据传输装置1000和第二数据传输装置1000’的解码器302输出的信号进行采样输出。
在一实施例中，所述第一数据传输装置1000和第二数据传输装置1000’的编码器101还被配置为编码数据以避免连续两个以上的时钟信号上所述N条数据线中的同一条连续两次发生电平的翻转。在该实施例中，所述第一数据传输装置1000和第二数据传输装置1000’的解码器还对所述编码器101编码的数据进行解码。
在一实施例中，所述第一数据传输装置1000和第二数据传输装置1000’共用同一个时钟生成器600。在其他实施例中，第一数据传输装置1000和第二数据传输装置1000’也可以采用各自的时钟生成器。
在一实施例中，所述第一数据传输装置1000和第二数据传输装置1000’分别用于传输不同大小的数据。本实施例中，第一数据传输装置1000可以传输S个比特的数据，所述第二数据传输装置1000’可以传输L个比特的数据。在该实施例中，传输相同的大小的数据，该数据传输系统的数据传输比仅采 用一个数据传输装置传输两次花费的时间少。
高速信号总线接口的操作速度取决于所有总线信号之间的延迟的匹配，因此高速总线设计对可在总线中施加多少并行信号施加了限制。本实施例中可以将窄总线组合在一起以形成宽总线，可以将窄总线的接收器时钟“与”在一起，例如使用Muller C-元件，以生成宽带总线的最终接收器时钟，在保持高速总线运行的同时扩展总线宽度，
实施例三
本申请的实施例三中公开了一种双向数据传输系统，图6示出了双向数据传输系统3000的示意图，系统3000包括以N条数据线连接的主数据传输装置700和从数据传输装置800，其中，N为大于1的整数。其中，所述主数据传输装置700包括实施例一中描述的发射机100和接收机300，所述从数据传输装置800包括实施例一中描述的发射机100和接收机300。可以理解，主数据传输装置700和从数据传输装置800可以通用相同的通道，即相同的N条数据线。
在一实施例中，所述双向数据传输系统3000还包括：连接所述主数据传输装置的发射机的时钟生成器910和连接所述从数据传输装置800的发射机的时钟恢复/生成器920。
在一实施例中，所述双向数据传输系统3000还包括传输控制器(图中未示出)，用于控制所述主数据传输装置700和所述从数据传输装置800之间的传输过程，避免发生传输冲突。在一实施例中，传输控制器可以为命令/地址控制器。例如，传输控制器包括以命令/地址总线连接的命令/地址生成器和命令/地址接收器，所述命令/地址接收器连接所述时钟恢复/生成器。
实施例四
本申请的实施例四中公开了一种数据传输方法，用于在以N条数据线连 接的发射机和接收机之间传输数据，N为大于1的整数，该方法可以通过前文所述的数据传输装置1000、数据传输系统2000或双向数据传输系统3000实现。图7示出了本申请一实施例中数据传输方法的流程图，所述方法包括：
步骤S101，逐个发送多个数据单元；
步骤S102，在每个传输信号上有且仅有一条与当前发送的数据单元对应的数据线中的电平发生翻转；
步骤S103，提取出所述传输信号，根据所述N条数据线中电平翻转的数据线解码出该数据线对应的数据单元；
步骤S104，对所述数据单元进行采样后输出。
在一实施例中，所述方法进一步包括：编码数据以避免连续发送两个以上相同的数据单元，使得所述N条数据线中的同一条连续两次以上发生电平的翻转。
在一实施例中，所述方法进一步包括：
通过时钟信号采样当前发送的数据单元生成所述传输信号；
将所述传输信号进行时钟恢复运算，并输出恢复的时钟信号；
通过所述恢复的时钟信号对解码的数据单元进行采样后输出
需要说明的是，在本专利的申请文件中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。本专利的申请文件中，如果提到根据某要素执行某行为，则是指 至少根据该要素执行该行为的意思，其中包括了两种情况：仅根据该要素执行该行为、和根据该要素和其它要素执行该行为。多个、多次、多种等表达包括2个、2次、2种以及2个以上、2次以上、2种以上。
在本说明书提及的所有文献都被认为是整体性地包括在本申请的公开内容中，以便在必要时可以作为修改的依据。此外应理解，以上所述仅为本说明书的较佳实施例而已，并非用于限定本说明书的保护范围。凡在本说明书一个或多个实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本说明书一个或多个实施例的保护范围之内。
在一些情况下，在权利要求书中记载的动作或步骤可以按照不同于实施例中的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序才能实现期望的结果。在某些实施方式中，多任务处理和并行处理也是可以的或者可能是有利的。

Claims (17)

  1. 一种数据传输装置，包括以N条数据线连接的发射机和接收机，N为大于1的整数；其中，所述发射机包括：
    N个第一发射单元，分别输出传输信号到所述N条数据线；
    编码器，被配置为根据当前发送的数据单元控制在每个传输信号上有且仅有一个第一发射单元输出的电平发生翻转，使得所述N条数据线中有且仅有一条数据线中的电平发生翻转；
    所述接收机包括：
    N个接收单元，分别从所述N条数据线接收传输信号；
    解码器，连接所述N个接收单元并配置为根据所述N条数据线中电平翻转的数据线解码出该数据线对应的数据单元。
  2. 根据权利要求1所述的数据传输装置，其特征在于，所述编码器还被配置为编码数据以避免连续发送两个以上相同的数据单元，使得所述N条数据线中的同一条连续两次以上发生电平的翻转。
  3. 根据权利要求2所述的数据传输装置，其特征在于，所述解码器还对所述编码器编码的数据进行解码。
  4. 根据权利要求3所述的数据传输装置，其特征在于，所述编码器包括状态机，所述解码器包括状态机。
  5. 根据权利要求1所述的数据传输装置，其特征在于，所述数据传输装置还包括时钟生成器，用于生成时钟信号，所述时钟信号采样所述编码器发送的数据单元生成所述传输信号；
    所述接收机还包括时钟恢复逻辑，其连接所述N个接收单元并用于将所述N个接收单元输出的传输信号进行时钟恢复运算，并输出恢复的时钟信号，所述恢复的时钟信号对解码的数据单元进行采样后输出。
  6. 根据权利要求5所述的数据传输装置，其特征在于，所述时钟信号为非差分时钟信号。
  7. 根据权利要求1所述的数据传输装置，其特征在于，所述接收单元包括边沿检测模块和边沿反馈模块，所述边沿检测模块用于检测所述N条数据线的电平翻转，所述边沿反馈模块获取所述边沿检测模块输出的信号，并输出到所述边沿检测模块以用于下一次的检测。
  8. 根据权利要求1所述的数据传输系统，其特征在于，所述编码器将多个M比特的数据单元逐个输出，其中，M为大于1的整数。
  9. 一种数据传输系统，其特征在于，包括多个如权利要求1-8中任意一项所述数据传输装置，还包括：
    异步时钟恢复逻辑，将所述多个数据传输装置的接收机输出的时钟信号进行异步逻辑运算，并输出恢复的时钟信号。
  10. 根据权利要求9所述的数据传输系统，其特征在于，所述多个数据传输装置共用同一个时钟生成器。
  11. 根据权利要求9所述的数据传输系统，其特征在于，所述多个据传输装置分别用于传输不同大小的数据。
  12. 一种数据传输方法，用于在以N条数据线连接的发射机和接收机之间传输数据，N为大于1的整数，所述方法包括：
    逐个发送多个数据单元；
    在每个传输信号上有且仅有一条与当前发送的数据单元对应的数据线中的电平发生翻转；
    提取出所述传输信号，根据所述N条数据线中电平翻转的数据线解码出该数据线对应的数据单元；
    对所述数据单元进行采样后输出。
  13. 根据权利要求12所述的数据传输方法，其特征在于，还包括：
    通过时钟信号采样当前发送的数据单元生成所述传输信号；
    将所述传输信号进行时钟恢复运算，并输出恢复的时钟信号；
    通过所述恢复的时钟信号对解码的数据单元进行采样后输出。
  14. 根据权利要求12所述的数据传输方法，其特征在于，还包括：编码数据以避免连续发送两个以上相同的数据单元，使得所述N条数据线中的同一条连续两次以上发生电平的翻转。
  15. 一种双向数据传输系统，其特征在于，包括以N条数据线连接的主数据传输装置和从数据传输装置，N为大于1的整数；其中，所述主数据传输装置包括如权利要求1-8中任意一项所述的发射机和接收机，所述从数据传输装置包括如权利要求1-8中任意一项所述的发射机和接收机。
  16. 根据权利要求15所述的双向数据传输系统，其特征在于，所述双向数据传输系统还包括：连接所述主数据传输装置的发射机的时钟生成器；连接所述从数据传输装置的发射机的时钟恢复/生成器。
  17. 根据权利要求16所述的双向数据传输系统，其特征在于，所述双向数据传输系统还包括传输控制器，用于控制所述主数据传输装置和所述从数据传输装置之间的传输过程，避免发生传输冲突。
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